Asynchronous extensible address event coding circuit for neuromorphic chip

Abstract

The invention relates to an asynchronous extensible address event coding circuit for a neuromorphic chip, the circuit comprises a layered structure, each layer of structure comprises one or more extensible basic units, the input of each basic unit is a plurality of pulse signals, and each basic unit comprises an input cache, a control path and a data path; the final output address end of the kth layer is connected with the address selector of the (k + 1) th layer, and the output pulse end of the basic unit of the kth layer is connected with the input cache of the basic unit of the (k + 1) th layer. Compared with the prior art, the address event coding circuit has the advantages of improving the applicability and expansibility of the address event coding circuit and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of encoding circuits, and in particular to an asynchronous scalable address event encoding circuit for a neuromorphic chip. Background Art

[0002] In recent years, neuromorphic computing has received more and more attention due to its similar information processing methods to biological systems. Neuromorphic computing requires less energy than traditional computing methods, so it is suitable for edge artificial intelligence applications. The algorithm commonly used in neuromorphic computing is the Spiking Neural Network (SNN). In order to deploy this network, multiple artificial neurons that use pulses to transmit information are implemented in the neuromorphic chip. The address event representation protocol is a common way to encode and transmit pulses in neuromorphic chips. In this protocol, the pulses emitted by each neuron inside the chip core will be encoded and assigned an independent address, which is output to the outside of the core through a common bus with the neuron pulse. On the other hand, the receiver of the pulse decodes the address signal sent from the bus through a decoder and sends the pulse to the target neuron, thus completing the transmission process of the pulse information.

[0003] In the circuit implementation of the address event representation protocol, the design of the decoder is often relatively fixed, while the encoder has many different design methods, which means there is a large room for optimization. In some neuromorphic chips in recent years, the encoding and decoding circuits of address event representation occupy about a quarter of the chip's overall area and one-fifth of its power consumption. In addition, optimizing address event encoding circuits with longer critical paths can improve the chip's real-time computing capabilities. Therefore, designing low-latency, low-power, and low-area address event encoding circuits is an important topic in neuromorphic chip design.

[0004] Existing technologies, such as S. Ouyang et al., "A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips," in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109 / TCSII.2024.3351840, only designed a two-layer address event encoding circuit structure, which is limited in application flexibility and cannot achieve a good balance between area, power consumption and delay. The applicability and scalability of the circuit are poor. Summary of the invention

[0005] The purpose of the present invention is to provide an asynchronous and scalable address event encoding circuit for a neuromorphic chip in order to improve the applicability and scalability of the address event encoding circuit.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] An asynchronous scalable address event encoding circuit for a neuromorphic chip, the circuit comprising a hierarchical structure, each layer of the structure comprising one or more scalable basic units, the input of each basic unit being a plurality of pulse signals, the basic unit comprising an input cache, a control path and a data path, wherein the control path comprises a merge connection module and a control AND gate, the data path comprises a mask arbitrator, an encoder and two triggers, the two triggers being a second trigger and a third trigger, the mask arbitrator comprising a first trigger, each basic unit being provided with an output address terminal and an output pulse terminal, one end of the merge connection module being connected to the control AND gate, and the other end being connected to a bus port and an output pulse terminal, and the Q end of the third trigger of the data path being connected to the output address terminal;

[0008] The final output address terminal of the kth layer is connected to the address selector of the k+1th layer, and the output pulse terminal of the basic unit of the kth layer is connected to the input buffer of the basic unit of the k+1th layer.

[0009] Furthermore, the input buffer stores multiple input pulse signals.

[0010] Furthermore, the input end of the mask arbitrator is connected to the output end of the input buffer, the output end of the mask arbitrator is connected to the input end of the encoder and the D end of the second trigger, and the output end of the encoder is connected to the D end of the third trigger.

[0011] Furthermore, the merging and connecting module is provided with a trigger signal output terminal, and the trigger signal output terminal is connected to the clock signal input terminals of the first trigger, the second trigger and the third trigger.

[0012] Furthermore, the Q terminal and the output pulse terminal of the second trigger are commonly connected to the input terminal of the address AND gate, and the output terminal of the address AND gate is connected to the control terminal of the input buffer.

[0013] Furthermore, the mask arbitrator includes two AND gate arrays, a selector and a first trigger, and the two AND gate arrays are a first AND gate array and a second AND gate array.

[0014] Furthermore, the input end of the first AND gate array is connected to the output end of the input buffer, the output end of the input buffer and the output end of the first AND gate array are connected to the input end of the selector, the output end of the selector is connected to the input end of the mask generation module, the output end of the mask generation module and the input end of the mask generation module are input into the second AND gate array together, the output end of the second AND gate array is connected to the input end of the encoder, the output end of the mask generation module is also connected to the D end of the first trigger, and the Q end of the first trigger is connected to the input end of the first AND gate array.

[0015] Furthermore, the mask generation module outputs a mask signal, the 0th bit of the mask signal is 0, and the nth bit is obtained by performing an OR operation on the n-1th bit of the mask signal and the signal at the input end of the mask generation module, where n is greater than or equal to 1.

[0016] Furthermore, the selection signal output end of the basic unit of the k+1th layer is connected to the address selector of the k+1th layer and the address trigger of the k+1th layer, where k is greater than or equal to 1, and the selection signal output end is connected to the output end of the second AND gate array.

[0017] Furthermore, the trigger signal output terminal of the basic unit of the k+1th layer is connected to the clock signal input terminal of the address trigger, the D terminal of the address trigger is connected to the output terminal of the address selector of the k+1th layer, and the Q terminal of the address trigger and the output address terminal of the basic unit of the k+1th layer are connected together to the final output address terminal of the k+1th layer.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The present invention proposes a hierarchical expandable address event coding circuit, designs the output pulses of all the basic units in the previous layer as input signals to be sent to the basic units in the next layer, and then converted into output pulses of the entire two-layer structure. The address selector selects the output pulse address of the basic unit in the previous layer according to the arbitration result of the next layer. This address and the output pulse address of the basic unit in the next layer together constitute the output address of the entire two-layer structure. Such an inter-layer connection structure enables the coding circuit to be expanded into a circuit structure of any number of layers, and the number of layers of the circuit and the scale of each layer can be customized, so as to meet different practical application requirements in terms of area, power consumption and delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the structure of an existing binary tree address event encoding circuit;

[0021] Figure 2 The basic unit structure of the hierarchical scalable address event encoding circuit of the present invention;

[0022] Figure 3The overall structure of the hierarchical scalable address event coding circuit and the inter-layer connection mode of the present invention;

[0023] Figure 4 It is the address event output under different input conditions of the present invention. DETAILED DESCRIPTION

[0024] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0025] The present invention proposes an asynchronous scalable address event encoding circuit for a neuromorphic chip, the overall structure of the circuit and the inter-layer connection method are as follows: Figure 3 As shown. The circuit of the present invention includes a layered structure, each layer of the structure includes one or more expandable basic units, the input of each basic unit is a plurality of pulse signals, the basic unit includes an input cache, a control path and a data path, wherein the control path includes a merge connection module and a control AND gate, the data path includes a mask arbitrator, an encoder and two triggers, the two triggers are a second trigger and a third trigger, the mask arbitrator includes a first trigger, each basic unit is provided with an output address terminal and an output pulse terminal, one end of the merge connection module is connected to the control AND gate, and the other end is connected to the bus port and the output pulse terminal, the Q end of the third trigger of the data path is connected to the output address terminal;

[0026] The final output address terminal of the kth layer is connected to the address selector of the k+1th layer, and the output pulse terminal of the basic unit of the kth layer is connected to the input buffer of the basic unit of the k+1th layer.

[0027] The input buffer stores a plurality of input pulse signals.

[0028] The input end of the mask arbitrator is connected to the output end of the input buffer, the output end of the mask arbitrator is connected to the input end of the encoder and the D end of the second trigger, and the output end of the encoder is connected to the D end of the third trigger.

[0029] The merging and connecting module is provided with a trigger signal output terminal, and the trigger signal output terminal is connected to the clock signal input terminals of the first trigger, the second trigger and the third trigger.

[0030] The Q terminal and the output pulse terminal of the second trigger are commonly connected to the input terminal of the address AND gate, and the output terminal of the address AND gate is connected to the control terminal of the input buffer.

[0031] The mask arbitrator includes two AND gate arrays, a selector and a first trigger, and the two AND gate arrays are a first AND gate array and a second AND gate array.

[0032] The input end of the first AND gate array is connected to the output end of the input buffer, the output end of the input buffer and the output end of the first AND gate array are connected to the input end of the selector, the output end of the selector is connected to the input end of the mask generation module, the output end of the mask generation module and the input end of the mask generation module are input into the second AND gate array together, the output end of the second AND gate array is connected to the input end of the encoder, the output end of the mask generation module is also connected to the D end of the first trigger, and the Q end of the first trigger is connected to the input end of the first AND gate array.

[0033] The mask generation module outputs a mask signal, the 0th bit of the mask signal is 0, and the nth bit is obtained by performing an OR operation on the n-1th bit of the mask signal and the signal at the input end of the mask generation module, where n is greater than or equal to 1.

[0034] The selection signal output end of the basic unit of the k+1th layer is connected to the address selector of the k+1th layer and the address trigger of the k+1th layer, where k is greater than or equal to 1.

[0035] The trigger signal output end of the basic unit of the k+1th layer is connected to the clock signal input end of the address trigger, the D end of the address trigger is connected to the output end of the address selector of the k+1th layer, and the Q end of the address trigger and the output address end of the basic unit of the k+1th layer are connected together to the final output address end of the k+1th layer.

[0036] Figure 1 For the commonly used binary tree structure address event encoding circuit:

[0037] The upper left shows the connection method of the tree structure. A four-input encoding circuit can be built by three two-input arbitrator units (ARBITER) to form a two-level tree structure. Similarly, more levels of tree structures can be built to adapt to more inputs.

[0038] The upper right figure shows the circuit structure of the basic unit of the circuit, the arbiter unit (ARBITER). The following two figures show the specific circuit design of the connection module and arbitration logic in the arbiter unit structure.

[0039] The advantages of this binary tree structure are simple unit structure and relatively low energy consumption, but as the number of inputs increases, the number of layers of the tree structure also increases, which greatly increases the area and delay of the circuit, which limits the performance of neuromorphic chips. Therefore, this scheme designs a hierarchical and scalable address event encoding circuit, whose basic unit input is scalable, thereby greatly reducing the number of layers required for the overall circuit, thereby reducing delay and area.

[0040] The basic unit of the hierarchical scalable address event encoding circuit proposed by the present invention is as follows: Figure 2As shown. It is mainly divided into three parts: input buffer, control path and data path. The input buffer is composed of multiple "connection" module circuits, which are used to store the input pulse data until the pulse is successfully sent from the output port. The control path adopts the joint-link handshake method commonly used in bundled data asynchronous circuits. On the one hand, it realizes the handshake between the input pulse and the bus, and on the other hand, it ensures that no timing violations occur in the data path. The data path contains a new type of mask arbitrator, which performs polling arbitration on multiple input pulses so that the pulse of a certain channel can be output from the bus. The result of the arbitration is encoded into a binary address through the encoder for output.

[0041] Mask arbiter: The input multiple pulse signals first pass through an AND gate array with the mask signal of the mask arbiter, which shields some of the multiple pulse signals and prevents them from passing through the arbiter. If the mask signal shields all the input pulses, the selector selects the original input signal, otherwise it selects the input signal shielded by the mask signal. The signal after the selector will generate a mask signal through the mask generation module. The specific working mode of the mask generation module is: the 0th bit of the mask signal is 0; the 1st bit of the mask signal is obtained by the OR operation of the 0th bit of the input signal (passing through the selector) and the 0th bit of the mask signal; the 2nd bit of the mask signal is obtained by the OR operation of the 1st bit of the input signal and the 1st bit of the mask signal, and so on. On the one hand, the mask signal contains the information of the arbitration result (assuming that the Mth pulse signal is transmitted). In the next arbitration process, the mask signal shields the Mth pulse signal through the AND gate array, so that the arbitration priority of the Mth path is pulled to the lowest, thus realizing polling arbitration. On the other hand, the mask signal and the signal after passing through the selector are passed through an AND gate array to implement fixed priority arbitration for the signal after passing through the selector, thereby obtaining the final arbitration result.

[0042] Basic unit working mode: When one or more neurons in the core of the neuromorphic chip emit pulses, these pulses are first temporarily stored by the input buffer. At this time, the AND gate in the control path detects that there is pulse data in the input buffer and sends a request signal to the merge-connect handshake circuit. The handshake circuit determines whether the bus is idle. If the bus is idle, it sends an output pulse to the bus and sends a trigger signal to the data path at the same time. Otherwise, it suspends the sending process and waits for the bus to be idle again before sending subsequent signals. In the control path, there are two delay units in the "connection" module, which is used to ensure that when the trigger signal is generated, the data port signals of each trigger in the data path are stable, so that there will be no setup time violation. In the data path, the mask arbitrator polls and arbitrates the input pulses, and gives the addresses of the pulses that are allowed to be output from the bus in turn. The encoder converts the address from a one-hot code to a binary code. When the trigger signal of the control path arrives, the data path outputs a pulse address signal to the bus and releases the pulse signal of the corresponding address in the input buffer.

[0043] like Figure 3 As shown in the upper part of the figure, the overall structure of the address event coding circuit proposed by the present invention is composed of multiple expandable basic units stacked in a tree shape, thereby forming a hierarchical and expandable topological structure. For example, if there are a total of 256 neuron pulse inputs, a 2-layer structure can be designed, in which the first layer has 16 16-input basic units and the second layer has 1 16-input basic unit. If a binary tree design is adopted, an 8-layer structure needs to be built. The hierarchical and expandable structure greatly reduces the hierarchy of the circuit, thereby reducing the delay and area of ​​the circuit.

[0044] The number of layers in the hierarchical structure and the size of the basic unit in each layer: The delay and area of ​​the basic unit are proportional to the input scale of the basic unit. For the pulse input of N neurons, the input scale of the basic unit of each layer can be set to This minimizes the overall coding circuit delay, where k is the number of layers in the hierarchical structure. For less than 256 inputs, k can be 2; for more inputs, k can be larger to obtain lower delay. If it is not an integer, the nearest integer is selected. For example, if N=1024, k=3, the first layer can be designed as a 16-input basic unit, and the second and third layers can be designed as 8-input basic units.

[0045] Interlayer connection method: Figure 3As shown in the lower part of the figure, each basic unit in the previous layer will output a pulse and the corresponding pulse address. All the output pulses of the basic units in the previous layer are sent to the basic units in the next layer as input signals, and then converted into output pulses of the entire two-layer structure. The address selector selects the output pulse address of the basic unit in the previous layer according to the arbitration result of the next layer. This address and the output pulse address of the basic unit in the next layer together constitute the output address of the entire two-layer structure. If there are more layers, the connection relationship between the layers can be deduced in the same way.

[0046] like Figure 4 As shown in the figure, the hierarchical scalable address event coding circuit designed by this scheme is configured as a 2-layer structure, and the working conditions under two different pulse inputs are tested. It can be seen from the waveform that the circuit has a correct output. In the discrete pulse input mode, the neurons numbered 1, 8, and 15 (hexadecimal f) successively and independently emit pulses. It can be seen that after a short delay, the circuit successfully outputs the pulse, and the address of each output pulse also corresponds to the neuron that emits the pulse. On the other hand, in the short-term intensive pulse input mode, the neurons numbered 1, 4, 5, 8, and 9 emit pulses at the same time in a very short time window. After these pulses pass through the address event coding circuit designed by this scheme, 5 pulses appear in sequence at the serial output port, and the corresponding addresses are consistent with the numbers of the neurons that emit them, verifying the arbitration function of the circuit under concurrent pulse input. In summary, the address event coding circuit designed by this scheme can correctly output the neuron pulses emitted from the bus under different circumstances.

[0047] The present invention designs a coding circuit structure that can be expanded to any number of layers. In application scenarios with a large number of input channels such as brain-computer interfaces (such as 1024 input channels), a circuit structure with only two layers is limited in application flexibility and cannot achieve a good balance between area, power consumption and delay. The circuit structure designed by the present invention that can be expanded to any number of layers can customize the number of layers of the circuit and the scale of each layer, so as to meet different practical application requirements in terms of area, power consumption and delay.

[0048] Comparison of area, delay, and power consumption between hierarchical scalable structure and traditional tree structure: As can be seen from Table 1, the hierarchical scalable address event coding circuit designed in this scheme has a significant improvement in delay and area compared with the traditional binary number structure, which can reduce the delay by about 40% and the area by 50%, while the power consumption is only increased by about 19% at most. Therefore, this design is applied in neuromorphic chips, which can greatly improve the computing real-time performance of the chip and reduce the chip manufacturing cost.

[0049] Table 1 Comparison of area, delay and power consumption between hierarchical scalable structure and traditional tree structure

[0050]

[0051] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. An asynchronous scalable address event encoding circuit for a neuromorphic chip, characterized in that: The circuit includes a layered structure, each layer of the structure includes one or more expandable basic units, the input of each basic unit is a plurality of pulse signals, the basic unit includes an input cache, a control path and a data path, wherein the control path includes a merge connection module and a control AND gate, the data path includes a mask arbitrator, an encoder and two triggers, the two triggers are a second trigger and a third trigger, the mask arbitrator includes a first trigger, each basic unit is provided with an output address terminal and an output pulse terminal, one end of the merge connection module is connected to the control AND gate, and the other end is connected to the bus port and the output pulse terminal, and the Q end of the third trigger of the data path is connected to the output address terminal; The final output address terminal of the kth layer is connected to the address selector of the k+1th layer, and the output pulse terminal of the basic unit of the kth layer is connected to the input buffer of the basic unit of the k+1th layer.

2. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 1, characterized in that: The input buffer stores a plurality of input pulse signals.

3. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 2, characterized in that: The input end of the mask arbitrator is connected to the output end of the input buffer, the output end of the mask arbitrator is connected to the input end of the encoder and the D end of the second trigger, and the output end of the encoder is connected to the D end of the third trigger.

4. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 3, characterized in that: The merging and connecting module is provided with a trigger signal output terminal, and the trigger signal output terminal is connected to the clock signal input terminals of the first trigger, the second trigger and the third trigger.

5. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 4, characterized in that: The Q terminal and the output pulse terminal of the second trigger are commonly connected to the input terminal of the address AND gate, and the output terminal of the address AND gate is connected to the control terminal of the input buffer.

6. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 3, characterized in that: The mask arbitrator includes two AND gate arrays, a selector and a first trigger, and the two AND gate arrays are a first AND gate array and a second AND gate array.

7. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 6, characterized in that: The input end of the first AND gate array is connected to the output end of the input buffer, the output end of the input buffer and the output end of the first AND gate array are connected to the input end of the selector, the output end of the selector is connected to the input end of the mask generation module, the output end of the mask generation module and the input end of the mask generation module are input into the second AND gate array together, the output end of the second AND gate array is connected to the input end of the encoder, the output end of the mask generation module is also connected to the D end of the first trigger, and the Q end of the first trigger is connected to the input end of the first AND gate array.

8. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 7, characterized in that: The mask generation module outputs a mask signal, the 0th bit of the mask signal is 0, and the nth bit is obtained by performing an OR operation on the n-1th bit of the mask signal and the signal at the input end of the mask generation module, where n is greater than or equal to 1.

9. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 8, characterized in that: The selection signal output end of the basic unit of the k+1th layer is connected to the address selector of the k+1th layer and the address trigger of the k+1th layer, where k is greater than or equal to 1, and the selection signal output end is connected to the output end of the second AND gate array.

10. The asynchronous scalable address event encoding circuit for a neuromorphic chip according to claim 9, characterized in that: The trigger signal output end of the basic unit of the k+1th layer is connected to the clock signal input end of the address trigger, the D end of the address trigger is connected to the output end of the address selector of the k+1th layer, and the Q end of the address trigger and the output address end of the basic unit of the k+1th layer are connected together to the final output address end of the k+1th layer.

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