An encoder, encoding method and chip

Abstract

The application discloses an encoder, an encoding method and a chip, relates to the technical field of encoding, and discloses the following technical scheme: in the scene of large bandwidth and high parallelism input, a feedback loop in the encoder cannot produce a technical defect that cannot converge in time sequence. The encoder comprises a feedforward module, which is used for receiving to-be-encoded data with a parallelism of n symbols per beat, and calculating a single-beat polynomial corresponding to a current beat in a finite field according to symbols in the to-be-encoded data received in the current beat. A feedback module is used for receiving the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculating a second polynomial in a finite field according to the single-beat polynomial corresponding to the current beat and a first polynomial representing symbols received in historical beats, wherein the second polynomial is used for determining a target polynomial representing to-be-encoded data, the target polynomial is used for generating a check sequence of the to-be-encoded data, and thus a codeword obtained after the to-be-encoded data is encoded by a forward error correction encoding mode is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of coding, and particularly relates to an encoder, a coding method and a chip. BACKGROUND

[0002] In a data communication scenario based on Ethernet, to ensure the reliability of data transmission, a data sending end can use a forward error correction (FEC) technology to encode the to-be-transmitted data. The FEC is an error control technology, and the FEC can self-correct and recover the data when an error occurs in the data transmission process.

[0003] With the development of information technologies such as cloud computing, big data, artificial intelligence and the Internet of Things, the global data scale is currently growing explosively. To improve the transmission efficiency of data, when the to-be-transmitted data is encoded by using the FEC, an encoder receives symbols of the to-be-encoded data in parallel to implement the FEC encoding of the to-be-encoded data.

[0004] However, when the parallelism of the symbols in the to-be-encoded data input to the encoder is large, the feedback loop in the current encoder can have a technical risk that the timing cannot converge. SUMMARY

[0005] The present application provides an encoder, a coding method and a chip. In the scenario of large bandwidth and high parallelism input, the feedback circuit in the encoder will not have a technical defect that the timing cannot converge.

[0006] To achieve the above purpose, the present application provides the following technical solutions:

[0007] In a first aspect, an encoder is provided. The encoder includes a feedforward module configured to receive data to be encoded at a parallelism of n (n is a positive integer) symbols per slot, and to calculate, in a finite field, a single-slot polynomial corresponding to a current slot based on symbols of the data to be encoded received in the current slot. The single-slot polynomial represents the symbols received by the feedforward module in the current slot. The encoder also includes a feedback module configured to receive the single-slot polynomial corresponding to the current slot output by the feedforward module, and to calculate, in the finite field, a second polynomial based on the single-slot polynomial corresponding to the current slot and a first polynomial representing symbols received in historical slots. The second polynomial represents the symbols received from a first slot to the current slot, and the second polynomial is used to determine a target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence of the data to be encoded, the check sequence of the data to be encoded is used to perform check error correction on the data to be encoded, and a codeword of the data to be encoded encoded in a forward error correction encoding manner includes the data to be encoded and the check sequence of the data to be encoded. In addition, the first slot is a first slot at which the feedforward module receives the data to be encoded, and the historical slots are slots between the current slot and slots at which the feedforward module receives the data to be encoded.

[0008] When the encoder is used to encode, the target polynomial representing the data to be encoded is calculated by the feedforward module and the feedback module in the encoder. When the encoder calculates the target polynomial representing the data to be encoded by the feedforward module and the feedback module, the feedforward circuit calculates the corresponding single-slot polynomial based on the symbols received in each slot, and the feedback module calculates the target polynomial representing the data to be encoded by iteratively calculating the single-slot polynomial output by the feedforward module at least once. It can be seen that the feedback module is independent of the number of symbols of the data to be encoded input to the feedforward module per slot (i.e., the parallelism), or it can be understood that the feedback module is decoupled from the parallelism of the data to be encoded input to the feedforward module. In this way, in a large bandwidth scenario, even if the parallelism of the data to be encoded input to the encoder is large, the amount of calculation of the feedback module will not increase with the increase of the parallelism, so that the feedback module will not have a technical problem of time sequence not being able to converge.

[0009] In a possible design, the data to be encoded includes K symbols, and K is a positive integer. When a length of a codeword of the data to be encoded encoded in a forward error correction encoding manner is N, and N is an integer greater than K, the encoder includes N-K polynomial evaluation modules, each of which includes the feedforward module and the feedback module. The N-K polynomial evaluation modules are configured to calculate, in a finite field, N-K target polynomials representing the data to be encoded by the feedforward module and the feedback module in each of the N-K polynomial evaluation modules.

[0010] In another possible design, when the code word length obtained after the to-be-encoded data is encoded in the forward error correction manner is N+AN, the encoder comprises N+AN-K polynomial evaluation modules, each of which comprises the feedforward module and the feedback module. The N+AN-K polynomial evaluation modules are configured to calculate N+AN-K target polynomials representing the to-be-encoded data in the finite field through the feedforward module and the feedback module in each of the polynomial evaluation modules. The N+AN-K polynomial evaluation modules comprise the N-K polynomial evaluation modules.

[0011] For an RS(N, K) code type with a code word length of N and a payload length of K, the error correction capability is (N-K) / 2. For an RS(N+AN, K) code type with a code word length of N+AN and a payload length of K, the error correction capability is (N+AN-K) / 2. Therefore, through the above two possible designs, the encoder provided in this application can reuse the polynomial evaluation modules in the encoder of the RS code type with a lower error correction capability when the polynomial evaluation modules in the encoder of the RS code type with a higher error correction capability are used to encode the RS code type with a lower error correction capability. That is, through the design of the encoder provided in this application, the encoder of the RS code type with a higher error correction capability and the encoder of the RS code type with a lower error correction capability can share common (i.e., reused) polynomial evaluation modules, thereby greatly saving the circuit area and power consumption in actual module implementation. The error correction capability when the encoded code word length is (N+AN) is (N+AN-K), and the error correction capability when the encoded code word length is N is N-K.

[0012] In another possible design, the encoder further comprises a constant coefficient multiplication and addition module configured to calculate a check sequence of the to-be-encoded data according to the constant coefficient matrix and the target polynomials. The merging module is configured to merge the to-be-encoded data and the check sequence of the to-be-encoded data to obtain the code word obtained after the to-be-encoded data is encoded in the forward error correction manner.

[0013] In another possible design, when the code word length obtained after the to-be-encoded data is encoded in the forward error correction manner is N, the constant coefficient matrix is a first constant coefficient matrix of (N-K)×(N-K). When the code word length obtained after the to-be-encoded data is encoded in the forward error correction manner is N+AN, the constant coefficient matrix is a second constant coefficient matrix of (N+AN-K)×(N+AN-K). The second constant coefficient matrix comprises the first constant coefficient matrix.

[0014] By the above possible design, the preset constant coefficient matrix (the second constant coefficient matrix) in the encoder with high error correction capability includes the preset constant coefficient matrix (the second constant coefficient matrix) in the encoder with low error correction capability. In this way, the encoder with high error correction capability and the encoder with low error correction capability provided in the application can share a module constructed based on the same coefficient matrix, so that the encoder provided in the embodiments of the application can not only implement encoding of forward error correction codes with different error correction capabilities, but also save circuit area and power consumption of the encoder.

[0015] In another possible design, the encoder supports encoding of at least one forward error correction code type, and each of the at least one forward error correction code type has different error correction capability.

[0016] By this possible design, the encoder provided in the embodiments of the application is a fusion encoder capable of supporting forward error correction encoding of multiple error correction capability code types.

[0017] In another possible design, when the value of n is greater than a threshold value, the feedforward module includes a register. The register is configured to control the feedforward module to complete calculation of one single-tap polynomial through at least two clock cycles.

[0018] By this possible design, it can be ensured that the feedforward module of the encoder provided in the application completes calculation of one single-tap polynomial through at least two clock cycles. That is, in a large bandwidth scenario, even if the parallelism of the to-be-encoded data input to the encoder is large, the encoder provided in the application can still complete forward error correction encoding.

[0019] In another possible design, when a length of a code word obtained by encoding the to-be-encoded data in an error correction encoding manner is N, and a root of a primitive polynomial of a finite field is α, the first constant coefficient matrix is calculated in advance based on the following formula:

[0020]

[0021] In another possible design, the feedback module is specifically configured to, when the first polynomial is A1, and a polynomial representing a symbol received in a current tap is A 2a , calculate a second polynomial A2 through the following formula: A2=A1×(α i ) n +A 2a ; where α i is a root of a generating polynomial in a finite field, and i is an integer in [0, N-K-1].

[0022] It can be seen from the possible design that the feedback module in the encoder provided by the present application is irrelevant to the parallelism of the input data to be encoded, i.e., the two are decoupled, and thus the length of the feedback module is fixed and will not become longer due to the increase of the parallelism of the input data to be encoded. Therefore, in the scenario of large bandwidth and high input parallelism, the feedback module in the encoder provided by the present application will not have the problem of being unable to converge in time.

[0023] In a second aspect, the present application provides an encoding method, which is applied to an encoder. The encoder includes a feedforward module and a feedback module. The method includes: receiving, by the feedforward module, data to be encoded in parallel with n (n is a positive integer) symbols per beat, and calculating, in a finite field, a single-beat polynomial corresponding to a current beat according to the symbols in the data to be encoded received in the current beat. Here, the single-beat polynomial represents the symbols received by the feedforward module in one beat. Receiving, by the feedback module, the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculating, in the finite field, a second polynomial according to the single-beat polynomial corresponding to the current beat and a first polynomial representing the symbols received in historical beats. The second polynomial represents the symbols received from the first beat to the current beat, and is used to determine a target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence of the data to be encoded, the check sequence of the data to be encoded is used to check and correct errors of the data to be encoded, and a codeword obtained by encoding the data to be encoded in a forward error correction encoding manner includes the data to be encoded and the check sequence of the data to be encoded. In addition, the first beat is the first beat at which the feedforward module receives the data to be encoded, and the historical beats are the beats between the current beat in the process in which the feedforward module receives the data to be encoded.

[0024] In another possible design, the data to be encoded includes K symbols, K is a positive integer. When the length of a codeword obtained by encoding the data to be encoded in a forward error correction encoding manner is N, and N is an integer greater than K, the encoder includes N-K polynomial evaluation modules, each of which includes the feedforward module and the feedback module. And the N-K polynomial evaluation modules are used to calculate, in a finite field, N-K target polynomials representing the data to be encoded by the feedforward module and the feedback module in each of the N-K polynomial evaluation modules.

[0025] In another possible design, when the length of a codeword obtained by encoding the data to be encoded in a forward error correction encoding manner is N+ΔN, the encoder includes N+ΔN-K polynomial evaluation modules, each of which includes the feedforward module and the feedback module. And the N+ΔN-K polynomial evaluation modules are used to calculate, in a finite field, N+ΔN-K target polynomials representing the data to be encoded by the feedforward module and the feedback module in each of the N+ΔN-K polynomial evaluation modules. The N+ΔN-K polynomial evaluation modules include the N-K polynomial evaluation modules.

[0026] In another possible design, the method further includes: determining the second polynomial as the target polynomial when it is determined that the current beat is the K / n beat at which the to-be-encoded data is received. A check sequence of the to-be-encoded data is calculated according to the constant coefficient matrix and the target polynomial. The to-be-encoded data and the check sequence of the to-be-encoded data are merged to obtain a codeword after the to-be-encoded data is encoded in the forward error correction manner. It should be understood that if the current beat is the K / n beat at which the to-be-encoded data is received by the encoder, it indicates that the payload of a codeword has been completely input. Correspondingly, if the current beat is not the K / n beat at which the to-be-encoded data is received by the encoder, it indicates that the payload of a codeword has not been completely input.

[0027] In another possible design, when the length of the codeword obtained after the to-be-encoded data is encoded in the forward error correction manner is N, the constant coefficient matrix is a first constant coefficient matrix of (N-K) x (N-K). When the length of the codeword obtained after the to-be-encoded data is encoded in the forward error correction manner is N+ΔN, the constant coefficient matrix is a second constant coefficient matrix of (N+ΔN-K) x (N+ΔN-K). The second constant coefficient matrix includes the first constant coefficient matrix.

[0028] In another possible design, the encoder supports encoding of at least one type of forward error correction code, and each type of the at least one type of forward error correction code has different error correction capability.

[0029] In another possible design, when the value of n is greater than a threshold, the method further includes: controlling the feedforward module to complete calculation of a single-beat polynomial through at least two clock cycles, by using a register inserted in the feedforward module.

[0030] It should be understood that the descriptions of the beneficial effects of the second aspect and any possible design of the second aspect can refer to the descriptions of the beneficial effects of the first aspect and any possible design of the first aspect, and will not be repeated here.

[0031] In a third aspect, the present application provides an encoding apparatus. In a possible design, the encoding apparatus is used to execute any method provided in the second aspect. The present application can divide the encoding apparatus into functional modules according to any method provided in the second aspect. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. For example, the present application can divide the malicious domain name determination apparatus into a receiving unit and a calculating unit according to functions. The possible technical solutions and beneficial effects of the above-mentioned division of each functional module can refer to the technical solutions and beneficial effects provided in the second aspect or the corresponding possible design, which will not be repeated here.

[0032] In a fourth aspect, the present application provides a chip, comprising an encoding circuit, configured to perform any of the methods provided in the second aspect and any possible implementation manner thereof, so as to encode the to-be-encoded data in a forward error correction coding manner.

[0033] In a fifth aspect, the present application provides a computer readable storage medium, comprising program instructions, when the program instructions are executed on a computer or a processor, causing the computer or the processor to perform any of the methods provided in any possible implementation manner of the second aspect.

[0034] In a sixth aspect, the present application provides a computer program product, when executed on an encoding device, causing any of the methods provided in any possible implementation manner of the second aspect to be performed.

[0035] In the present application, the names of the above-mentioned encoders, encoding devices, encoding circuits and the like do not constitute a limitation on the devices or functional modules themselves, and in actual implementation, these devices or functional modules can appear with other names. As long as the functions of each device or functional module are similar to those of the present application, they belong to the scope of the claims of the present application and equivalent technologies thereof. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A schematic diagram of a current encoding circuit;

[0037] Figure 2 A schematic diagram of another current encoding circuit;

[0038] Figure 3 An application scenario diagram provided by an embodiment of the present application;

[0039] Figure 4 An application schematic diagram of the FEC encoding technology provided by an embodiment of the present application in an Ethernet architecture;

[0040] Figure 5 Another application schematic diagram of the FEC encoding technology provided by an embodiment of the present application in an Ethernet architecture;

[0041] Figure 6 An architecture schematic diagram of an encoding system provided by an embodiment of the present application;

[0042] Figure 7 A structure schematic diagram of a general-purpose computer provided by an embodiment of the present application;

[0043] Figure 8 A schematic diagram of an encoder provided by an embodiment of the present application;

[0044] Figure 9A circuit structure schematic diagram of a feedforward circuit provided for an embodiment of the present application;

[0045] Figure 10 A structure schematic diagram of a feedforward circuit and a feedback circuit provided for an embodiment of the present application;

[0046] Figure 11 A structure schematic diagram of an encoder provided for an embodiment of the present application;

[0047] Figure 12 Another structure schematic diagram of an encoder provided for an embodiment of the present application;

[0048] Figure 13 Another structure schematic diagram of an encoder provided for an embodiment of the present application;

[0049] Figure 14 A schematic diagram of a feedforward circuit provided for an embodiment of the present application;

[0050] Figure 15 A relationship schematic diagram of a polynomial set representing a payload under different code word lengths provided for an embodiment of the present application;

[0051] Figure 16 Another schematic diagram of an encoder provided for an embodiment of the present application;

[0052] Figure 17 A relationship schematic diagram of a constant coefficient set under different code word lengths provided for an embodiment of the present application;

[0053] Figure 18 Another structure schematic diagram of an encoder provided for an embodiment of the present application;

[0054] Figure 19 A structure schematic diagram of an encoder supporting multi-code type fusion encoding provided for an embodiment of the present application;

[0055] Figure 20 A flow schematic diagram of an encoding method provided for an embodiment of the present application;

[0056] Figure 21 A schematic diagram of a constant coefficient matrix of an RS (544, 514, 15, 10) code type provided for an embodiment of the present application;

[0057] Figure 22 A structure schematic diagram of an encoding apparatus provided for an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to more clearly understand the embodiments of the present application, part of the terms or technologies involved in the embodiments of the present application are described as follows:

[0059] 1) Forward error correction (FEC)

[0060] FEC, also known as forward error correction coding, is an error control technique.

[0061] FEC is widely used in communication systems to ensure the accuracy of transmitted data. The basic idea of FEC is to add a check sequence of a certain length to the data to be sent at the sending end, thereby obtaining a codeword after FRC coding of the data to be sent. Obviously, the codeword after FRC coding is composed of the data to be sent and the check sequence. After the FRC coded codeword is transmitted to the receiving end, if the error of the data is within the range of the check sequence that can be corrected, the receiving end corrects the error according to the check sequence obtained after decoding. In this way, the error rate of the data can be reduced, and the reliability of the communication system can be improved.

[0062] Common encoding types of FEC include, but are not limited to, the following: Reed Solomon code (RS code), hamming code, low-density parity-check code, etc.

[0063] Taking RS code as an example, a specific implementation scheme of RS code FEC technology is a linear block cyclic code. RS code can correct both random errors and burst errors, and is also commonly referred to as RS FEC.

[0064] Among them, the cyclic code includes but is not limited to RS code, cyclic redundancy check (CRC) code, Bose-Chaudhuri-Hocquenghem codes (BCH), fire code, etc. The basic unit constituting the cyclic code codeword is called a symbol. Therefore, the basic unit of RS code encoding and decoding calculation is also a symbol. Usually, a symbol contains m bits, and m is an integer greater than or equal to 1. It should be understood that when m = 1, the symbol and the bit have the same meaning. As an example, for BCH, CRC code, fire code, etc., m usually takes the value of 1. While for RS code, m usually takes a value greater than 1. Therefore, the basic unit of a cyclic code can be a bit, such as BCH, CRC, etc., or a symbol, such as RS code, etc.

[0065] Specifically, the length of an RS code word refers to the number of symbols contained in the RS code, and is usually denoted by the letter N. The payload length in an RS code word refers to the number of symbols contained in the payload in an RS code word, and is usually denoted by the letter K. Here, the payload in an RS code word refers to the original data information protected by the RS code. For example, the payload in an RS code word can be a message data to be transmitted in a communication network, and is not limited thereto. In addition, the redundancy length of an RS code word refers to the number of symbols contained in the check sequence in an RS code word, and is usually denoted by the letter R. Here, the symbols in the check sequence are also referred to as redundant symbols. Obviously, R=N-K.

[0066] For convenience of description, when the length of a code word of an RS code is N and the payload length is K, it can be denoted as RS(N, K) code. For example, the RS code type of KR4 is denoted as RS(528, 514), indicating that the length of a code word of the RS code is 528 and the payload length is 514. For another example, the RS code type of KP4 is denoted as RS(544, 514), indicating that the length of a code word of the RS code is 544 and the payload length is 514.

[0067] The error correction capability of an RS code refers to the maximum number of symbols that can be successfully corrected by an RS code word, and is usually denoted by T. For an RS code, the error correction capability T=(N-K) / 2 (i.e., half of the redundant symbols in an RS code word). For example, for the RS code type of KR4, the error correction capability T=(528-514) / 2=7, i.e., the maximum number of symbols that can be successfully corrected by an RS code word of the RS code type of KR4 is 7. For another example, for the RS code type of KP4, the error correction capability T=(544-514) / 2=15, i.e., the maximum number of symbols that can be successfully corrected by an RS code word of the RS code type of KP4 is 15.

[0068] In addition, the coding overhead of an FEC code refers to the ratio of the redundancy length to the payload length in an FEC code word. That is, the coding overhead of an FEC code is ((N-K) / K, or denoted as R / K.

[0069] The coding principle of a cyclic code will be briefly described below by taking the length of a code word of a cyclic code as N and the payload length as K as an example.

[0070] Here, the payload with the length of K can be represented as a polynomial M(x), which satisfies the following formula (1):

[0071] Formula (1) M(x)=mK -1 ·x K-1 +m K-2 ·x K-2 +…+m1·x+m0

[0072] Here, m represents the value of each symbol in the payload, and x represents the position of each symbol in the payload.

[0073] The preset generator polynomial of the cyclic code in the finite field is denoted as g(x), which satisfies the following formula (2):

[0074] Formula (2) g(x) = g N-K ·x N-K + g N-K-1 ·x N-K-1 + … + g1·x + g0

[0075] Here, g represents the coefficient of the generator polynomial, and x represents the position of each symbol in the check sequence.

[0076] Based on the polynomials shown in formula (1) and formula (2), the encoding process of the cyclic code can be implemented by dividing M(x) by g(x) to obtain the remainder p(x). Wherein, p(x) is the check sequence of the cyclic code. Thus, the code polynomial of a cyclic code satisfies the following formula (3):

[0077] Formula (3) x N-K ·M(x) = q(x)·g(x) + p(x)

[0078] Here, q(x) is the quotient of the division of M(x) by g(x).

[0079] Further, the code polynomial of the cyclic code can be denoted as C(x), and C(x) satisfies the following formula (4):

[0080] Formula (4) C(x) = x N-K ·M(x) + p(x)

[0081] In this way, the check sequence p(x) in the cyclic code can be calculated according to formula (4) as shown in formula (5). Wherein, MOD is the modulo operation.

[0082] Formula (5) p(x) = (x N-K ·M(x)) MOD g(x)

[0083] Thus, the check sequence p(x) of the payload data is obtained, and the payload and the check sequence are combined to obtain the encoded code word.

[0084] It should be noted that the calculation of the polynomials in the above encoding principle is the calculation of the polynomials in the finite field.

[0085] The finite field is also called Galois field, which is a field containing only a finite number of elements, and can be represented by GF(2 m ). Here, 2 mrepresents an element in a finite field, and m is a positive integer. The addition of a polynomial in a finite field is to combine like terms and perform an exclusive or operation on the coefficients, such as x 4 +x 4 = 0. The subtraction in a finite field is equal to addition, and there is no negative number in a finite field. For example, x 4 -x 4 is equal to x 4 +x 4 , and -x 3 is x 3 .

[0086] Further, the code type of the RS code can also be represented by RS(N, K, T, m). Wherein, N is the code length of the RS code word, K is the payload length in the RS code word, T is the error correction capability of the RS code, and m is used to indicate the finite field for RS encoding calculation.

[0087] 2) feedforward circuit, feedback circuit

[0088] In the embodiments of the present application, when the signal output by the circuit at t1 time does not affect the signal output at t2 time in the time domain, the circuit is called feedforward circuit. When the signal output by the circuit at t1 time affects the signal output at t2 time in the time domain, the circuit is called feedback circuit. Wherein, t2 time is a certain time after t1 time. For example, t1 time is the time before t2 time.

[0089] 3) beat

[0090] The "beat" described in the embodiments of the present application refers to a beat, and the "beat" and "beat" in the embodiments of the present application can be replaced with each other.

[0091] Generally, one clock cycle is defined as one beat.

[0092] 4) parallelism

[0093] The parallelism described in the embodiments of the present application refers to the number of symbols of the to-be-encoded data allowed to be input to the encoder / coding circuit in parallel in one beat when the to-be-encoded data is input to the encoder / coding circuit. For example, when the parallelism of the to-be-encoded data input to the encoder / coding circuit is n, it means that n symbols of the to-be-encoded data are allowed to be input to the encoder / coding circuit in parallel in one beat.

[0094] When the parallelism of the input data to the encoder / coding circuit is n and the number of symbols included in the input data is K, K symbols of the input data can be input to the encoder / coding circuit in K / n beats. The specific value of K / n is the integer value of the quotient of K / n. For example, when K is 10 and n is 4, the value of K / n is the integer value of the quotient of 10 / 4 (i.e. 2.5), which is 3.

[0095] In this way, in the scenario where the parallelism of the input data to the encoder / coding circuit is n and the number of symbols included in the input data is K, assuming that K is divisible by n, in the first beat, the first to the n-th symbols of the K symbols are allowed to be input to the encoder / coding circuit in parallel; in the second beat, the (n+1)-th to the 2n-th symbols of the K symbols are allowed to be input to the encoder / coding circuit in parallel; and so on, in the [K / n]-th beat, the (K-n+1)-th to the K-th symbols are allowed to be input to the encoder / coding circuit in parallel.

[0096] 5), other terms

[0097] In the embodiments of the present application, the terms "first" and "second" do not represent a sequential relationship, but are used to distinguish different objects. The first, second, etc. mentioned in the following documents are also used to distinguish different messages, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

[0098] It should also be understood that in various embodiments of the present application, the size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0099] Currently, when FEC encoding is used for the to-be-transmitted data, since the essence of the cyclic code encoding process is a polynomial division calculation process, the encoding circuit can be implemented as the circuit shown in FIG. 10. As shown in FIG. 10, taking a cyclic code RS(N, K) code as an example, the circuit 10 can receive K payload symbols in series through K clock cycles. During the input of the K payload symbols, the selector points to "1", so that the K payload symbols input to the circuit 10 are output in series through the selector in K clock cycles, and at the same time, the K payload symbols are input to the circuit 10 to be operated by the multiplier and the adder in the circuit 10. When the K payload symbols are input completely through K clock cycles, the values stored in the N-K registers in the circuit 10 are the symbols of the check sequence. At this time, the selector is switched to 0, and the circuit 10 will output the symbols of the check sequence in series through N-K clock cycles, so that a complete RS code word (including K payload symbols and N-K check sequence symbols) can be obtained. Figure 1 Figure 1 Currently, when FEC encoding is used for the to-be-transmitted data, since the essence of the cyclic code encoding process is a polynomial division calculation process, the encoding circuit can be implemented as the circuit shown in FIG. 10. As shown in FIG. 10, taking a cyclic code RS(N, K) code as an example, the circuit 10 can receive K payload symbols in series through K clock cycles. During the input of the K payload symbols, the selector points to "1", so that the K payload symbols input to the circuit 10 are output in series through the selector in K clock cycles, and at the same time, the K payload symbols are input to the circuit 10 to be operated by the multiplier and the adder in the circuit 10. When the K payload symbols are input completely through K clock cycles, the values stored in the N-K registers in the circuit 10 are the symbols of the check sequence. At this time, the selector is switched to 0, and the circuit 10 will output the symbols of the check sequence in series through N-K clock cycles, so that a complete RS code word (including K payload symbols and N-K check sequence symbols) can be obtained.​

[0100] However, encoding data by serially inputting it into the encoder is too inefficient. Therefore, in practical implementations of cyclic code encoding, a parallel input encoding architecture is often used. That is, multiple payload symbols are input to the encoding circuit simultaneously to improve encoding efficiency. Common parallel bit widths are 40 bits, 80 bits, and 160 bits. Therefore, with a parallel bit width of 40 bits, four 10-bit payload symbols can be input to the encoding circuit simultaneously. With a parallel bit width of 80 bits, eight 10-bit payload symbols can be input simultaneously. With a parallel bit width of 160 bits, sixteen 10-bit payload symbols can be input simultaneously.

[0101] Existing cyclic codes (such as RS code and BCH code) typically use Figure 1 The circuit structure shown is an encoding circuit using a linear feedback shift register (LFSR). Based on this circuit, a parallel encoding computation circuit can be derived for high-bandwidth scenarios. As an example, according to... Figure 1 From the circuit structure shown, it can be deduced that when there are 32 symbols in parallel input encoding circuit, the data calculation in the encoding circuit satisfies the following formula (6):

[0102] Formula (6)

[0103] Where REGicurrent represents the current value of the i-th register, and REGinext represents the value of the i-th register in the next clock cycle. Dj represents the j-th data currently input, where i = 1, 2, 3, ..., 14 (i.e., the number of symbols in the parity sequence); j = 1, 2, 3, ..., 32 (i.e., the parallelism). G is a 14×14 constant coefficient matrix, which can be represented as the following matrix (1). H' is a 14×18 constant coefficient matrix, which can be represented as the following matrix (2).

[0104] Matrix (1)

[0105] Matrix (2)

[0106] Furthermore, for RS(528,514) encoding, when the payload is input to the encoding circuit in parallel with 32 symbols, the encoding circuit can be as follows: Figure 2 As shown. Figure 2 As shown, for the 32 symbols (including D1 to D32) input to the encoding circuit within one clock cycle, inputs D1 to D18... Figure 2The circuit 201 shown is used to perform the operation between the payload and the aforementioned constant coefficient matrix H'. D19 to D32 are added to the feedback value of the previous clock cycle and then fed into circuit 202 to perform the operation between the payload and the aforementioned constant coefficient matrix G. Furthermore, the operation results of the constant coefficient matrices H' (D1 to D18) and G (D19 to D32) are processed by 31 adders (e.g., via...). Figure 2 The block 203 shown includes 31 adders, which sum to output the operation results D1 to D32. The feedback value of the previous clock cycle refers to the result calculated based on D1 to D32 in the previous clock cycle. In other words, the operation result within one clock cycle serves as the feedback value for the next clock cycle. The loop used to obtain the feedback value is called the feedback loop.

[0107] It can be seen that for the input encoder payload of each clock cycle, the result of the coefficient matrix operation often needs to be cascaded through n-1 adders (i.e., the result of the previous adder is used as the input of the next adder). Here, n is the number of symbols in the parallel input payload, or the degree of parallelism. Therefore, the length of the feedback loop in the encoder is strongly correlated with the degree of parallelism of the encoder input payload symbols; that is, the larger the number of symbols in the encoder's parallel input payload, the more addition operations (n-1 addition operations) there are in the encoder's feedback loop, and thus the longer the feedback loop in the encoder. In this case, when the number of symbols in the parallel input payload is very large... Figure 2 The encoder circuit shown cannot complete n-1 addition operations within one clock cycle, which leads to a technical risk that the timing of the feedback loop in the encoder cannot converge.

[0108] Furthermore, for various FEC codes, such as the two RS FEC codes defined in the 802.3 standard: RS(528,514) and RS(544,514), the coefficients of the generator polynomials in the finite field are completely different, making it difficult to share the circuit resources (adders and multipliers) used to implement these two codes. Referring to Table 1, which shows the coefficient values ​​of the generator polynomials for RS(528,514) and RS(544,514) codes, as shown in Table 1, the 15 (i∈[0,15]) coefficients of the generator polynomial for RS(528,514) and the 31 (i∈[0,30]) coefficients of the generator polynomial for RS(544,514) are all different. Here, i is an integer. It should be understood that the coefficients of the generator polynomial are the same as the coefficient g in the polynomial (2) above.

[0109] Table 1

[0110]

[0111]

[0112] Based on this, the embodiment of the present application provides an encoder. When encoding, the encoder calculates a target polynomial representing the data to be encoded through a feedforward module and a feedback module in the encoder. The feedforward module is used to receive the data to be encoded with a parallel degree of n symbols per shot, and calculate a single-shot polynomial corresponding to the current shot in a finite field according to the symbols in the data to be encoded received in the current shot. The feedback module is used to calculate the target polynomial representing the data to be encoded according to the single-shot polynomial corresponding to the current shot received from the feedforward module, and a first polynomial representing the symbols received in the historical shot. In this way, the purpose of decoupling the feedback module in the encoder and the parallel degree of the data to be encoded input into the encoder is achieved. That is, even if the number of symbols per shot of the data to be encoded input into the encoder is large, the length of the feedback module will not be long, so that the feedback module will not have the technical problem of time sequence unable to converge.

[0113] Wherein, the data to be encoded can be data to be transmitted in a communication network, or data to be stored in a storage system (such as a distributed storage system), which is not limited. The single-shot polynomial is used to represent the symbols received by the feedforward module in one shot.

[0114] Reference Figure 3 , Figure 3 An application scenario diagram of the embodiment of the present application is shown. As shown in Figure 3 , the payload data to be encoded is input into the encoder provided by the embodiment of the present application with a parallel degree of n symbols per shot. Or it can be understood that the payload data to be encoded is input into the encoder provided by the embodiment of the present application with a parallel degree of n per shot. Therefore, the encoder performs forward error correction encoding on the payload data to be encoded, and outputs the code word of the encoded data, which includes the payload and the check sequence, and the payload is the data to be encoded. Further, the encoded code word can be transmitted or stored. It should be understood that, since the feedback module in the encoder provided by the embodiment of the present application will not have the technical risk of time sequence unable to converge, the encoder provided by the embodiment of the present application supports high parallel degree forward error correction encoding on the payload data to be encoded in a large bandwidth scenario.

[0115] Optionally, the process of encoding data by the encoder provided by the embodiment of the present application is generally applied to the media access control (MAC) sublayer and the physical layer (PHY) layer in the Ethernet architecture.

[0116] In one example, referring to Figure 4 , Figure 4 An application diagram of the FEC encoding technology provided by the embodiment of the present application in the Ethernet architecture is shown. As shown inFigure 4 As shown, Figure 4 A hierarchical architecture of Ethernet is shown. In the Ethernet architecture, MAC sublayer, physical coding sublayer (PCS) sublayer, physical medium attachment (PMA) sublayer, and physical medium dependent (PMD) sublayer are included according to functions. Among them, the PCS, PMA, and PMD constitute the PHY layer. The FEC encoding technology is applied to Figure 4 the MAC sublayer and the PHY layer of the Ethernet architecture as shown. For example, the CRC encoding is generally applied to Figure 4 the MAC sublayer of the Ethernet architecture as shown, and the RS encoding is generally applied to Figure 4 the PCS sublayer of the Ethernet architecture as shown, which will not be described again.

[0117] In another example, reference is made to Figure 5 , Figure 5 Another application of the FEC encoding technology provided by the embodiments of the present application in the Ethernet architecture is shown. As shown, Figure 5 the standard Ethernet architecture includes an application layer, a presentation layer, a session layer, a transport layer, a network layer, a data link layer, and a physical layer. Among them, the data link layer includes a MAC sublayer and a reconciliation sublayer, which is a special sublayer (equivalent to the top layer of the physical layer) responsible for handling MII signaling and MAC sublayer translation or mapping requirements. The physical layer includes a PCS sublayer, a PMA sublayer, and a PMD sublayer. The FEC encoding technology provided by the embodiments of the present application is applied to the physical layer and the MAC sublayer of the data link layer. For example, the RS encoder provided by the embodiments of the present application can be deployed in the PCS sublayer in the physical layer as shown. Figure 5

[0118] ​Optionally, the physical implementation of the above-mentioned encoder includes, but is not limited to, a chip, an integrated circuit, or a computing device or a computing equipment with computing processing capability, etc. As an example, the chip includes, but is not limited to, a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a programmable array logic (PAL) device, a generic array logic (GAL) device, a network card, a microcontroller unit (MCU), etc. The integrated circuit includes, but is not limited to, an application-specific integrated circuit (ASIC), etc. The computing equipment includes, but is not limited to, a general-purpose computer, a notebook computer, a tablet computer, etc.

[0119] The embodiment of the present application further provides an encoding system, which includes a controller and the encoder provided by the embodiment of the present application. The controller is configured to control the input of the symbols of the to-be-encoded data to the encoder in parallel. The encoder is configured to perform forward error correction encoding on the to-be-encoded data according to the received to-be-encoded data. The specific process can be referred to the description below, and will not be described here.

[0120] As an example, reference is made to Figure 6 , Figure 6 A schematic architecture of an encoding system 60 provided by the embodiment of the present application is shown. As shown in Figure 6 , the encoding system 60 includes a controller 610 and an encoder 620. The controller 610 controls the input of the symbols of the to-be-encoded data to the encoder 620 in parallel at a parallelism of n symbols per shot, where n is a positive integer. The encoder 620 performs forward error correction encoding on the to-be-encoded data according to the received to-be-encoded data, and outputs the encoded data. The specific process can be referred to the description below, and will not be described here.

[0121] Optionally, the controller and the encoder in the above-mentioned encoding system can be integrated in one device (such as a serdes chip (serdes is the abbreviation of SERializer (serializer) / DESerializer (deserializer))), or can be integrated in different devices, which is not limited. The device can be a chip, an integrated circuit, or a computing device or a computing equipment with computing processing capability, which is not limited. The detailed description of the "chip, integrated circuit, or computing device or computing equipment with computing processing capability" can be referred to the description above, and will not be described here.

[0122] In one example, the above-mentioned encoding system is implemented as an example by a general-purpose computer, referring to Figure 7 , Figure 7 A structure diagram of a general-purpose computer 70 is shown. As shown in Figure 7 , the general-purpose computer 70 includes a processor 710, a memory 720, an encoder 730, a network / communication interface 740, and a bus 750. The processor 710, the memory 720, the encoder 730, and the network / communication interface 740 are connected through the bus 750.

[0123] The processor 710 is the control center of the general-purpose computer 70, which can be a general-purpose central processing unit (CPU). The processor 710 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), artificial intelligence chips, data processing units (DPUs), etc.

[0124] As an example, the processor 710 includes one or more CPUs, such as the CPU 0 and the CPU 1 shown in Figure 7 .

[0125] In addition, the processor 710 is used to implement the controller function in the above-mentioned encoding system to control the parallel input of the to-be-encoded data to the encoder.

[0126] The memory 720 is used to store program instructions or data to be accessed by application processes. The processor 710 can execute the program instructions in the memory 720. As an example, the memory 720 can be used to store to-be-encoded data and encoded data.

[0127] The memory 720 includes a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memory. The volatile memory can be a read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), or flash memory, among others. The volatile memory can be a random access memory (RAM), which is used as the external cache. By way of example, and not limitation, many forms of RAM are available, for example, static RAM (SRAM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). The non-volatile memory can be a storage class memory (SCM), a solid state drive (SSD), a hard disk drive (HDD), or the like. The storage class memory may, for example, be a non-volatile memory (NVM), a phase-change memory (PCM), a persistent memory, or the like.

[0128] In one possible implementation, the memory 720 is independent of the processor 710. The memory 720 is connected with the processor 710 through the bus 750, for storing data, instructions, or program codes. For example, the processor 710 controls the input of the data to be encoded stored in the memory 720 to the encoder in parallel, and writes the data encoded by the encoder into the memory 720.

[0129] In another possible implementation, the memory 720 and the processor 710 are integrated together.

[0130] The encoder 730, i.e., the encoder in the above-mentioned encoding system, is configured to perform forward error correction encoding on the received data to be encoded and output the encoded codeword. The encoder will be described in detail below, and thus will not be described here.

[0131] The network / communication interface 740 is configured to connect the general-purpose computer 70 to other devices (e.g., a device configured to receive the encoded data) via a communication network, which can be an Ethernet network, a radio access network (RAN), a wireless local area network (WLAN), or the like. The network / communication interface 740 includes a receiving unit configured to receive data / packets and a sending unit configured to send data / packets.

[0132] The bus 750 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, a compute express link (CXL) bus, an extended industry standard architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, or the like. For ease of representation, Figure 7 Only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0133] It should be noted that Figure 7 The structure shown in the figure does not constitute a limitation on the general-purpose computer 70, except Figure 7 The general-purpose computer 70 includes more or fewer components than those shown in the figure, or combines some components, or has different component arrangements. Figure 7

[0134] The encoder provided in the embodiments of the present application will be described in detail below with reference to the accompanying drawings, taking the FEC encoding as an RS(N, K) code for example. Here, RS(N, K) means that the length of the encoded codeword is N and the length of the payload is K. Correspondingly, the length of the check sequence in the encoded codeword is N-K. N and K are both integers, and N is greater than K.

[0135] ​It should be understood that according to the definition of the RS (N, K) code, the RS encoded codeword C(x) satisfies the mathematical constraint of formula (4) described above. Therefore, the root a i Substituting formula (4) into formula (7), formula (7) can be obtained. Wherein, i ∈ [0, N-K-1].

[0136] Formula (7) C(a i ) = (a i ) N-K · M(a i ) + p(a i ) = 0, i = 0, 1, 2, …, N-K-1

[0137] It should also be understood that the polynomial operations described in the embodiments of the present application are all operations of polynomials in a finite field, and based on this, formula (8) can be obtained from formula (7) (a i ) N-K · M(a i ) + p(a i ) = 0:

[0138] Formula (8) p(a i ) = (a i ) N-K · M(a i ), i = 0, 1, 2, …, N-K-1

[0139] And as known from the above, the polynomial p(x) used to obtain the check sequence is the remainder of the division of the polynomial M(x) representing the payload by the generator polynomial g(x). Therefore, based on the polynomials (1) and (2) described above, the polynomial p(x) satisfies formula (9) as follows.

[0140] Formula (9) p(x) = p0+ p1x + p2x 2 + … + p N-K-1 x N-K-1

[0141] Therefore, the root a i of the generator polynomial in the finite field is brought into formula (9), and combined with formula (8), formula (10) as follows can be obtained. Wherein, i ∈ [0, N-K-1].

[0142] Formula 10

[0143] Further, (a 0 ) N-K in formula (10) is moved to the left side of formula (10), and the operation is converted into a matrix operation, and formula (11) as follows can be obtained:

[0144] Formula (11)

[0145]

[0146]

[0147] After matrix operation of formula (11), the following formula (12) is obtained:

[0148] Formula (12)

[0149] On the basis of formula (12), symbols Θ, Φ and Ω are introduced, and when RS(N, K) encoding is implemented, Θ N,K satisfies formula (13), Φ N,K satisfies formula (14), and Ω N,K satisfies formula (15):

[0150] Formula (13)

[0151] Formula (14)

[0152] Formula (15)

[0153] It can be seen that in the RS(N, K) code type, Θ N,K represents a set of (N-K) 2 constant coefficients, Φ N,K represents a set of polynomials of the payload in the RS code word, and Ω N,K represents the check sequence in the RS code word. And according to formula (12), formula (13), formula (14) and formula (15), Θ N,K , Φ N,K and Ω N,K satisfy the mathematical constraint relationship Ω N,K = Θ N,K × Φ N,K .

[0154] Therefore, the process of calculating the check sequence in the RS code word in the RS encoding process can be converted into the process of calculating Θ N,K × Φ N,K . In specific implementation, corresponding modules are needed to realize Θ N,K and Φ N,K respectively. The specific implementation module of Φ N,K includes (N-K) modules for calculating the polynomial M(α i ) representing the payload (hereinafter referred to as polynomial evaluation module), i∈[0,N-K-1]. Θ N,K is then realized to calculate (N-K) 2 constant coefficients θj，1 θ j，2 θ j，3 , …, θ j，N-K , j = 1, 2, ..., NK.

[0155] Where M(α) i Let α be a polynomial representing the net charge in a finite field. i For the roots of the generating polynomial in the finite field, therefore α i Substituting into formula (1), we can obtain M(α) that satisfies formula (16). i ):

[0156] Formula (16) M(α) i ) = m K-1 ·(α i ) K-1 +m K-2 ·(α i ) K-2 +…+m1·(α i )+m0

[0157] Based on this, the polynomial M(α) used in the embodiments of this application will be used to calculate the net load. i The module that performs the evaluation of the polynomial is called the polynomial evaluation module. This module includes the feedforward module and the feedback module described above. Optionally, the feedforward module and the feedback module can be implemented using hardware circuits, or a combination of software and hardware circuits; there is no limitation on this. As an example, the feedforward module can be implemented using a feedforward circuit, and the feedback module can be implemented using a feedback circuit.

[0158] For simplicity, the embodiments of this application will be described below using the example of a feedforward module in the encoder being a feedforward circuit and a feedback module in the encoder being a feedback circuit. In this case, the polynomial evaluation module includes both a feedforward circuit and a feedback circuit; therefore, in the following text, the polynomial evaluation module will be referred to as a polynomial evaluation circuit.

[0159] refer to Figure 8 , Figure 8 A schematic diagram of an encoder provided in an embodiment of this application is shown. For example... Figure 8 As shown, the encoder 80 includes a feedforward circuit 810 and a feedback circuit 820.

[0160] The feedforward circuit 810 is configured to receive the data to be encoded with a parallelism of n symbols per shot. In this way, the feedforward circuit 810 can receive the data to be encoded through K / n shots. The data to be encoded (i.e. the payload data in the encoded codeword) includes K symbols, and n and K are positive integers, and K is greater than or equal to n. The value of K / n is the integer value of the quotient of K / n. Therefore, the K / nth shot of receiving the data to be encoded is the last shot of receiving the K symbols of the data to be encoded.

[0161] It should be understood that when the encoding of the data to be encoded including K symbols begins, the controller in the encoding system controls the data to be encoded to be input to the feedforward circuit 810 of the encoder 81 with a parallelism of n symbols per shot. The detailed description of the controller can be referred to the above description, and will not be repeated here. In response, the feedforward circuit 810 receives the data to be encoded with a parallelism of n symbols per shot, and receives the data to be encoded through K / n shots.

[0162] The feedforward circuit 810 is further configured to calculate a single-shot polynomial corresponding to the current shot based on the symbols in the data to be encoded received by the current shot. Here, the single-shot polynomial represents the symbols received by the feedforward module through one shot.

[0163] Specifically, the feedforward circuit 810 includes n multipliers configured to receive n symbols of the data to be encoded input to the feedforward circuit 810 with a parallelism of n. Based on formula (16), the n multipliers are respectively configured to multiply the received n symbols by the coefficients (α i ) u , and then sum the multiplication results through n-1 adders, so as to obtain a polynomial representing the n symbols input to the feedforward circuit 810 through one shot, denoted as a single-shot polynomial. Here, u ∈ [0, n-1].

[0164] It should be understood that the operation implemented by the feedforward circuit 810 is an operation in a finite field. Here, α i is a root of a generating polynomial used by the feedforward circuit 810 when performing the operation in the finite field, and i ∈ [0, N-K-1]. α is a root of a primitive polynomial in the finite field. Taking the finite field GF(2 10 ) as an example, the primitive polynomial in the finite field is x 10 +x 3 +1, and α is a root of the primitive polynomial, so that the value of α can be solved based on the primitive polynomial. Correspondingly, the value of α i can also be calculated.

[0165] Furthermore, based on the K symbols of the data to be encoded input to the feedforward circuit 810 in K / n cycles, the feedforward circuit can output K / n single-cycle polynomials in K / n cycles. That is, the feedforward circuit 810 can calculate the polynomial (i.e., single-cycle polynomial) representing the symbol received in each cycle in a finite field.

[0166] refer to Figure 9 , Figure 9 A schematic diagram of the circuit structure of a feedforward circuit provided in an embodiment of this application is shown. Figure 9 As shown, m represents the symbol in the data to be encoded.

[0167] like Figure 9 As shown, in the first cycle, the feedforward circuit 810 receives the first to nth symbols in the data to be encoded, which are m... K-1 m K-2 , ..., m K-n Among them, m K-1 Through the multiplier and the coefficient (α) i ) n-1 Multiplication, m K-2 Through the multiplier and the coefficient (α) i ) n-2 Multiplication, ..., m K-n Through the multiplier and the coefficient (α) i ) 0 Multiplying these n multipliers and summing the results of the multiplications using n-1 adders yields a single-phase polynomial representing the n symbols of the first input, i.e., the single-phase polynomial corresponding to the first phase, denoted as B. 1a .

[0168] Similarly, in the second pulse, the feedforward circuit 810 receives the (n+1)th to 2nth symbols in the data to be encoded, which are m... K-n-1 m K-n-2 , ..., m K-2n Among them, m K-n-1 Through the multiplier and the coefficient (α) i ) n-1 Multiplication, m K-n-2 Through the multiplier and the coefficient (α) i ) n-2 Multiplication, ..., m K-2n Through the multiplier and the coefficient (α) i ) 0 Multiply the results and sum the results of multiplication by n multipliers using n-1 adders to obtain a single-phase polynomial representing the n symbols of the second-phase input, i.e., the single-phase polynomial corresponding to the second phase, denoted as B. 2a .

[0169] Similarly, at the K / nth tap, the feedforward circuit 810 receives [(K / n)-1]x n+1~(K / n)x n symbols in the data to be encoded, respectively, m n-1 , m n-2 , …, m K-(K / n)×n , and m K-(K / n)×n , i.e., m0. Wherein, m n-1 is multiplied by a coefficient (a i ) n-1 , m n-2 is multiplied by a coefficient (a i ) n-2 , …, m0is multiplied by a coefficient (a i ) 0 , and the multiplication results of the n multipliers are summed by n-1 adders, so that the single-tap polynomial representing n symbols input at the K / nth tap, i.e., the single-tap polynomial corresponding to the K / nth tap, is obtained, denoted as B (K / n)a .

[0170] It should be understood that, in the process of inputting the data to be encoded with a parallel degree of n and a length of K symbols, the K / nth tap is the last tap. When the number of symbols (denoted as "last-tap payload symbol") in the data to be encoded input to the feedforward circuit 810 at the K / nth tap is less than n, the n symbols including the last-tap payload symbol can be input to the encoder by setting the last-tap payload symbol as the low-order symbol of the n symbols input at the K / nth tap, and filling the n symbols input at the K / nth tap with 0 except the bit for setting the last-tap payload symbol.

[0171] The feedback circuit 820 is configured to receive the single-tap polynomial corresponding to the current tap output by the feedforward circuit, and calculate a second polynomial in a finite field according to the single-tap polynomial corresponding to the current tap and a first polynomial representing the symbols received at the historical taps, the second polynomial representing the symbols received from the first tap to the current tap, and the second polynomial being used to determine the polynomial representing the data to be encoded. Here, the first tap refers to the first tap at which the feedforward circuit receives the data to be encoded, and the historical taps refer to the taps between the current tap in the process of receiving the data to be encoded by the feedforward circuit. As an example, assuming that the current tap is the 3rd tap in the process of receiving the data to be encoded, the historical taps include the 1st tap and the 2nd tap at which the data to be encoded is received. As another example, assuming that the current tap is the 5th tap in the process of receiving the data to be encoded, the historical taps include the 1st tap, the 2nd tap, the 3rd tap, and the 4th tap at which the data to be encoded is received.

[0172] Specifically, the feedback circuit 820 includes one adder and one multiplier. The implementation principle of the feedback circuit 820 is that, when the first polynomial is denoted as A1, the second polynomial is denoted as A2, and the single-tap polynomial representing the symbols received at the current tap is denoted as A 2aAt this time, the feedback circuit 820 is configured to calculate the second polynomial A2 by using the following formula (17):

[0173] Formula (17) A2=A1x(a i ) n +A 2a

[0174] It should be understood that the operation implemented by the feedback circuit 820 is an operation in a finite field. In the formula (17), a i is a root of a generating polynomial used by the feedback circuit 820 when performing the operation in the finite field, and i∈[0,N-K-1]. a is a root of a primitive polynomial in the finite field. The solution process of a can be referred to the description above, and will not be described herein again.

[0175] It should be noted that if the current shot is the K / n shot, and the number of the last shot payload symbols is less than the parallelism n, when calculating the second polynomial at the K / n shot, n in the formula (a i ) n is the number of the last shot payload symbols. For example, the parallelism n is 10, and the number of the payload symbols (i.e., the last shot payload symbols) input at the K / n shot is 2, and when calculating the second polynomial corresponding to the K / n shot, n in the formula (a i ) n is 2.

[0176] It can be seen that, although in terms of timing, the calculation result of the feedback circuit 820 at the current clock cycle participates in the operation in the next clock cycle, the length of the feedback circuit 820 is independent of the parallelism of the data to be encoded received by the feedforward circuit 810. In this way, even in a large bandwidth scenario, the parallelism of the data to be encoded input to the encoder is large, and the length of the feedback circuit in the encoder will not be affected. That is, the encoder provided in the embodiment of the present application decouples the parallelism of the data to be encoded input to the encoder and the length of the feedback circuit in the encoder, so that in a large bandwidth scenario, when the data to be encoded is input to the encoder with high parallelism, no technical problem of timing divergence can be caused. This is because the addition and multiplication operations required to be completed by the feedback circuit in the encoder provided in the embodiment of the present application can be completely completed in one clock cycle.

[0177] Further, the feedforward circuit 810 receives the data to be encoded through K / n-tap, thereby outputting K / n monomial polynomials, and the feedback circuit calculates a polynomial representing the data to be encoded according to each monomial polynomial output by the feedforward circuit 810 through (K / n)-1 iteration calculation, and the polynomial is recorded as a target polynomial. Further, the target polynomial is used to generate a check sequence of the data to be encoded, the check sequence of the data to be encoded is used to check and correct the data to be encoded, and a code word obtained by encoding the data to be encoded in a forward error correction coding mode comprises the data to be encoded and the check sequence of the data to be encoded.

[0178] In combination Figure 9 with Figure 10 , Figure 10 A structure schematic diagram of a feedforward circuit and a feedback circuit provided by an embodiment of the present application is shown.

[0179] As shown in Figure 10 , in the first tap, the feedback circuit 820 receives the monomial polynomial B 1a output by the feedforward circuit 810 representing n symbols input in the first tap. The feedback circuit 820 inputs 0 to the multiplier 1003 through the selector 1002. Then, the multiplier 1003 performs multiplication operation on 0 and the coefficient (α i ) n and outputs the multiplication result, and at this time, the result is 0. The adder 1001 performs addition operation on the result 0 output by the multiplier 1003 and the monomial polynomial B 1a output by the feedforward circuit 810, thereby obtaining a polynomial of the symbols input to the feedforward circuit 810 through the first tap, which is recorded as B 1b .

[0180] In the second tap, the feedback circuit 820 receives the monomial polynomial B 2a output by the feedforward circuit 810 representing n symbols input in the second tap. The feedback circuit 820 inputs the polynomial B 1b calculated by the feedback circuit 820 in the first tap to the multiplier 1003 through the selector 1002. It should be understood that the polynomial B 1b calculated by the feedback circuit 820 in the first tap is the calculation result calculated by the adder 1001 of the feedback circuit 820 in the first tap. Then, the multiplier 1003 performs multiplication operation on B 1b and the coefficient (α i ) n and outputs the multiplication result, and at this time, the result is B 1b ×(α i ) n . The adder 1001 performs addition operation on the result B 1b ×(α i ) nB = B + B x (α 2a . 1b ×(α i ) n +B 2a , denoted as B 2b .

[0181] Similarly, at the K / nth tap, the feedback circuit 820 receives the single-tap polynomial B (K / n)a output by the feedforward circuit 810 representing the n symbols input at the K / nth tap. The feedback circuit 820 inputs the polynomial B ((K / n)-1)b calculated by the feedback circuit 820 at the [(K / n)-1]th tap to the multiplier 1003 through the selector 1002. It should be understood that the polynomial B ((K / n)-1)b calculated by the feedback circuit 820 at the [(K / n)-1]th tap is the result output by the adder 1001 of the feedback circuit 820 at the [(K / n)-1]th tap. The multiplier 1003 multiplies B ((K / n)-1)b by the coefficient (α i ) n and outputs the multiplication result, which is B ((K / n)-1)b x (α i ) n at this time. The adder 1001 adds the result B ((K / n)-1)b x (α i ) n output by the multiplier 1003 to the single-tap polynomial B (K / n)a calculated by the feedforward circuit 810 for the n symbols input at the K / nth tap, thereby obtaining the polynomial B ((K / n)-1)b x (α i ) n + B (K / n)a , denoted as B (K / n)b at this time. B (K / n)b is the target polynomial mentioned above, which is output by the feedback circuit 820.

[0182] The feedforward circuit 810 and the feedback circuit 820 in the encoder 80 mentioned above constitute a polynomial evaluation circuit in the encoder 80.

[0183] It should be understood that one polynomial evaluation circuit includes a feedforward circuit 810 and a feedback circuit 820, and the feedforward circuit 810 and the feedback circuit 820 in the same polynomial evaluation circuit operate in the same finite field and use the same root of the generating polynomial when performing the finite field operation. In this way, through one polynomial evaluation circuit, a target polynomial of the data to be encoded input to the encoder 80 in a parallel manner can be calculated in the finite field.

[0184] To calculate the above Φ N,K In some embodiments, when the value of (N-K) is 1, the encoder 80 includes one polynomial evaluation circuit. And the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit when performing the finite field operation is α 0 .

[0185] In other embodiments, when the value of (N-K) is greater than 1, the encoder 80 includes (N-K) polynomial evaluation circuits. In this way, the (N-K) polynomial evaluation circuits are used to calculate (N-K) target polynomials representing the data to be encoded in the finite field through the feedforward circuit and the feedback circuit in each of the (N-K) polynomial evaluation circuits. Referring to Figure 11 , Figure 11 Another structure diagram of the encoder provided by the embodiments of the present application is shown.

[0186] As Figure 11 shown, the encoder 80 includes (N-K) polynomial evaluation circuits, which are polynomial evaluation circuit 0, polynomial evaluation circuit 1, …, polynomial evaluation circuit (N-K-2), and polynomial evaluation circuit (N-K-1). Among them, the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit 0 when performing the finite field operation is α 0 , the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit 1 when performing the finite field operation is α 1 , …, the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit (N-K-2) when performing the finite field operation is α N-K-2 , and the root of the generating polynomial used by the feedforward circuit and the feedback circuit in the polynomial evaluation circuit (N-K-1) when performing the finite field operation is α N-K-1 . In this way, the data to be encoded received by the K / n taps can be input to each of the (N-K) polynomial evaluation circuits in the encoder 80, so as to calculate and output the corresponding target polynomials.

[0187] For example, encoder 80 receives the data to be encoded in K / n cycles and inputs it sequentially into polynomial evaluation circuit 0. Polynomial evaluation circuit 0 then calculates the root of the generator polynomial α based on the data received in K / n cycles. 0 The objective polynomial M(α) at ​​time 0 ).

[0188] Similarly, the encoder 80 receives the data to be encoded via K / n beats and then sequentially inputs it into the polynomial evaluation circuit 1. The polynomial evaluation circuit 1 then calculates the root of the generator polynomial α based on the data received via K / n beats. 1 The objective polynomial M(α) at ​​time 1 ).

[0189] Similarly, the encoder 80 receives the data to be encoded via K / n beats and then sequentially inputs it into the polynomial evaluation circuit (NK-2). The polynomial evaluation circuit (NK-2) then calculates the root of the generator polynomial α based on the data received via K / n beats. N-K-2 The objective polynomial M(α) at ​​time N-K-2 ).

[0190] Similarly, the encoder 80 receives the data to be encoded via K / n beats and then sequentially inputs it into the polynomial evaluation circuit (NK-1). The polynomial evaluation circuit (NK-1) then calculates the root of the generator polynomial α based on the data received via K / n beats. N-K-1 The objective polynomial M(α) at ​​time N-K-1 ).

[0191] The polynomial evaluation circuit calculates the root α of the generator polynomial based on the data to be encoded received in K / n cycles. i The objective polynomial M(α) at ​​time i For a detailed explanation of ), please refer to the description above, which will not be repeated here.

[0192] Furthermore, after calculating (NK) target polynomials through (NK) polynomial evaluation circuits, in order to calculate the verification sequence of the data to be encoded through these (NK) target polynomials, reference is made to... Figure 12 , Figure 12 This illustration shows yet another structural diagram of the encoder provided in an embodiment of this application. For example... Figure 12 As shown, the encoder 80 also includes a constant coefficient multiply-accumulate module 1210 and a merging module 1220.

[0193] The constant coefficient multiply-add module 1210 is used to calculate the check sequence of the data to be encoded based on the constant coefficient matrix and the target polynomials representing the data to be encoded. Specifically, the constant coefficient multiply-add module 1210 is used to calculate the check sequence of the data to be encoded based on the constant coefficient matrix and (NK) target polynomials representing the data to be encoded.

[0194] Here, the constant coefficient matrix is ​​the matrix Θ described in formula (13) above. N,K Let be the first constant coefficient matrix, representing the (NK) objective polynomials of the data to be encoded, which is the Φ mentioned above. N,K Therefore, the constant coefficient multiply-accumulate module 1210 is based on Θ N,K and Φ N,K And the mathematical constraint relationship Ω mentioned above. N,K =Θ N,K ×Φ N,K Ω can be calculated N,K Ω N,K This is the verification sequence of the data to be encoded.

[0195] Specifically, such as Figure 12 As shown, when the data to be encoded is input to the encoder 80 with a parallelism of n, it is calculated by the (NK) polynomial evaluation circuits described above, and (NK) target polynomials are output [including M(α)]. 0 M(α) 1 M(α) N-K-2 M(α) N-K-1 After that, the constant coefficient multiply-add module 1210 receives the (NK) target polynomials and calculates the verification sequence of the data to be encoded based on the first constant coefficient matrix and the (NK) target polynomials.

[0196] For RS(N,K), the first coefficient matrix Θ N,K It is a matrix of size (NK)×(NK). Therefore, in the encoder implementing RS(N,K) encoding, a first constant coefficient matrix is ​​pre-set. Each coefficient in the first constant coefficient matrix is ​​pre-determined by formula (13). Since α is the root of the primitive polynomial in the finite field, when determining each coefficient in the first constant coefficient matrix, the root α can be solved based on the primitive polynomial of the finite field, and each coefficient in the first constant coefficient matrix can be determined according to α, constant N, constant K and formula (13). 10 For example, the primitive polynomial in this finite field is x. 10 +x 3 +1, so that the root α of the primitive polynomial can be solved based on the primitive polynomial. Then, based on the solved α, constant N, constant K and formula (13), each coefficient in the first constant coefficient matrix is ​​determined.

[0197] Further, based on the principle of matrix operation, the constant coefficient multiplication and addition module 1210 can be implemented by multiple sub-modules according to the above-mentioned mathematical constraint relationship Ω N,K = Θ N,K × Φ N,K . When Ω N,K is calculated, the constant coefficient multiplication and addition module 1210 includes (N-K) sub-modules, each of which is used to calculate a corresponding check value according to the coefficient corresponding to each sub-module and the (N-K) target polynomials (i.e., Φ N,K ) representing the data to be encoded. The (N-K) sub-modules obtain corresponding (N-K) check values, which constitute the check sequence of the data to be encoded.

[0198] In combination with Figure 11 and Figure 12 , reference is made to Figure 13 , Figure 13 to show another structure of the encoder provided by the embodiments of the present application. As shown in Figure 13 , the constant coefficient multiplication and addition module 1210 includes (N-K) sub-modules, i.e., sub-module 0, sub-module 1, …, sub-module (N-K-2), and sub-module (N-K-1). The sub-module 0 corresponds to the first row coefficients in the matrix Θ N,K shown in formula (13), i.e., θ 1,1 ~ θ 1,N-K , the sub-module 1 corresponds to the second row coefficients in the matrix Θ N,K shown in formula (13), i.e., θ 2,1 ~ θ 2,N-K , …, the sub-module (N-K-2) corresponds to the (N-K-1)th row coefficients in the matrix Θ N,K shown in formula (13), i.e., θ N-K-1,1 ~ θ N-K-1,N-K , and the sub-module (N-K-1) corresponds to the (N-K)th row coefficients in the matrix Θ N,K shown in formula (13), i.e., θ N-K,1 ~ θ N-K,N-K .

[0199] In this way, when the data to be encoded input to the encoder 80 through K / N shots and parallel degree n is calculated by the (N-K) polynomial evaluation circuits described above and (N-K) target polynomials [including M(α 0 ), M(α 1 ), …, M(α N-K-2 ), M(α N-K-1) and the (N-K) target polynomials (i.e. Φ N,K ), the corresponding check value p is calculated. Then, the (N-K) sub-modules obtain the corresponding (N-K) check values p, which constitute the check sequence of the data to be encoded.

[0200] For example, the encoder 80 sends the (N-K) target polynomials into the sub-module 0 of the constant coefficient multiplication-addition module 1210, and the sub-module 0 performs multiplication-addition operation on the coefficients θ 1,1 ~ θ 1,N-K and the (N-K) target polynomials, so as to obtain the check value p N-K-1 . Based on the mathematical constraint relationship Ω N,K = Θ N,K × Φ N,K , the formula (13) and the formula (14), the multiplication-addition operation is specifically the operation of [θ 1,1 × M(α 0 ) + θ 1,2 × M(α 1 ) + … + θ 1,N-K-1 × M(α N-K-2 ) + θ 1,N-K × M(α N-K-1 )].

[0201] Similarly, the encoder 80 sends the (N-K) target polynomials into the sub-module 1 of the constant coefficient multiplication-addition module 1210, and the sub-module 1 performs multiplication-addition operation on the coefficients θ 2,1 ~ θ 2,N-K and the (N-K) target polynomials, so as to obtain the check value p N-K-2 .

[0202] Similarly, the encoder 80 sends the (N-K) target polynomials into the sub-module (N-K-2) of the constant coefficient multiplication-addition module 1210, and the sub-module (N-K-2) performs multiplication-addition operation on the coefficients θ N-K-1,1 ~ θ N-K-1,N-K and the (N-K) target polynomials, so as to obtain the check value p1.

[0203] Similarly, the encoder 80 sends the (N-K) target polynomials into the sub-module (N-K-1) of the constant coefficient multiplication-addition module 1210, and the sub-module (N-K-1) performs multiplication-addition operation on the coefficients θ N-K,1 ~ θ N-K,N-K and the (N-K) target polynomials, so as to obtain the check value p0.

[0204] The combining module 1220 is configured to combine the to-be-encoded data and the check sequence of the to-be-encoded data, so as to obtain a code word of the to-be-encoded data after being encoded by the forward error correction coding mode.

[0205] Specifically, the combining module 1220 receives the check sequence of the to-be-encoded data calculated by the constant coefficient multiplication and addition module 1210, and receives the to-be-encoded data, and combines the to-be-encoded data and the check sequence of the to-be-encoded data, so as to obtain a code word of the to-be-encoded data after being encoded by the forward error correction coding mode. Then, the combining module 1220 outputs the code word including the payload and the check sequence. The payload of the code word is the to-be-encoded data, and the check sequence of the code word is the check sequence of the to-be-encoded data output by the constant coefficient multiplication and addition module 1210.

[0206] In this way, based on the encoder described above in the embodiments of the present application, when the to-be-encoded data input to the encoder in parallel is forward error correction coded, the feedback circuit in the encoder is decoupled from the parallelism when the to-be-encoded data is input to the encoder. Therefore, when the to-be-encoded data is input to the encoder provided in the embodiments of the present application at a high parallelism in a large bandwidth scenario, there is no technical problem of time sequence that cannot converge. This is because the addition and multiplication operations that the feedback circuit in the encoder provided in the embodiments of the present application needs to complete can be completely completed within one clock cycle.

[0207] However, the parallelism of the feedforward circuit in the encoder 80 when the to-be-encoded data is input to the encoder 80 is related, and therefore when the parallelism n of the to-be-encoded data input to the encoder 80 is greater than the threshold value, the feedforward circuit in the encoder 80 cannot complete the calculation of the single-tap polynomial within one clock cycle (or within one beat, or within one tact).

[0208] In this case, the feedforward circuit 810 of the encoder 80 described above further includes a register, which is configured to control the feedforward circuit 810 to complete the calculation of the polynomial representing n symbols of single-tap input (i.e., the single-tap polynomial) through at least two clocks, that is, the register is configured to control the feedforward circuit 810 to complete the calculation of one single-tap polynomial through at least two clocks. It should be understood that the insertion of one register in the feedforward circuit 810 can extend the length of one clock cycle for the feedforward circuit 810 to complete the calculation of one single-tap polynomial. The insertion of two registers in the feedforward circuit 810 can extend the length of two clock cycles for the feedforward circuit 810 to complete the calculation of one single-tap polynomial.

[0209] In a first possible implementation, when the feedforward circuit 810 is capable of completing the calculation of a single-tap polynomial through at least two clocks, the feedforward circuit 810 comprises at least one register for time delay and a plurality of sub-circuits, each of the plurality of sub-circuits is capable of completing the calculation within one clock cycle, and the number of sub-circuits in the feedforward circuit 810 is one more than the number of registers for time delay in the feedforward circuit 810. For example, when the feedforward circuit 810 comprises one register for time delay, the feedforward circuit 810 comprises two sub-circuits. For another example, when the feedforward circuit 810 comprises two registers for time delay, the feedforward circuit 810 comprises three sub-circuits. Thus, through the at least one register for time delay in the feedforward circuit 810, the feedforward circuit 810 is capable of completing the calculation of a single-tap polynomial through the pipelining of at least two sub-circuits within at least two clock cycles. Moreover, the last sub-circuit in the pipelining of the feedforward circuit 810 is connected to the feedback circuit 820 to output the single-tap polynomial to the feedback circuit. It should be understood that the working principle of the sub-circuit is the same as that of the feedforward circuit 810 described above, and thus will not be described again.

[0210] The implementation process of the first possible implementation is described below with the feedforward circuit 810 comprising one register and the parallel degree n of the input data to the encoder 80 being 4 as an example. Figure 10 , reference is made to Figure 14 , Figure 14 Another schematic diagram of the feedforward circuit is shown. The feedforward circuit 1400 is a feedforward circuit in which one register 1401 is inserted into the feedforward circuit 810 and n is 4. The feedforward circuit 1400 comprises a sub-circuit 1410 and a sub-circuit 1420, and the sub-circuit 1420 is the last sub-circuit in the pipelining of the feedforward circuit 1400, and thus the sub-circuit 1420 is connected to the feedback circuit.

[0211] It is assumed that the input data comprises 12 symbols, and the 12 symbols are m 11 , m 10 , m9, m8, m7, m6, m5, m4, m3, m2, m1 and m0. As shown in Figure 14 , the input data needs to be input to the feedforward circuit 1400 of the encoder through (K / n)+1 taps (i.e. (12 / 4)+1=4 taps).

[0212] In the first tap, the four symbols received by the feedforward circuit 1400 are m 11 , m 10 , 0 and 0. Among them, the sub-circuit 1410 receives m 11 , m 10Thus, result la is calculated and sent to sub-circuit 1420. Sub-circuit 1420 receives 0, 0 and calculates a result of 0 (or sub-circuit 1420 does not receive any symbol at the first clock). It should be noted that sub-circuit 1420 connected to the feedback circuit in feedforward circuit 1400 does not output a result at the first clock.

[0213] At the second clock, feedforward circuit 1400 receives four symbols m7, m6, m9, and m8. Sub-circuit 1410 receives m7, m6 and calculates result 2a, which is sent to sub-circuit 1420. Sub-circuit 1420 receives m9, m8 and calculates result lb. Sub-circuit 1420 then performs a summation operation on result lb calculated at the second clock and result la sent from sub-circuit 1410 at the first clock to sub-circuit 1420, and obtains result 1 at the second clock, which is output to the feedback circuit. It can be seen that result 1 is a single-tap polynomial representing m7, m6, m9, and m8, and result 1 is a result calculated by feedforward circuit 1400 in two clock cycles (the first and second clocks). In other words, at the second clock, sub-circuit 1420 in feedforward circuit 1400 outputs a single-tap polynomial representing m7, m6, m9, and m8 (i.e., result 1) to the feedback circuit. 11 10 11 10

[0214] Similarly, at the third clock, feedforward circuit 1400 receives four symbols m3, m2, m5, and m4. Sub-circuit 1410 receives m3, m2 and calculates result 3a, which is sent to sub-circuit 1420. Sub-circuit 1420 receives m5, m4 and calculates result 2b. Sub-circuit 1420 then performs a summation operation on result 2b calculated at the third clock and result 2a sent from sub-circuit 1410 at the second clock to sub-circuit 1420, and obtains result 2 at the third clock, which is output to the feedback circuit. It can be seen that result 2 is a single-tap polynomial representing m7, m6, m5, and m4, and result 2 is a result calculated by feedforward circuit 1400 in two clock cycles (the second and third clocks). In other words, at the third clock, sub-circuit 1420 in feedforward circuit 1400 outputs a single-tap polynomial representing m7, m6, m5, and m4 (i.e., result 2) to the feedback circuit.

[0215] ​​​​Similarly, in the 4th tap, the 4 symbols received by the feedforward circuit 1400 are 0, 0, m1, m0. Among them, the sub-circuit 1410 receives 0, 0, and thus the result calculated is actually 0, and 0 is sent to the sub-circuit 1420. The sub-circuit 1420 receives m1, m0, and calculates the result 3b. Then the sub-circuit 1420 performs summation operation on the result 3b calculated by the sub-circuit 1420 in the 4th tap and the result 3a sent by the sub-circuit 1410 in the 3rd tap to the sub-circuit 1420, thereby obtaining the result 3 of the 3rd tap and outputting the result 3 to the feedback circuit. It can be seen that the result 3 is a single-tap polynomial representing m3, m2, m1, m0, and the result 3 is a result calculated by the feedforward circuit 1400 through two clock periods (the 3rd tap and the 4th tap). In other words, in the 4th tap, the sub-circuit 1420 in the feedforward circuit 1400 outputs a single-tap polynomial representing m3, m2, m1, m0 (i.e., the result 3) to the feedback circuit.

[0216] By the 4th tap, all the 12 characters in the to-be-encoded data are input to the feedforward circuit 1400, and the single-tap polynomials representing m 11 , m 10 , m9, m8, the single-tap polynomial representing m7, m6, m5, m4, and the single-tap polynomial representing m3, m2, m1, m0 are output in the 2nd tap, the 3rd tap, and the 4th tap, respectively. The manner of inputting the to-be-encoded data shown in FIG. 8 to the feedforward circuit 1400 is referred to as a differential half-tap input manner, and through the manner, the calculation of the polynomial representing n symbols when the parallelism is n can be completed through two clock periods (two taps). Figure 14

[0217] Through the implementation manner described above, it can be ensured that the feedforward circuit 810 of the encoder 80 completes the calculation of the single-tap polynomial through at least two clocks. That is, in a large bandwidth scenario, even if the parallelism input to the encoder 80 is large, the encoder 80 provided in the embodiment of the present application can also complete the forward error correction encoding. Compared with the encoding circuit shown in FIG. 1, when the feedback loop cannot complete the data operation within one clock period, due to the constraint of the feedback loop in the time domain, the encoding circuit shown in FIG. 1 cannot insert a register into the feedback loop to prolong the operation time of the feedback loop, and thus the current technology has a technical defect that the time domain cannot converge in the scenario of large bandwidth and high parallel input, while the encoder provided in the embodiment of the present application does not have the technical defect. Figure 2 Figure 2

[0218] In some other embodiments, the code type of RS(N+ΔN, K) is introduced. RS(N+ΔN, K) represents that the code word length after encoding is N+ΔN, and the payload length is K. Correspondingly, the length of the check sequence in the code word after encoding is N+ΔN-K. N, ΔN, and K are all integers, and N is greater than K.​​​

[0219] Based on the above introduction of RS(N, K) code type, in implementing RS(N+ΔN, K) encoding, Θ N+ΔN,K satisfies formula (18), so that Φ N+ΔN,K satisfies formula (19), and so that Ω N+ΔN,K satisfies formula (20). Wherein, Θ N+ΔN,K is obtained by replacing N in Θ N,K shown in formula (13) above with (N+ΔN), Φ N+ΔN,K is obtained by replacing N in Φ N,K shown in formula (14) above with (N+ΔN), and Ω N+ΔN,K is obtained by replacing N in Ω NK shown in formula (15) above with (N+ΔN).

[0220] Formula (18)

[0221]

[0222] Formula (19)

[0223] Formula (20)

[0224] It can be seen that in RS(N+ΔN, K) code type, Θ N+ΔN,K represents a set of (N+ΔN-K) 2 constant coefficients, Φ N+ΔN,K represents a set of polynomials of the payload in RS code word, Ω N+ΔN,K represents the check sequence in RS code word. And, Θ N+ΔN,K , Φ N+ΔN,K and Ω N+ΔN,K satisfy the mathematical constraint relationship of Ω N+ΔN,K = Θ N+ΔN,K × Φ N+ΔN,K .

[0225] Thus, for RS(N+ΔN, K) code type, that is, when the code word length of the data to be encoded after being encoded in a forward error correction encoding manner is N+ΔN, and the payload length is K, the encoder for implementing RS(N+ΔN, K) encoding includes (N+ΔN-K) polynomial evaluation circuits, each of the (N+ΔN-K) polynomial evaluation circuits includes the feedforward circuit and the feedback circuit described above. Thus, the (N+ΔN-K) polynomial evaluation circuits are used to calculate (N+ΔN-K) target polynomials representing the data to be encoded, that is, to obtain Φ N+ΔN,KThe detailed explanations of the structure and working principle of the feedforward circuit, feedback circuit, and polynomial evaluation circuit can be found in the description above and will not be repeated here.

[0226] From formulas (14) and (19), we can see that Φ N+ΔN,K Including Φ N,K For details, please refer to Figure 15 , Figure 15 This illustration shows a schematic diagram of the relationship between polynomial sets representing payloads under different codeword lengths, as provided in an embodiment of this application. For example... Figure 15 As shown, Φ N,K It is Φ N+ΔN,K A part of it, namely Φ N+ΔN,K Including Φ N,K .

[0227] Given Φ N+ΔN,K Including Φ N,K The encoder for implementing RS(N+ΔN,K) encoding includes (N+ΔN-K) polynomial evaluation circuits, specifically (NK) polynomial evaluation circuits. In other words, the (N+ΔN-K) polynomial evaluation circuits in the encoder for implementing RS(N,K) encoding can reuse the (NK) polynomial evaluation circuits in the encoder for implementing RS(N,K) encoding.

[0228] refer to Figure 16 , Figure 16 A schematic diagram of the encoder 1600 provided in an embodiment of this application is shown. The encoder 1600 is an encoder that implements RS(N+ΔN,K) encoding. Figure 16 As shown, in addition to the (NK) polynomial evaluation circuits in the encoder 80 described above, the encoder 1600 also includes ΔN polynomial evaluation circuits, namely: polynomial evaluation circuit (NK), ..., and polynomial evaluation circuit (N+ΔN-K-1). The encoder 1600 also includes a constant coefficient multiply-accumulate module 1610 and a merging module 1620. Detailed descriptions of the constant coefficient multiply-accumulate module 1610 and the merging module 1620 can be found above and will not be repeated here.

[0229] The polynomial evaluation circuit (NK) is used to calculate the root of the generator polynomial α based on the data to be encoded received in K / n cycles. N-K The objective polynomial M(α) at ​​time N-K The polynomial evaluation circuit (N+ΔN-K-1) is used to calculate the roots of the generator polynomial α based on the data to be encoded received in K / n cycles. N+ΔN-K-1 The objective polynomial M(α) at ​​time N+ΔN-K-1 ).

[0230] It can be seen that the polynomial evaluation circuit of (N+ΔN-K) in the encoder 1600 for implementing RS(N+ΔN, K) code type encoding includes the polynomial evaluation circuit of (N-K) in the encoder 80 for implementing RS(N, K) code type encoding. Since (N+ΔN-K) / 2 is the error correction capability of the RS(N+ΔN, K) code type and (N-K) / 2 is the error correction capability of the RS(N, K), the error correction capability of the RS(N+ΔN, K) code type is higher than that of the RS(N, K). Therefore, by the encoder provided in the embodiment of the present application, the polynomial evaluation circuit in the encoder of the RS code type with higher error correction capability can reuse the polynomial evaluation circuit in the encoder of the RS code type with lower error correction capability when encoding RS code types with different error correction capabilities. That is, by the encoder design provided in the embodiment of the present application, the encoder of the RS code type with higher error correction capability and the encoder of the RS code type with lower error correction capability can share a common (i.e., reused) polynomial evaluation circuit, thereby greatly saving the circuit area and circuit power consumption in actual circuit implementation.

[0231] In addition, for the RS(N+ΔN, K) code type, that is, when the code word length of the data to be encoded is N+ΔN and the payload length is K after the data is encoded in the forward error correction encoding mode, the constant coefficient matrix preset in the constant coefficient multiplication and addition module of the encoder for implementing RS(N+ΔN, K) encoding is the above-mentioned matrix Θ N+ΔN,K , which is referred to as a second constant coefficient matrix. As can be seen from formula (18), the second constant coefficient matrix Θ N+ΔN,K is an (N+ΔN-K)×(N+ΔN-K) matrix.

[0232] As can be seen from formula (13) and formula (18), Θ N+ΔN,K includes Θ N,K . For details, refer to Figure 17 , Figure 17 Fig. 1 shows a relationship diagram of constant coefficient sets under different code word lengths provided in an embodiment of the present application. As shown in Figure 17 , Θ N,K is a part of Θ N+ΔN,K , that is, Θ N+ΔN,K includes Θ N,K .

[0233] In view of the fact that Θ N+ΔN,K includes Θ N,K , the second constant coefficient matrix Θ N+ΔN,K preset in the constant coefficient multiplication and addition module of the encoder for implementing RS(N+ΔN, K) encoding includes the first constant coefficient matrix Θ N,KThat is, the second constant coefficient matrix Θ preset in the constant coefficient multiplication-addition module in the encoder for implementing RS(N+ΔN, K) encoding N+ΔN,K , the first constant coefficient matrix Θ preset in the constant coefficient multiplication-addition module in the encoder for implementing RS(N, K) encoding can be reused N,K .

[0234] In combination with Figure 16 , reference is made to Figure 18 , Figure 18 Another structural schematic diagram of the encoder 1600 provided by the embodiment of the present application is shown, and the encoder 1600 is an encoder for implementing RS(N+ΔN, K) encoding. As shown in Figure 18 , the constant coefficient multiplication-addition module 1610 in the encoder 1600 includes (N+ΔN-K) sub-modules, which are sub-module 0, sub-module 1, …, sub-module (N-K-2), sub-module (N-K-1), sub-module (N-K), …, and sub-module (N+ΔN-K-1). Wherein, the coefficient corresponding to the sub-module 0 is the first row coefficient in the matrix Θ shown in formula (18), that is, θ N+ΔN,K ~ θ 1,1 ~ θ 1,N-K ~ θ 1,N+ΔN-K The coefficient corresponding to the sub-module 1 is the second row coefficient in the matrix Θ shown in formula (18), that is, θ N+ΔN,K ~ θ 2,1 ~ θ 2,N-K ~ θ 2,N+ΔN-K The coefficient corresponding to the sub-module (N-K-2) is the (N-K-1) row coefficient in the matrix Θ shown in formula (18), that is, θ N+ΔN,K ~ θ N-K-1,1 ~ θ N-K-1,N-K ~ θ N-K-1,N+ΔN-K The coefficient corresponding to the sub-module (N-K-1) is the (N-K) row coefficient in the matrix Θ shown in formula (18), that is, θ N+ΔN,K ~ θ N-K,1 ~ θ N-K,N-K ~ θ N-K,N+ΔN-K The coefficient corresponding to the sub-module (N-K) is the (N+1-K) row coefficient in the matrix Θ shown in formula (18), that is, θ N+ΔN,K ~ θ N+1-K,1 ~ θ N+1-K,N-K ~ θ N+1-K,N+ΔN-K The coefficient corresponding to the sub-module (N+ΔN-K-1) is the (N+ΔN-K) row coefficient in the matrix Θ shown in formula (18), that is, θ N+ΔN,K ~ θ N+ΔN-K,1 ~ θ N+ΔN-K,N-K ~ θ N+ΔN-K,N+ΔN-K .

[0235] Thus, when the to-be-encoded data input to the encoder 1600 through K / N shots and parallelism n is calculated by the above-mentioned (N+ΔN-K) polynomial evaluation circuits and (N+ΔN-K) target polynomials [including M(α 0 ), M(α 1 ), …, M(α N-K-2 ), M(α N-K-1 ), M(α N-K ), …, M(α N+ΔN-K-1 )] are output, the encoder 1600 sends the (N+ΔN-K) target polynomials to each sub-module in the constant coefficient multiplication-addition module 1610, so that each sub-module calculates a corresponding check value p according to the coefficients corresponding to each sub-module and the (N+ΔN-K) target polynomials (i.e., Θ N+ΔN,K ).

[0236] For example, the encoder 1600 sends the (N+ΔN-K) target polynomials to the sub-module 0 in the constant coefficient multiplication-addition module 1610, and the sub-module 0 performs multiplication-addition operation on the coefficients (θ 1,1 ~ θ 1,N-K ~ θ 1,N+ΔN-K ) and the (N+ΔN-K) target polynomials, so as to obtain the check value p N+ΔN-K-1 . Based on the mathematical constraint relationship Ω N+ΔN,K = Θ N+ΔN,K × Φ N+ΔN,K , formula (18) and formula (19), the multiplication-addition operation is specifically the operation of [θ 1,1 × M(α 0 ) + θ 1,2 × M(α 1 ) + … + θ 1,N-K-1 × M(α N-K-2 ) + θ 1,N-K × M(α N-K-1 ) + θ 1,N+1-K × M(α N-K ) + θ 1,N+ΔN-K × M(α N+ΔN–K-1 )].

[0237] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials to the sub-module 1 in the constant coefficient multiplication-addition module 1610, and the sub-module 1 performs multiplication-addition operation on the coefficients (θ 2,1 ~ θ 2,N-K ~ θ 2,N+ΔN-K ) and the (N+ΔN-K) target polynomials, so as to obtain the check value p N+ΔN-K-2 .

[0238] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials into the sub-module (N-K-2) in the constant coefficient multiplication-addition module 1610, and the sub-module (N-K-2) performs multiplication-addition operation on the coefficients (θ N-K-1,1 ~θ N-K-1,N-K ~θ N-K-1,N+ΔN-K and the (N+ΔN-K) target polynomials, thereby obtaining the check value p ΔN+1 .

[0239] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials into the sub-module (N-K-1) in the constant coefficient multiplication-addition module 1610, and the sub-module (N-K-1) performs multiplication-addition operation on the coefficients (θ N-K,1 ~θ N-K,N-K ~θ N-K,N+ΔN-K and the (N+ΔN-K) target polynomials, thereby obtaining the check value p ΔN .

[0240] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials into the sub-module (N-K) in the constant coefficient multiplication-addition module 1610, and the sub-module (N-K) performs multiplication-addition operation on the coefficients (θ N+1-K,1 ~θ N+1-K,N-K ~θ N+1-K,N+ΔN-K and the (N+ΔN-K) target polynomials, thereby obtaining the check value p ΔN-1 .

[0241] Similarly, the encoder 1600 sends the (N+ΔN-K) target polynomials into the sub-module (N+ΔN-K-1) in the constant coefficient multiplication-addition module 1610, and the sub-module (N+ΔN-K-1) performs multiplication-addition operation on the coefficients (θ N+ΔN-K,1 ~θ N+ΔN-K,N-K ~θ N+ΔN-K,N+ΔN-K and the (N+ΔN-K) target polynomials, thereby obtaining the check value p0.

[0242] In combination with the description of Figure 13 , it can be known that the constant coefficient multiplication-addition module 1610 in the encoder for realizing the RS(N+ΔN, K) code type includes the specific implementation circuit of the constant coefficient multiplication-addition module 1210 in the encoder for realizing the RS(N, K) code type. For example, taking the sub-module 0 in the constant coefficient multiplication-addition module 1610 as an example, the sub-module 0 in the constant coefficient multiplication-addition module 1610 includes the specific implementation circuit of the sub-module 0 in the constant coefficient multiplication-addition module 1210 as shown in Figure 13 , which is the specific implementation circuit for realizing multiplication-addition operation on the coefficients (θ 1,1 ~θ 1,N-KThis refers to a circuit that performs multiplication and addition. For example, taking submodule (NK-1) of the constant coefficient multiplication and addition module 1610 as an example, submodule (NK-1) of the constant coefficient multiplication and addition module 1610 includes... Figure 13 The circuit shown is the specific implementation circuit of submodule (NK-1) in the constant coefficient multiply-add module 1210. This implementation circuit is used to implement the addition of the coefficient (θ). N-K,1 ~θ N-K,N-K A circuit that performs multiplication and addition.

[0243] In other words, the (N+ΔN-K) sub-modules in the constant coefficient multiply-accumulate module of encoder 1600 each include (NK) sub-modules in the constant coefficient multiply-accumulate module of encoder 80. Since the error correction capability [(N+ΔN-K) / 2] of encoder 1600, used to implement RS(N+ΔN,K) code encoding, is higher than the error correction capability [(NK) / 2] of encoder 80, used to implement RS(N,K) code encoding, the constant coefficient multiply-accumulate module 1610 in encoder 1600, with higher error correction capability, can reuse the specific implementation circuit of the constant coefficient multiply-accumulate module 1210 in encoder 80, with lower error correction capability. In other words, the encoder provided in this application embodiment enables the reuse of the constant coefficient multiply-accumulate module in the encoder of RS code with higher error correction capability when encoding RS code with different error correction capabilities. That is, through the encoder design provided in the embodiments of this application, it is possible to enable encoders with high error correction capability and encoders with low error correction capability to share the common (i.e., reused by both) implementation circuit of constant coefficient multiply-accumulate module, thereby achieving a significant reduction in circuit area and power consumption in actual circuit implementation.

[0244] Furthermore, combined with Figures 15-18 The encoder provided in this application embodiment for implementing the RS(N+ΔN,K) code pattern with high error correction capability can reuse the polynomial evaluation circuit and the constant coefficient multiply-accumulate module circuit in the encoder for implementing the RS(N,K) code pattern with low error correction capability. Thus, by implementing the RS(N+ΔN,K) code pattern with high error correction capability, encoding of the RS(N,K) code pattern with low error correction capability can be achieved. That is, the encoder described in this application embodiment can support encoding of at least one forward error correction coding pattern, and each of these at least one forward error correction coding patterns has a different error correction capability. Alternatively, it can be understood that the encoder provided in this application embodiment is a fusion encoder capable of supporting forward error correction coding of multiple error correction capability patterns.

[0245] As an example, when the encoder provided in this application embodiment is an encoder for implementing the RS(N+ΔN,K) code pattern, the encoder supports encoding of at least one forward error correction coding pattern. Each of the at least one forward error correction coding pattern has a different error correction capability, and the error correction capability of the codeword encoded by the at least one forward error correction coding pattern is less than or equal to (N+ΔN-K) / 2. That is, the error correction capability of the codeword encoded by the at least one forward error correction coding pattern is less than or equal to the error correction capability of the RS(N+ΔN,K) code pattern.

[0246] It should be understood that when implementing RS(N,K) code encoding using an encoder of RS(N+ΔN,K) code type, it is only necessary to make Φ N+ΔN,K Φ in ΔN,K =0, and Θ in the constant coefficient multiplication and addition module N+ΔN,K Replace with Θ N,K (Or, reuse based on Θ) N+ΔN,K The constant coefficient multiply-add module is used to implement the addition of coefficient Θ. N,K (A circuit module for multiplication and addition). This allows for the encoding of the RS(N,K) code pattern in an encoder of the RS(N+ΔN,K) code pattern. Where Φ ΔN,K Including [M(α) N-K M(α), ..., M(α) N+ΔN-K-1 )).

[0247] As an example, when Φ needs to be set ΔN,K When = 0, the encoder can send to the selector Figure 16 In the ΔN polynomial evaluation circuits shown, the multiplier of each polynomial evaluation circuit is fed with a coefficient of 0, thereby enabling the realization of Φ ΔN,K =0.

[0248] To enhance understanding of the beneficial effects of the embodiments of this application, the encoder provided in the embodiments of this application will be further described below through examples.

[0249] It can simultaneously support RS(N1, K1, T1, m) code patterns, RS(N2, K2, T2, m) code patterns, ..., and RS(N s K s T s Taking an encoder that encodes m-type codes as an example, refer to... Figure 19 , Figure 19 This diagram illustrates the structure of an encoder supporting multi-code pattern fusion coding according to an embodiment of this application. Wherein, N is the codeword length after forward error correction coding, K is the length of the payload in the codeword, m indicates the finite field for RS coding calculation, T is the error correction capability, and T = (NK) / 2, therefore NK = 2T. Furthermore, T1, T2, ..., T... are set... smonotonically increasing, i.e., T1 s , s is an integer.

[0250] As shown in FIG. 19, the encoder 1900 comprises s polynomial evaluation modules, i.e., a first polynomial evaluation module, a second polynomial evaluation module, …, and an s-th polynomial evaluation module. Figure 19

[0251] The first polynomial evaluation module comprises (N1-K1) polynomial evaluation circuits and is configured to calculate (N1-K1) (i.e., 2T1) target polynomials from the received data according to the following formula: That is, The second polynomial evaluation module comprises (2T2-2T1) polynomial evaluation circuits and is configured to calculate (2T2-2T1) target polynomials from the received data according to the following formula: And, the s-th polynomial evaluation module comprises (2T s -2T s-1 ) polynomial evaluation circuits and is configured to calculate (2T s -2T s-1 ) target polynomials from the received data according to the following formula: It can be understood that the detailed description of calculating the target polynomials by the polynomial evaluation circuits can be referred to the description above and will not be repeated here.

[0252] The encoder 1900 further comprises s constant coefficient multiplication and addition modules, i.e., a first constant coefficient multiplication and addition module, a second constant coefficient multiplication and addition module, …, and an s-th constant coefficient multiplication and addition module.

[0253] The constant coefficient preset in the first constant coefficient multiplication and addition module is: wherein j1=1, 2, …, (N1-K1). It should be understood that when j1=[1, 2, …, (N1-K1)], the constant coefficient is a (N1-K1)×(N1-K1) coefficient matrix. Further, the first constant coefficient multiplication and addition module is configured to calculate the corresponding check sequence The constant coefficient preset in the second constant coefficient multiplication and addition module is: wherein j2=1, 2, …, (N2-K2). It should be understood that when j2=[1, 2, …, (N2-K2)], the constant coefficient is a (N2-K2)×(N2-K2) coefficient matrix. Further, the second constant coefficient multiplication and addition module is configured to calculate the corresponding check sequence The constant coefficient preset in the s-th constant coefficient multiplication and addition module is: wherein j​s =1,2,…,(N) s -K s It should be understood that j s = [1, 2, ..., (N)] s -K s When )], constant coefficient It is (N) s -K s )×(N s -K s The coefficient matrix of (N). Furthermore, the s-th multiplier multiplier-adder module is used to calculate the coefficient matrix based on preset constant coefficients and the received (N) s -K s The corresponding verification sequence is obtained by calculating ) objective polynomials.

[0254] The encoder 1900 also includes a merging module 1910, which is used to merge the received verification sequence and the corresponding data to be encoded to obtain the encoded codeword and output the codeword.

[0255] Based on the above description, for the RS(N1, K1, T1, m) code pattern, assuming that data 1 includes K1 symbols, the encoder 1900 sends the data 1 to be encoded in the RS(N1, K1, T1, m) code pattern to the first polynomial evaluation module in the encoder 1900 at a parallelism of n through K1 / n steps, thereby obtaining (N1-K1) (i.e., 2T1) target polynomials representing data 1. Next, encoder 1900 will generate (N1-K1) target polynomials The input is fed into the first constant coefficient multiply-add module to process (N1-K1) target polynomials. Sum of coefficients The multiplication and addition operations are used to obtain the check sequence of length (N1-K1) for data 1. in, Where i = 0, 1, 2, ..., (N1-K1). Then, encoder 1900 will verify the sequence. The data is sent to the merging module 1910, which then processes the verification sequence. Combine it with data 1 to obtain the codeword of data 1 encoded by RS(N1, K1, T1, m), and output the codeword.

[0256] For RS(N2, K2, T2, m) code type, assuming data 2 includes K2 symbols, the encoder 1900 sends the data 2 which needs to be encoded in RS(N2, K2, T2, m) code type into the first polynomial evaluation module and the second polynomial evaluation module through K2 / n taps at parallelism n. In this way, the first polynomial evaluation module can calculate and output 2T1 target polynomials of the data 2 and the second polynomial evaluation module can calculate and output (2T2-2T1) target polynomials of the data 2 Then, the encoder 1900 sends the 2T2 target polynomials into the second constant coefficient multiplication-addition module to implement multiplication-addition operation of the 2T2 target polynomials and the coefficient , so as to obtain the check sequence of the data 2 wherein the detailed process of the multiplication-addition operation can refer to the detailed explanation of the multiplication-addition operation in the first constant coefficient multiplication-addition module above, and will not be described herein again. Further, the encoder 1900 sends the check sequence into the merging module 1910, and the merging module 1910 merges the check sequence and the data 2, so as to obtain the codeword after RS(N2, K2, T2, m) encoding of the data 2, and outputs the codeword.

[0257] Similarly, for RS(N s , K s , T s , m) code type, assuming data 3 includes K s symbols, the encoder 1900 sends the data 3 which needs to be encoded in RS(N s , K s , T s , m) code type into the first polynomial evaluation module, the second polynomial evaluation module, …, and the third polynomial evaluation module through K s / n taps at parallelism n, so as to obtain 2T s target polynomials of the data 3 Then, the encoder 1900 implements multiplication-addition operation of the 2T s target polynomials and the coefficient through the s-th constant coefficient multiplication-addition module, so as to obtain the check sequence of the data 3 Further, the encoder 1900 sends the check sequence into the merging module 1910, and the merging module 1910 merges the check sequence and the data 3, so as to obtain the codeword after RS(N s , K s , T s , m) encoding of the data 3, and outputs the codeword.

[0258] By Figure 19 The description of the examples, the embodiment of the application in the encoding of RS code type with different error correction capabilities, for the realization of multiplexing circuit structure (such as Figure 20 The first polynomial evaluation module and the second polynomial evaluation module) in the encoder of RS code type with different error correction capabilities, therefore, the encoder provided by the embodiment of the application can not only support RS code type encoding with different error correction capabilities, but also save the circuit area and circuit power consumption of the encoder.

[0259] The above describes the encoder provided by the application from the structural aspect, and the following describes the encoding method executed by the encoder described above from the method aspect.

[0260] Reference Figure 20 , Figure 8 The flowchart of the encoding method provided by the embodiment of the application is shown. The method is executed by the encoder described above (for example Figure 11 , Figure 13 , Figure 16 , Figure 18 , Figure 19 Or Figure 20 The encoder shown in the figure. As Figure 21 The method comprises the following steps:

[0261] S101, receiving the data to be encoded by the feedforward module with a parallel degree of n symbols per beat.

[0262] Wherein, n is a positive integer.

[0263] Specifically, the detailed description of the encoder receiving the data to be encoded can be referred to the description above, and will not be repeated here.

[0264] S102, calculating the single-beat polynomial corresponding to the current beat according to the symbol in the data to be encoded received by the feedforward module in the finite field.

[0265] Wherein, the data to be encoded comprises K symbols, K is a positive integer, and K is greater than or equal to n. And the polynomial representing the symbol received per beat is the single-beat polynomial described above.

[0266] Specifically, the detailed description of the encoder calculating the single-beat polynomial in the finite field through the feedforward module can be referred to the description of calculating the single-beat polynomial above, and will not be repeated here.

[0267] S103, receiving the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculating the second polynomial in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbol received by the historical beat.

[0268] wherein the second polynomial represents the symbols received from the first beat to the current beat, and the second polynomial is used to determine a target polynomial representing the data to be encoded. Here, the first beat is the first beat at which the feedforward module receives the data to be encoded, and the history beats are the beats between the current beat in the process of the feedforward module receiving the data to be encoded. It should be noted that the input parallelism of the feedback module of the encoder and the data to be encoded is decoupled, and detailed description can be referred to the foregoing, and will not be repeated here.

[0269] wherein the target polynomial is used to generate a check sequence of the data to be encoded, and the check sequence of the data to be encoded is used to check and correct errors of the data to be encoded, and the codeword of the data to be encoded encoded in the forward error correction coding manner includes the data to be encoded and the check sequence of the data to be encoded.

[0270] Specifically, the encoder receives the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculates and outputs the second polynomial in the finite field according to the single-beat polynomial corresponding to the current beat and the first polynomial representing the symbols received in the history beats. Detailed description can be referred to the detailed description of the feedback circuit in the foregoing, and will not be repeated here.

[0271] Further, the encoder determines whether the current beat is the K / n beat at which the data to be encoded is received.

[0272] When the encoder determines that the current beat is the K / n beat at which the data to be encoded is received, it means that the payload of a codeword has been completed to be input. In this case, the encoder determines the second polynomial calculated by the feedback module as the target polynomial representing the data to be encoded, and the encoder performs S104.

[0273] When the encoder determines that the current beat is not the K / n beat at which the data to be encoded is received, it means that the payload of a codeword has not been completed to be input. In this case, the encoder repeatedly performs S102-S103 until the K / n beat at which the data to be encoded is received.

[0274] S104, calculating a check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial.

[0275] wherein the detailed description of the encoder calculating the check sequence of the data to be encoded according to the constant coefficient matrix and the target polynomial can be referred to the detailed description of the constant coefficient multiplication and addition module in the foregoing, and will not be repeated here.

[0276] S105, merging the data to be encoded and the check sequence of the data to be encoded to obtain a codeword of the data to be encoded encoded in the forward error correction coding manner.

[0277] The encoder merges the to-be-encoded data and the check sequence of the to-be-encoded data to obtain a code word of the to-be-encoded data encoded in the forward error correction mode. Details can be referred to the foregoing description of the merging module, and will not be described herein again.

[0278] In this way, the encoder provided in the embodiments of the present application can encode forward error correction codes with different error correction capabilities by using the encoding method described in S101-S105, and can save the circuit area and power consumption of the encoder.

[0279] To further understand the encoder and the encoding method described in the embodiments of the present application, the following further describes specific examples.

[0280] Example 1 RS (528, 514, 7, 10) code

[0281] The RS (528, 514, 7, 10) code indicates that the RS code word length is 528, the payload length in the code word is 514, the check sequence length (528-514) = 14 (i.e., the (N-K) described above), the error correction capability is 7, and the finite field for RS encoding calculation is GF (2 10 ).

[0282] When the encoder performs the encoding method described above in the RS (528, 514, 7, 10) code, the constant coefficient matrix preset in the constant coefficient multiplication and addition module in the encoder is recorded as the following matrix (3) :

[0283] Matrix (3)

[0284] In this way, the 14 polynomial evaluation modules in the encoder first calculate 14 target polynomials of the to-be-encoded data: [M (α 13 ), M (α 12 ), …, M (α 0 )]. Then, the constant coefficient multiplication and addition module in the encoder performs multiplication and addition operation on [M (α 13 ), M (α 12 ), …, M (α 0 ) and the preset constant coefficient matrix (i.e., matrix (3)) to obtain the check sequence [p 13 , p 12 …, p0]. Wherein, p 13 =∑θ (1，i+1) ×M (α i ), p 12 =∑θ (2，i+1) ×M (α i ), …, p0=∑θ (14，i+1) ×M (α i), where i = 1, 2,..., 14.

[0285] where [M(a 13 ), M(a 12 ),..., M(a 0 )] can be calculated according to the following formula (21) and the root a of the primitive polynomial x 10 + x 10 + 1 in the finite field GF(2 3 ).

[0286] Formula (21)

[0287] Each coefficient in the above matrix (3) can be calculated according to the following formula (22) and the root a of the primitive polynomial x 10 + x 10 + 1 in the finite field GF(2 3 ). Where formula (22) can be derived according to the above formula (13) and matrix (3), and will not be repeated here.

[0288] Formula 22

[0289] The coefficients in the matrix (3) are calculated in advance as shown in the following matrix (4):

[0290] Matrix (4)

[0291] Further, the encoder calculates the check sequence [p 13 , p 12 ,..., p0] according to the values of [M(a 0 ), M(a 13 ),..., M(a 12 )] calculated according to formula (21) and the coefficients shown in matrix (4). The encoder combines the data to be encoded and the check sequence to obtain the code word after the RS (528, 514, 7, 10) code type encoding of the data to be encoded.

[0292] Example 2 RS (544, 514, 15, 10)

[0293] Where the RS (544, 514, 15, 10) code type represents that the RS code word length is 544, the payload length in the code word is 514, the check sequence length (544-514) = 30 (i.e. the above (N-K)), the error correction capability is 15, and the finite field for RS encoding calculation is GF(2 10 ).

[0294] The encoder provided by the present application performs the encoding method described above. When the encoder encodes in the RS (544, 514, 15, 10) code type, the constant coefficient matrix preset in the constant coefficient multiplication and addition module in the encoder is recorded as the following matrix (5):

[0295] Matrix (5)

[0296] In this way, the 30 polynomial evaluation modules in the encoder first calculate 30 target polynomials of the data to be encoded: [M (α 29 ), …, M (α 0 )]. Then, the constant coefficient multiplication and addition module in the encoder performs multiplication and addition operation on [M (α 29 ), …, M (α 0 ) and the preset constant coefficient matrix (i.e. matrix (5)) to obtain the check sequence [p 29 , p 28 , …, p0]. Wherein, p 29 =∑θ (1 , i+1) ×M (α i ), p 28 =∑θ (2 , i+1) ×M (α i ), …, p0=∑θ (30 , i+1) ×M (α i ), wherein i=1, 2, …30.

[0297] Wherein, the values of [M (α 29 ), …, M (α 0 )] can be calculated according to the following formula (23) and the root α of the primitive polynomial x 10 +x 10 +1 in the finite field GF (2 3 ):

[0298] Formula (23)

[0299] As can be seen from formula (21) and formula (23), in the process of encoding in the RS (544, 514, 15, 10) code type, the 30 polynomial evaluation circuits in the encoder can reuse the 14 polynomial evaluation circuits corresponding to [M (α 29 ), …, M (α 0 )] in the RS (528, 514, 7, 10) when calculating [M (α 13 ), …, M (α 0 )], thereby saving circuit area and circuit power consumption.

[0300] Each coefficient in the matrix (5) above can be derived from the following formula (24) and the finite field GF(2 10 The primitive polynomial x in ) 10 +x 3 The root α is calculated from +1. Formula (24) can be derived from formula (13) and matrix (5) above, and will not be repeated here.

[0301] Formula 24

[0302] Based on calculations, reference Figure 21 , Figure 21 The constant coefficient matrix of the RS(544,514,15,10) code pattern provided in this application embodiment is shown. Compared to the coefficients of the RS(528,514) and RS(544,514) code patterns in the current encoding method shown in Table 1, Figure 21 The submatrix shown in the embodiment of this application is the first 14 rows × first 14 columns of the constant coefficient matrix of the preset RS(544,514,15,10) code pattern in the encoder. Figure 21 (Indicated by the bolded rectangle in the image) This is the constant coefficient matrix of the preset RS(528,514,7,10) code pattern in the encoder provided in this embodiment. Based on this, according to the same coefficient matrix, the encoders of the RS(544,514,15,10) code pattern and the encoders of the RS(528,514,7,10) code pattern provided in this embodiment can share the circuit constructed based on the aforementioned same coefficient matrix. Therefore, the encoder provided in this embodiment can not only encode forward error correction codes with different error correction capabilities, but also save the encoder's circuit area and power consumption.

[0303] Furthermore, the encoder calculates [M(α) according to formula (23). 29 ), ..., M(α) 0 The value of )] and Figure 22 The coefficients shown are used to calculate the check sequence [p]. 29 p 28 …, p0]. After the encoder merges the data to be encoded and the check sequence, it can obtain the codeword after the data to be encoded is encoded by the RS(544,514,15,10) code pattern.

[0304] In summary, the encoder provided in this application embodiment will not suffer from the technical defect of timing non-convergence in scenarios with high bandwidth and high parallelism input. Furthermore, the encoder provided in this application embodiment can not only encode forward error correction codes with different error correction capabilities, but also save the encoder's circuit area and power consumption.

[0305] To achieve the functions described in the above method, such as Figure 22 As shown,Figure 20 A schematic diagram of an encoding device 2200 according to an embodiment of this application is shown. The encoding device 2200 is used to perform the above-described encoding method, for example, to perform... Figure 20 The method is illustrated. The encoding device 2200 can be the encoder described above, which includes a feedforward module and a feedback module, or the encoding device 2200 can be applied to the encoder described above, which includes a feedforward module and a feedback module. The encoding device 2200 may include a receiving unit 2210 and a computing unit 2220.

[0306] The receiving unit 2210 is used to receive the data to be encoded at a parallelism of n symbols per beat through the feedforward module, where n is a positive integer. The calculation unit 2220 is used to calculate, through the feedforward module and based on the symbols in the data to be encoded received in the current beat, a single-beat polynomial corresponding to the current beat in a finite field. Here, the single-beat polynomial represents the symbols received by the feedforward module in one beat. The calculation unit 2220 is also used to receive the single-beat polynomial corresponding to the current beat output by the feedforward module through the feedback module, and calculate a second polynomial in a finite field based on the single-beat polynomial corresponding to the current beat and a first polynomial representing the symbols received in previous beats. The second polynomial represents the symbols received from the first beat to the current beat, and is used to determine the target polynomial representing the data to be encoded. The target polynomial is used to generate a check sequence for the data to be encoded, and the check sequence is used for error correction. The codeword obtained after encoding the data to be encoded using forward error correction coding includes the data to be encoded and its check sequence. In addition, the aforementioned first beat refers to the first beat in which the feedforward module receives the data to be encoded, and the historical beats refer to the beats in the process of the feedforward module receiving the data to be encoded that are between the current beats.

[0307] As an example, combined Figure 20 The receiving unit 2210 can be used to execute S101, and the calculation unit 2220 can be used to execute S102 and S103.

[0308] Optionally, the data to be encoded includes K symbols, where K is a positive integer. When the codeword length obtained after encoding the data to be encoded using forward error correction coding is N, and N is an integer greater than K, the encoder includes NK polynomial evaluation modules, each of which includes a feedforward module and a feedback module. These NK polynomial evaluation modules are used to calculate NK target polynomials representing the data to be encoded in a finite field through the feedforward and feedback modules in each polynomial evaluation module.

[0309] Optionally, when the code word length of the to-be-encoded data after being encoded in the forward error correction encoding mode is N+ΔN, the encoder comprises N+ΔN-K polynomial evaluation modules, each of which comprises a feedforward module and a feedback module. The N+ΔN-K polynomial evaluation modules are configured to calculate N+ΔN-K target polynomials representing the to-be-encoded data through the feedforward modules and the feedback modules in each of the polynomial evaluation modules in a finite field. In addition, the N+ΔN-K polynomial evaluation modules comprise the N-K polynomial evaluation modules.

[0310] Optionally, the encoding apparatus 2200 further comprises a determination unit 2230 configured to determine the second polynomial as the target polynomial when it is determined that the current shot is the K / n shot of receiving the to-be-encoded data. The calculation unit 2220 is further configured to calculate the check sequence of the to-be-encoded data according to the constant coefficient matrix and the target polynomial. The merging unit 2240 is configured to merge the to-be-encoded data and the check sequence of the to-be-encoded data to obtain the code word of the to-be-encoded data after being encoded in the forward error correction encoding mode.

[0311] As an example, in combination with Figure 12 The calculation unit 2220 can be configured to perform S104, and the merging unit 2240 can be configured to perform S105.

[0312] Optionally, when the code word length of the to-be-encoded data after being encoded in the forward error correction encoding mode is N, the constant coefficient matrix is a first constant coefficient matrix of (N-K)×(N-K). When the code word length of the to-be-encoded data after being encoded in the forward error correction encoding mode is N+ΔN, the constant coefficient matrix is a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K). The second constant coefficient matrix comprises the first constant coefficient matrix.

[0313] Optionally, the encoder supports encoding of at least one forward error correction encoding code type, and each of the at least one forward error correction encoding code type has different error correction capability.

[0314] Optionally, when the value of n is greater than a threshold value, the encoding apparatus 2200 further comprises a control unit 2250 configured to control the feedforward module to complete the calculation of one single-shot polynomial through at least two clock cycles through the register inserted in the feedforward module.

[0315] For specific descriptions of the optional modes, refer to the foregoing method embodiments, which will not be described here. In addition, the explanations and beneficial effect descriptions of any one of the encoding apparatuses 2200 provided above can refer to the foregoing corresponding methods and the embodiments of the encoder, which will not be described here.

[0316] As an example, in combination with Figure 12The function implemented by the receiving unit 2210 in the encoding device 2200 can be performed by the polynomial evaluation circuit in FIG. 13B. Figure 12 The function implemented by the calculation unit 2220 can be performed by the polynomial evaluation circuit and the constant coefficient multiply-add module 1210 shown in FIG. 13C. Figure 12 The function implemented by the determination unit 2230 can be performed by the polynomial evaluation circuit shown in FIG. 13D. Figure 12 The function implemented by the merging unit 2240 can be performed by the merging module 1220 shown in FIG. 13E. Figure 14 In combination with FIG. 13F, Figure 14 The function implemented by the control unit 2250 can be performed by the register of the feedforward circuit 1400 in FIG. 13G. Figure 22

[0317] Those skilled in the art should easily understand that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is realized in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0318] It should be noted that the division of modules in Figure 20 is illustrative, and is merely a logical functional division. Actual implementation can have another division manner. For example, two or more functions can be integrated in one processing module. The integrated module can be realized in the form of hardware or software function module.

[0319] The embodiments of the present application also provide a chip, which includes an encoding circuit configured to perform the encoding method as described above to realize encoding of the to-be-encoded data in a forward error correction coding manner.

[0320] The embodiments of the present application also provide a computer program product and a computer readable storage medium for storing the computer program product. The computer program product can include one or more program instructions, which, when executed by one or more processors, can provide the functions or part of the functions described above with reference to Figure 20 . Therefore, for example, one or more features of S101-S105 in Figure 20 can be assumed by one or more instructions in the computer program product.

[0321] In some examples, such as for ​ ​The described encoding apparatus can be configured to provide various operations, functions, or actions in response to one or more program instructions stored in a computer-readable storage medium.

[0322] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer executes the instructions, all or part of the processes or functions according to the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that can be accessed by a computer or data storage device including one or more servers, data centers, etc. integrated with the medium. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0323] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An encoder, characterized by The encoder comprises: a feedforward module, configured to receive to-be-encoded data with a parallelism of n symbols per shot, and to calculate a single-shot polynomial corresponding to a current shot from symbols of the to-be-encoded data received by the current shot in a finite field, the single-shot polynomial representing symbols received by the feedforward module through the current shot, n being a positive integer; a feedback module, configured to receive the single-shot polynomial corresponding to the current shot output by the feedforward module, and to calculate a second polynomial from the single-shot polynomial corresponding to the current shot and a first polynomial representing symbols received by historical shots in the finite field, the second polynomial representing symbols received from a first shot to the current shot, and the second polynomial being used to determine a target polynomial representing the to-be-encoded data; wherein the target polynomial is used to generate a check sequence of the to-be-encoded data, the check sequence of the to-be-encoded data being used for check error correction of the to-be-encoded data, and a code word obtained by encoding the to-be-encoded data in a forward error correction coding manner comprises the to-be-encoded data and the check sequence of the to-be-encoded data; the first shot is a first shot at which the feedforward module receives the to-be-encoded data, and the historical shots are shots between the current shot in a process in which the feedforward module receives the to-be-encoded data.

2. The encoder of claim 1, wherein, The to-be-encoded data comprises K symbols, K being a positive integer; when a code word obtained by encoding the to-be-encoded data in a forward error correction coding manner has a length of N, and N is an integer greater than K, the encoder comprises N-K polynomial evaluation modules, each of which comprises the feedforward module and the feedback module; The N-K polynomial evaluation modules are configured to calculate N-K target polynomials representing the to-be-encoded data in the finite field through the feedforward module and the feedback module in each of the polynomial evaluation modules.

3. The encoder of claim 2, wherein, When a code word obtained by encoding the to-be-encoded data in a forward error correction coding manner has a length of N+ΔN, the encoder comprises N+ΔN-K polynomial evaluation modules, each of which comprises the feedforward module and the feedback module; The N+ΔN-K polynomial evaluation modules are configured to calculate N+ΔN-K target polynomials representing the to-be-encoded data in the finite field through the feedforward module and the feedback module in each of the polynomial evaluation modules, and the N+ΔN-K polynomial evaluation modules comprise the N-K polynomial evaluation modules.

4. The encoder according to any one of claims 1 to 3, characterized in that, The encoder further comprises: a constant coefficient multiplication and addition module, configured to calculate a check sequence of the to-be-encoded data from a constant coefficient matrix and the target polynomial; a merging module, configured to merge the to-be-encoded data and the check sequence of the to-be-encoded data to obtain a code word obtained by encoding the to-be-encoded data in a forward error correction coding manner.

5. The encoder of claim 4, wherein: when the code word obtained by encoding the to-be-encoded data in a forward error correction coding manner has a length of N, the constant coefficient matrix is a first constant coefficient matrix of (N-K)×(N-K). When a code word length of the to-be-encoded data after being encoded in a forward error correction encoding mode is N+ΔN, the constant coefficient matrix is a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K), and the second constant coefficient matrix comprises the first constant coefficient matrix.

6. The encoder according to any one of claims 1 to 5, characterized in that, The encoder supports encoding of at least one forward error correction encoding code type, each of the at least one forward error correction encoding code type having different error correction capabilities.

7. The encoder according to any one of claims 1 to 6, characterized in that, When the value of n is greater than a threshold value, the feedforward module comprises a register. The register is configured to control the feedforward module to complete calculation of one single-tap polynomial through at least two clock cycles.

8. An encoding method characterized by comprising: The method is applied to an encoder, and the encoder comprises a feedforward module and a feedback module, and the method comprises: The feedforward module receives to-be-encoded data at a parallelism of n symbols per tap, and a single-tap polynomial corresponding to a current tap is calculated in a finite field according to symbols in the to-be-encoded data received at the current tap, the single-tap polynomial representing symbols received by the feedforward module at one tap, and n is a positive integer. The feedback module receives the single-tap polynomial corresponding to the current tap output by the feedforward module, and a second polynomial is calculated in the finite field according to the single-tap polynomial corresponding to the current tap and a first polynomial representing symbols received at historical taps, the second polynomial representing symbols received from a first tap to the current tap, and the second polynomial being used to determine a target polynomial representing the to-be-encoded data; wherein the target polynomial is used to generate a check sequence of the to-be-encoded data, the check sequence of the to-be-encoded data being used for check error correction of the to-be-encoded data, and a code word obtained after the to-be-encoded data is encoded in a forward error correction encoding mode comprises the to-be-encoded data and the check sequence of the to-be-encoded data; the first tap is a first tap at which the feedforward module receives the to-be-encoded data, and the historical taps are taps located between the current tap in a process in which the feedforward module receives the to-be-encoded data.

9. The method of claim 8, wherein, The to-be-encoded data comprises K symbols, and K is a positive integer; when a code word length of the to-be-encoded data after being encoded in a forward error correction encoding mode is N, and N is an integer greater than K, the encoder comprises N-K polynomial evaluation modules, each polynomial evaluation module comprising the feedforward module and the feedback module; and the N-K polynomial evaluation modules are configured to calculate N-K target polynomials representing the to-be-encoded data in the finite field through the feedforward module and the feedback module in each polynomial evaluation module.

10. The method of claim 9, wherein, When a code word length obtained after the to-be-encoded data is encoded in a forward error correction encoding mode is N+ΔN, the encoder comprises N+ΔN-K polynomial evaluation modules, each of which comprises the feedforward module and the feedback module; the N+ΔN-K polynomial evaluation modules are configured to calculate N+ΔN-K target polynomials representing the to-be-encoded data in the finite field through the feedforward module and the feedback module in each of the polynomial evaluation modules, and the N+ΔN-K polynomial evaluation modules comprise the N-K polynomial evaluation modules.

11. The method according to any one of claims 8 to 10, characterized in that, The method further comprises: When it is determined that the current shot is the K / n shot of receiving the to-be-encoded data, the second polynomial is determined as the target polynomial; According to the constant coefficient matrix and the target polynomial, a check sequence of the to-be-encoded data is calculated; The to-be-encoded data and the check sequence of the to-be-encoded data are merged to obtain a code word obtained after the to-be-encoded data is encoded in the forward error correction encoding mode.

12. The method of claim 11, wherein, When a code word length obtained after the to-be-encoded data is encoded in a forward error correction encoding mode is N, the constant coefficient matrix is a first constant coefficient matrix of (N-K)×(N-K); When a code word length obtained after the to-be-encoded data is encoded in a forward error correction encoding mode is N+ΔN, the constant coefficient matrix is a second constant coefficient matrix of (N+ΔN-K)×(N+ΔN-K), and the second constant coefficient matrix comprises the first constant coefficient matrix.

13. The encoding method according to any one of claims 8 to 12, characterized in that, The encoder supports encoding of at least one forward error correction encoding mode, and each of the at least one forward error correction encoding mode has different error correction capabilities.

14. The method according to any one of claims 8 to 13, characterized in that, When the value of n is greater than a threshold value, the method further comprises: The feedforward module is controlled to complete calculation of a single-shot polynomial through at least two clock cycles by means of the register inserted in the feedforward module.

15. A chip, characterized by The chip comprises an encoding circuit configured to perform the method of any one of claims 8 to 14 to encode to-be-encoded data in a forward error correction encoding mode.

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