Chip and display device

Abstract

The application discloses a chip and a display device. The chip comprises an image receiving module, an image display module and a frame rate synchronization module. The image receiving module is used for sending an input image to a frame buffer under the triggering of a vertical synchronization signal to store the input image in the frame buffer. The image display module is used for reading the input image stored in the frame buffer to obtain an output image for a display screen to display the output image. The frame rate synchronization module is used for determining a tearing position range corresponding to frame rates of the input image and the output image and determining a first reading position. The speed of the image display module reading the input image stored in the frame buffer is adjusted according to the first reading position and the tearing position range. Thus, the speed of the image display module reading the input image stored in the frame buffer is adjusted according to the first reading position and the tearing position range by the frame rate synchronization module, so that each frame of output image is continuous and the input image is synchronized with the output image under the premise of a single frame buffer.

Description

Technical Field

[0001] This application relates to the technical field of chips, and more specifically, to a chip and a display device. Background Technology

[0002] When the Mobile Industry Processor Interface (MIPI) is in video mode, the hardware synchronization method involves the Liquid Crystal Display Controller (LCDC) outputting one frame of image upon triggering the vertical sync signal. In other words, if the vertical sync signal hasn't been triggered before the current frame of image is displayed, the LCDC will wait until the vertical sync signal is triggered before outputting the next frame. However, this hardware synchronization method suffers from discontinuous output images, causing the transmission channel (TX lane) to be pulled high, leading to incompatibility with some displays and resulting in display abnormalities.

[0003] In related technologies, two frame buffers are used to store the input image, enabling arbitrary frame rate conversion between the input and output images. This ensures the continuity of the output image and is compatible with different frame rates and displays for the input image, but it places higher demands on hardware costs and increases chip costs. Summary of the Invention

[0004] In view of the above problems, this application proposes a chip and a display device that can effectively ensure continuous output images and effectively reduce the cost of the chip.

[0005] In a first aspect, embodiments of this application provide a chip comprising: an image receiving module, an image display module, a frame buffer, and a frame rate synchronization module. The image receiving module, the frame buffer, and the image display module are connected sequentially, and the image receiving module and the image display module are also connected to the frame rate synchronization module. Specifically: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal, so as to store the input image in the frame buffer; the vertical synchronization signal is sent to the image receiving module by a signal source; the image display module is used to read the input image stored in the frame buffer to obtain an output image for display on a screen; the frame rate synchronization module is used to determine the tear position range corresponding to the frame rates of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input time of the vertical synchronization signal corresponding to the next frame input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tear position range, so as to change the frame rate at which the display shows the output image.

[0006] Secondly, embodiments of this application also provide a display device, which includes: the chip and the display screen described above, wherein the chip is used to send an output image to the display screen, and the display screen is used to display the output image.

[0007] The technical solution provided in this application includes a chip comprising: an image receiving module, an image display module, a frame buffer, and a frame rate synchronization module. The image receiving module, the frame buffer, and the image display module are connected sequentially, and the image receiving module and the image display module are also connected to the frame rate synchronization module. Specifically: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal, so as to store the input image in the frame buffer; the vertical synchronization signal is sent to the image receiving module by a signal source; the image display module is used to read the input image stored in the frame buffer to obtain an output image for display on the screen; the frame rate synchronization module is used to determine the tear position range corresponding to the frame rate of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input time of the vertical synchronization signal corresponding to the next frame input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tear position range, so as to change the frame rate at which the display shows the output image. Therefore, the frame rate synchronization module adjusts the speed at which the image display module reads the input image stored in the frame buffer according to the range of the first reading position and the tear position, so as to achieve continuous output image for each frame and synchronization between the input image and the output image under the premise of a single frame buffer. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0009] Figure 1 This illustration shows a schematic diagram of an input and output structure provided in an embodiment of this application.

[0010] Figure 2 This illustration shows a schematic diagram of another input and output image provided in an embodiment of this application.

[0011] Figure 3 This illustration shows a structural diagram of another input image and output image provided in an embodiment of this application.

[0012] Figure 4A schematic diagram of the structure of a chip provided in an embodiment of this application is shown.

[0013] Figure 5 This illustration shows a structural diagram of another input image and output image provided in an embodiment of this application.

[0014] Figure 6 This illustration shows a structural diagram of another input image and output image provided in an embodiment of this application.

[0015] Figure 7 This illustration shows a structural diagram of yet another input and output image provided in an embodiment of this application.

[0016] Figure 8 This illustration shows a structural diagram of yet another input image and output image provided in an embodiment of this application.

[0017] Figure 9 This illustration shows a structural diagram of yet another input image and output image provided in an embodiment of this application.

[0018] Figure 10 This illustration shows a structural diagram of yet another input image and output image provided in an embodiment of this application.

[0019] Figure 11 This illustration shows a structural diagram of another input and output image provided in an embodiment of this application.

[0020] Figure 12 This illustration shows a structural diagram of yet another input image and output image provided in an embodiment of this application.

[0021] Figure 13 This illustration shows a structural diagram of another input image and output image provided in an embodiment of this application.

[0022] Figure 14 A schematic diagram of the structure of a display device provided in an embodiment of this application is shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. In the following description, the term "a plurality of" means at least two.

[0025] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0027] When the Mobile Industry Processor Interface (MIPI) is in video mode, the hardware synchronization method involves the Liquid Crystal Display Controller (LCDC) outputting one frame of image upon triggering the vertical sync signal. In other words, if the vertical sync signal hasn't been triggered before the current frame of image is displayed, the LCDC will wait until the vertical sync signal is triggered before outputting the next frame. However, this hardware synchronization method suffers from discontinuous output images, causing the transmission channel (TX lane) to be pulled high, leading to incompatibility with some displays and resulting in display abnormalities.

[0028] For example, when both the input and output images have a frame rate of 60Hz, there is a time interval between the two output frames waiting for the vertical synchronization signal to be triggered. For details, please refer to... Figure 1 , Figure 1 This illustration shows a structural diagram of an input image and an output image provided in an embodiment of this application. For example... Figure 1 As shown, the blue line represents the input image, the green line represents the output image, and the red line between two output images represents the time waiting for the vertical synchronization signal to be triggered, which results in the discontinuity of the output image.

[0029] For example, when the input image frame rate is 90Hz and the output image frame rate is 60Hz, three input frames will trigger two output frames to ensure synchronization between the input and output images. However, the third output frame is triggered by the fourth input frame, which can result in a discontinuity between the second and third output frames. For details, please refer to [link to relevant documentation]. Figure 2 , Figure 2 This illustration shows a schematic diagram of another input and output image structure provided in an embodiment of this application. For example... Figure 2 As shown, the red line represents the input image, the blue line represents the output image, and time t1 is the time it takes for the third frame output image to wait for the fourth frame input image to be triggered.

[0030] Based on the above, related technologies utilize two frame buffers to store the input image, enabling arbitrary frame rate conversion of the output image. For example, the input image has a frame rate of 120Hz, and the output image has a frame rate of 60Hz. Another example is an input image with a frame rate of 90Hz and an output image with a frame rate of 60Hz. Yet another example is an input image with a frame rate of 60Hz and an output image with a frame rate of 60Hz.

[0031] Specifically, assuming the input image has a frame rate of 90Hz and the output image has a frame rate of 60Hz, please refer to [link / reference]. Figure 3 , Figure 3 This illustration shows a schematic diagram of another input and output image structure provided in an embodiment of this application. For example... Figure 3 As shown, when the first input image 1 is input, the pointer of the video encoder (VIDC) points to frame buffer FB2 to store the first input image 1 in frame buffer FB2; when the second input image 2 is input, the pointer of the video encoder (VIDC) points to frame buffer FB1 to store the second input image 2 in frame buffer FB1. This allows frame buffer FB2 and frame buffer FB1 to alternately store input images. When the second output image 2 is output, the pointer of the display controller (LCDC) points to frame buffer FB1 to output the second input image 2 stored in frame buffer FB1; when the third output image 3 is output, the pointer of the display controller points to frame buffer FB2 to output the third input image 3 stored in frame buffer FB2; when the fourth output image 4 is output, the pointer of the display controller points to frame buffer FB2 to output the fifth input image 5 stored in frame buffer FB2.

[0032] While the above-mentioned scheme, which uses two frame buffers to store the input image to achieve arbitrary frame rate conversion of the output image, can ensure continuous output image and is compatible with different frame rates of input images and different displays, it has higher hardware cost requirements and increases chip cost.

[0033] To address the aforementioned issues, this application provides a chip and a display device. The chip includes a receiving module, an image display module, a frame buffer, and a frame rate synchronization module. The image receiving module, frame buffer, and image display module are connected sequentially, and the image receiving module and image display module are also connected to the frame rate synchronization module. Specifically: the image receiving module sends an input image to the frame buffer under the triggering of a vertical synchronization signal to store the input image in the frame buffer; the vertical synchronization signal is sent to the image receiving module by a signal source; the image display module reads the input image stored in the frame buffer to obtain an output image for display on the screen; the frame rate synchronization module determines the tear position range corresponding to the frame rates of the input and output images; the frame rate synchronization module also determines the first reading position of the image display module in the frame buffer at the input time of the vertical synchronization signal corresponding to the next frame input image; and the frame rate synchronization module further adjusts the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the tear position range, thereby changing the frame rate at which the screen displays the output image.

[0034] Therefore, the frame rate synchronization module adjusts the speed at which the image display module reads the input image stored in the frame buffer according to the range of the first reading position and the tear position, so as to achieve continuous output image for each frame and synchronization between the input image and the output image under the premise of a single frame buffer.

[0035] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0036] Please see Figure 4 , Figure 4 A schematic diagram of the structure of a chip provided in an embodiment of this application is shown. Figure 4 As shown, the chip 100 includes an image receiving module 110, an image display module 120, a frame buffer 130, and a frame rate synchronization module 140. The image receiving module 110, the frame buffer 130, and the image display module 120 are connected in sequence. The image receiving module 110 and the image display module 120 are also connected to the frame rate synchronization module 140. Wherein:

[0037] The image receiving module 110 is used to send an input image to the frame buffer 130 upon triggering a vertical synchronization signal, so as to store the input image in the frame buffer 130; wherein the vertical synchronization signal is sent to the image receiving module 110 by a signal source. The image display module 120 is used to read the input image stored in the frame buffer 130 to obtain an output image for display on the screen. The frame rate synchronization module 140 is used to determine the tear position range corresponding to the frame rates of the input and output images. The frame rate synchronization module 140 is also used to determine the first reading position of the image display module 120 in the frame buffer 130 at the input time of the vertical synchronization signal corresponding to the next frame input image. The frame rate synchronization module 140 is also used to adjust the speed at which the image display module 120 reads the input image stored in the frame buffer 130 according to the first reading position and the tear position range, so as to change the frame rate at which the display shows the output image.

[0038] The input image is the image data sent by the signal source to the image receiving module 110. In some embodiments, the input image includes image information and vertical synchronization signal information. After the signal source sends the input image to the image receiving module 110, the image receiving module 110 reads the vertical synchronization signal information in the input image while parsing the input image and sends the image information to the frame buffer 130. The image information can be the pixels contained in a frame of the input image.

[0039] The image receiving module 110 may include a transmitting module of the Mobile Industry Processor Interface (MIPI), such as a MIPI TX module.

[0040] The image display module 120 may include a MIPI receiving module, such as a MIPI RX module.

[0041] In some embodiments, the image receiving module 110 further includes a first image processing module, which is used to reduce the size of the received input image data to reduce the storage pressure of the frame buffer. The image display module 120 further includes a second image processing module, which is used to enlarge the received output image to restore the image quality of the output image.

[0042] Frame buffer 130 (FB) can be used to store valid pixel data of the input image.

[0043] Please see Figure 5 , Figure 5 This illustration shows a schematic diagram of another input and output image structure provided in an embodiment of this application. For example... Figure 5 As shown, Figure 5The horizontal axis in the figure represents time t. Figure 5 The vertical axis represents the position d of the input image stored in the frame buffer that the image display module reads. The green line represents output image 1, the blue line represents input image 2, and time a is the generation time of the vertical synchronization signal corresponding to input image 2. Position A is the first reading position of the image display module 120 in the frame buffer 130 at time a.

[0044] Please see Figure 5 and 6 , Figure 6 This illustration shows a schematic diagram of another input and output image structure provided in an embodiment of this application. For example... Figure 6 As shown, Figure 6 The horizontal axis in the figure represents time t. Figure 6 The vertical axis represents the position d of the input image stored in the frame buffer that the image display module reads. The green line represents output image 1, the blue line represents input image 2, and time a is the generation time of the vertical synchronization signal corresponding to input image 2. Position A is the first read position of the image display module 120 in the frame buffer 130 at time a. Figure 5 Middle position A and Figure 6 Position A can be used to increase the output speed of output image 1. Figure 6 The middle position A is relative to Figure 5 The value of position A increases.

[0045] Please see Figure 6 and 7 , Figure 7 This illustration shows a schematic diagram of yet another input and output image structure provided in an embodiment of this application. For example... Figure 7 As shown, Figure 7 The horizontal axis in the figure represents time t. Figure 7 The vertical axis represents the position d of the input image stored in the frame buffer that the image display module reads. The green line represents output image 1, the blue line represents input image 2, and time a is the generation time of the vertical synchronization signal corresponding to input image 2. Position A is the first read position of the image display module 120 in the frame buffer 130 at time a. Figure 5 Middle position A and Figure 7 Position A in the middle can be used to reduce the output speed of output image 1. Figure 6 The middle position A is relative to Figure 5 The value of position A decreases.

[0046] Therefore, the frame rate synchronization module 140 can ensure the continuity between each output frame by increasing or decreasing the output speed of the output image. However, simply adjusting the output speed of the output image to ensure continuity between each output frame may result in a desynchronization between the input and output images. That is, the image display module 120 reads the input image stored in the frame buffer 130 faster than the image receiving module 110 writes the input image into the frame buffer 130, resulting in screen tearing.

[0047] Based on the above, under the action of the vertical synchronization signal sent by the signal source, the image receiving module 110 starts to send an input image frame to the frame buffer 130. The frame buffer 130 starts to store the input image frame sent by the image receiving module 110. The read pointer of the image display module 120 moves in the storage space of the frame buffer 130 to read the input image stored in the frame buffer 130, thereby obtaining the output image for the display screen to display.

[0048] During this process, the frame rate synchronization module 140 determines whether the first reading position is within the tear position range based on the tear position range and the first reading position. When the frame rate synchronization module 140 determines that the first reading position is within the tear position range, it means that the progress of the image display module 120 reading the input image stored in the frame buffer 130 is keeping up with the progress of the image receiving module 110 writing the input image into the frame buffer 130, which will cause the input image and the output image to be out of sync, i.e., tearing will occur. At this time, the frame rate synchronization module 140 adjusts the speed at which the image display module 120 reads the input image stored in the frame buffer 130 to change the frame rate at which the display screen displays the output image, so that the frame rate synchronization module 140 can adjust the input image and the output image from an out-of-sync relationship to a synchronized relationship, thereby preventing tearing.

[0049] When the frame rate synchronization module 140 determines that the first reading position is not within the tear position range, it means that the progress of the image display module 120 in reading the input image stored in the frame buffer 130 will not catch up with the progress of the image receiving module 110 in writing the input image into the frame buffer 130. The input image and the output image are in a synchronized relationship, that is, there will be no tearing.

[0050] Therefore, the frame rate synchronization module 140 adjusts the speed at which the image display module 120 reads the input image stored in the frame buffer 130 to ensure that each frame of output image is continuous and that the input and output images are synchronized, thereby avoiding screen tearing. Compared with the prior art's solution using a dual frame buffer 130, this application uses a single frame buffer 130 and the frame rate synchronization module 140 adjusts the speed at which the image display module 120 reads the input image stored in the frame buffer 130. This ensures that each frame of output image is continuous and that the input and output images are synchronized, thus avoiding screen tearing and effectively reducing the cost of the chip 100.

[0051] It is worth noting that, in order to synchronize the input image and output image of chip 100, under certain circumstances, a portion of the input image sent by the signal source to the image receiving module 110 may be discarded. The discarded input image cannot be read by the image display module 120 and output to the display screen. In other words, the image display module 120 does not read each frame of input image written by the image receiving module 110 into the frame buffer 130.

[0052] Specific cases include situations where the frame rate of the input image is greater than the frame rate of the output image.

[0053] The frame rate of the input image refers to the number of input images received by the image receiving module within 1 second. For example, if the image receiving module receives 60 input images within 1 second, the frame rate is 60Hz.

[0054] The frame rate of the output image refers to the number of images output by the image display module within 1 second. For example, if the image display module outputs 60 input images within 1 second, the frame rate is 60Hz.

[0055] For example, when the frame rate of the input image is 90Hz and the frame rate of the output image is 60Hz, the image receiving module 110, triggered by three vertical synchronization signals, will send three frames of input image to the frame buffer 130 respectively. The image display module 120 will only read the two frames of input image written to the frame buffer 130 by the image receiving module 110, thus obtaining two frames of output image. That is to say, when the frame rate of the input image is 90Hz and the frame rate of the output image is 60Hz, one frame of the three input images will be discarded, thus obtaining two frames of output image.

[0056] For example, when the frame rate of the input image is 120Hz and the frame rate of the output image is 60Hz, the image receiving module 110, triggered by two vertical synchronization signals, will send two frames of input image to the frame buffer 130 respectively. The image display module 120 will only read the one frame of input image written to the frame buffer 130 by the image receiving module 110, thus obtaining one frame of output image. That is to say, when the frame rate of the input image is 120Hz and the frame rate of the output image is 60Hz, one frame of input image will be discarded, thus obtaining one frame of output image.

[0057] For example, when the frame rate of the input image is 60Hz and the frame rate of the output image is 60Hz, the image display module 120 will read each frame of the input image written into the frame buffer 130 by the image receiving module 110. That is to say, when the frame rate of the input image is 60Hz and the frame rate of the output image is 60Hz, each frame of the input image will not be discarded, and each frame of the input image will have a corresponding output image.

[0058] Furthermore, in some embodiments, the frame rate synchronization module 140 is also used to determine the target input image to be discarded among multiple input images based on the frame rates of the input image and the output image. The frame rate synchronization module 140 is also used to determine the synchronization region corresponding to the output image of the previous input image of the first input image based on two adjacent input images of the first input image in the target input image. The frame rate synchronization module 140 is also used to determine the tearing location range based on the synchronization region and the generation time of the vertical synchronization signal corresponding to the next input image of the first input image.

[0059] The synchronization region is the area where the output image corresponding to the previous input image of the first input image can be output. In other words, when the output image corresponding to the previous input image of the first input image is within the synchronization region, there is no asynchrony between the previous input image and its corresponding output image. Furthermore, when the output image corresponding to the previous input image of the first input image is within the synchronization region, it ensures that each output image is continuous.

[0060] In some implementations, the frame rate synchronization module 140 is used to determine the extreme position of the output image corresponding to the previous input image of the first input image read by the image display module 120 from the frame buffer 130 at the time the vertical synchronization signal corresponding to the next input image of the first input image is generated. The frame rate synchronization module 140 then determines the tearing position range based on the extreme position. That is, when the first read position of the output image corresponding to the previous input image of the first input image is within the tearing position range, the input image and the output image are out of sync, and the display screen will show tearing.

[0061] In some implementations, the frame rate synchronization module 140 is specifically used to determine the target input image among multiple input images when the frame rate of the input image is greater than the frame rate of the output image.

[0062] For example, the frame rate synchronization module 140 is further specifically used to determine the second frame of every two input images in a multi-frame input image as the target input image when the frame rate of the input image is 120Hz and the frame rate of the output image is 60Hz. As another example, the frame rate synchronization module is further specifically used to determine the second frame of every three input images in a multi-frame input image as the target input image when the frame rate of the input image is 90Hz and the frame rate of the output image is 60Hz.

[0063] For example, when the input image frame rate is 90Hz and the output image frame rate is 60Hz, one input image frame is discarded every three input images, resulting in two output images. For details, please refer to [link to relevant documentation]. Figure 8 , Figure 8 This illustration shows yet another structural diagram of an input image and an output image provided in an embodiment of this application. For example... Figure 8 As shown, Figure 8 The horizontal axis in the figure represents time t. Figure 8 The vertical axis in the graph represents the position d of the input image stored in the frame buffer read by the image display module. The blue line represents the input image, and the blue dashed line represents the first frame input image 1 in the target input images to be discarded. Input images 2 and 3 are the two adjacent input images of the first frame input image 1. The frame rate synchronization module 140 determines the synchronization region A of the output image corresponding to input image 2 (i.e., the synchronization region A is the area represented by the green line) based on input image 2 and input image 3. Time a is the generation time of the vertical synchronization signal corresponding to the next frame input image 3 after the first frame input image 1. At time a, the frame rate synchronization module 140 determines the extreme position b of the output image corresponding to the previous frame input image 2 of the first frame input image 1 read by the image display module 120 from the frame buffer 130.

[0064] Please continue to refer to Figure 8 When the frame rate synchronization module 140 reads the output image corresponding to the previous frame input image 2 of the first frame input image 1 in the frame buffer 130 at time a, the position of the output image will be less than the limit position b. Therefore, the output image corresponding to the previous frame input image 2 of the first frame input image 1 in the frame buffer 130 will have an intersection point with the next frame image of the first frame input image 1, resulting in tearing. Therefore, the tearing position range is [0, b].

[0065] For example, when the input image frame rate is 120Hz and the output image frame rate is 60Hz, one input image frame is discarded every two input image frames to obtain one output image frame. For details, please refer to... Figure 9 , Figure 9 This illustration shows a schematic diagram of yet another input and output image structure provided in an embodiment of this application. For example... Figure 9 As shown, Figure 9 The horizontal axis in the figure represents time t. Figure 9 The vertical axis in the graph represents the position d of the input image stored in the frame buffer read by the image display module. The blue line represents the input image, and the blue dashed line represents the first frame input image 1 in the target input images to be discarded. Input images 2 and 3 are the two adjacent input images of the first frame input image 1. The frame rate synchronization module 140 determines the synchronization region A of the output image corresponding to input image 2 (i.e., the synchronization region A is the area represented by the green line) based on input image 2 and input image 3. Time a is the generation time of the vertical synchronization signal corresponding to the next frame input image 3 after the first frame input image 1. At time a, the frame rate synchronization module 140 determines the extreme position b of the output image corresponding to the previous frame input image 2 of the first frame input image 1 read by the image display module 120 from the frame buffer 130.

[0066] Please continue to refer to Figure 9 When the frame rate synchronization module 140 reads the output image corresponding to the previous frame input image 2 of the first frame input image 1 in the frame buffer 130 at time a, the position of the output image will be less than the limit position b. Therefore, the output image corresponding to the previous frame input image 2 of the first frame input image 1 in the frame buffer 130 will have an intersection point with the next frame image of the first frame input image 1, resulting in tearing. Therefore, the tearing position range is [0, b].

[0067] In one specific embodiment, the frame rate synchronization module 140 is specifically used to ensure that when the frame rate of the input image is 120Hz and the frame rate of the output image is 60Hz, the tearing position range is [0, ...]. Wherein, VTT is the second read position after the image display module 120 has read a frame of output image stored in the frame buffer 130.

[0068] In another specific embodiment, the frame rate synchronization module 140 is specifically used to determine the tear position range as [0, ] when the frame rate of the input image is 90Hz and the frame rate of the output image is 60Hz. VTT].

[0069] After determining the tear position range, the frame rate synchronization module 140 can adjust the speed at which the image display module 120 reads the input image stored in the frame buffer 130 based on whether the first reading position is within the tear position range, thereby changing the frame rate of the display screen displaying the output image, so as to synchronize the input image and the output image of the chip.

[0070] As described above, when the frame rate synchronization module 140 determines that the first reading position is within the tear position range, it can increase or decrease the speed at which the image display module reads the input image stored in the frame buffer to synchronize the output image with the input image and to make each frame of the output image continuous. To further accelerate the adjustment of the speed at which the image display module reads the input image stored in the frame buffer, so as to quickly synchronize the output image with the input image.

[0071] In some implementations, the frame rate synchronization module 140 is further configured to divide the tear position range into a first tear position sub-range and a second tear position sub-range; specifically, when the first reading position is within the first tear position sub-range, the frame rate synchronization module 140 increases the speed at which the image display module reads the input image stored in the frame buffer; specifically, when the first reading position is within the second tear position sub-range, the frame rate synchronization module 140 decreases the speed at which the image display module reads the input image stored in the frame buffer.

[0072] The frame rate synchronization module 140 divides the tear position range into a first tear position sub-range and a second tear position sub-range. By determining whether the first reading position is within the first tear position sub-range or the second tear position sub-range, it quickly determines whether to increase the speed at which the image display module reads the input image stored in the frame buffer to synchronize the output image with the input image, or to decrease the speed at which the image display module reads the input image stored in the frame buffer to synchronize the output image with the input image. This allows the frame rate synchronization module 140 to quickly adjust the speed at which the image display module reads the input image stored in the frame buffer when it determines that the first reading position is within the tear position range, thus achieving rapid synchronization between the output image and the input image; that is, the speed of the input image will not be caught up by the speed of the output image.

[0073] In one specific embodiment, the first tear location sub-range is [ , ], the second tear position sub-range [0, ].

[0074] In another specific embodiment, the first tear location sub-range is [ , ], the second tear position sub-range [0, ].

[0075] As described above, the frame rate synchronization module 140 quickly adjusts the speed at which the image display module reads the input image stored in the frame buffer by determining that the first reading position is within the first tear position sub-range and the second tear position sub-range, thereby achieving rapid synchronization between the output image and the input image. When the frame rate of the input image changes, for example, the frame rate of multiple input images changes from 90Hz to 60Hz, or vice versa, the output image may become out of sync with the input image, leading to screen tearing.

[0076] Based on the above, in some embodiments, the frame rate synchronization module 140 is further configured to determine the target reading position corresponding to the current frame rate switch when the frame rate of the multi-frame input image switches from the first frame rate to the second frame rate; the frame rate synchronization module 140 is further configured to determine the first frame input image with the second frame rate in the multi-frame input image as the reference input image; the frame rate synchronization module 140 is further configured to adjust the speed at which the image display module reads the output image corresponding to the second frame input image with the second frame rate in the multi-frame input image when the target reading position is not equal to the reference reading position.

[0077] The reference reading position is the reading position of the output image corresponding to the previous frame input image in the multi-frame input images, which is stored in the frame buffer 130 at the time when the vertical synchronization signal corresponding to the reference input image is generated.

[0078] For example, the frame rate of the multi-frame input image is switched from 90Hz to 60Hz; see [link to relevant documentation]. Figure 10 , Figure 10 This illustration shows a schematic diagram of yet another input and output image structure provided in an embodiment of this application. For example... Figure 10 As shown, Figure 10 In the figure, the x-axis of 10a and 10b represents time t. Figure 10 The vertical coordinates of 10a and 10b in the diagram represent the position d of the input image stored in the frame buffer by the image display module. The blue lines in 10a and 10b represent the input image, and the green lines in 10a and 10b represent the output image, as shown below. Figure 10As shown in Figure a, at time a, the frame rate switches from 90Hz to 60Hz, synchronizing the input and output images, meaning there is no screen tearing. However, after the switch, the target reading position and the reference reading position are not equal. To make the target reading position equal to the reference reading position, the speed at which the image display module reads the output image corresponding to the second frame of the multi-frame input image with the second frame rate is adjusted, so that the target reading position is equal to the reference reading position. At time c, the relationship between the output image and the input image is adjusted so that the target reading position is equal to the reference reading position.

[0079] like Figure 10 As shown in b, when the frame rate is switched from 90Hz to 60Hz, the input image and the output image are synchronized, and the target reading position and the reference reading position are equal after the switch. That is, it is not necessary to adjust the speed at which the image display module reads the output image corresponding to the second frame input image with the second frame rate among multiple frames of input images.

[0080] For example, the frame rate of the multi-frame input image is switched from 60Hz to 90Hz; see [link to relevant documentation]. Figure 11 , Figure 11 This illustration shows a schematic diagram of another input and output image structure provided in an embodiment of this application. For example... Figure 11 As shown, Figure 11 The x-axis of 11a, 11b, and 11c in the figure represents time t. Figure 11 The vertical coordinates of 11a, 11b, and 11c represent the position d of the input image stored in the frame buffer read by the image display module. The blue lines in 11a, 11b, and 11c represent the input image, and the green lines in 11a, 11b, and 11c represent the output image, as shown below. Figure 11 As shown in Figure a, at time a, the frame rate switches from 60Hz to 90Hz, synchronizing the input and output images, meaning there is no screen tearing. The frame rate synchronization module 140 reduces the speed at which the image display module 120 reads the image data stored in the frame buffer 130, so that at time c, the relationship between the output and input images is adjusted so that the target reading position is equal to the reference reading position.

[0081] like Figure 11 As shown in b, at time a, the frame rate switches from 60Hz to 90Hz, and tearing occurs during the synchronization process between the input and output images. The frame rate synchronization module 140 increases the speed at which the image display module 120 reads the image data stored in the frame buffer 130, so that at time c, the relationship between the output and input images is adjusted so that the target reading position is equal to the reference reading position, thereby synchronizing the input and output images.

[0082] like Figure 11As shown in c, at time a, the frame rate switches from 60Hz to 90Hz. After the frame rate switch, the relationship between the output image and the input image is that the target reading position and the reference reading position are equal. Therefore, there is no need to adjust the relationship between the output image and the input image.

[0083] For example, the frame rate of the multi-frame input image is switched from 60Hz to 90Hz; see [link to relevant documentation]. Figure 12 , Figure 12 This illustration shows a schematic diagram of yet another input and output image structure provided in an embodiment of this application. For example... Figure 12 As shown, Figure 12 In the diagram, the horizontal axis of 12a and 12b represents time t. Figure 12 In the diagram, the vertical coordinates of 12a and 12b represent the position d of the input image stored in the frame buffer read by the image display module. The blue lines in 12a and 12b represent the input image, and the green lines represent the output image. At time a, the frame rate switches from 120Hz to 60Hz, synchronizing the input and output images, thus preventing screen tearing. By reducing the speed at which the image display module 120 reads the image data stored in the frame buffer 130, at time c, the relationship between the output and input images is adjusted so that the target reading position is equal to the reference reading position, thereby synchronizing the input and output images.

[0084] like Figure 12 As shown in b, at time a, the frame rate is switched from 120Hz to 60Hz, and the relationship between the input image and the output image has been adjusted so that the target reading position and the reference reading position are equal. Therefore, there is no need to adjust the relationship between the output image and the input image.

[0085] For example, the frame rate of the multi-frame input image is switched from 60Hz to 120Hz; see [link to relevant documentation]. Figure 13 , Figure 13 This illustration shows a structural diagram of another input image and output image provided in an embodiment of this application. For example... Figure 13 As shown, Figure 13 In the diagram, the x-axis of 13a and 13b represents time t. Figure 13 In the diagram, the vertical coordinates of 13a and 13b represent the position d of the input image stored in the frame buffer read by the image display module. The blue lines in 13a and 13b represent the input image, and the green lines represent the output image. At time a, the frame rate switches from 60Hz to 120Hz, synchronizing the input and output images, preventing screen tearing. By reducing the speed at which the image display module 120 reads the image data stored in the frame buffer 130, at time c, the relationship between the output and input images is adjusted so that the target read position is equal to the reference read position, thus synchronizing the input and output images.

[0086] like Figure 13 As shown in b, at time a, the frame rate is switched from 60Hz to 120Hz, and the relationship between the input image and the output image has been adjusted so that the target reading position and the reference reading position are equal. Therefore, there is no need to adjust the relationship between the output image and the input image.

[0087] In one specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 90Hz to 60Hz. VTT; where VTT is the second position of the image display module after reading one frame of the image.

[0088] In another specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 60Hz to 90Hz. VTT; where VTT is the second position of the image display module after reading one frame of the image.

[0089] In another specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 120Hz to 60Hz. VTT; where VTT is the second position of the image display module after reading one frame of the image.

[0090] In another specific embodiment, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image changes from 60Hz to 120Hz. VTT; where VTT is the second position of the image display module after reading one frame of the image.

[0091] Please see Figure 14 , Figure 14 This illustration shows a schematic diagram of a display device 200 provided in an embodiment of this application. The display device 200 includes: the aforementioned chip 100 and a display screen 210, specifically:

[0092] Chip 100 is used to send the output image to display screen 210, and display screen 210 is used to display the output image.

[0093] In some embodiments, a signal source 220 is also included, which is used to send an input image to the chip 100.

[0094] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the chip 100, display screen 210, and signal source 220 described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0095] The technical solution provided in this application includes a chip comprising: an image receiving module, an image display module, a frame buffer, and a frame rate synchronization module. The image receiving module, the frame buffer, and the image display module are connected sequentially, and the image receiving module and the image display module are also connected to the frame rate synchronization module. Specifically: the image receiving module is used to send an input image to the frame buffer under the triggering of a vertical synchronization signal, so as to store the input image in the frame buffer; the vertical synchronization signal is sent to the image receiving module by a signal source; the image display module is used to read the input image stored in the frame buffer to obtain an output image for display on the screen; the frame rate synchronization module is used to determine the tear position range corresponding to the frame rate of the input image and the output image; the frame rate synchronization module is also used to determine the first reading position of the image display module in the frame buffer at the input time of the vertical synchronization signal corresponding to the next frame input image; the frame rate synchronization module is also used to adjust the speed at which the image display module reads the input image stored in the frame buffer according to the first reading position and the tear position range, so as to change the frame rate at which the display shows the output image. Therefore, the frame rate synchronization module adjusts the speed at which the image display module reads the input image stored in the frame buffer according to the range of the first reading position and the tear position, so as to achieve continuous output image for each frame and synchronization between the input image and the output image under the premise of a single frame buffer.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A chip, characterized in that, The system includes an image receiving module, an image display module, a frame buffer, and a frame rate synchronization module. The image receiving module, the frame buffer, and the image display module are connected sequentially. The image receiving module and the image display module are also connected to the frame rate synchronization module, wherein: The image receiving module is used to send an input image to the frame buffer when triggered by a vertical synchronization signal, so as to store the input image in the frame buffer; the vertical synchronization signal is sent to the image receiving module by a signal source; The image display module is used to read the input image stored in the frame buffer to obtain an output image for display on the screen; The frame rate synchronization module is used to determine the tear position range corresponding to the frame rate of the input image and the output image; The frame rate synchronization module is also used to determine the input time of the vertical synchronization signal corresponding to the next frame of input image, and the first reading position of the image display module in the frame buffer; The frame rate synchronization module is further configured to adjust the speed at which the image display module reads the input image stored in the frame buffer based on the first reading position and the tear position range, so as to change the frame rate at which the display screen displays the output image.

2. The chip according to claim 1, characterized in that, The frame rate synchronization module is also used to determine the target input image to be discarded among multiple input images based on the frame rates of the input image and the output image; The frame rate synchronization module is further configured to determine the synchronization region corresponding to the output image corresponding to the previous frame of the first frame of the target input image based on the two adjacent frames of the first frame of the target input image. The frame rate synchronization module is further configured to determine the tear location range based on the synchronization region and the generation time of the vertical synchronization signal corresponding to the next frame input image of the first frame input image.

3. The chip according to claim 2, characterized in that, The frame rate synchronization module is specifically used to determine the target input image from the multiple input images when the frame rate of the input image is greater than the frame rate of the output image.

4. The chip according to claim 3, characterized in that, The frame rate synchronization module is further specifically used to determine the second frame of every two frames of input images in the multi-frame input images as the target input image when the frame rate of the input image is 120Hz and the frame rate of the output image is 60Hz. Alternatively, the frame rate synchronization module is further configured to determine the second frame of every three frames of input images in the multi-frame input images as the target input image when the frame rate of the input image is 90Hz and the frame rate of the output image is 60Hz.

5. The chip according to claim 1, characterized in that, The frame rate synchronization module is also used to divide the tear location range into a first tear location sub-range and a second tear location sub-range; The frame rate synchronization module is specifically used to increase the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the first tear position sub-range. The frame rate synchronization module is specifically used to reduce the speed at which the image display module reads the input image stored in the frame buffer when the first reading position is within the range of the second tear position.

6. The chip according to claim 5, characterized in that, The frame rate synchronization module is specifically configured such that when the frame rate of the input image is 120Hz and the frame rate of the output image is 60Hz, the tearing position range is [0, ...]. ]; Alternatively, the frame rate synchronization module is specifically configured such that when the frame rate of the input image is 90Hz and the frame rate of the output image is 60Hz, the tearing position range is [0, ...]. VTT], where VTT is the second read position after the image display module has read a frame of the output image stored in the frame buffer.

7. The chip according to claim 6, characterized in that, The first tear location sub-range is [ , ], the second tear position sub-range [0, ]; Alternatively, the first tear location sub-range is [ , ], the second tear position sub-range [0, ].

8. The chip according to claim 1, characterized in that, The frame rate synchronization module is also used to determine the target reading position corresponding to the current frame rate switch when the frame rate of the multi-frame input image is switched from the first frame rate to the second frame rate. The frame rate synchronization module is further configured to determine the first frame input image with a frame rate of the second frame rate among the multi-frame input images as the reference input image; The frame rate synchronization module is also used to adjust the speed at which the image display module reads the output image corresponding to the second frame input image with a frame rate of the second frame rate from the multi-frame input images when the target reading position is not equal to the reference reading position; Wherein, the reference reading position is the reading position of the output image corresponding to the previous frame input image in the multi-frame input images, where the image display module reads the reference input image stored in the frame buffer at the time when the vertical synchronization signal corresponding to the reference input image is generated.

9. The chip according to claim 8, characterized in that, The frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 90Hz to 60Hz. VTT; Alternatively, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 60Hz to 90Hz. VTT; Alternatively, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 120Hz to 60Hz. VTT; Alternatively, the frame rate synchronization module is specifically used to determine the target reading position when the frame rate of the multi-frame input image switches from 60Hz to 120Hz. VTT; Wherein, VTT is the second position after the image display module has read one frame of the output image.

10. A display device, characterized in that, Includes a chip and a display screen as described in any one of claims 1-9, wherein the chip is configured to send an output image to the display screen, and the display screen is configured to display the output image.

11. The display device according to claim 10, characterized in that, It also includes a signal source for sending an input image to the chip.

Images