Image sensing apparatus

Abstract

There is provided an image sensing apparatus including: a photoelectric element configured to receive a reset signal at a first end and connected to a sensing node at a second end; a reset transistor configured to reset the floating diffusion node at a first voltage; a capacitor disposed between the floating diffusion node and the sensing node; a driving transistor configured to generate a pixel signal from the charge generated by the photoelectric element based on a second voltage; and a selection transistor configured to provide a pixel signal to an external device, in which when the selection transistor is turned on, the reset transistor is turned off at a first time point, and the sensing node is reset by the reset signal at a second time point later than the first time point.

Description

[0001] This application is a divisional application of the Chinese patent application with the application date of June 3, 2020, application number 202010493188.3, ​​and invention name “Image Sensing Device”. Technical Field

[0002] Example embodiments of the present disclosure relate to an image sensing device. Background Art

[0003] An image sensing device is a type of semiconductor element that can convert optical information into electrical signals. Image sensing devices may include charge coupled device (CCD) image sensing devices and complementary metal-oxide semiconductor (CMOS) image sensing devices.

[0004] A CMOS image sensor (CIS) may include a plurality of pixels arranged in two dimensions. Each of the pixels may include, for example, a photodiode (PD). The photodiode may be used to convert incident light into an electrical signal.

[0005] Recently, with the development of computer and communication industries, the demand for image sensors with improved performance has increased in various fields such as digital cameras, video cameras, smart phones, game consoles, security cameras, medical micro cameras and robots. In addition, as semiconductor devices are highly integrated, image sensors are also more highly integrated. Summary of the invention

[0006] Example embodiments provide an image sensing apparatus that improves sensed image quality by improving dark level characteristics and performing reliable correlated double sampling (CDS).

[0007] According to one aspect of an example embodiment, there is provided an image sensing device, comprising: a photoelectric element configured to receive a reset signal at a first end and connected to a sensing node at a second end; a reset transistor configured to reset a floating diffusion node at a first voltage; a capacitor arranged between the floating diffusion node and the sensing node; a drive transistor configured to generate a pixel signal from charges generated by the photoelectric element based on a second voltage; and a selection transistor configured to provide the pixel signal to an external device, wherein when the selection transistor is turned on, the reset transistor is turned off at a first time point, and the sensing node is reset by the reset signal at a second time point later than the first time point.

[0008] According to another aspect of an example embodiment, there is provided an image sensing device, comprising: a pixel array including at least one pixel; and a timing generator configured to provide a first reset signal, a second reset signal, and a selection signal to the pixel array, wherein each of the at least one pixel comprises: a photoelectric element configured to reset a storage node connected to a first end based on a first reset signal received at a second end; a reset transistor gated to the second reset signal and configured to reset a floating diffusion node; a capacitor arranged between the storage node and the floating diffusion node; a drive transistor configured to generate a pixel signal based on a charge generated by the photoelectric element; and a selection transistor gated to the selection signal and configured to output the pixel signal to an external device, and wherein the timing generator is configured to first disable the second reset signal when the selection signal is enabled, and then enable the first reset signal.

[0009] According to yet another aspect of the example embodiments, there is provided an image sensing device, comprising: a first circuit configured to generate a first pixel signal based on charges generated by a first photoelectric element using three transistors, and configured to output the first pixel signal to a first comparator; a second circuit configured to generate a second pixel signal based on charges generated by a second photoelectric element using four transistors, and configured to output the second pixel signal to a second comparator; and a ramp signal generator configured to provide a first ramp signal to the first comparator, and configured to provide a second ramp signal to the second comparator, wherein during a sensing period of the first pixel signal and the second pixel signal, the ramp signal generator is configured to provide the first ramp signal to the first comparator, wherein a first pulse of a first size and a second pulse of a second size greater than the first size are sequentially applied to the first ramp signal, and configured to provide the second ramp signal to the second comparator, wherein a third pulse of a third size and a fourth pulse of a fourth size greater than the third size are sequentially applied to the second ramp signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an image sensing device according to an example embodiment;

[0012] Figure 2 is a diagram showing a conceptual layout of an image sensing device according to an example embodiment;

[0013] Figure 3 is with Figure 1 A block diagram of a pixel array and an analog-to-digital converter;

[0014] Figure 4 yes Figure 3 A unit pixel circuit diagram included in a pixel array;

[0015] Figure 5 It is shown Figure 4 The diagram of the capacitor;

[0016] Figure 6 It is shown Figure 4 a timing diagram of the operation of the circuit;

[0017] Figures 7 to 10 It is shown Figure 4 a schematic diagram of the operation of the circuit;

[0018] Fig.11 It is shown Figure 3 A timing diagram of the operation of the analog-to-digital converter;

[0019] Figures 12 to 15 is a diagram showing the effect of an image sensing device according to the related art;

[0020] Fig.16 is a unit pixel circuit diagram of an image sensing device according to an example embodiment;

[0021] Fig.17 It is shown Fig.16 a timing diagram of the operation of the circuit;

[0022] Fig.18 is to show where Fig.16 A diagram showing an operation of comparing a pixel signal output by a circuit with a ramp signal;

[0023] Fig.19 is a circuit diagram of a pixel array of an image sensing device according to example embodiments; and

[0024] Fig. 20 is a diagram illustrating an operation of an image sensing apparatus according to example embodiments. DETAILED DESCRIPTION

[0025] Figure 1 is a block diagram of an image sensing apparatus according to example embodiments.

[0026] refer to Figure 1 , the image sensing device 100 may include a control register block 110 , a timing generator 120 , a row driver 130 , a pixel array 140 , an analog-digital converter (ADC) 150 , a ramp signal generator 160 , and a buffer 170 .

[0027] The control register block 110 may generally control the operation of the image sensing device 100. In particular, the control register block 110 may directly send operating signals to the timing generator 120, the ramp signal generator 160, and the buffer 170.

[0028] The timing generator 120 may generate a signal used as a reference for operation timing of various constituent elements of the image sensing device 100. The operation timing reference signal generated by the timing generator 120 may be transmitted to the row driver 130, the analog-to-digital converter 150, the ramp signal generator 160, and the like.

[0029] The ramp signal generator 160 may generate and transmit a ramp signal used in the analog-to-digital converter 150. For example, the analog-to-digital converter 150 may include a correlated double sampler (CDS), a comparator, etc. The ramp signal generator 160 may generate and transmit a ramp signal for a correlated double sampler (CDS), a comparator, etc.

[0030] The buffer 170 may include, for example, a latch unit. The buffer 170 may temporarily store an image signal to be provided to the outside, and may transmit the image data to an external memory or an external device.

[0031] The pixel array 140 may sense an external image. The pixel array 140 may include a plurality of pixels or unit pixels. The row driver 130 may selectively activate a row in the pixel array 140.

[0032] The analog-to-digital converter 150 may sample a pixel signal provided from the pixel array 140 , compare the pixel signal with a ramp signal, and then convert analog image data into digital image data based on a result of the comparison.

[0033] Although the drawings show that the analog-to-digital converter 150 includes a correlated double sampler (CDS), the embodiment is not limited thereto. According to example embodiments, the correlated double sampler (CDS), a comparator, etc. may be implemented as a logic circuit separate from the analog-to-digital converter 150 .

[0034] Figure 2 is a diagram illustrating a conceptual layout of an image sensing device according to example embodiments.

[0035] refer to Figure 2 , the image sensing device 100 may include a first region S1 and a second region S2 stacked in a first z-axis direction (eg, a vertical direction). As shown in the figure, the first region S1 and the second region S2 may extend in a second x-axis direction and a third y-axis direction, and Figure 1 The blocks shown in FIG. 1 may be arranged in the first region S1 and the second region S2 .

[0036] According to an example embodiment, a third area in which a memory is arranged may be arranged below the second area S2. The memory arranged in the third area may receive image data sent from the first area S1 and the second area S2, store or process the image data, and resend the image data to the first area S1 and the second area S2. The memory may include memory elements, such as dynamic random access memory (DRAM) elements, static random access memory (SRAM) elements, spin transfer torque magnetic random access memory (STT-MRAM) elements, and flash memory elements. For example, when the memory includes a DRAM element, the memory may receive the sent image data at a relatively high speed and process the image data.

[0037] The first region S1 includes a pixel array region PA and a first peripheral region PH1, and the second region S2 may include a logic circuit region LC and a second peripheral region PH2. The first region S1 and the second region S2 may be sequentially stacked in a first z-axis direction.

[0038] In the first region S1, the pixel array region PA may be a region in which the pixel array 140 ( Figure 1 The pixel array region PA may include a plurality of unit pixels PX ( Figure 4 ). Each pixel PX may include a photodiode and a transistor. A more specific explanation thereof will be described later.

[0039] The first peripheral area PH1 may include a plurality of pads and may be arranged around the pixel array area PA. The plurality of pads may transmit and receive electrical signals to and from an external device or the like.

[0040] In the second region S2, the logic circuit region LC may include electronic components including a plurality of transistors. The electronic components included in the logic circuit region LC may be electrically connected to the pixel array region PA to provide a constant signal or a control output signal to each unit pixel PX of the pixel array region PA.

[0041] For example, refer to Figure 1 The control register block 110, the timing generator 120, the row driver 130, the analog-to-digital converter 150, the ramp signal generator 150, the buffer 170, etc. described above may be arranged in the logic circuit region LC. For example, in the logic circuit region LC, Figure 1 Elements outside the pixel array 140 in.

[0042] The second peripheral area PH2 of the second area S2 may be disposed in an area corresponding to the first peripheral area PH1 of the first area S1. However, the embodiment is not limited thereto.

[0043] Figure 3 is with Figure 1 A block diagram of a pixel array 140 and an analog-to-digital converter 150 is shown.

[0044] refer to Figure 3 , the pixel array 140 may include a plurality of pixels PX (i, j). The plurality of pixels PX (i, j) may be arranged in a plurality of rows i and a plurality of columns j. A row line may be arranged for each of the plurality of rows i, and a column line may be arranged for each of the plurality of columns j. Each pixel PX (i, j) may be selected by selecting signals SEL (i), SEL (i+1) and SEL (i+2) to output pixel signals VO (j), VO (j+1) and VO (j+2).

[0045] The analog-to-digital converter 150 may include a plurality of comparators 152(j), 152(j+1), and 152(j+2) and a plurality of counters 154(j), 154(j+1), and 154(j+2) respectively connected to a plurality of columns j of the pixel array 140. The analog-to-digital converter 150 may perform correlated double sampling and analog-to-digital conversion operations, for example, through the plurality of comparators 152(j), 152(j+1), and 152(j+2) and the plurality of counters 154(j), 154(j+1), and 154(j+2).

[0046] The ramp signal generator 160 may generate a ramp signal VR. The ramp signal VR is a signal for converting pixel signals VO(j), VO(j+1), and VO(j+2) as analog signals into digital signals OD(j), OD(j+1), and OD(j+2), and may have, for example, a triangular waveform.

[0047] The ramp signal generator 160 may generate a ramp signal VR in response to a ramp enable signal R_EN generated by the control register block 110. According to an example embodiment, the ramp signal generator 160 may control the ramp signal VR by causing a pulse to be generated in the ramp signal VR according to a voltage drop during a segment in which the ramp enable signal R_EN is enabled. However, the embodiment is not limited thereto.

[0048] The ramp signal VR generated by the ramp signal generator 160 may be provided to the corresponding comparators 152(j), 152(j+1), and 152(j+2). Each of the comparators 152(j), 152(j+1), and 152(j+2) may correspond one-to-one to the column line j of one pixel PX(i, j).

[0049] The comparators 152(j), 152(j+1), and 152(j+2) may compare the ramp signal VR with the pixel signals VO(j), VO(j+1), and VO(j+2). Specifically, the comparators 152(j), 152(j+1), and 152(j+2) may compare the ramp signal VR with the reset voltages of the pixel signals VO(j), VO(j+1), and VO(j+2), and may compare the ramp signal VR with the signal voltages of the pixel signals VO(j), VO(j+1), and VO(j+2). A detailed description thereof will be described later.

[0050] According to an example embodiment, comparators 152(j), 152(j+1), and 152(j+2) compare the ramp signal VR with the pixel signals VO(j), VO(j+1), and VO(j+2), and may output a comparison signal corresponding to the result of the comparison. The comparison signal may be a binary signal indicating which of the ramp signal VR and the pixel signals VO(j), VO(j+1), and VO(j+2) is greater. For example, when the ramp signal VR is greater than the pixel signals VO(j), VO(j+1), and VO(j+2), "1" may be output, and when the pixel signals VO(j), VO(j+1), and VO(j+2) are greater than the ramp signal VR, "0" may be output. Alternatively, it may also be configured to output the comparison signal inversely.

[0051] Each of the counters 154(j), 154(j+1), and 154(j+2) may correspond one-to-one to the comparators 152(j), 152(j+1), and 152(j+2). That is, one comparison signal may be counted by one of the counters 154(j), 154(j+1), and 154(j+2). However, the embodiment is not limited thereto.

[0052] Based on the time point when the ramp enable signal R_EN is enabled or based on the time point when another counter signal is enabled, the counters 154(j), 154(j+1), and 154(j+2) can count how long the comparison signals output by the comparators 152(j), 152(j+1), and 152(j+2) maintain the same value. In addition, digital signals OD(j), OD(j+1), and OD(j+2) of the pixel signals VO(j), VO(j+1), and VO(j+2) as analog signals can be output based on the count result of the count.

[0053] Figure 4 yes Figure 3 Schematic diagram of a unit pixel circuit included in the pixel array 140.

[0054] refer to Figure 4 , the pixel PX may include a photoelectric element PD, a reset transistor RT, a driving transistor DT, a selection transistor ST, and a capacitor C.

[0055] Figure 4 The circuit shown may be a three transistor (3T) pixel circuit in which a photoelectric element PD arranged in a unit pixel PX outputs charges generated by sensing an external image as a pixel signal VO using three transistors.

[0056] The gate terminal of the driving transistor DT is connected to the floating diffusion node FD, and the charge generated by the photoelectric element PD can be transferred to the floating diffusion node FD through the storage node SN. The driving transistor DT can operate as a source follower buffer amplifier by the charge transferred to the floating diffusion node FD. That is, the driving transistor DT can amplify the charge generated by the photoelectric element PD and transferred to the floating diffusion node FD using the pixel voltage VPIX, and can transfer the charge to the selection transistor ST.

[0057] The selection transistor ST can be connected through the row driver 130 ( Figure 1 ) is turned on by the selection signal SEL provided, and switching and addressing operations can be performed. When the selection signal SEL is applied from the row driver, the pixel signal VO can be output to the column line connected to the selection transistor ST. Figure 1 ) detects pixel signal VO.

[0058] The reset transistor RT can be reset by the row driver 130 ( Figure 1 ) is turned on by a reset signal RG inputted from the pixel. When the reset transistor RT is turned on by the reset signal RG, the floating diffusion node FD may be reset to the pixel voltage VPIX.

[0059] According to an example embodiment, the reset transistor RT and the driving transistor DT are shown as each being supplied with the pixel voltage VPIX, but the embodiment is not limited thereto. The voltage supplied to the reset transistor RT and the driving transistor DT may be modified to be different from Figure 4 For example, in example embodiments, a read voltage may be provided to the reset transistor RT, and a power supply voltage may be applied to the drive transistor DT.

[0060] The photoelectric element PD may generate charges by sensing an external image or light. In example embodiments, the photoelectric element PD may include an organic photodiode.

[0061] When the photoelectric element PD is an organic photodiode, the photoelectric element PD may include first and second electrodes arranged in parallel with each other, and an organic light conversion layer may be provided between the first and second electrodes, and the organic light conversion layer may generate charges by receiving light of a predetermined wavelength band.

[0062] The storage reset signal VPD may be provided to the cathode of the photoelectric element PD, and the anode of the photoelectric element PD may be connected to the storage node SN. As will be described in more detail later, the storage reset signal VPD is a variable signal in which an enable segment and a disable segment are repeated. When the storage reset signal VPD is enabled, the storage node SN may be reset. That is, the storage reset signal VPD may reset the storage node SN by moving the charge of the storage node SN according to the signal level.

[0063] The photoelectric element PD may be, for example, a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof, but the embodiment is not limited thereto.

[0064] The capacitor C may be disposed between the storage node SN and the floating diffusion node FD. Based on the capacitor C, the storage node SN and the floating diffusion node FD may not be reset at the same time, and the dark level characteristics of the image sensing device may be improved. A detailed description thereof will be described later.

[0065] In example embodiments, the capacitor C may include, for example, a capacitor used in a DRAM. Figure 5 Give a more specific description.

[0066] Figure 5 It is shown Figure 4 Schematic diagram of a capacitor.

[0067] refer to Figure 5 , the capacitor C may include a top electrode TE, a bottom electrode BE and a dielectric film DE.

[0068] In example embodiments, in order to maximize the storage capacity of the capacitor C, the top electrode TE and the bottom electrode BE may be formed in a cylindrical shape, and the dielectric film DE may be disposed therebetween.

[0069] For example, Figure 5 As shown, the top electrode TE and the bottom electrode BE of the capacitor C may be formed in a hollow cylindrical shape and face each other with the dielectric film DE interposed therebetween. The dielectric film DE may be formed in a conformal form along the surface of the bottom electrode BE.

[0070] The dielectric film DE may include, for example, oxide-nitride, oxide-nitride-oxide, metal oxide, etc. In example embodiments, the dielectric film DE may include a hafnium oxide film (eg, HfO 2 ), but embodiments are not limited thereto.

[0071] The top electrode TE and the bottom electrode BE may include, for example, polysilicon, metal, metal nitride, etc. In example embodiments, the top electrode TE may include a titanium nitride film (eg, TiN), but embodiments are not limited thereto.

[0072] In an example embodiment, the capacitor C may be arranged at Figure 2 In the pixel array area PA. That is, the capacitor C may be disposed on the same layer as the photoelectric element PD. However, the embodiment is not limited thereto, and the position where the capacitor C is disposed may be changed.

[0073] In the following, reference will be made to Figures 6 to 10 The operation of the unit pixel PX circuit is described.

[0074] Figure 6 It is shown Figure 4 Timing diagram of the circuit's operation. Figures 7 to 10 It is shown Figure 4 Diagram of the operation of the circuit.

[0075] Figure 6 is a diagram showing a waveform of a signal applied to a unit pixel during one sensing period and a change in a charge level of each node. Figure 6 The storage reset signal VPD, reset signal RG, selection signal SEL, etc. shown in FIG. 1 can be obtained from, for example, a control register block 110 ( Figure 1 ) controlled timing generator 120( Figure 1 However, the embodiments are not limited thereto.

[0076] First, refer to Figure 6 and 7At the first time point T1, the storage reset signal VPD changes from a logic high level (H level) to a logic low level (L level). That is, the storage reset signal VPD may be enabled. Therefore, the charge of the storage node SN may be released, and the storage node SN may be reset.

[0077] On the other hand, the reset signal RG can remain at the H level. That is, the reset signal RG can remain enabled. When the reset signal RG remains at the H level, the reset transistor RT ( Figure 4 ) maintains the on state, and therefore, the pixel voltage VPIX can be supplied to the floating diffusion node FD. Therefore, the floating diffusion node FD maintains the state of being reset to the pixel voltage VPIX.

[0078] The selection signal SEL may be maintained at an L level. That is, the selection signal SEL may be maintained in a disabled state. Therefore, the selection transistor ST ( Figure 4 ) remains in the off state. As a result, the pixel signal VO is not output to the outside ( Figure 4 ).

[0079] Next, refer to Figure 6 and Figure 8 At the second time point T2, the storage reset signal VPD changes from the L level to the H level. That is, the storage reset signal VPD is disabled. Therefore, the charges generated from the photoelectric element PD are accumulated in the storage node SN.

[0080] On the other hand, although the pixel voltage VPIX is supplied to the floating diffusion node FD, since the floating diffusion node FD and the storage node SN are separated by the capacitor C, the charges generated from the photo element PD are accumulated in the storage node SN.

[0081] Next, refer to Figure 6 and Fig. 9 At the third time point T3, the reset signal RG changes from the H level to the L level while the storage reset signal VPD is maintained at the H level. That is, while the storage reset signal VPD is disabled, the reset signal RG is disabled.

[0082] When the reset signal RG is disabled, the reset transistor RT ( Figure 4 ) is turned off, and the floating diffusion node FD floats. However, due to element characteristics, the charge level of the floating diffusion node FD decreases by the first level d1.

[0083] On the other hand, before the third time point T3, the selection signal SEL may have changed from the L level to the H level. That is, at the third time point T3, the selection signal SEL is already in the enabled state. As a result, the driving transistor DT outputs the charge level of the floating diffusion node FD as the pixel signal VO to the outside using the pixel voltage VPIX. At this time, since the charge level of the floating diffusion node FD is a level lowered by the first level d1 from the pixel voltage VPIX, the pixel signal VO output from the pixel PX can be a reset voltage VRST lowered by the first level d1 from the reference voltage.

[0084] Next, refer to Figure 6 and 10 At the fourth time point T4, the storage reset signal VPD turns to the L level. That is, the storage reset signal VPD is enabled.

[0085] When the storage reset signal VPD is enabled, the storage node SN is reset, and the charge level of the floating diffusion node FD decreases by the charge accumulated in the storage node SN by the capacitor C. That is, the charge level of the floating diffusion node FD decreases by the second level d2 due to the influence of the storage node SN.

[0086] On the other hand, since the selection signal SEL remains enabled at the fourth time point T4, the driving transistor DT outputs the charge level of the floating diffusion node FD as the pixel signal VO to the outside using the pixel voltage VPIX. At this time, since the charge level of the floating diffusion node FD is a level lowered by the second level d2 from the pixel voltage VPIX, the pixel signal VO output from the pixel PX can be a signal voltage VSIG lowered by the second level d2 from the reference voltage.

[0087] Thereafter, at a fifth time point T5, the storage reset signal VPD transitions to the H level, and the reset signal RG transitions to the H level. That is, the storage reset signal VPD is disabled, and the reset signal RG is enabled.

[0088] Thereafter, by repeating the above-described operations, the unit pixel PX may generate and output a pixel signal VO from the charges generated by the photoelectric element PD.

[0089] refer to Figure 6 Since the charge generated by the photoelectric element PD is accumulated in the storage node SN from the second time point T2 when the storage node SN is first reset to the fourth time point T4 when the storage node SN is reset again, an effective accumulation time EIT can be formed from the second time point T2 to the fourth time point T4. In addition, since the reset voltage VRST and the signal voltage VSIG are in the selection transistor ST ( Figure 4) is output to the outside in the form of a pixel signal VO when it is turned on, so the segment in which the selection signal SEL maintains the H level can be a sensing period of 1H.

[0090] In the following, reference will be made to Fig.11 The operation of the analog-to-digital converter in which the pixel signal VO output from the pixel PX is converted into a digital signal is described.

[0091] Fig.11 It is shown Figure 3 The operation of the analog-to-digital converter described below is merely an example, and its detailed configuration may be modified.

[0092] refer to Figure 3 and Fig.11 , the ramp signal generator 160 can provide a ramp signal VR to the comparator 152 (j), wherein during one sensing period 1H, a first pulse P1 having a size reduced from a reference voltage by a first level dV1 and a second pulse P2 having a size reduced from a reference voltage by a second level dV2 are sequentially applied to the ramp signal VR.

[0093] Specifically, the ramp signal generator 160 sequentially generates a first pulse P1 having a first size and a second pulse P2 having a second size greater than the first size as a ramp signal VR in response to the ramp enable signal R_EN during one sensing period 1H, and may provide the ramp signal VR to the comparator 152j.

[0094] The comparator 152 j compares the ramp signal VR with the pixel signal VO from a specific time point (eg, a time point when the comparator 152 j is enabled), and may output the comparison result as a comparison signal COM to the counter 154 j.

[0095] The counter 154 j may count the comparison signal COM to convert the pixel signal VO into a digital signal.

[0096] That is, the image sensing device 100 ( Figure 1 ) has a 3T structure in which a unit pixel PX generates a pixel signal VO using three transistors, and compares the pixel signal VO generated in the 3T structure with a ramp signal VR to output digital image data, wherein a first pulse P1 having a first size and a second pulse P2 having a second size greater than the first size are sequentially applied to the ramp signal VR.

[0097] Figures 12 to 15 is a diagram illustrating the effect of an image sensing device according to the related art.

[0098] Fig.12 It is different from the above reference Figure 4 A circuit diagram of a unit pixel PXb of an image sensing device 999 of an example embodiment is described.

[0099] refer to Fig.12 , the pixel PXb may include a photoelectric element PDb, a reset transistor RTb, a driving transistor DTb, and a selection transistor STb. The circuit shown may be a 3T pixel circuit, in which the photoelectric element PDb arranged in the unit pixel PXb accumulates charges generated by sensing an external image in a floating diffusion node FDb using three transistors, and outputs the accumulated charges as a pixel signal VOb.

[0100] Fig.13 It is shown Fig.12 Timing diagram of the circuit's operation.

[0101] refer to Fig.12 and 13 ,exist Fig.12 In the circuit of FIG. 1 , since the pixel signal VOb outputted from the unit pixel PXb during one sensing period 1H includes the nth sensing voltage VSIG(n) and the n+1th reset voltage VRST(n+1), it is different from the above reference voltage VSIG(n). Figure 4 In the example embodiments described above, accurate correlated double sampling is difficult. Figure 4 The example embodiments described herein are as follows: Fig.12 Compared with the circuit of , correlated double sampling with higher reliability is possible.

[0102] In addition, Fig.12 In the case of a circuit of FIG. 1 , during the effective accumulation time EIT for accumulating the charges generated in the photoelectric element PDb, as Fig.14 As shown, leakage LK of charges from the floating diffusion node FDb to the P-type substrate P-SUB occurs, and therefore, the dark level characteristics of the image sensing device 999 may deteriorate.

[0103] On the other hand, referring to the above Figure 4 In the case of the exemplary embodiments described, Fig.15 As shown, during the effective accumulation time EIT for accumulating the charges generated in the photoelectric element PD, since the charges are stored in the storage node SN separated from the floating diffusion node FD by the capacitor C, no leakage of the charges from the floating diffusion node FD to the P-type substrate P-SUB occurs. Therefore, the dark level characteristics of the image sensing device 100 are improved, and the quality of the sensed image can be improved.

[0104] In the following, reference will be made to Fig.16 and 17An image sensing device according to an example embodiment is described. Hereinafter, repeated descriptions of the above-described embodiments will be omitted, and differences will be mainly described.

[0105] Fig.16 is a unit pixel circuit diagram of an image sensing device according to example embodiments.

[0106] refer to Fig.16 , the pixel PX1 may include a photoelectric element PD1, a reset transistor RT1, a driving transistor DT1, a selection transistor ST1, and a capacitor C1.

[0107] The gate terminal of the driving transistor DT1 is connected to the floating diffusion node FD1, and the charge generated by the photoelectric element PD1 can be transferred to the floating diffusion node FD1 through the storage node SN1. The driving transistor DT1 can operate as a source follower buffer amplifier by the charge transferred to the floating diffusion node FD1. That is, the driving transistor DT1 can amplify the charge generated by the photoelectric element PD1 and transferred to the floating diffusion node FD1 using the pixel voltage VPIX, and can transfer the charge to the selection transistor ST1.

[0108] The selection transistor ST1 may be turned on by the selection signal SEL and may perform switching and addressing operations. When the selection signal SEL1 is applied from the row driver, the pixel signal VO1 may be output to the column line connected to the selection transistor ST1.

[0109] The reset transistor RT1 may be turned on by the reset signal RG1. When the reset transistor RT1 is turned on by the reset signal RG1, the floating diffusion node FD1 may be reset to the bias voltage VBIAS. In example embodiments, the bias voltage VBIAS may be less than the pixel voltage VPIX.

[0110] The storage reset signal VPD1 may be provided to an anode of the photo element PD1 , and a cathode of the photo element PD1 may be connected to the storage node SN1 .

[0111] The capacitor C1 may be disposed between the storage node SN1 and the floating diffusion node FD1 .

[0112] Fig.17 It is shown Fig.16 A timing diagram of the operation of the circuit.

[0113] refer to Fig.16 and 17 At the first time point T11, the storage reset signal VPD1 changes from the L level to the H level. That is, the storage reset signal VPD1 is enabled. As a result, the storage node SN1 may be fully charged. That is, the storage node SN1 may be reset.

[0114] The reset signal RG1 can maintain the H level unchanged. That is, the reset signal RG1 can remain enabled. When the reset signal RG1 maintains the H level, the reset transistor RT1 ( Fig.16 ) maintains the on state, and the bias voltage VBIAS can be provided to the floating diffusion node FD1 accordingly. Therefore, the floating diffusion node FD1 maintains the state of being reset to the bias voltage VBIAS.

[0115] The selection signal SEL1 may be maintained at an L level. That is, the selection signal SEL1 may be maintained in a disabled state. Therefore, the selection transistor ST1 ( Fig.16 ) remains in the off state. As a result, the pixel signal VO1 ( Fig.16 ) is not output externally.

[0116] Next, at the second time point T12, the storage reset signal VPD1 changes from the H level to the L level. That is, the storage reset signal VPD1 is disabled. As a result, the charge level of the storage node SN1 is lowered by the photoelectric element PD1.

[0117] Although the floating diffusion node FD1 is provided with the bias voltage VBIAS, since the floating diffusion node FD1 and the storage node SN1 are separated by the capacitor C1 , only the charge level of the storage node SN1 is lowered by the photoelectric element PD.

[0118] Thereafter, in a state where the storage reset signal VPD1 maintains the L level at the third time point T13, the reset signal RG1 transitions from the H level to the L level. That is, in a state where the storage reset signal VPD1 is disabled, the reset signal RG1 is disabled.

[0119] When the reset signal RG1 is disabled, the reset transistor RT1 ( Fig.16 ) is turned off, and the floating diffusion node FD1 floats. However, due to element characteristics, the charge level of the floating diffusion node FD1 decreases by the first level D1.

[0120] Before the third time point T13, the selection signal SEL1 may have changed from the L level to the H level. That is, the selection signal SEL1 is in an enabled state before the third time point T13. As a result, the driving transistor DT1 outputs the charge level of the floating diffusion node FD1 as the pixel signal VO1 to the outside using the pixel voltage VPIX. At this time, since the charge level of the floating diffusion node FD1 is a level reduced by the first level d1 from the bias voltage VBIAS, the pixel signal VO1 output from the pixel PX1 can be a reset voltage VRST reduced by the first level d1 from the reference voltage.

[0121] Thereafter, at a fourth time point T14, the storage reset signal VPD1 is turned to the H level. That is, the storage reset signal VPD1 is enabled.

[0122] When the storage reset signal VPD1 is enabled, the storage node SN1 is reset and the charge level of the floating diffusion node FD1 decreases by the charge accumulated in the storage node SN1 by the capacitor C1. That is, due to the influence of the storage node SN1, the charge level of the floating diffusion node FD1 increases by a second level d2 compared to the bias voltage VBIAS.

[0123] When the selection signal SEL1 remains enabled at the fourth time point T14, the driving transistor DT1 outputs the charge level of the floating diffusion node FD1 as the pixel signal VO1 to the outside using the pixel voltage VPIX1. At this time, since the charge level of the floating diffusion node FD1 is a level increased by the second level d2 from the bias voltage VBIAS, the pixel signal VO1 output from the pixel PX1 can be a signal voltage VSIG increased by the second level d2 from the reference voltage.

[0124] Thereafter, at the fifth time point T15, the storage reset signal VPD1 turns to the L level, and the reset signal RG1 turns to the H level. That is, the storage reset signal VPD1 is disabled, and the reset signal RG1 is enabled. Thereafter, by repeating the above operation, the unit pixel PX1 can generate and output the pixel signal VO1 based on the information sensed by the photoelectric element PD1.

[0125] Hereinafter, since the process of generating a digital image signal based on the generated pixel signal VO1 has been described above, a repeated description will not be provided.

[0126] In the following, reference will be made to Fig.18 An operation in which the pixel signal VO1 output from the pixel PX1 is compared with the ramp signal is described.

[0127] Fig.18 is to show where Fig.16 A diagram of the operation of comparing the pixel signal output by the circuit with the ramp signal.

[0128] refer to Fig.18 , the ramp signal VR1 according to an exemplary embodiment may include a first pulse P1 having a size increased from a reference voltage by a first level dV1, and a second pulse P2 applied after the first pulse P1 and having a size increased from the reference voltage by a second level dV2.

[0129] In an example embodiment, if Fig.18As shown, the size of the second pulse P2 can be greater than the size of the first pulse P1. The comparator compares the ramp signal VR1 with the pixel signal VO1 and outputs the comparison result of the comparison to the counter as a comparison signal. The counter can count the comparison signal to convert the pixel signal VO1 into a digital signal. Since the description of the corresponding operation has been given above, a repeated description will not be provided.

[0130] Fig.19 is a circuit diagram of a pixel array of an image sensing device according to example embodiments.

[0131] refer to Fig.19 , the image sensing device 300 may include a plurality of pixel groups PG.

[0132] Pixels PX11 to PX14 adjacent to each other may provide a pixel group PG, and the pixel group PG may include, for example, four pixels PX11 to PX14 arranged in a 2×2 matrix form. Each of the four pixels PX11 to PX14 included in the pixel group PG may include a first circuit and a second circuit.

[0133] Each of the first circuits included in the pixel group PG may be connected to a corresponding one of the first photo elements OPD1 to OPD4 including an organic photodiode to generate a first pixel signal VOpix. A storage reset signal VPD may be provided at one end of the first photo elements OPD1 to OPD4.

[0134] Each of the second circuits included in the pixel group PG can be connected to a corresponding one of the second photo elements SPD1 to SPD4 including, for example, semiconductor photodiodes to generate a second pixel signal VSpix. The first pixel signal VOPix and the second pixel signal VSpix can be output through the first column line OC0 and the second column line SC0, respectively.

[0135] The first circuit included in each of the pixels PX11 to PX14 may be implemented as a 3T circuit including three transistors.

[0136] For example, the first circuit included in the first pixel PX1 may include a reset transistor OR1, a drive transistor OD1, a select transistor OS1, and a capacitor C11. The reset transistor OR1 and the select transistor OS1 may be controlled by a reset signal ORG[1] and a select signal OSEL[1] input by a row driver, respectively.

[0137] In each sensing period, the row driver may turn on only one of four selection transistors OS1 to OS4 included in the first circuit of one pixel group PG. Therefore, a plurality of first circuits included in the pixel group PG may share one first column line OC0.

[0138] Each of the second circuits may be implemented as a 4T circuit including four transistors.

[0139] For example, the second circuit of the first pixel PX11 may include a transfer transistor TX1, a reset transistor RX, a selection transistor SX, and a drive transistor DX. The reset transistor RX, the selection transistor SX, and the drive transistor DX may also be connected to the transfer transistors TX2 to TX4 included in other pixels. That is, the second circuit included in one pixel group PG may share the reset transistor RX, the selection transistor SX, and the drive transistor DX.

[0140] The transfer transistors TX1 to TX4 included in one pixel group PG may be controlled by transfer signals TG[ 1 ] to TG[ 4 ] different from each other.

[0141] In each sensing period, the row driver may input transmission signals TG[1] to TG[4] to turn on only one of the transmission transistors TX1 to TX4. Therefore, a plurality of second pixel circuits included in the pixel group PG may share the reset transistor RX, the selection transistor SX, the drive transistor DX, and the second column line SC0.

[0142] In example embodiments, output orders of the first pixel signal VOpix and the second pixel signal VSpix through the first column line OC0 and the second column line SC0 may be identical to each other.

[0143] For example, the selection transistor OS1 of the first pixel PX11 may be turned on during the first sensing period, while all other selection transistors OS2 to OS4 included in the other pixels PX12 to PX14 may be turned off. Therefore, the first pixel signal VOpix generated by the first circuit of the first pixel PX11 using the charge of the first photo element OPD1 may be output through the first column line OC0 during the first sensing period.

[0144] Meanwhile, during the first sensing period, the transfer transistor TX1 of the first pixel PX11 may be turned on, while all other transfer transistors TX2 to TX4 included in other pixels PX12 to PX14 may be turned off. Therefore, the second pixel signal VSpix generated by the second circuit of the first pixel PX11 may be output through the second column line SC0 during the first sensing period.

[0145] In this manner, by turning on only one of the selection transistors OS1 to OS4 in each sensing period and by turning on only one of the transfer transistors TX1 to TX4 , each of the first and second circuits included in one pixel group PG can share the first and second column lines OC0 and SC0 .

[0146] Fig. 20 is a diagram illustrating an operation of an image sensing apparatus according to example embodiments.

[0147] refer to Fig. 20 , the first pixel signal VOpix is ​​provided to the comparator 352 from the 3T circuit 3TC included in the pixel array PXA, and the second pixel signal VSpix may be provided to the comparator 352 from the 4T circuit 4TC.

[0148] The control register block 310 generates a ramp enable signal R11_EN that is enabled during a first time TA at one sensing period and then enabled at a second time TB longer than the first time TA and may provide the ramp enable signal R11_EN to the ramp signal generator 360 .

[0149] The ramp signal generator 360 may provide a ramp signal VR11 to the comparator 352 in response to the ramp enable signal R11_EN, wherein a first pulse P11 having a size reduced by a first level dV11 from a reference voltage and a second pulse P12 having a size reduced by a second level dV12 from the reference voltage are sequentially applied to the ramp signal VR11.

[0150] Specifically, the ramp signal generator 360 sequentially generates a first pulse P11 having a first size and a second pulse P12 having a second size greater than the first size as the ramp signal VR11 in response to the ramp enable signal R11_EN during one sensing period, and may provide the ramp signal VR11 to the comparator 352 .

[0151] The comparator 352 compares the ramp signal VR11 with the pixel signals VOpix and VSpix from a specific time point (e.g., a time point when the comparator 352 is enabled), and may output the comparison result of the comparison as a comparison signal to the counter 354. The counter 354 may count the comparison signal and convert the pixel signals VOpix and VSpix into digital signals.

[0152] The image sensing device 300 according to an exemplary embodiment may compare all of the first pixel signal VOpix output from the 3T circuit 3TC and the second pixel signal VSpix output from the 4T circuit 4TC with the ramp signal VR11, to which a first pulse P11 having a first size and a second pulse P12 having a second size greater than the first size are sequentially applied, thereby outputting digital image data.

[0153] Although exemplary embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope defined by the following claims.

Claims

1. An image sensing device, comprising: a first circuit configured to generate a first pixel signal based on the charge generated by the first photoelectric element using three transistors, and configured to output the first pixel signal to a first comparator; a second circuit configured to generate a second pixel signal based on the charge generated by the second photoelectric element using four transistors, and configured to output the second pixel signal to a second comparator; and a ramp signal generator configured to provide a first ramp signal to the first comparator and configured to provide a second ramp signal to the second comparator, Wherein, during a sensing period of the first pixel signal and the second pixel signal, the ramp signal generator is configured to provide the first ramp signal to the first comparator, wherein a first pulse of a first size and a second pulse of a second size greater than the first size are sequentially applied to the first ramp signal, and the ramp signal generator is configured to provide the second ramp signal to the second comparator, wherein a third pulse of a third size and a fourth pulse of a fourth size greater than the third size are sequentially applied to the second ramp signal.

2. The image sensing device according to claim 1, wherein: The first circuit comprises: a first reset transistor configured to reset the first floating node, a first driving transistor configured to generate the first pixel signal based on the charge generated by the first photoelectric element, a first selection transistor configured to transmit the first pixel signal to the first comparator, and A capacitor is arranged between the first floating node and the first optoelectronic element.

3. The image sensing device according to claim 2, wherein: The second circuit comprises: a second reset transistor configured to reset the second floating node, a second driving transistor configured to generate the second pixel signal based on the charge generated by the second photoelectric element, a transfer transistor configured to receive a transfer signal and transfer the charge generated by the second photoelectric element to the second drive transistor, and A second selection transistor is configured to send the second pixel signal to the second comparator.

4. The image sensing device according to claim 1, wherein: The ramp signal generator is configured to receive a ramp enable signal to generate the first ramp signal and the second ramp signal, and The ramp enable signal is enabled for a first period and then enabled for a second period that is longer than the first period.

5. The image sensing device according to claim 1, wherein: The first photoelectric element comprises an organic photodiode, and The second photoelectric element includes a semiconductor photodiode.

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