Solid-state imaging device

Abstract

[Problem] To optimize a pixel configuration by connecting elements using a connector other than metal wiring. [Solution] This solid-state imaging device comprises a light receiving element, a transfer transistor, a capacitor, an amplification transistor, and a floating diffusion layer. The transfer transistor transfers a signal output by the light receiving element. The capacitor is connected at one end to the light receiving element via the transfer transistor, is connected at the other end to a negative-side power supply voltage, and converts charges output by the light receiving element into voltages and accumulates the same. A voltage from the capacitor is applied to a gate of the amplification transistor and the amplification transistor outputs a signal corresponding to the voltage. The floating diffusion layer includes one end of the capacitor and a gate of the amplification transistor, and is formed from an electrode integrated with the one end of the capacitor and the gate of the amplification transistor.

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device.

[0002] Image sensors that use MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) generally have a floating diffusion layer that temporarily maintains the signal converted by the photodetector in each pixel and propagates it to the gate of the amplifier transistor in the pixel's output stage. A capacitor that holds the signal is connected to this floating diffusion layer, and one end of this capacitor is connected to the gate of the amplifier transistor by metal wiring.

[0003] However, because the polysilicon that forms one end of this capacitance and the gate of the amplifying transistor is divided, space is required for the isolation region between the gates, which results in issues such as an increase in circuit area, a need for layout space for metal wiring in the wiring layer, and the possibility of coupling with surrounding nodes occurring.

[0004] Japanese Patent Application Laid-Open No. 2008-041689

[0005] Therefore, one non-limiting problem to be solved by the embodiments of the present disclosure is to optimize the pixel configuration or improve the output accuracy from the pixel by connecting elements using something other than metal wiring. The problem to be solved by the embodiments of the present disclosure can also be, as some further non-limiting examples, a problem corresponding to the effects described in the embodiments. In other words, a problem corresponding to at least one of the effects described in the description of the embodiments of the present disclosure can be a problem to be solved by the present disclosure.

[0006] According to one embodiment, a solid-state imaging device includes a light-receiving element, a transfer transistor, a capacitor, an amplification transistor, and a floating diffusion layer. The transfer transistor transfers a signal output from the light-receiving element. The capacitor has one end connected to the light-receiving element via the transfer transistor and the other end connected to a negative power supply voltage, and converts and stores charge output from the light-receiving element into a voltage. The amplification transistor receives a voltage from the capacitor at its gate and outputs a signal corresponding to the voltage. The floating diffusion layer includes one end of the capacitor and the gate of the amplification transistor, and is formed of an electrode integrated with one end of the capacitor and the gate of the amplification transistor.

[0007] The floating diffusion layer may not include a metal wiring.

[0008] The light receiving element may be formed on the same substrate as the capacitor, the amplifying transistor, and the floating diffusion layer.

[0009] The light receiving element may be formed on a substrate different from that on which the capacitor, the amplifying transistor, and the floating diffusion layer are formed.

[0010] The gate oxide film of the amplifying transistor may be thinner than the gate oxide films of other transistors connected to the floating diffusion layer.

[0011] The other end of the capacitor and a channel forming region of the amplifying transistor may be separated by an oxide film.

[0012] The other end of the capacitor and a channel forming region of the amplifying transistor may be separated by an insulating region into which impurities are implanted.

[0013] The other end of the capacitor and the channel formation region of the amplifying transistor may be formed by an n-type semiconductor layer formed on a p-type well region.

[0014] The other end of the capacitor and the channel formation region of the amplifying transistor may be formed by a p-type semiconductor layer formed on an n-type well region.

[0015] According to one embodiment, a solid-state imaging device includes a light-receiving element, a transfer transistor, a floating diffusion layer, an amplification transistor, an offset transistor, and a capacitor. The transfer transistor transfers a signal from the light-receiving element. The floating diffusion layer is connected to the light-receiving element via the transfer transistor and converts the signal output from the light-receiving element into a voltage and stores the voltage. The amplification transistor has a gate connected to the floating diffusion layer and outputs a signal corresponding to the voltage. The offset transistor is connected to the light-receiving element and controls charge overflow at a terminal of the light-receiving element. The capacitor has one end connected to the gate of the offset transistor and the other end connected to a negative power supply voltage, and the one end is formed as an electrode integrated with the gate of the offset transistor.

[0016] 1 is a block diagram schematically showing an example of a solid-state imaging device according to an embodiment; FIG. 2 is a circuit diagram schematically showing an example of a pixel according to an embodiment; FIG. 3 is a plan view schematically showing an example of a configuration on a substrate including a floating diffusion layer according to an embodiment; FIG. 4 is a cross-sectional view schematically showing an example of a configuration on a substrate including a floating diffusion layer according to an embodiment; FIG. 5 is a cross-sectional view schematically showing an example of a configuration on a substrate including a floating diffusion layer according to an embodiment; FIG. 6 is a plan view schematically showing an example of a configuration on a substrate including a floating diffusion layer according to an embodiment; FIG. 7 is a diagram showing an outline of a configuration using a different substrate according to an embodiment; FIG. 8 is a cross-sectional view schematically showing an example of a configuration on a different substrate according to an embodiment; FIG. 9 is a cross-sectional view schematically showing an example of a configuration on a substrate including a floating diffusion layer according to an embodiment;

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0018] 1 is a block diagram schematically illustrating a portion of the configuration of a solid-state imaging device according to one embodiment. The solid-state imaging device 1 includes a pixel array 10, a control circuit 12, a first scanning circuit 14, a second scanning circuit 16, and a signal processing circuit 18. The solid-state imaging device 1 may also include a power supply circuit and the like for appropriately controlling each of the components. The solid-state imaging device 1 is a device that outputs a signal based on light irradiated onto pixels 100 in the pixel array 10.

[0019] The pixel array 10 is a region in which pixels 100 are arranged in a two-dimensional array. Each pixel 100 includes at least a light-receiving element and a pixel circuit that outputs a signal based on the intensity of light irradiated onto the light-receiving element. Within the pixel array 10, the pixels 100 are arranged in an array along a first direction (e.g., a line direction) and a second direction (e.g., a column direction) that intersects with the first direction.

[0020] The control circuit 12 is a circuit that controls light reception in the pixel array 10 and output from the pixel array 10. The control circuit 12 performs drive control to output from appropriate pixels 100 at appropriate timing, for example, by sending control signals to the first scanning circuit 14 and the second scanning circuit 16.

[0021] The first scanning circuit 14 is a circuit that selects pixels 100 that belong to a line along a first direction among the pixels 100. The first scanning circuit 14 performs control so that the pixels 100 that belong to the same line can be driven, for example, by control lines 140 arranged along the line.

[0022] The second scanning circuit 16 is a circuit that drives the pixels 100 that belong to a column along the second direction of the pixels 100. The second scanning circuit 16 controls, for example, the pixels that belong to a line that is selected and made drivable by the first scanning circuit 14 via control lines 160 arranged along the column, thereby outputting signals from each pixel 100 at appropriate timing.

[0023] The pixel 100 is driven and controlled via the first scanning circuit 14 and the second scanning circuit 16, and outputs a signal based on the intensity of the received light via the signal line 180 to the signal processing circuit 18 at an appropriate timing.

[0024] The signal processing circuit 18 is a circuit that converts the signals output from each pixel 100 into signals of an appropriate format and outputs the signals. The signal processing circuit 18 may include, for example, an analog-to-digital converter (ADC). An ADC may be provided for each pixel 100, for each pixel 100 belonging to a predetermined region of the pixel array 10, or for each column. In addition to this, the signal processing circuit 18 may include, for example, a circuit that converts the output digital signals into image signals.

[0025] The signal output from the signal processing circuit 18 is output and stored via appropriate circuitry, such as, for example, an image processing circuit, where the signal is converted into a format suitable for subsequent processing or viewing.

[0026] 2 is a block diagram showing a non-limiting example of a pixel 100 according to an embodiment. The configuration of the pixel 100 may include any other components other than the connection from the capacitor C1 in the floating diffusion layer FD to the gate of the amplifier transistor AMP. That is, as a pixel in an image sensor, the pixel 100 does not exclude the inclusion of components not shown in this figure.

[0027] A power supply voltage is applied to each power supply voltage line to properly drive each element. At least some of the power supply voltage lines may intersect with a power supply voltage line that applies a ground voltage.

[0028] The light receiving element P is connected between the power supply voltage line VPD and the transfer transistor TR. The light receiving element P is a region in the pixel 100 that receives light and may be, for example, a photodiode. When the light receiving element P receives light, it performs photoelectric conversion and outputs an analog charge signal based on the intensity of the light. Each light receiving element P may be equipped with a filter, such as a color filter, that limits the wavelength band of light received.

[0029] The transfer transistor TR is connected between the light receiving element P and the floating diffusion layer FD. The transfer transistor TR has a gate connected to a control line 160, is driven based on a drive signal from the second scanning circuit 16, and transfers the signal output from the light receiving element P to the floating diffusion layer FD.

[0030] The capacitor C1 is connected between the floating diffusion layer FD and the negative power supply voltage line VSS. The capacitor C1 converts the charge output via the transfer transistor TR into a voltage and stores it in the floating diffusion layer FD, and also serves to maintain the potential of the floating diffusion layer FD. In this disclosure, one end of the capacitor C1 (the upper terminal in the drawing) is particularly configured as part of the floating diffusion layer FD.

[0031] The floating diffusion layer FD is a region connected between the transfer transistor TR and the amplifier transistor AMP. The floating diffusion layer FD is a diffusion region that holds a potential based on the signal output from the light-receiving element P. The floating diffusion layer FD applies the held potential to the gate of the amplifier transistor AMP.

[0032] The reset transistor RST is connected between the floating diffusion layer FD and the positive power supply voltage line VDD. It is a transistor for resetting the potential of the floating diffusion layer FD. The reset transistor RST resets the potential of the floating diffusion layer FD by turning on at the appropriate timing.

[0033] The amplifier transistor AMP has its gate connected to the floating diffusion layer FD. The amplifier transistor AMP outputs a current based on the voltage applied to its gate by the floating diffusion layer FD and the voltage applied to its drain (or source) from the power supply voltage line VDD. In other words, the amplifier transistor AMP amplifies and outputs a signal based on the magnitude of the signal output from the floating diffusion layer FD, i.e., the light receiving element P.

[0034] The selection transistor SEL is connected between the amplification transistor AMP and a signal line 180. The selection transistor SEL has a gate connected to a control line 140, is driven based on a selection signal from the first scanning circuit 14, and outputs the signal output from the amplification transistor AMP to the signal processing circuit 18 via the signal line 180 at an appropriate timing.

[0035] 2 shows a pixel 100 with a general configuration, but the present disclosure is characterized by the formation of the floating diffusion layer FD, which is the area indicated by the dotted line. In other words, even if the pixel circuit has a different configuration, each embodiment of the present disclosure can be applied to pixel circuits that have a similar relationship between the floating diffusion layer and the output transistor (amplification transistor). The formation of the floating diffusion layer FD is described below.

[0036] Each semiconductor device in the present disclosure can use appropriate materials for each element, wiring, etc.

[0037] The semiconductor layer (including the oxide film) can be formed using materials such as, but not limited to, Si, InGaAs, InP, SiC, and SiO2. When ions are implanted, the ions to be implanted can be, but not limited to, F, P, C, N, Ge, and As ions, depending on the conductivity type.

[0038] The metal wiring can be formed using, as a non-limiting example, materials such as Cu, Au, W, Ti, or a composite material of these.

[0039] Of course, elements, compounds, crystals, etc. other than those listed above may also be used.

[0040] (First embodiment)

[0041] FIG. 3 is a plan view showing the configuration of a pixel 100 according to one embodiment, particularly the region relating to the floating diffusion layer FD.

[0042] 3, the rectangular areas marked with an X represent contacts through which appropriate voltages are applied or signals are transmitted. Although contacts are not shown for the select transistor SEL, contacts may be provided as needed to apply appropriate voltages to the gates of the select transistors SEL.

[0043] 3, the area surrounded by the dotted line is an area that shares a well region. In this area surrounded by the dotted line, the capacitor C1, the amplifier transistor AMP, and the select transistor SEL are formed in the common well region. One end of the capacitor C1 and the electrode that acts as the gate of the amplifier transistor AMP can be formed integrally without including metal wiring.

[0044] For example, the capacitor C1 forms a capacitance with a well region and an electrode formed separately from the well region, the electrode indicated by FD in the figure. For example, the amplifier transistor AMP is formed as an n-type or p-type MOSFET formed on the well region. For example, the select transistor SEL is formed as a MOSFET of the same conductivity type as the amplifier transistor AMP formed on the well region.

[0045] Figure 4 is a cross-sectional view of the well region taken along line AA in Figure 3. The capacitor C1 and the amplifier transistor AMP are formed on the same substrate. In the following explanation, the terms "top" and "bottom" are sometimes used, but these terms indicate directions in the figure and do not necessarily represent top and bottom in terms of the use or process of the device.

[0046] The well region 200 is a well region formed on a substrate, and its conductivity type is determined by the conductivity type of the amplifier transistor AMP. In the following description, the well region 200 is assumed to be a p-type and the amplifier transistor AMP is an n-type MOSFET, but this is not limiting, and the well region 200 may be an n-type and the amplifier transistor AMP may be a p-type MOSFET.

[0047] The element isolation film 202 is an insulating region selectively formed on the upper surface of the well region 200, and is formed as an isolation film that separates the capacitor C1 from the element region of the amplifying transistor AMP. This element isolation film 202 separates, on a predetermined surface of the well region 200, a channel region 204 that is the other end of the capacitor C1 from a channel region 206 that forms the channel of the amplifying transistor AMP.

[0048] The element isolation film 202 may be an insulating film selectively formed on the upper surface of the well region 200. The element isolation film 202 may be formed, for example, by selectively etching the upper surface of the well region 200 and forming an insulating film such as an oxide film in the etched area.

[0049] 5 is a cross-sectional view according to another example of FIG. 4. The element isolation film 202 may be an impurity-doped region selectively formed on the upper surface of the well region 200. The element isolation film 202 may be formed, for example, by selectively implanting ions into the upper surface of the well region 200. In this case, the element isolation film 202 is not an insulating region as in FIG. 4, but is formed from a semiconductor layer having an appropriate conductivity type for the well region 200.

[0050] The configuration in FIG. 4 and the configuration in FIG. 5 can be appropriately selected depending on conditions such as constraints on the circuit layout, constraints on the process, and the relationship with other element configurations in the circuit.

[0051] The channel region 204 serves as the other end of the capacitor C1 and is formed, for example, by implanting ions of an appropriate conductivity type into the top surface of the well region 200.

[0052] The channel region 206 is a region that operates as the channel region of the amplifying transistor AMP, and is formed, for example, by implanting ions to give it an appropriate conductivity type on the upper surface of the well region 200. When a voltage is applied to the electrode 210, a channel is formed between the front and back sides of the drawing in the channel region 206, electrically connecting the drain and source and propagating carriers.

[0053] The gate insulating film 208 is an insulating film formed on the upper surfaces of the element isolation film 202, the channel region 204, and the channel region 206 on the substrate, and serves to electrically isolate the electrodes constituting the gate from the channel regions of the respective elements. The gate insulating film 208 may be formed by forming an insulating film, for example, an oxide film, on the upper surfaces of the element isolation film 202, the channel region 204, and the channel region 206 after their formation is completed.

[0054] The electrode 210 is an electrode formed so that its lower surface is in contact with the upper surface of the gate insulating film 208. This electrode 210 forms a capacitance in combination with, for example, the channel region 204, which is the other end of the capacitor C1, and also functions as a gate electrode for forming a channel in the channel region 206 of the amplifying transistor AMP.

[0055] The electrode 210 may be formed of polysilicon, as a non-limiting example. In this embodiment, the electrode 210 does not include metal wiring, but is integrally formed with one end of the capacitor C1 and the gate electrode of the amplifier transistor AMP.

[0056] By forming the electrode 210 in this manner, the electrode 210 that operates as the floating diffusion layer FD is formed integrally as an electrode common to the capacitor C1 and the amplifying transistor AMP without including any metal wiring.

[0057] As described above, according to this embodiment, the solid-state imaging device 1 can be formed by integrating the floating diffusion layer FD region with one end of the capacitor C1 and the gate electrode of the amplifier transistor AMP without including metal wiring. By forming this electrode, only one poly gate is required in the floating diffusion layer FD, and by eliminating the metal wiring, area efficiency can be improved. The absence of metal wiring also prevents the influence of unnecessary coupling to the floating node.

[0058] Furthermore, if the floating diffusion layer (FD) has metal wiring, a contact is required to connect the poly gate electrode and the metal wiring, but by forming it as an integrated structure, this contact can be eliminated. Furthermore, compared to when there are multiple gates, the number of gate electrodes can be reduced to one. In addition to reducing parasitic capacitance and securing wiring space, the elimination of the need for space between gates also improves layout efficiency.

[0059] (Second embodiment)

[0060] 6 is a plan view schematically illustrating an example of a configuration on a substrate including a floating diffusion layer according to an embodiment. In the pixel 100, the light receiving element P and the pixel circuit may be formed on the same semiconductor substrate.

[0061] The reset transistor RST and the transfer transistor TR can be arranged to connect the floating diffusion region FD to the capacitor C1 and the poly gate of the amplifier transistor AMP via metal wiring 212. In the top view, the reset transistor RST and the transfer transistor TR are shown as gate electrodes forming the respective transistors, for example. Appropriate voltages are applied to these gate electrodes via contacts (not shown) as described above.

[0062] As indicated by the diagonal lines, the metal wiring 212 is a metal wiring that connects a contact electrically connected to the output of the light-receiving element P via the transfer transistor TR, and electrodes of the capacitor C1 and the amplifier transistor AMP. The floating diffusion layer FD can include a region between the transfer transistor TR and the reset transistor RST, and a region that shares the electrodes of the capacitor C1 and the amplifier transistor AMP.

[0063] The signal output from the light-receiving element P is transferred to the floating diffusion layer FD at the appropriate timing via the transfer transistor TR, converted to a voltage by the capacitor C1, and applied to the gate of the amplifier transistor AMP. The floating diffusion layer FD is initialized at the appropriate timing by the reset transistor RST.

[0064] In this way, the light receiving element P and the pixel circuit including the floating diffusion layer FD can be formed on the same substrate.

[0065] (Third embodiment)

[0066] 7 is a plan view schematically illustrating an example of a configuration on a substrate including a floating diffusion layer according to an embodiment. In the pixel 100, the light receiving element P and the pixel circuit may be formed on different semiconductor substrates.

[0067] The configurations of the reset transistor RST and the transfer transistor TR are the same as those in the second embodiment. A metal wiring 212 electrically connects the floating diffusion region between the transfer transistor TR and the reset transistor RST to the floating diffusion regions that form the electrodes of the capacitor C1 and the amplifier transistor AMP.

[0068] The contact connection region SN is a region that connects a contact for transmitting a signal from a light-receiving element P provided on a different substrate to a substrate on which a pixel circuit is provided. By transferring a signal transmitted from a substrate different from the pixel circuit via this contact connection region SN to the floating diffusion region at an appropriate timing by the transfer transistor TR, it is possible to achieve the same operation as in the above embodiment.

[0069] 8 is a diagram schematically showing an example of a semiconductor substrate formed by lamination. The sensor section of the solid-state imaging device 1 can be formed as a laminated substrate 30, for example.

[0070] The laminated substrate 30 is formed by stacking a first substrate 32 and a second substrate 34. The first substrate 32 and the second substrate 34 are stacked by a method such as CoC (Chip on Chip), CoW (Chip on Wafer), or WoW (Wafer on Wafer). The first substrate 32 and the second substrate 34 may be electrically connected via a contact connection region SN by any method such as microbumps, micropads, or TSVs (Through-Silicon Vias).

[0071] The first substrate 32 may include a light receiving region of the light receiving element P. The second substrate 34 may include a pixel circuit other than the light receiving region of the light receiving element P, other signal processing circuits, and the like.

[0072] The stacking is not limited to the above example. For example, a third substrate may be further provided, and a signal processing circuit or a memory circuit may be provided on the third substrate. In other words, the connection of this embodiment can be applied to the configuration of a semiconductor device formed by any stacked semiconductor layers.

[0073] 9 is a schematic cross-sectional view of a configuration spanning multiple substrates according to a portion of the plan view shown in FIG. 7. While this figure shows a non-limiting example of a so-called InGaAs sensor in which the light-receiving region is formed of InGaAs, the present invention is not limited to this, and is also applicable to other non-limiting examples, such as sensors formed on Si substrates. Furthermore, the conductivity type can be appropriately set.

[0074] In the stacked semiconductors, the boundary between the first substrate 32 and the second substrate 34 is indicated by a dotted line. The first substrate 32 and the second substrate 34 are connected, for example, by metal wiring as shown in the figure. This wiring is connected to the pixel circuit in the contact connection region SN. A signal output to the second substrate 34 via the contact connection region SN is transferred to the floating diffusion layer FD via a channel formed at the appropriate timing when a voltage is applied to the gate electrode TRG of the transfer transistor TR.

[0075] In this way, the light receiving element P and the pixel circuit in the present disclosure can be formed on separate substrates, and signals can be transmitted appropriately via wiring formed by various methods.

[0076] (Fourth embodiment)

[0077] 10 is a cross-sectional view showing a schematic example of a configuration on a substrate including a floating diffusion layer according to an embodiment. As an example, this figure also shows a cross-sectional view of a transfer transistor TR, which is a transistor located in a region separate from the electrode 210. The transfer transistor TR may be replaced with a transistor other than the amplifier transistor AMP in the pixel circuit.

[0078] The transfer transistor TR is configured to include, for example, a gate electrode TRG, a channel region 214, and a gate insulating film 216. When an appropriate voltage is applied to the gate electrode TRG, a channel is formed in the channel region 214 between the front and back sides of the drawing, and carriers are propagated between the drain and the source.

[0079] As shown in the figure, the gate insulating film 208 can be made thinner than other insulating films, such as the gate insulating film 216. More specifically, when the thickness of the gate insulating film 216 is D [nm] and the thickness of the gate insulating film 208 is d [nm], D > d can be satisfied. The capacitance C of the capacitor C1 ox is the dielectric constant of a vacuum, ε s If is the dielectric constant of the gate insulating film and S is the channel area of ​​the capacitor C1, it can generally be calculated as follows:

[0080] The magnitude of the 1 / f noise of the amplifier transistor AMP is V. f Let be a constant, W be the channel width, L be the channel length, and f be the frequency, then it can be calculated as follows:

[0081] Therefore, by reducing the thickness of the gate insulating film 208 (reducing d), the capacitance of the capacitor C1 can be increased and the influence of 1 / f noise in the amplifying transistor AMP can be reduced.

[0082] That is, in the solid-state imaging device 1 according to this embodiment, by thinning the insulating film for the electrode 210 that is integrally formed, it is possible to improve the capacitance density and reduce the 1 / f noise.

[0083] (Fifth embodiment)

[0084] Figure 11 shows an application example of the above-described electrode formation according to one embodiment. The pixel circuit configuration is basically the same as that shown in Figure 2, but further includes an offset transistor OFG that controls charge overflow from the anode potential of the light-receiving element P. Note that the capacitor C1 may be omitted.

[0085] The drain of the offset transistor OFG is connected to the power supply voltage line VDD, and the source is connected to the anode of the light-receiving element P. The relationship between the drain and source may be reversed depending on the conductivity type of the offset transistor OFG. In addition, the gate of the offset transistor OFG is connected to the capacitor C2.

[0086] One electrode of the capacitor C2 and one electrode of the offset transistor OFG can be formed as a single unit without including metal wiring, similar to one electrode of the capacitor C1 and the gate electrode of the amplification transistor AMP in each of the above-mentioned embodiments.

[0087] By forming it in this manner, the configuration between one electrode of capacitor C2, which appropriately holds the voltage applied to the gate of offset transistor OFG, and the gate electrode of offset transistor OFG can be configured in the same manner as the relationship between one electrode of capacitor C1 and the gate electrode of amplifier transistor AMP described in each of the above embodiments.

[0088] Figure 12 is a plan view of the configuration shown in Figure 11. As shown in this figure, the gate electrode of the offset transistor OFG and one electrode of the capacitor C2 are integrally formed. Metal wiring 218 is a wiring that applies the voltage of the floating diffusion layer FD between the transfer transistor TR and the reset transistor RST to the gate of the amplifier transistor AMP.

[0089] As in the previous embodiment, this integrally formed electrode may be an electrode that does not include metal wiring, for example, made of polysilicon, etc. In this case, it is also possible to simultaneously reduce 1 / f noise in the offset transistor OFG and improve the capacitance density of the capacitor C2.

[0090] By appropriately controlling the voltage held in the capacitor C2, the level at which the charge is discharged from the offset transistor OFG can be appropriately set.

[0091] In addition to the connection state of the offset transistor OFG and the capacitor C2 in this embodiment, the electrode configuration related to the amplifier transistor AMP and the capacitor C1 described above can be added. In this case, these polysilicon electrodes can be formed with the same oxide film thickness in the same process.

[0092] The above-described embodiment may be modified as follows.

[0093] (1) A solid-state imaging device comprising: a light-receiving element; a transfer transistor that transfers a signal output from the light-receiving element; a capacitor having one end connected to the light-receiving element via the transfer transistor and the other end connected to a negative power supply voltage, which converts the charge output from the light-receiving element into a voltage and stores the voltage; an amplifying transistor having a gate to which a voltage from the capacitor is applied and which outputs a signal corresponding to the voltage; and a floating diffusion layer that includes one end of the capacitor and the gate of the amplifying transistor and is formed by an electrode that is integrated with one end of the capacitor and the gate of the amplifying transistor.

[0094] (2) The solid-state imaging device according to (1), wherein the floating diffusion layer does not include metal wiring.

[0095] (3) The solid-state imaging device according to (1) or (2), wherein the light receiving element is formed on the same substrate as the capacitor, the amplifying transistor, and the floating diffusion layer.

[0096] (4) The solid-state imaging device according to (1) or (2), wherein the light receiving element is formed on a substrate different from that on which the capacitor, the amplifying transistor, and the floating diffusion layer are formed.

[0097] (5) The solid-state imaging device according to any one of (1) to (4), wherein the gate oxide film of the amplifying transistor is thinner than the gate oxide films of other transistors connected to the floating diffusion layer.

[0098] (6) The solid-state imaging device according to any one of (1) to (5), wherein the other end of the capacitor and a channel formation region of the amplifying transistor are separated by an oxide film.

[0099] (7) The solid-state imaging device according to any one of (1) to (5), wherein the other end of the capacitor and a channel formation region of the amplifying transistor are separated by an insulating region into which impurities are implanted.

[0100] (8) The solid-state imaging device according to any one of (1) to (7), wherein the other end of the capacitor and the channel formation region of the amplifying transistor are formed by an n-type semiconductor layer formed on a p-type well region.

[0101] (9) The solid-state imaging device according to any one of (1) to (7), wherein the other end of the capacitor and the channel formation region of the amplifying transistor are formed by a p-type semiconductor layer formed on an n-type well region.

[0102] (10) A solid-state imaging device comprising: a light-receiving element; a transfer transistor that transfers a signal from the light-receiving element; a floating diffusion layer that is connected to the light-receiving element via the transfer transistor and that converts the signal output from the light-receiving element into a voltage and stores the voltage; an amplifying transistor that has a gate connected to the floating diffusion layer and outputs a signal corresponding to the voltage; an offset transistor that is connected to the light-receiving element and controls charge overflow at a terminal of the light-receiving element; and a capacitor that has one end connected to the gate of the offset transistor and the other end connected to a negative power supply voltage, and that is formed as an electrode integrated with the gate of the offset transistor.

[0103] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0104] 1: solid-state imaging device, 10: pixel array, 100: pixel, FD: floating diffusion layer, P: light receiving element, TR: transfer transistor, RST: reset transistor, AMP: amplifying transistor, SEL: selection transistor, OFG: offset transistor, C1: capacitor, VPD, VDD, VSS: power supply voltage line, C2: capacitor, 12: control circuit, 14: first scanning circuit, 140: control line, 16: second scanning circuit, 160: control line, 18: signal processing circuit, 180: signal line, 200: well region, 202: element isolation film, 204: channel region, 206: channel region, 208: gate insulating film, 210: electrode, 212: metal wiring, 214: channel region, 216: gate insulating film, 218: Metal wiring, SN: Contact connection area, 30: Laminated substrate, 32: First substrate, 34: Second substrate

Claims

1. A solid-state imaging device comprising: a light-receiving element; a transfer transistor that transfers a signal output from the light-receiving element; a capacitor having one end connected to the light-receiving element via the transfer transistor and the other end connected to a negative power supply voltage, the capacitor converting and accumulating electric charge output from the light-receiving element into a voltage; an amplification transistor having a voltage applied by the capacitor to its gate and outputting a signal corresponding to the voltage; and a floating diffusion layer including one end of the capacitor and the gate of the amplification transistor, the floating diffusion layer being formed of an electrode integrated with one end of the capacitor and the gate of the amplification transistor.

2. The solid-state imaging device according to claim 1, wherein the floating diffusion layer does not include metal wiring.

3. The solid-state imaging device according to claim 1, wherein the light-receiving element is formed on the same substrate as the capacitor, the amplification transistor, and the floating diffusion layer.

4. The solid-state imaging device according to claim 1, wherein the light-receiving element is formed on a substrate different from the capacitor, the amplification transistor, and the floating diffusion layer.

5. The solid-state imaging device according to claim 1, wherein a gate oxide film of the amplification transistor is thinner than a gate oxide film of another transistor connected to the floating diffusion layer.

6. The solid-state imaging device according to claim 1, wherein the other end of the capacitor and the channel formation region of the amplification transistor are separated by an oxide film.

7. The solid-state imaging device according to claim 1, wherein the other end of the capacitor and the channel formation region of the amplification transistor are separated by an insulating region into which impurities are implanted.

8. The solid-state imaging device according to claim 1, wherein the other end of the capacitor and the channel formation region of the amplification transistor are formed of an n-type semiconductor layer formed on a p-type well region.

9. The solid-state imaging device according to claim 1, wherein the other end of the capacitor and the channel formation region of the amplification transistor are formed of a p-type semiconductor layer formed on an n-type well region.

10. A solid-state imaging device comprising: a light-receiving element; a transfer transistor that transfers a signal from the light-receiving element; a floating diffusion layer that is connected via the light-receiving element and the transfer transistor and converts and accumulates the signal output from the light-receiving element into a voltage; an amplification transistor having a gate connected to the floating diffusion layer and outputting a signal corresponding to the voltage; an offset transistor that is connected to the light-receiving element and controls the charge overflow of the terminal of the light-receiving element; and a capacitor having one end connected to the gate of the offset transistor, the other end connected to a negative power supply voltage, and the one end formed as an electrode integrated with the gate of the offset transistor.

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