Multi-channel parallel receiver and device

Abstract

The present invention discloses a multi-channel parallel receiver and device. The receiver includes a frequency hopping multiplexer (FHM), N automatic gain control (AGC) amplification paths, an N×M power combining module, an M-channel analog-to-digital conversion unit, and a baseband processing unit. The FHM receives N input signals, separates them into N output signals, and suppresses out-of-band input signals. Each output signal of the FHM is input to an AGC amplification path, where the gain is automatically adjusted. After each AGC amplification path outputs its output signal, the N×M power combiner performs frequency band integration on the output signal. The integrated output signal enters M-channel A / D conversion units, each of which samples the output signal at a set sampling frequency within the frequency band. The sampled output signal is then demodulated by the baseband processing unit. The receiver can balance signal reception dynamics and signal frequency band coverage.

Description

Technical Field

[0001] The present invention relates to the technical field of signal reception, and more particularly to a multi-channel parallel receiver and device. Background Art

[0002] Multi-channel parallel reception can realize the simultaneous reception of multiple signals, which can improve transmission efficiency and enhance anti-interference ability.

[0003] To ensure sensitivity, traditional multi-channel parallel receivers need to achieve full-band reception. On the one hand, they can adopt the method of first amplifying the signal and then distributing the power and filtering. However, the nonlinear amplification of the front-end amplifier will lead to insufficient resolution of the receiver for the signal and severely reduce the instantaneous dynamics. On the other hand, a fixed multiplexer can be used for signal separation. Although this can guarantee the resolution of the receiver to a certain extent, it cannot achieve seamless coverage of the signal at multiple frequencies.

[0004] The prior art discloses a broadband dynamic multi-channel parallel receiver, comprising an analog terminal connected to an antenna and a digital terminal connected to the analog terminal. The analog terminal includes a differential balanced amplifier module, a power inversion module, and a cross-sampling module connected in sequence. The digital terminal utilizes a master control module. This parallel receiver utilizes band-stop filters to attenuate signals with larger amplitudes within the parallel received signals. However, each band-stop filter can only attenuate a single received signal with a large amplitude and cannot filter out interference outside the frequency band. Upon entering the receiver, these interference signals mix with the useful signal, causing signal distortion and a reduced signal-to-noise ratio, thereby seriously affecting the receiver's normal reception. Furthermore, the presence of interference signals can affect the receiver's sensitivity, resulting in reduced performance in weak signal environments. Summary of the Invention

[0005] The present invention addresses the drawbacks of conventional multi-channel parallel receivers, which cannot balance signal reception dynamics and signal frequency band coverage and have high noise coefficients, and provides a multi-channel parallel receiver and device. The multi-channel parallel receiver can balance signal reception dynamics and signal frequency band coverage and has a low noise coefficient.

[0006] The primary purpose of the present invention is to solve the above technical problems, and the technical solutions of the present invention are as follows:

[0007] A multi-channel parallel receiver, comprising: a frequency hopping multiplexer, N automatic gain control amplification paths, an N×M power synthesis module, M-channel analog-to-digital conversion units, and a baseband processing unit;

[0008] The frequency hopping multiplexer receives N input signals, separates the N input signals into N output signals, and suppresses out-of-band input signals; the operating frequency band of the frequency hopping multiplexer is divided into at least 2N segments;

[0009] Each output signal of the frequency hopping multiplexer is input to each automatic gain control amplification path respectively, and the gain is automatically adjusted in the automatic gain control amplification path;

[0010] After each automatic gain control amplification path outputs the output signal, the frequency band of the output signal is integrated in the N×M power combiner;

[0011] The output signal after frequency band integration enters M analog-to-digital conversion units respectively. Each analog-to-digital conversion unit samples the output signal at a set sampling frequency within the frequency band range, and the sampled output signal is demodulated by the baseband processing unit.

[0012] Furthermore, the isolation between adjacent frequency bands in the at least 2N divided frequency bands is greater than a set value.

[0013] Furthermore, the frequency hopping multiplexer includes: a phase shifter unit, N inductor-capacitor matching circuits and N sets of filters;

[0014] The phase shifter unit includes a first phase shifter group and a second phase shifter group. The first phase shifter group includes N first phase shifters, and the second phase shifter group includes N second phase shifters. The input end of the first first phase shifter and the input end of the first second phase shifter are both connected to the input signal. The output end of the i-th first phase shifter is connected to the input end of the i+1-th first phase shifter and the input end of the i+1-th second phase shifter, respectively. The output end of the N-th first phase shifter is grounded. The output end of the i-th second phase shifter is connected to the input end of the i-th inductor-capacitor matching circuit. The output end of the i-th inductor-capacitor matching circuit is connected to one end of the i-th group of filters. The other end of the i-th group of filters outputs the output signal, where i=1, 2, 3, ..., N.

[0015] Furthermore, the phase shifter in the phase shifter unit is any one of a microstrip line, a stripline, a coaxial line, or an inductor-capacitor phase shift circuit.

[0016] Furthermore, the LC matching circuit includes: a π-type matching circuit and a T-type matching circuit composed of at least one capacitor and at least one inductor.

[0017] Furthermore, each filter group in the N filter groups includes at least two filters, and the filters are switched by a radio frequency switch.

[0018] Furthermore, the frequency band of the filter group completely covers the operating frequency band of the multi-channel parallel receiver, and the bandwidth of each filter is equal to or equal to the absolute bandwidth of the bandwidth of the multi-channel parallel receiver.

[0019] Furthermore, the analog-to-digital conversion unit adopts a direct radio frequency sampling method, and the sampling frequency of each analog-to-digital conversion unit is greater than 2.5 times the frequency band width of the output signal of the corresponding power synthesis module.

[0020] Furthermore, the baseband processing unit includes a DSP module, an FPGA module, a memory, and a GPP module.

[0021] A multi-channel parallel receiving device comprises a multi-channel parallel receiver.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] By providing a frequency-hopping multiplexer (FHM), the present invention divides the operating frequency band into at least twice the number of input signal paths, enabling a multi-channel parallel receiver to effectively separate multiple input signals within the frequency band. Simultaneously, the input signals are fed into automatic gain control (AGC) amplifier paths via the FHM. The output signals from the AGC amplifier paths undergo frequency band integration, sampling, and demodulation to produce the final signal. This approach balances signal reception dynamics with signal frequency band coverage. High-dynamic, seamless reception of wide-band signals is achieved while maintaining the receiver's noise figure. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a structural diagram of a multi-channel parallel receiver provided in Example 1.

[0025] Figure 2 This is a structural diagram of the frequency hopping multiplexer provided in Example 1.

[0026] Figure 3 This is a structural diagram of the inductor-capacitor matching unit provided in Example 3.

[0027] Figure 4 This is a structural diagram of the inductor-capacitor matching unit provided in Example 3.

[0028] Figure 5 This is a structural diagram of the inductor-capacitor matching unit provided in Example 3.

[0029] Figure 6 This is a structural diagram of the inductor-capacitor matching unit provided in Example 3. DETAILED DESCRIPTION

[0030] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0031] In order to better illustrate this embodiment, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product size;

[0032] It is understandable to those skilled in the art that some well-known structures and descriptions thereof may be omitted in the drawings.

[0033] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0034] Example 1

[0035] like Figure 1 As shown, a multi-channel parallel receiver includes: a frequency hopping multiplexer 1, N automatic gain control amplification paths 2, an N×M power synthesis module, M-channel analog-to-digital conversion units, and a baseband processing unit 3;

[0036] The frequency hopping multiplexer 1 receives N input signals, separates the N input signals into N output signals, and suppresses out-of-band input signals; the operating frequency band of the frequency hopping multiplexer 1 is divided into at least 2N segments;

[0037] Each output signal of the frequency hopping multiplexer 1 is input to each automatic gain amplification path 2, and the gain is automatically adjusted in the automatic gain control amplification path 2;

[0038] After each automatic gain control amplification path 2 outputs the output signal, the frequency band of the output signal is integrated in the N×M power combiner;

[0039] The output signal after frequency band integration enters M analog-to-digital conversion units respectively. Each analog-to-digital conversion unit samples the output signal at a set sampling frequency within the frequency band range. The sampled output signal is demodulated by the baseband processing unit 3.

[0040] It should be noted that, compared with the frequency modulation multiplexer in the prior art, the frequency hopping multiplexer 1 has a wider frequency band coverage and more multiplexing paths.

[0041] Furthermore, the isolation between adjacent frequency bands in the at least 2N divided frequency bands is greater than a set value, and the set value mentioned here is a sufficiently large isolation value.

[0042] Furthermore, if Figure 2 As shown, the frequency hopping multiplexer 1 includes: a phase shifter unit, N inductor and capacitor matching circuits and N sets of filters;

[0043] The phase shifter unit includes a first phase shifter group and a second phase shifter group. The first phase shifter group includes N first phase shifters, and the second phase shifter group includes N second phase shifters. The input end of the first first phase shifter and the input end of the first second phase shifter are both connected to the input signal. The output end of the i-th first phase shifter is connected to the input end of the i+1-th first phase shifter and the input end of the i+1-th second phase shifter, respectively. The output end of the N-th first phase shifter is grounded. The output end of the i-th second phase shifter is connected to the input end of the i-th inductor-capacitor matching circuit. The output end of the i-th inductor-capacitor matching circuit is connected to one end of the i-th group of filters. The other end of the i-th group of filters outputs the output signal, where i=1, 2, 3, ..., N.

[0044] In a specific embodiment, the output frequency bands of the filter bank are arranged from small to large according to the sequence number i.

[0045] It should be noted that the first phase shifter group maximizes the impedance from each filter branch to the ground point, that is, the phase is 90 degrees. The second phase shifter group is used for the i-th filter group, and the impedance of other frequency bands is maximized.

[0046] It should be noted that the frequency hopping multiplexer 1 is realized by using a filter switched by a phase shifter and a radio frequency switch, so that the insertion loss of the multi-channel parallel receiver is small and full-band frequency hopping is supported.

[0047] Furthermore, the phase shifter in the phase shifter unit is any one of a microstrip line, a stripline, a coaxial line, or an inductor-capacitor phase shift circuit.

[0048] Furthermore, the LC matching circuit includes: a π-type matching circuit and a T-type matching circuit composed of at least one capacitor and at least one inductor.

[0049] Furthermore, each filter group in the N filter groups includes at least two filters, and the filters are switched by a radio frequency switch.

[0050] Furthermore, the frequency band of the filter group completely covers the operating frequency band of the multi-channel parallel receiver, and the bandwidth of each filter is equal to or equal to the absolute bandwidth of the bandwidth of the multi-channel parallel receiver.

[0051] Furthermore, the analog-to-digital conversion unit adopts a direct radio frequency sampling method, and the sampling frequency of each analog-to-digital conversion unit is greater than 2.5 times the frequency band width of the output signal of the corresponding power synthesis module.

[0052] Furthermore, the baseband processing unit includes a DSP module, an FPGA module, a memory, and a GPP module.

[0053] It should be noted that the principle of achieving high dynamics in the multi-channel parallel receiver is, on the one hand, that the frequency hopping multiplexer 1 filters and suppresses out-of-band signals, and on the other hand, that the automatic gain control amplification path 2 is used to control in-band signals.

[0054] Example 2

[0055] A multi-channel parallel receiving device, in which a multi-channel parallel receiver proposed in embodiment 1 is applied, includes: a multi-channel parallel receiver.

[0056] The parallel receiver may include necessary components such as a housing and a signal processing unit, and may also be combined with a communication base station, etc., as a multi-channel parallel receiving device suitable for a communication base station.

[0057] Example 3

[0058] Based on the multi-channel parallel receiver described in Example 1, this embodiment adopts the same multi-channel parallel receiver as that in Example 1.

[0059] like Figure 3 As shown, the inductor-capacitor matching unit includes a first inductor, a second inductor, and a first capacitor;

[0060] One end of the first inductor is connected to one end of the first capacitor and the output end of the second phase shifter, the other end of the first capacitor is connected to one end of the second inductor and the input end of the RF switch, and the other end of the first inductor and the other end of the second inductor are grounded.

[0061] like Figure 4 As shown, the inductor-capacitor matching unit includes: a third inductor, a second capacitor, and a third capacitor;

[0062] One end of the third inductor is connected to one end of the second capacitor and the output end of the second phase shifter, the other end of the third inductor is connected to one end of the third capacitor and the input end of the RF switch, and the other end of the second capacitor and the other end of the third capacitor are grounded.

[0063] like Figure 5 As shown, the inductor-capacitor matching unit includes: a fourth capacitor, a fifth capacitor, and a fourth inductor;

[0064] One end of the fourth capacitor is connected to the output end of the second phase shifter, the other end of the fourth capacitor is connected to one end of the fourth inductor and one end of the fifth capacitor, the other end of the fourth inductor is grounded, and the other end of the fifth capacitor is connected to the input end of the RF switch.

[0065] like Figure 6 As shown, it is characterized in that the inductor-capacitor matching unit includes: a fifth inductor, a sixth inductor, and a sixth capacitor;

[0066] One end of the fifth inductor is connected to the output end of the second phase shifter, the other end of the fifth inductor is connected to one end of the sixth inductor and one end of the sixth capacitor, the other end of the sixth capacitor is grounded, and the other end of the sixth inductor is connected to the input end of the RF switch.

[0067] A method for designing a frequency hopping multiplexer, which is used to design a multi-channel parallel receiver proposed in Example 1, includes:

[0068] S1: Determine the number of filter groups according to the number of parallel receiving paths;

[0069] S2: Determine the number of filters and bandwidth based on the frequency interval;

[0070] S3: Determine the filter isolation according to the dynamic reception requirements;

[0071] S4: Determine the parameters of each phase shifter of 2N according to the frequency of each filter segment;

[0072] S5: Determine the parameters of the final phase shifter and the specific values ​​of the LC matching network through simulation optimization.

[0073] It should be noted that adjacent frequency bands require a certain degree of isolation to avoid mixing of adjacent signals, but if the isolation is set too high, the filter will be easily damaged.

[0074] In this embodiment, the operating frequency band of the 10-channel parallel receiver is 1300-1700 MHz; the signal spacing is 40 MHz; the maximum received signal range is 10 dBm, and the sensitivity is -100 dBm; the ADC sampling rate is up to 800 Msps; the ADC demodulation range is -70 dBm to +5 dBm; and the ADC demodulation signal-to-noise ratio is 5 dB (QPSK signal with a bandwidth of 1 MHz).

[0075] According to the above conditions, the steps of designing the frequency hopping multiplexer are as follows:

[0076] For the receiving path, the frequency hopping multiplexer contains 10 filter banks.

[0077] Based on frequency spacing requirements, each filter group contains two filters, for a total of 20 filters. The 1300-1700 MHz frequency band is evenly divided into 20 segments, with each filter covering a 20 MHz segment.

[0078] In view of the reception signal range requirements and ADC dynamic range, the isolation between adjacent frequency bands of the frequency hopping multiplexer shall be no less than 40dB.

[0079] Based on the maximum received signal amplitude, operating frequency band, and isolation requirements, a surface acoustic wave filter is used as the filter; a microstrip line is used to implement the phase shifter; and the maximum insertion loss of the frequency hopping multiplexer is expected to be 5.5dB.

[0080] According to the receiver operating bandwidth requirements and ADC sampling rate, the ADC uses two parallel channels, covering the 1300~1500MHz frequency band and the 1500~1700MHz frequency band respectively.

[0081] The power synthesis module realizes 10-way input and 2-way output, with an overall insertion loss of 7.5dB.

[0082] According to the receiving dynamics of the analog-to-digital conversion unit and the insertion loss of the multiplexer and power synthesis module, the automatic gain control amplifier path 2 gain range is +8dB~﹢48dB, and the noise figure does not exceed 2.5dB.

[0083] The same or similar reference numerals correspond to the same or similar components;

[0084] The terms used in the drawings to describe positional relationships are for illustrative purposes only and should not be construed as limiting this patent;

[0085] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A multi-channel parallel receiver, characterized in that: include: Frequency hopping multiplexer (1), N automatic gain control amplification paths (2), N×M power synthesis module, M-channel analog-to-digital conversion units, baseband processing unit (3); The frequency hopping multiplexer (1) receives N input signals, separates the N input signals into N output signals, and suppresses out-of-band input signals; The operating frequency band of the frequency hopping multiplexer (1) is divided into at least 2N segments; Each output signal of the frequency hopping multiplexer (1) is input to each automatic gain control amplification path (2) respectively, and the gain is automatically adjusted in the automatic gain control amplification path (2); After each automatic gain control amplification path (2) outputs the output signal, the frequency band of the output signal is integrated in the N×M power combiner; The output signals after frequency band integration enter M analog-to-digital conversion units respectively. Each analog-to-digital conversion unit samples the output signal at a set sampling frequency within the frequency band. The sampled output signals are demodulated by the baseband processing unit (3). The frequency hopping multiplexer (1) comprises: a phase shifter unit, N inductor and capacitor matching circuits and N sets of filters; The phase shifter unit includes a first phase shifter group and a second phase shifter group. The first phase shifter group includes N first phase shifters, and the second phase shifter group includes N second phase shifters. The input end of the first first phase shifter and the input end of the first second phase shifter are both connected to the input signal. The output end of the i-th first phase shifter is connected to the input end of the i+1-th first phase shifter and the input end of the i+1-th second phase shifter, respectively. The output end of the N-th first phase shifter is grounded. The output end of the i-th second phase shifter is connected to the input end of the i-th inductor-capacitor matching circuit. The output end of the i-th inductor-capacitor matching circuit is connected to one end of the i-th group of filters. The other end of the i-th group of filters outputs the output signal, where i=1, 2, 3, ..., N.

2. A multi-channel parallel receiver according to claim 1, characterized in that: The isolation between adjacent frequency bands in at least 2N divided frequency bands is greater than a set value.

3. The multi-channel parallel receiver according to claim 1, characterized in that: The phase shifter in the phase shifter unit is any one of a microstrip line, a stripline, a coaxial line, or an inductor-capacitor phase shift circuit.

4. The multi-channel parallel receiver according to claim 1, characterized in that: The LC matching circuit includes: a π-type matching circuit and a T-type matching circuit composed of at least one capacitor and at least one inductor.

5. The multi-channel parallel receiver according to claim 1, characterized in that: Each filter group in the N filter groups includes at least two filters, and the filters are switched between by a radio frequency switch.

6. A multi-channel parallel receiver according to claim 5, characterized in that: The frequency band of the filter group completely covers the working frequency band of the multi-channel parallel receiver, and the bandwidth of each filter is equal to or equal to the bandwidth of the multi-channel parallel receiver.

7. The multi-channel parallel receiver according to claim 1, characterized in that: The analog-to-digital conversion unit adopts a direct radio frequency sampling method, and the sampling frequency of each analog-to-digital conversion unit is greater than 2.5 times the frequency band width of the output signal of the corresponding power synthesis module.

8. The multi-channel parallel receiver according to claim 1, characterized in that: The baseband processing unit (3) comprises a DSP module, an FPGA module, a memory, and a GPP module.

9. A multi-channel parallel receiving device, characterized in that: The invention comprises the multi-channel parallel receiver according to any one of claims 1 to 8.

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