Manufacturing method of 1.5 T SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory

Abstract

The invention discloses a manufacturing method of a 1.5 T SONOS (Silicon Oxide Nitride Oxide Semiconductor) memory. The manufacturing method comprises the following steps of: depositing a selection gate material layer on a bottom layer structure; and forming a hard mask layer. And performing self-alignment etching to form a selection gate on the side surface of the control gate structure, which comprises the following sub-steps: performing non-selective first BT etching, removing the hard mask layer on the surface and forming a side wall protection structure on the side surface. A first SL etch is performed to selectively etch the select gate material layer to lower the exposed top surface of the select gate material layer and increase the flatness of the top surface of the select gate material layer. And performing non-selective second BT etching, pushing down the flat top surface of the selection gate material layer, and removing the side wall protection structure. And performing second SL etching of selective etching on the selection gate material layer to form a selection gate and adjust the height and morphology of the selection gate. According to the invention, the side perpendicularity and size uniformity of the selection gate formed by the side wall process can be improved, the process window can be improved, and the size of the device can be reduced.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a 1.5T SONOS memory. Background Art

[0002] like Figure 1A to Figure 1B As shown, a schematic diagram of the device structure in each step of the manufacturing method of the existing 1.5T SONOS memory;

[0003] like Figure 1A As shown, a selection gate material layer 107a is deposited on the underlying structure, a control gate structure is formed on the underlying structure, and the selection gate material layer 107a covers the top surface, the side surface of the control gate structure and the top surface of the semiconductor substrate 101 outside the control gate structure; a first sidewall 105 is provided between the selection gate material layer 107a and the side surface of the control gate structure, and a gate dielectric layer 106 is provided between the selection gate material layer 107a and the top surface of the semiconductor substrate 101.

[0004] Typically, the material of the selection gate material layer 107 a includes polysilicon.

[0005] The semiconductor substrate 101 includes a silicon substrate.

[0006] The gate dielectric layer 106 includes a gate oxide layer formed by oxidizing the semiconductor substrate 101 .

[0007] The control gate structure includes a first ONO layer 102 and a control gate conductive material layer 103 which are stacked in sequence.

[0008] The first ONO layer 102 includes a silicon oxide tunneling layer, a silicon nitride storage layer and a silicon oxide control layer stacked in sequence.

[0009] The material of the control gate conductive material layer 103 includes polysilicon.

[0010] A cap layer 104 is further formed on the top surface of the control gate conductive material layer 103 . The material of the cap layer 104 includes silicon oxide or silicon nitride.

[0011] Two adjacent control gate structures form a gate combination structure. Figure 1A A gate combination structure is shown.

[0012] In the gate assembly structure, first side surfaces of two control gate structures are adjacent to each other.

[0013] The spaced region between the first sides of the two control gate structures will be completely filled with the select gate material layer 107 a .

[0014] like Figure 1BAs shown, the select gate material layer 107a is self-aligned and etched to form the select gate 107 on the side of the control gate structure. Therefore, the select gate 107 is formed by the sidewall process, so that the morphology of the select gate 107 is affected by the sidewall etching process. For example, the side of the select gate 107 is inclined, and the top width of the select gate 107 becomes smaller. The overall width of the select gate 107, that is, the critical dimension (CD), cannot be accurately controlled due to the influence of the etching process. This makes the uniformity of the size of the select gate 107 poor, including the uniformity of the size at different positions above and below the same select gate 107, and the uniformity of the size between different select gates 107. This will have an adverse effect on the performance of the device and the process manufacturing window. In order to ensure the process manufacturing window, the size of the device cannot be further reduced, which is not conducive to the reduction of the area of ​​the memory. Summary of the invention

[0015] The technical problem to be solved by the present invention is to provide a method for manufacturing a 1.5T SONOS memory, which can form a select gate by a sidewall process and improve the side verticality and size uniformity of the select gate, thereby increasing the process window and further reducing the size of the device and the chip area.

[0016] In order to solve the above technical problems, the present invention provides a method for manufacturing a 1.5T SONOS memory, comprising the following steps:

[0017] A selection gate material layer is deposited on the underlying structure, a control gate structure is formed on the underlying structure, and the selection gate material layer covers the top surface, the side surface of the control gate structure and the top surface of the semiconductor substrate outside the control gate structure; a first sidewall is spaced between the selection gate material layer and the side surface of the control gate structure, and a gate dielectric layer is isolated between the selection gate material layer and the top surface of the semiconductor substrate.

[0018] A hard mask layer (HM) is formed on a top surface of the select gate material layer.

[0019] Performing self-aligned etching to form a select gate on the side of the control gate structure, the self-aligned etching comprising the following steps:

[0020] A first break through (BT) etch is performed, and the first BT etch is non-selective etching. The first BT etch removes the hard mask layer above the top surface of the control gate structure, and the hard mask layer on the side of the control gate structure is retained to form a sidewall protection structure, and the hard mask layer outside the control gate structure outside the sidewall protection structure is removed.

[0021] A first soft landing (SL) etch is performed, wherein the first SL etch is for selectively etching the select gate material layer, and the etching thickness of the select gate material layer by the first SL etch is less than or equal to the thickness of the select gate material layer on the top surface of the control gate structure, so as to partially or completely remove the select gate material layer on the top surface of the control gate structure, so as to lower the top surface of the exposed select gate material layer and increase the flatness of the top surface of the select gate material layer.

[0022] A second BT etching is performed, which is non-selective etching and pushes down the top surface of the select gate material layer on a flat basis to ensure the vertical morphology of the side of the select gate. After the second BT etching is completed, the sidewall protection structure is removed.

[0023] A second SL etch is performed, wherein the second SL etch is to selectively etch the select gate material layer to form the select gate on the side of the control gate structure. The second SL etch ensures that the select gate material layer remaining on the outer step surface of the select gate is removed and the height and morphology of the select gate are corrected to meet the requirements.

[0024] A further improvement is that the material of the select gate material layer includes polysilicon.

[0025] A further improvement is that the material of the hard mask layer includes silicon nitride.

[0026] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0027] A further improvement is that the gate dielectric layer includes a gate oxide layer formed by oxidizing the semiconductor substrate.

[0028] A further improvement is that the control gate structure includes a first ONO layer and a control gate conductive material layer stacked in sequence.

[0029] A further improvement is that the material of the control gate conductive material layer includes polysilicon.

[0030] A further improvement is that the process for forming the first sidewall includes:

[0031] A first silicon oxide layer and a second silicon nitride layer are sequentially formed.

[0032] The second silicon nitride layer is etched and stopped on the top surface of the first silicon oxide layer, and the remaining second silicon nitride layer is located on the side of the control gate structure.

[0033] The first silicon oxide layer not covered by the second silicon nitride layer is removed, and the first sidewall spacer is formed by stacking the first silicon oxide layer and the second silicon nitride layer.

[0034] A further improvement is that, in the oxidation process of forming the gate oxide layer, the second silicon nitride layer is also partially oxidized to form a third silicon oxide layer, and the third silicon oxide layer also serves as a component of the first sidewall spacer.

[0035] A further improvement is that two adjacent control gate structures form a gate combination structure.

[0036] In the gate combination structure, the first sides of the two control gate structures are adjacent; each selection gate is formed on the second side of the corresponding control gate structure; after the second SL etching is completed, the selection gate material layer is retained in the spacing area between the first sides of the two control gate structures; the subsequent process also includes: removing the selection gate material layer in the spacing area between the first sides of the two control gate structures.

[0037] Further improvements include:

[0038] Source and drain implantation is performed to form a source region and a drain region in the semiconductor substrate; in the gate combination structure, the source region and the corresponding side of the selection gate are self-aligned, and the drain region is formed in the semiconductor substrate between the first sides of the two control gate structures and is located in common with the two control gate structures.

[0039] A further improvement is that the semiconductor substrate includes both a logic area and a storage area, and the control gate structure and the select gate are both located in the storage area.

[0040] The logic area is located outside the storage area and is a formation area of ​​a logic device.

[0041] The second gate dielectric layer of the logic device and the gate dielectric layer are formed simultaneously.

[0042] The second gate conductive material layer of the logic device and the select gate material layer are deposited simultaneously.

[0043] Unlike the prior art, in which anisotropic self-aligned etching is directly performed on the select gate material layer after deposition, thereby self-aligning the side of the control gate structure to form a select gate, in the present invention, a hard mask layer is formed after the select gate material layer is deposited, and then a special arrangement is made for the self-aligned etching process for forming the select gate, and the self-aligned etching process is divided into a first BT etching, a first SL etching, a second BT etching and a second SL etching. After the first BT etching opens the hard mask layer in the surface area, during the process of selectively etching the select gate material layer by the first SL etching, the select gate material layer on the side will not be consumed due to the protection of the side wall protection structure formed by the hard mask layer, so the top surface of the select gate material layer can be flattened and lowered, thereby preventing the select gate material layer in the top area of ​​the side from being excessively consumed, resulting in unevenness and finally causing defects such as non-vertical sides. The second BT etching can remove the sidewall protection structure on the basis of further pushing down the flat top surface of the selection gate material layer, so that the vertical side of the selection gate is exposed, and at the same time, the size of the top area and the bottom area of ​​the selection gate at the side is kept uniform; and the second SL etching can further modify the height and morphology of the selection gate, so that the height of the selection gate meets the requirements and removes the residue of the selection gate material layer outside the selection gate, and at the same time, the morphology of the selection gate can be further modified, and finally a selection gate with good size uniformity of side verticality, height and morphology that meets the requirements is obtained. Therefore, the present invention can form the selection gate by using the sidewall process, and can improve the side verticality and size uniformity of the selection gate, thereby improving the process window and further reducing the size and chip area of ​​the device. Among them, the sidewall process can form the selection gate to obtain a 1.5T SONOS memory, which can reduce the size of the device; the present invention can improve the controllability of the size of the selection gate and have no bull horns by further increasing the side verticality and size uniformity of the selection gate, and can improve the process window, which is conducive to the improvement of device performance and further miniaturization of size. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0045] Figure 1A-1B Schematic diagram of the device structure in each step of the manufacturing method of the existing 1.5T SONOS memory;

[0046] Figure 2 is a flow chart of a method for manufacturing a 1.5T SONOS memory according to an embodiment of the present invention;

[0047] Figure 3A-3D It is a schematic diagram of the device structure in each step of the manufacturing method of the 1.5T SONOS memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] like Figure 2 As shown, it is a flow chart of a method for manufacturing a 1.5T SONOS memory according to an embodiment of the present invention; FIG. 3A to FIG. 3D , which is a schematic diagram of the device structure in each step of the manufacturing method of the 1.5T SONOS memory according to an embodiment of the present invention; the manufacturing method of the 1.5T SONOS memory according to an embodiment of the present invention comprises the following steps:

[0049] Step S101: Figure 3A As shown, a selection gate material layer 207a is deposited on the underlying structure, a control gate structure is formed on the underlying structure, and the selection gate material layer 207a covers the top surface, the side surface of the control gate structure and the top surface of the semiconductor substrate 201 outside the control gate structure; a first sidewall 205 is provided between the selection gate material layer 207a and the side surface of the control gate structure, and a gate dielectric layer 206 is provided between the selection gate material layer 207a and the top surface of the semiconductor substrate 201.

[0050] In the embodiment of the present invention, the material of the selection gate material layer 207a includes polysilicon.

[0051] The semiconductor substrate 201 includes a silicon substrate.

[0052] The gate dielectric layer 206 includes a gate oxide layer formed by oxidizing the semiconductor substrate 201 .

[0053] The control gate structure includes a first ONO layer 202 and a control gate conductive material layer 203 which are stacked in sequence.

[0054] The first ONO layer 202 includes a silicon oxide tunneling layer, a silicon nitride storage layer and a silicon oxide control layer stacked in sequence.

[0055] The material of the control gate conductive material layer 203 includes polysilicon.

[0056] A cap layer 204 is further formed on the top surface of the control gate conductive material layer 203 . The material of the cap layer 204 includes silicon oxide or silicon nitride.

[0057] In some embodiments, the process of forming the first sidewall spacer 205 includes:

[0058] A first silicon oxide layer and a second silicon nitride layer are sequentially formed.

[0059] The second silicon nitride layer is etched and stopped on the top surface of the first silicon oxide layer, and the remaining second silicon nitride layer is located on the side of the control gate structure.

[0060] The first silicon oxide layer not covered by the second silicon nitride layer is removed, and the first silicon oxide layer and the second silicon nitride layer are stacked to form a first sidewall spacer 205 .

[0061] In the oxidation process of forming the gate oxide layer, the second silicon nitride layer is also partially oxidized to form a third silicon oxide layer, and the third silicon oxide layer also serves as a component of the first spacer 205. In this way, the first spacer 205 also has an ONO structure.

[0062] In some embodiments, two adjacent control gate structures form a gate combination structure. Figure 3A A gate combination structure is shown.

[0063] In the gate assembly structure, first side surfaces of two control gate structures are adjacent to each other.

[0064] The space between the first sides of the two control gate structures will be completely filled with the select gate material layer 207a.

[0065] Step S102: Figure 3A As shown, a hard mask layer 208 is formed on the top surface of the select gate material layer 207a.

[0066] In the embodiment of the present invention, the material of the hard mask layer 208 includes silicon nitride.

[0067] Step S103, performing self-aligned etching to form a select gate 207 on the side of the control gate structure, the self-aligned etching includes the following steps:

[0068] Step S103a, Figure 3B As shown, the first BT etching is performed, and the first BT etching is non-selective etching. The first BT etching removes the hard mask layer 208 on the top surface of the control gate structure, and the hard mask layer 208 on the side of the control gate structure is retained to form a sidewall protection structure. The hard mask layer 208 outside the control gate structure outside the sidewall protection structure is removed. In the present application, non-selective etching means that there is no selectivity for different materials. For example, it can not only etch the material of the hard mask layer 208, but also etch the exposed select gate material layer 207a. When etching the hard mask layer 208, it is anisotropic etching from top to bottom, so that the sidewall protection structure can be formed.

[0069] Step S103b: Figure 3CAs shown, the first SL etching is performed, and the first SL etching is to selectively etch the select gate material layer 207a. The etching thickness of the select gate material layer 207a in the first SL etching is less than or equal to the thickness of the select gate material layer 207a on the top surface of the control gate structure, so as to partially or completely remove the select gate material layer 207a on the top surface of the control gate structure, so as to lower the top surface of the exposed select gate material layer 207a and increase the flatness of the top surface of the select gate material layer 207a. In the present application, the selective etching corresponding to the first SL etching is an etching with a high selectivity ratio for the select gate material layer 207a, that is, the etching rate of the select gate material layer 207a will be much greater than the etching rate of the hard mask layer 208. The first SL etching is mainly to remove the selection gate material layer 207a on the top surface of the control gate structure. After the selection gate material layer 207a on the top surface of the control gate structure is completely removed, the selection gate material layer 207a is basically only located on the side of the control gate structure, and only the height of the selection gate material layer 207a needs to be adjusted later to form the required selection gate 207. If the selection gate material layer 207a on the top surface of the control gate structure is not completely removed, it is necessary to further remove the residue of the selection gate material layer 207a on the top surface of the control gate structure, and then adjust the height and morphology of the selection gate 207.

[0070] Usually, the first BT etching and the first SL etching constitute the first dry etching.

[0071] Step S103c: Figure 3D As shown, a second BT etching is performed. The second BT etching is non-selective etching and pushes down the top surface of the selection gate material layer 207a on a flat basis to ensure the vertical morphology of the side of the selection gate 207. After the second BT etching is completed, the sidewall protection structure is removed.

[0072] Step S103d, Figure 3D As shown, a second SL etching is performed. The second SL etching is for selectively etching the select gate material layer 207a to form a select gate 207 on the side of the control gate structure. The second SL etching ensures that the select gate material layer 207a remaining on the outer step surface of the select gate 207 is removed and the height and morphology of the select gate 207 are corrected to meet the requirements.

[0073] Usually, the second BT etching and the second SL etching constitute the second dry etching.

[0074] like Figure 3DAs shown, in the gate combination structure, each selection gate 207 is formed on the second side of the corresponding control gate structure; after the second SL etching is completed, the selection gate material layer 207a is retained in the spacing area between the first sides of the two control gate structures; the subsequent process also includes: removing the selection gate material layer 207a in the spacing area between the first sides of the two control gate structures.

[0075] The follow-up also includes:

[0076] Source and drain implantation is performed to form source and drain regions in the semiconductor substrate 201; in the gate combination structure, the source region and the side of the corresponding selection gate 207 are self-aligned, and the drain region is formed in the semiconductor substrate 201 between the first sides of the two control gate structures and is located in common with the two control gate structures.

[0077] In some embodiments, the semiconductor substrate 201 includes both a logic region (not shown) and a storage region, and the control gate structure and the select gate 207 are both located in the storage region. The control gate structure is formed in the storage pipe region, i.e., the CG region, and the select pipe is formed in the select pipe region, i.e., the SG region.

[0078] The logic area is located outside the memory area and is a region where logic devices are formed.

[0079] The second gate dielectric layer of the logic device and the gate dielectric layer 206 are formed simultaneously.

[0080] The second gate conductive material layer of the logic device and the select gate material layer 207a are deposited simultaneously.

[0081] When the second gate conductive material layer is patterned and etched, the select gate material layer 207a in the spacing region between the first side surfaces of the two control gate structures is also removed simultaneously.

[0082] Unlike the prior art, in which anisotropic self-aligned etching is directly performed on the select gate material layer 207a after deposition, so as to self-align the select gate 207 on the side of the control gate structure, in the embodiment of the present invention, after depositing the select gate material layer 207a, a hard mask layer 208 is formed, and then a special arrangement is made for the self-aligned etching process for forming the select gate 207, and the self-aligned etching process is divided into a first BT etching, a first SL etching, a second BT etching and a second SL etching. After the first BT etching opens the hard mask layer 208 in the surface area, in the process of selectively etching the select gate material layer 207a by the first SL etching, the side select gate material layer 207a is not consumed due to the protection of the side wall protection structure formed by the hard mask layer 208, so the top surface of the select gate material layer 207a can be flattened and lowered, thereby preventing the select gate material layer 207a in the top area of ​​the side from being excessively consumed to cause unevenness and finally cause defects such as non-vertical side. The second BT etching can remove the sidewall protection structure on the basis of further pushing down the flat top surface of the selection gate material layer 207a, so that the vertical side of the selection gate 207 is exposed, and at the same time, the sizes of the top area and the bottom area of ​​the selection gate 207 at the side are kept uniform; and the second SL etching can further correct the height and morphology of the selection gate 207, so that the height of the selection gate 207 meets the requirements and removes the residue of the selection gate material layer 207a outside the selection gate 207, and at the same time, the morphology of the selection gate 207 can be further corrected, and finally the side verticality, height and morphology of the selection gate 207 with good size uniformity that meet the requirements are obtained. Therefore, the embodiment of the present invention can adopt the sidewall process to form the selection gate 207, while improving the side verticality and size uniformity of the selection gate 207, thereby improving the process window and further reducing the size of the device and the chip area. Among them, forming the selection gate 207 by the sidewall process can obtain a 1.5T SONOS memory, which can reduce the size of the device; the embodiment of the present invention can improve the controllability of the size of the selection gate 207 without corners by further increasing the side verticality and size uniformity of the selection gate 207, which can improve the process window and is conducive to improving device performance and further miniaturization of size.

[0083] In the embodiment of the present invention, the 1.5T SONOS non-volatile memory achieves size miniaturization by shrinking the space between CG and SG; by protecting SG with HM combined with BT1-SL1-BT2-SL2, the memory area is further reduced while achieving good control of the SG polysilicon gate morphology and CD, and only SG with good sidewall verticality and uniformity can be formed, reducing the variation of the SG process. Without HM to protect the SG sidewall, the SG verticality and CD cannot be guaranteed. Among them, BT1 represents the first BT etching, SL1 represents the first SL etching, BT2 represents the second BT etching, and SL2 represents the second SL etching.

[0084] The 1.5T SONOS structure can greatly reduce the space of CG / SG, thereby achieving the purpose of further shrinking the memory area. However, in the existing methods, it is difficult to form an SG structure with a vertical and flat surface morphology in the 1.5T SONOS structure. In the embodiment of the present invention, HM-protected SG sidewall self-aligned etching is used to form SG. Compared with the SG sidewall process without HM protection, the HM-protected SG process can be combined with the BT1-SL1-BT2-SL2 SG self-aligned etching scheme to achieve good control of the SG polysilicon gate morphology and size, significantly improve the verticality and uniformity of the SG sidewall, so that the memory area is further reduced while maintaining the uniformity of the SG size, reducing the variation of the SG process. The development of the method of the embodiment of the present invention improves the uniformity of the SG morphology and size, increases the process manufacturing window, and saves the memory area. The process manufacturing flow is simple and can be applied to mass production.

[0085] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0086] The integrated process of the embodiment of the present invention improves the sidewall SG polysilicon gate morphology of the self-aligned etching, has no vertical footing, greatly reduces the risk of ion implantation penetration, and greatly increases the device window.

[0087] The integrated process of the embodiment of the present invention improves the self-aligned etched Sidewall SG polysilicon gate morphology, enhances the verticality and uniformity of the SG sidewall, has good size controllability, and reduces the variation of the SG process.

[0088] The integration process of the embodiment of the present invention further reduces the memory area and improves the size controllability of the self-aligned etched Sidewall SG polysilicon gate, so the chip area can be further reduced, thereby improving product competitiveness.

[0089] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a 1.5T SONOS memory, characterized in that: The steps include: Depositing a select gate material layer on the underlying structure, on which a control gate structure is formed, the select gate material layer covering the top surface, the side surface of the control gate structure and the top surface of the semiconductor substrate outside the control gate structure; a first sidewall is spaced between the select gate material layer and the side surface of the control gate structure, and a gate dielectric layer is spaced between the select gate material layer and the top surface of the semiconductor substrate; forming a hard mask layer on a top surface of the select gate material layer; Performing self-aligned etching to form a select gate on the side of the control gate structure, the self-aligned etching comprising the following steps: Performing a first BT etching, wherein the first BT etching is non-selective etching, wherein the first BT etching removes the hard mask layer above the top surface of the control gate structure, retains the hard mask layer on the side of the control gate structure and forms a sidewall protection structure, and removes the hard mask layer outside the control gate structure outside the sidewall protection structure; Performing a first SL etching, wherein the first SL etching is to selectively etch the select gate material layer, wherein the etching thickness of the select gate material layer by the first SL etching is less than or equal to the thickness of the select gate material layer on the top surface of the control gate structure, so as to partially or completely remove the select gate material layer on the top surface of the control gate structure, so as to lower the top surface of the exposed select gate material layer and increase the flatness of the top surface of the select gate material layer; Performing a second BT etching, wherein the second BT etching is non-selective etching and pushes down the top surface of the select gate material layer on a flat basis to ensure the vertical morphology of the side of the select gate, and after the second BT etching is completed, the sidewall protection structure is removed; A second SL etch is performed, wherein the second SL etch is to selectively etch the select gate material layer to form the select gate on the side of the control gate structure. The second SL etch ensures that the select gate material layer remaining on the outer step surface of the select gate is removed and the height and morphology of the select gate are corrected to meet the requirements.

2. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: The material of the select gate material layer includes polysilicon.

3. The method for manufacturing a 1.5T SONOS memory according to claim 2, wherein: The material of the hard mask layer includes silicon nitride.

4. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.

5. The method for manufacturing a 1.5T SONOS memory according to claim 4, characterized in that: The gate dielectric layer includes a gate oxide layer formed by oxidizing the semiconductor substrate.

6. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: The control gate structure includes a first ONO layer and a control gate conductive material layer stacked in sequence.

7. The method for manufacturing a 1.5T SONOS memory according to claim 6, wherein: The material of the control gate conductive material layer includes polysilicon.

8. The method for manufacturing a 1.5T SONOS memory according to claim 5, characterized in that: The process for forming the first sidewall includes: sequentially forming a first silicon oxide layer and a second silicon nitride layer; Etching the second silicon nitride layer and stopping on the top surface of the first silicon oxide layer, the remaining second silicon nitride layer is located on the side of the control gate structure; The first silicon oxide layer not covered by the second silicon nitride layer is removed, and the first sidewall spacer is formed by stacking the first silicon oxide layer and the second silicon nitride layer.

9. The method for manufacturing a 1.5T SONOS memory according to claim 8, characterized in that: In the oxidation process of forming the gate oxide layer, the second silicon nitride layer is also partially oxidized to form a third silicon oxide layer, and the third silicon oxide layer also serves as a component of the first sidewall spacer.

10. The method for manufacturing a 1.5T SONOS memory according to claim 1, wherein: Two adjacent control gate structures form a gate combination structure; In the gate combination structure, the first sides of the two control gate structures are adjacent; each selection gate is formed on the second side of the corresponding control gate structure; after the second SL etching is completed, the selection gate material layer is retained in the spacing area between the first sides of the two control gate structures; the subsequent process also includes: removing the selection gate material layer in the spacing area between the first sides of the two control gate structures.

11. The method for manufacturing a 1.5T SONOS memory according to claim 10, wherein: The follow-up also includes: Source and drain implantation is performed to form a source region and a drain region in the semiconductor substrate; in the gate combination structure, the source region and the corresponding side of the selection gate are self-aligned, and the drain region is formed in the semiconductor substrate between the first sides of the two control gate structures and is located in common with the two control gate structures.

12. The method for manufacturing a 1.5T SONOS memory according to claim 10, wherein: The semiconductor substrate includes a logic area and a storage area, and the control gate structure and the select gate are both located in the storage area; The logic area is located outside the storage area and is a formation area of ​​a logic device; The second gate dielectric layer of the logic device and the gate dielectric layer are formed simultaneously; The second gate conductive material layer of the logic device and the select gate material layer are deposited simultaneously.

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