Semi-super junction side isolation plane gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a semi-super junction side isolation planar gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; performing epitaxial growth to obtain a first drift region; performing ion implantation to form a first source region; depositing to form a first insulating dielectric layer; epitaxially forming a second drift region, wherein the drift layer comprises a first drift region and a second drift region; performing ion implantation to form a second source region, wherein the P-type source region comprises a first source region and a second source region; depositing to form a second insulating medium layer, wherein the insulating medium region comprises the first insulating medium layer and the second insulating medium layer; forming a barrier layer again, and performing etching and ion implantation to form a column region, a P-type well region, a lug boss and an N-type source region; a barrier layer is formed again, and a gate dielectric layer is formed through etching and deposition; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer and a source metal layer; the voltage endurance capability of the device is effectively improved, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The invention relates to a semi-super junction side-isolated planar gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] As a high-performance power semiconductor device, silicon carbide (SiC) VDMOS has been widely used in electric vehicles, aerospace, power conversion and other fields due to its high withstand voltage, low on-resistance, fast switching speed and high reliability. However, traditional silicon carbide VDMOS devices still face some technical bottlenecks in the design and manufacturing process, mainly including the following points: The contradiction between voltage resistance and on-resistance: In order to improve the voltage resistance of the device, it is usually necessary to increase the thickness of the drift region, but this will cause a significant increase in on-resistance, thereby reducing device efficiency.

[0003] Insufficient terminal structure optimization: In high-voltage applications, the terminal structure of the device needs to withstand greater electric field stress. Traditional designs make it difficult to effectively optimize the terminal structure to improve voltage resistance.

[0004] Lateral diffusion problem: Under high voltage conditions, lateral diffusion of the device's pn junction may lead to increased leakage current, affecting the stability and reliability of the device. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a semi-superjunction side-isolated planar gate silicon carbide VDMOS and a preparation method, in which a semi-superjunction structure and a side isolation structure are constructed inside the device, which can effectively improve the voltage resistance of the device under fixed thickness and area conditions and reduce the on-resistance of the device, and the insulating dielectric area can effectively improve the reliability and voltage resistance.

[0006] In a first aspect, the present invention provides a method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the silicon carbide substrate to obtain a first drift region; Step 2, forming a barrier layer above the first drift region, etching the barrier layer to form a through hole, and performing ion implantation into the first drift region to form a first source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first drift region to the upper side of the silicon carbide substrate, and depositing to form a first insulating dielectric layer; Step 4, removing the barrier layer, and epitaxially growing a second drift region, wherein the drift layer includes the first drift region and the second drift region; Step 5, forming a barrier layer above the second drift region, etching the barrier layer to form a through hole, and implanting ions to form a second source region, wherein the P-type source region includes a first source region and a second source region; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift region to the upper side of the first insulating dielectric layer, and depositing to form a second insulating dielectric layer, wherein the insulating dielectric region includes the first insulating dielectric layer and the second insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a pillar region; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region and a protrusion; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0007] In a second aspect, the present invention provides a semi-super junction side-isolated planar gate silicon carbide VDMOS, and the silicon carbide VDMOS is prepared by the preparation method of a semi-super junction side-isolated planar gate silicon carbide VDMOS described in the first aspect.

[0008] The advantages of the present invention are: 1. The present invention realizes a semi-superjunction device structure of the device by constructing a pillar region in the device, thereby improving the voltage resistance of the device, reducing the on-resistance of the device, and reducing the process difficulty; Second, the present invention constructs an insulating dielectric region, i.e., a side isolation structure, which can isolate the diffusion region of the device during the pn lateral diffusion process when the drain of the device is subjected to a high voltage, thereby improving the withstand voltage capability of the device and optimizing the terminal structure of the device through the withstand voltage of the insulating dielectric region; 3. The present invention solves the contradiction between increasing the withstand voltage of the device and reducing the on-resistance by designing the semi-super junction structure and the side isolation structure of the device, thereby effectively improving the performance of the device; Fourth, the present invention adopts a two-step deposition and etching process, thereby solving the problem of difficult control of the accuracy of the deep etching process in the process of preparing the insulating dielectric area and optimizing the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0010] Figure 1 The schematic diagram of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS of the present invention is shown.

[0011] Figure 2 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 1 .

[0012] Figure 3 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 2 .

[0013] Figure 4 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 3 .

[0014] Figure 5 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 4 .

[0015] Figure 6 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 5 .

[0016] Figure 7 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 6 .

[0017] Figure 8 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 7 .

[0018] Fig. 9 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 8 .

[0019] Fig.10 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 9 .

[0020] Fig.11 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 .

[0021] Fig.12 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10one.

[0022] Fig.13 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 two.

[0023] Fig.14 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 three.

[0024] Fig.15 A cross-sectional view of the process of a semi-superjunction side-isolated planar-gate silicon carbide VDMOS according to the present invention Figure 10 Four. DETAILED DESCRIPTION

[0025] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0027] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0028] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0029] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0030] like Figures 1 to 15 As shown, the embodiment of the present application provides a method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS, comprising the following steps: Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9; epitaxially growing on the silicon carbide substrate 1 to obtain a first drift region 23; Step 2, forming a barrier layer a above the first drift region 23, etching the barrier layer a to form a through hole, and performing ion implantation into the first drift region 23 to form a first source region 51; Step 3, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, etching the first drift region 23 to the upper side of the silicon carbide substrate 1, and depositing to form a first insulating dielectric layer 41; Step 4, removing the barrier layer a, and epitaxially growing and forming the second drift region 24, wherein the drift layer 2 includes the first drift region 23 and the second drift region 24; Step 5, forming a barrier layer a above the second drift region 24, etching the barrier layer a to form a through hole, and ion implanting to form a second source region 52, the P-type source region 5 includes a first source region 51 and a second source region 52; the first source region 51 and the second source region 52 have the same pattern structure, and the same photolithography plate can be used for two photolithography operations, thereby reducing the device process cost; Step 6, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the second drift region 24 to the upper side of the first insulating dielectric layer 41, and deposit to form the second insulating dielectric layer 42. The insulating dielectric region 4 includes the first insulating dielectric layer 41 and the second insulating dielectric layer 42. The first insulating dielectric layer 41 and the second insulating dielectric layer 42 have the same graphic structure, and the same photolithography plate can be used for two photolithography operations, thereby reducing the device process cost. Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a pillar region 21; Step 8, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 2 to form a P-type well region 3 and a protruding portion 22; Step 9, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the P-type well region 3 to form an N-type source region 31; Step 10, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and depositing to form a gate dielectric layer 6; Step 11, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 7; Step 12: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, deposit metal to form a source metal layer 8, remove the barrier layer a, and complete the preparation.

[0031] In this embodiment, preferably, the silicon carbide substrate 1 and the drift layer 2 are both N-type, and the column region 21 is P-type.

[0032] In this embodiment, preferably, the thickness of the column region 21 is 40-60% of the thickness of the drift layer 2 .

[0033] In this embodiment, preferably, the doping concentration of the column region 21 is greater than the doping concentration of the drift layer 2 .

[0034] In this embodiment, preferably, the doping concentration of the P-type source region 5 is greater than the doping concentration of the drift layer 2 .

[0035] In this embodiment, preferably, the width of the insulating dielectric region 4 is 2-5 μm.

[0036] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1, A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a column region 21 and a protrusion 22 are provided in the drift layer 2; A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2 and the upper side of the column region 21, and the inner side of the P-type well region 3 is connected to the outer side of the protrusion 22; an N-type source region 31 is provided in the P-type well region 3; An insulating dielectric region 4, wherein the lower side of the insulating dielectric region 4 is connected to the upper side of the silicon carbide substrate 1, and the inner side of the insulating dielectric region 4 is connected to the outer side of the drift layer 2 and the outer side of the P-type well region 3; A P-type source region 5, wherein the lower side of the P-type source region 5 is connected to the upper side of the silicon carbide substrate 1, and the inner side of the P-type source region 5 is connected to the outer side of the insulating dielectric region 4; A gate dielectric layer 6, wherein the lower side of the gate dielectric layer 6 is connected to the upper side of the protrusion 22 and the upper side of the P-type well region 3; A gate metal layer 7, wherein the lower side of the gate metal layer 7 is connected to the upper side of the gate dielectric layer 6; A source metal layer 8, wherein the source metal layer 8 is respectively connected to the P-type source region 5, the insulating dielectric region 4, the P-type well region 3 and the N-type source region 31; and a drain metal layer 9 , wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0037] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3 , the doping concentration of the P-type source region 5 is 1-5e18cm -3 The insulating dielectric region 4 may be one of silicon dioxide, silicon nitride or a composite thereof. The doping concentration of the P-type column region 21 is 6-12e17cm -3 The doping concentration of the P-type well region is 5-8e17cm -3 The gate dielectric layer 6 can be silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm -3 ; The doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of low-resistance ohmic contact with the drain metal layer 9, and at the same time to ensure the construction of a pn junction with the P-type source region 5 to achieve the reverse withstand voltage of the device and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device, and the insulating dielectric region 4 is to achieve the lateral truncation of the electric field in the terminal region of the device to the left and right sides, thereby improving the withstand voltage of the device; the P-type column region 21 and the N-type drift layer 2 constitute a semi-superjunction structure of the device, achieving the longitudinal and lateral comprehensive withstand voltage of the pn junction of the device, improving the withstand voltage capability of the device and reducing the on-resistance of the device; the P-type well region 3 is the basis for forming the gate switch structure of the device, and the doping concentration of the N-type source region 31 is to reduce the contact resistance of the source metal layer 8 of the device, thereby reducing the on-resistance of the device; The thickness of the N-type silicon carbide substrate 1 of the device is 5 μm, which is to form a pn junction withstand voltage structure with the P-type source region 5 to ensure the withstand voltage capability of this region; the thickness of the N-type drift layer 2 is 50-100 μm (including the thickness of the protruding portion 22), which is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the P-type column region 21 is 40-60% of the thickness of the N-type drift layer 2, so as to achieve the device with vertical withstand voltage at the bottom and horizontal and vertical withstand voltage at the top, while reducing the process difficulty; the width of the insulating dielectric region 4 is The width of the P-type source region 5 is 2-10 μm. The thickness of the top of the P-type well region 3 in contact with the source metal layer 8 is 500 nm. The thickness of the N-type source region 31 is 200 nm. The width of the N-type source region 31 is 10% of the width of the drain metal layer 9. The thickness of the source metal layer 8 is 200 nm, and the thickness of the gate metal layer 7 is 150 nm. In addition to isolating the device terminals, the insulating dielectric region 4 also isolates the P-type source region 5 from the N-type drift layer 2 and the P-type well region 3, thereby overcoming the mutual diffusion problem and improving the stability and reliability of the device. This embodiment realizes the semi-super junction device structure of the device by constructing a P-type column area 21 in the device, thereby improving the voltage resistance of the device, reducing the on-resistance of the device and reducing the process difficulty. Insulating dielectric areas are constructed on the left and right sides of the device, namely, side isolation structures. This structure can isolate the diffusion area of ​​the device during the pn lateral diffusion process when the drain of the device is subjected to high voltage. The voltage resistance of the device is improved by the voltage resistance of the insulating dielectric area 4, and the terminal structure of the device is optimized. By designing the semi-super junction structure and the side isolation structure of the device, the contradiction between the increased voltage resistance of the device and the reduced on-resistance of the device is resolved, and the performance of the device is effectively improved.

[0038] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a semi-superjunction side-isolated planar-gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the silicon carbide substrate to obtain a first drift region; Step 2, forming a barrier layer above the first drift region, etching the barrier layer to form a through hole, and performing ion implantation into the first drift region to form a first source region; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first drift region to the upper side of the silicon carbide substrate, and depositing to form a first insulating dielectric layer; Step 4, removing the barrier layer, and epitaxially growing a second drift region, wherein the drift layer includes the first drift region and the second drift region; Step 5, forming a barrier layer above the second drift region, etching the barrier layer to form a through hole, and implanting ions to form a second source region, wherein the P-type source region includes a first source region and a second source region; Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second drift region to the upper side of the first insulating dielectric layer, and depositing to form a second insulating dielectric layer, wherein the insulating dielectric region includes the first insulating dielectric layer and the second insulating dielectric layer; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the drift layer to form a pillar region; Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region and a protrusion; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 10, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a gate dielectric layer; Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate and the drift layer are both N-type, and the column region is P-type.

3. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the column region is 40-60% of the thickness of the drift layer.

4. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the column region is greater than the doping concentration of the drift layer.

5. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the drift layer.

6. The method for preparing a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to claim 1, characterized in that: The width of the insulating dielectric region is 2-5 μm.

7. A semi-superjunction side-isolated planar gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 6.

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