Semiconductor structure, method of manufacturing the same, storage system, and electronic device

Abstract

Embodiments of the present application provide a semiconductor structure, a preparation method thereof, a storage system and an electronic device, and relate to the technical field of semiconductor chips, aiming to avoid the influence of the leakage of the channel structure of the connection area on the storage function of the channel structure of the array area, and improve the yield of the semiconductor structure. The semiconductor structure provided in the embodiments of the present application comprises a first channel structure located in an array area and a second channel structure located in a connection area, further comprises a first insulating isolation layer covering a stacked structure, and a semiconductor layer located on the first insulating isolation layer, a first semiconductor column is connected with the semiconductor layer through the first insulating isolation layer, and a second semiconductor column is located in the first insulating isolation layer. The first insulating isolation layer can prevent the semiconductor layer from being directly connected with a gate line layer at the second channel structure, thereby avoiding the influence of the leakage of the second channel structure on the storage function of the first channel structure, and improving the yield of the semiconductor structure.

Description

Semiconductor structure and its fabrication method, memory system, electronic device Technical Field

[0001] This invention relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate.

[0003] Semiconductor structures include multiple channel structures interconnected by semiconductor layers. The channel structures located in the connection region are easily damaged, causing the gate layer in the connection region to be directly connected to the semiconductor layer, resulting in leakage current in the connection region. This, in turn, affects the storage function of the channel structures located in the array region and reduces the yield of the semiconductor structure. Summary of the Invention

[0004] The embodiments of the present invention provide a semiconductor structure and its fabrication method, a storage system, and an electronic device, aiming to avoid leakage current in the channel structure of the connection region affecting the storage function of the channel structure of the array region and improve the yield of the semiconductor structure.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On one hand, the semiconductor structure provided in the embodiments of this application includes a stacked structure, a channel structure, a first insulating isolation layer, and a semiconductor layer. The stacked structure includes an array region and a connection region, which are arranged adjacent to each other. The channel structure includes a first channel structure and a second channel structure, both of which penetrate the stacked structure. The first channel structure is located in the array region, and the second channel structure is located in the connection region. The first channel structure includes a first semiconductor pillar; the second channel structure includes a second semiconductor pillar. The first insulating isolation layer covers the stacked structure. The end of the first semiconductor pillar away from the stacked structure passes through the first insulating isolation layer, and the end of the second semiconductor pillar away from the stacked structure is located within the first insulating isolation layer. The semiconductor layer is connected to a portion of the first semiconductor pillar located on the side of the first insulating isolation layer away from the stacked structure.

[0007] The semiconductor structure provided in this embodiment includes a stacked structure and a channel structure that penetrates the stacked structure. The stacked structure includes an array region and a connection region. The channel structure includes a first channel structure located in the array region and a second channel structure located in the connection region. The semiconductor structure also includes a first insulating isolation layer covering the stacked structure and a semiconductor layer located on the side of the first insulating isolation layer away from the stacked structure. A first semiconductor pillar of the first channel structure passes through the first insulating isolation layer and is connected to the semiconductor layer. A second semiconductor pillar of the second channel structure is located within the first insulating isolation layer, so that the first insulating isolation layer can fill the holes formed at the location of the second dielectric layer. That is, the first insulating isolation layer can prevent the semiconductor layer from directly connecting to the gate line layer at the second channel structure, thereby avoiding leakage current of the second channel structure from affecting the storage function of the first channel structure and improving the yield of the semiconductor structure.

[0008] In some embodiments, the projection of the semiconductor layer onto the stacked structure covers the first insulating isolation layer.

[0009] With the above settings, compared to covering the array region of the stacked structure with semiconductor layers, there is no need to restrict the location of semiconductor layer formation during the semiconductor layer formation process, which simplifies the semiconductor layer formation process.

[0010] In some embodiments, the semiconductor structure further includes an insulating capping layer and a first conductive pillar, wherein the insulating capping layer covers the semiconductor layer, the first conductive pillar penetrates the insulating capping layer, and the first conductive pillar is connected to the semiconductor layer.

[0011] With the above configuration, an insulating capping layer covers the semiconductor layer to form a flat surface. A contact pad is formed at the end of the insulating capping layer furthest from the stacked structure, facilitating the connection between the semiconductor layer and peripheral circuitry. The semiconductor structure also includes a first conductive pillar, which penetrates the insulating capping layer. One end of the first conductive pillar extends into the semiconductor layer and connects to it, while the other end connects to the contact pad, facilitating the connection between the semiconductor layer and peripheral circuitry.

[0012] In some embodiments, the first conductive pillar is connected to a portion of the semiconductor layer located in the array region.

[0013] By using the above settings, the length of the first conductive post can be shortened, thereby reducing the resistance of the first conductive post.

[0014] In some embodiments, the semiconductor structure further includes an isolation structure that extends through the array region; the first conductive pillar is connected to the semiconductor layer corresponding to the isolation structure.

[0015] With the above configuration, the isolation structure can support the stacked structure, thereby improving the stability of the semiconductor structure. The first conductive pillar is connected to the semiconductor layer corresponding to the isolation structure, which increases the connection area between the first conductive pillar and the semiconductor layer, thus improving the stability of the connection between the first conductive pillar and the semiconductor layer.

[0016] In some embodiments, the isolation structure includes a filler pillar and a second insulating isolation layer covering the filler pillar, wherein one end of the filler pillar facing away from the stacked structure is connected to the semiconductor layer.

[0017] With the above configuration, the filler pillars penetrate the stacked structure, and the end of the filler pillar away from the stacked structure passes through the first insulating isolation layer. The portion of the filler pillar located on the side of the first insulating isolation layer away from the stacked structure is located inside the semiconductor layer and connected to the semiconductor layer to improve the stability of the semiconductor layer.

[0018] In some embodiments, the semiconductor structure further includes a second conductive pillar that penetrates the semiconductor layer, and a third insulating isolation layer is disposed between the second conductive pillar and the semiconductor layer.

[0019] With the above configuration, the third insulating layer can achieve insulation between the second conductive post and the semiconductor layer.

[0020] In some embodiments, the semiconductor structure further includes a connection structure that extends through the stacked structure and is located in the connection region, and the second conductive post is connected to the connection structure.

[0021] With the above configuration, one end of the second conductive post passes through the semiconductor layer and is connected to the connection structure, while the other end of the second conductive post is connected to the contact pad, which facilitates the connection between the semiconductor layer and the peripheral circuit.

[0022] In some embodiments, the first channel structure further includes a first dielectric layer located between the first semiconductor pillar and the stacked structure; the second channel structure further includes a second dielectric layer located between the second semiconductor pillar and the stacked structure.

[0023] With the above configuration, the first dielectric layer can form a transistor with the gate line layer in the stacked structure, and the second dielectric layer can form a transistor with the gate line layer in the stacked structure to realize the storage function of the channel structure.

[0024] On the other hand, embodiments of this application also provide a method for fabricating a semiconductor structure, comprising:

[0025] A stacked structure is formed, the stacked structure includes an array region and a connection region, the array region and the connection region are arranged adjacent to each other; a first channel structure and a second channel structure are provided on the stacked structure, the first channel structure is located in the array region, and the second channel structure is located in the connection region; the first channel structure includes a first semiconductor pillar and a first dielectric layer enclosing the first semiconductor pillar; the second channel structure includes a second semiconductor pillar and a second dielectric layer enclosing the second semiconductor pillar.

[0026] Remove a portion of the first dielectric layer at the end of the first channel structure away from the stacked structure and a portion of the second dielectric layer at the end of the second channel structure away from the stacked structure.

[0027] An intermediate insulating isolation layer is formed on the stacked structure, a portion of the intermediate insulating isolation layer is removed to form a first insulating isolation layer, and one end of the first semiconductor pillar away from the stacked structure is located on the side of the first insulating isolation layer away from the stacked structure.

[0028] A semiconductor layer is formed on the first insulating layer, and the semiconductor layer covers the end of the first semiconductor pillar away from the stacked structure.

[0029] In some embodiments, forming an intermediate insulating isolation layer on the stacked structure, removing a portion of the intermediate insulating isolation layer to form a first insulating isolation layer, and having one end of the first semiconductor pillar away from the stacked structure located on the side of the first insulating isolation layer away from the stacked structure includes:

[0030] An intermediate insulating isolation layer is formed on the stacked structure, which covers the array area and the connection area;

[0031] A mask is formed on the intermediate insulating layer, and the mask covers the connection area;

[0032] Remove a portion of the intermediate insulating isolation layer located in the array region so that the end of the first semiconductor pillar away from the stacked structure is located on the side of the first insulating isolation layer away from the stacked structure.

[0033] With the above configuration, an intermediate insulating layer covers the first semiconductor pillar located in the array region and the second semiconductor pillar located in the connection region to cover leakage current in the second channel structure. A mask is formed that covers the connection region. Since the mask only covers the connection region, the intermediate insulating layer located in the connection region is not removed. After removing a portion of the intermediate insulating layer located in the array region, the remaining portion serves as the first insulating layer, ensuring that the end of the first semiconductor pillar furthest from the stacked structure is located on the side of the first insulating layer furthest from the stacked structure, facilitating connection between the first semiconductor pillars.

[0034] In some embodiments, forming a semiconductor layer on a first insulating layer, the semiconductor layer covering one end of the first semiconductor pillar away from the stacked structure includes:

[0035] After removing part of the intermediate insulating isolation layer located in the array region, a semiconductor layer is formed in the array region.

[0036] With the above-mentioned configuration, the amount of material used to form the semiconductor layer is reduced while still enabling interconnection between multiple first channel structures.

[0037] In some embodiments, forming a semiconductor layer on a first insulating layer, the semiconductor layer covering one end of the first semiconductor pillar away from the stacked structure includes:

[0038] After removing part of the intermediate insulating isolation layer located in the array area, remove the mask.

[0039] A semiconductor layer is formed, which covers the array region and the connection region.

[0040] With the above-described configuration, the semiconductor layer covers the array region and the connection region. One end of a portion of the first semiconductor pillar, furthest from the stacked structure, is located on the side of the first insulating layer furthest from the stacked structure. Therefore, during the formation of the semiconductor layer, a portion of the first semiconductor pillar is located within the semiconductor layer. Both the first semiconductor pillar and the semiconductor layer can comprise monocrystalline silicon or polycrystalline silicon, thus achieving the connection between the first semiconductor pillar and the semiconductor layer.

[0041] In some embodiments, after forming the semiconductor layer, the semiconductor structure fabrication method further includes:

[0042] An insulating capping layer is formed on the semiconductor layer, and a first conductive hole is formed on the insulating capping layer, with the bottom of the first conductive hole located on the semiconductor layer;

[0043] A first conductive post is formed inside the first conductive hole, and the first conductive post is connected to the semiconductor layer.

[0044] With the above configuration, one end of the first conductive post extends to and connects to the semiconductor layer, while the other end of the first conductive post connects to the contact pad, facilitating the connection between the semiconductor layer and the peripheral circuit.

[0045] In some embodiments, forming the stacked structure further includes:

[0046] An isolation structure is formed on the array region;

[0047] Forming a first conductive hole on an insulating cover layer includes: forming a first conductive hole on an insulating cover layer corresponding to an isolation structure.

[0048] With the above settings, the first conductive post formed in the first conductive hole can be connected to the semiconductor layer corresponding to the isolation structure. Compared with the connection between the first conductive post and the semiconductor layer corresponding to the first semiconductor post, the diameter of the filling post is larger than the diameter of the first semiconductor post. Therefore, the connection between the first conductive post and the semiconductor layer corresponding to the isolation structure can increase the connection area between the first conductive post and the semiconductor layer and improve the stability of the connection between the first conductive post and the semiconductor layer.

[0049] In some embodiments, the isolation structure includes a filler post and a second insulating isolation layer covering the filler post;

[0050] Before forming a semiconductor layer on the stacked structure, the method further includes: removing a portion of the second insulating isolation layer to expose one end of the fill pillar away from the stacked structure and the sidewall near the end of the fill pillar away from the stacked structure;

[0051] Forming a semiconductor layer on the stacked structure also includes: the semiconductor layer further covering one end of the fill pillar away from the stacked structure and the sidewall near the end of the fill pillar away from the stacked structure.

[0052] By setting it up as described above, some of the filling pillars are located within the semiconductor layer and connected to the semiconductor layer, thereby improving the stability of the semiconductor layer.

[0053] In some embodiments, after forming the semiconductor layer, the method further includes:

[0054] A second conductive hole is formed in the connection area;

[0055] A second conductive pillar is formed inside the second conductive hole, and a third insulating isolation layer is formed between the second conductive pillar and the semiconductor layer.

[0056] With the above configuration, the second conductive hole penetrates through the insulating cover layer and the semiconductor layer to the connection structure, so that the second conductive post formed in the second conductive hole can be connected to the connection structure. The third insulating isolation layer can achieve insulation between the second conductive post and the semiconductor layer. One end of the second conductive post passes through the semiconductor layer and is connected to the connection structure, while the other end of the second conductive post is connected to the contact pad, facilitating the connection between the semiconductor layer and the peripheral circuit.

[0057] In another aspect, embodiments of this application also provide a storage system, including a semiconductor structure and a controller, wherein the semiconductor structure is as described above; the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0058] In another aspect, embodiments of this application also provide an electronic device, including the storage system described above.

[0059] It is understood that the beneficial effects that the semiconductor structure preparation method, storage system and electronic device provided in the above embodiments of this application can achieve can be referred to the beneficial effects of the semiconductor structure in the above text, and will not be repeated here. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of this invention, the accompanying drawings used in some embodiments of this invention will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this invention, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this invention.

[0061] Figure 1 is a schematic diagram of the three-dimensional structure of the three-dimensional memory in some embodiments of the present invention;

[0062] Figure 2 is a cross-sectional view of a three-dimensional memory in some embodiments of the present invention;

[0063] Figure 3 is a cross-sectional view of a storage cell string along section line AA' in the three-dimensional memory shown in Figure 1;

[0064] Figure 4 is an equivalent circuit diagram of a storage cell string in some embodiments of the present invention;

[0065] Figure 5 is a cross-sectional schematic diagram of the semiconductor structure in some embodiments of the present invention;

[0066] Figure 6 is a flowchart of a method for fabricating a semiconductor structure in some embodiments of the present invention;

[0067] Figure 7A is a schematic diagram of the structure after removing the substrate in the method provided by the embodiment of the present invention;

[0068] Figure 7B is a schematic diagram of the structure after removing part of the first dielectric layer and part of the second dielectric layer in the method provided by the embodiment of the present invention;

[0069] Figure 7C is a schematic diagram of the structure after forming the intermediate insulating isolation layer in the method provided by the embodiment of the present invention;

[0070] Figure 7D is a schematic diagram of the structure after the mask plate is formed in the method provided by the embodiment of the present invention;

[0071] Figure 7E is a schematic diagram of the structure after removing part of the intermediate insulating layer in the method provided in the embodiment of the present invention;

[0072] Figure 7F is a schematic diagram of the structure after the semiconductor layer is formed in the method provided by the embodiment of the present invention;

[0073] Figure 7G is a second schematic diagram of the structure after the semiconductor layer is formed in the method provided by the embodiment of the present invention;

[0074] Figure 7H is a schematic diagram of the structure after removing the mask plate in the method provided by the embodiment of the present invention;

[0075] Figure 7I is a schematic diagram of the structure after the semiconductor layer is formed in the method provided by the embodiment of the present invention;

[0076] Figure 7J is a schematic diagram of the structure after the insulating covering layer is formed in the method provided by the embodiment of the present invention;

[0077] Figure 7K is a schematic diagram of the structure after the formation of the first conductive pillar and the second conductive pillar in the method provided by the embodiment of the present invention;

[0078] Figure 8 is a block diagram of a storage system according to some embodiments;

[0079] Figure 9 is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0080] The technical solutions in some embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments provided by the present invention, all other embodiments obtained by those skilled in the art are within the scope of protection of the present invention.

[0081] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0082] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0083] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0084] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments invented herein are not necessarily limited to the content of this document.

[0085] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0086] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0087] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0088] In the context of this invention, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers therebetween, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers therebetween (i.e., directly on) something.

[0089] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0090] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0091] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0092] Referring to Figures 1 and 2, the three-dimensional memory 10 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor structure 200 is located (e.g., the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor structure 200 is located, that is, perpendicular to the XY plane.

[0093] As used in this invention, whether a component (e.g., layer, structure, or device) is "on," "above," or "below" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to the substrate or source layer of the semiconductor device in the third direction Z, when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concepts are applied throughout this invention to describe spatial relationships.

[0094] To illustrate the device structure more clearly, Figure 2 shows a view of the array region CA and a view of the connection region SS. The view of the array region CA is based on the left coordinate system, and the view of the connection region SS is based on the right coordinate system. That is, the view of the array region CA shows the cross-sectional structure along the Y direction, and the view of the connection region SS shows the cross-sectional structure along the X direction.

[0095] Referring to Figures 1 and 2, some embodiments of the present invention provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The three-dimensional memory 10 may also include peripheral devices 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral devices 100 may be disposed on the side of the semiconductor structure 200 away from the source layer SL.

[0096] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0097] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as "channel structure") 40. Source layer SL may be coupled to the source ends of multiple strings of memory cells 40.

[0098] In some embodiments, referring to Figures 3 and 4, the memory cell string 40 may include a plurality of transistors T, and one transistor T (e.g., T1 to T6 in Figure 4) may be configured as a memory cell. These transistors T are connected together to form a memory cell string. A transistor T (e.g., each transistor T) may be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0099] It is understood that the number of transistors in Figures 1 to 4 is only illustrative. The storage cell string of the three-dimensional memory provided in the embodiments of the present invention may also include other numbers of transistors, such as 4, 16, 32, and 64.

[0100] In some embodiments, along the third direction Z, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 40. The uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 40. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. Data writing, reading, and erasing of corresponding memory cells (e.g., transistor T) in the memory cell string 40 can be performed through the word lines WL.

[0101] Referring again to Figures 1 and 2, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 40. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 40, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 40.

[0102] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT coupled to the bit line BL, and drain select gate contacts SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as the bit line BL, and word line interconnect lines WL-CL coupled to the word line WL. The materials of the first interconnect conductor layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or other suitable materials.

[0103] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0104] In some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include the transistor 120.

[0105] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0106] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0107] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuits in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 200 to achieve the transmission of electrical signals between the peripheral circuits and the memory cell string. In some possible implementations, an bonding interface 50 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0108] Referring to Figure 5, the semiconductor structure 200 provided in this embodiment of the invention may include a stacked structure 300, one side of which is coupled to a wafer layer 280. The wafer layer 280 includes a peripheral circuit wafer, which may also be referred to as a complementary metal-oxide-semiconductor (CMOS) wafer. The CMOS wafer includes peripheral circuitry for signal transmission to memory cells. The stacked structure 300 includes an array region CA and a connection region SS, which are arranged adjacent to each other.

[0109] In the above implementation, the stacked structure 300 includes multiple dielectric layers 310 and multiple gate line layers 320 alternately stacked. In some embodiments, the dielectric layers 310 may include insulating materials, such as at least one of silicon oxide and silicon oxynitride. The gate line layers 320 may include conductive materials, such as at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicides. A protective layer may also be provided between the dielectric layers 310 and the gate line layers 320, covering the gate line layers 320. The material of the protective layer may include materials with high dielectric constants, such as alumina (Al2O3), hafnium dioxide (HfO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), and silicon oxynitride (SiO2). x N y )wait.

[0110] Referring again to FIG5, the semiconductor structure 200 may further include a first insulating isolation layer 610. The first insulating isolation layer 610 is located on the side of the stacked structure 300 away from the wafer layer 280 and covers the connection area SS of the stacked structure 300. The first insulating isolation layer 610 may include an insulating material, such as at least one of silicon oxide and silicon oxynitride.

[0111] Referring again to Figure 5, the semiconductor structure 200 may further include a semiconductor layer 620. The semiconductor layer 620 is located on the side of the stacked structure 300 away from the wafer layer 280 and covers the array region CA of the stacked structure 300. The semiconductor layer 620 may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material and other suitable semiconductor materials.

[0112] Referring again to Figure 5, the semiconductor structure 200 may further include a channel structure 500. The channel structure 500 includes a first channel structure 510 located in the array region CA and a second channel structure 520 located in the connection region SS. Both the first channel structure 510 and the second channel structure 520 penetrate the stacked structure and extend towards the side of the stacked structure 300 away from the wafer layer 280. In an implementation where the semiconductor structure 200 includes a first insulating isolation layer 610 and a semiconductor layer 620, the end of the first channel structure 510 away from the stacked structure 300 is connected to the semiconductor layer 620; the end of the second channel structure 520 away from the stacked structure 300 is located within the first insulating isolation layer 610, and the first insulating isolation layer 610 encloses the portion of the second channel structure 520 extending out of the stacked structure 300.

[0113] In the above implementation, the first channel structure 510 includes a first semiconductor pillar 511 and a first dielectric layer 512. The first semiconductor pillar 511 penetrates the stacked structure 300, and the end of the first semiconductor pillar 511 away from the stacked structure 300 is located in the semiconductor layer 620 and connected to the semiconductor layer 620. The first dielectric layer 512 is located between the first semiconductor pillar 511 and the stacked structure 300. The first dielectric layer 512 can form a transistor T with the gate layer 320 in the stacked structure 300 to realize the storage function of the channel structure 500.

[0114] Referring again to Figure 5, the second channel structure 520 includes a second semiconductor pillar 521 and a second dielectric layer 522. The second semiconductor pillar 521 extends through the stacked structure 300, and one end of the second semiconductor pillar 521 away from the stacked structure 300 is located within the first insulating isolation layer 610. The first insulating isolation layer 610 encloses the portion of the second semiconductor pillar 521 that extends out of the stacked structure 300. The second dielectric layer 522 is located between the second semiconductor pillar 521 and the stacked structure 300. The second dielectric layer 522 can form a transistor T with the gate layer 320 in the stacked structure 300 to realize the storage function of the channel structure 500.

[0115] Referring to Figures 5 and 7A, during the formation of the semiconductor structure 200, the end of the second channel structure 520 away from the wafer layer 280 is prone to wear after the substrate is removed. During the removal of the first intermediate layer 750, the second dielectric layer 522 in the second channel structure 520 is also removed, forming a hole at the location of the second dielectric layer 522 to expose the gate layer 320 used to form the transistor T with the second dielectric layer 522. Consequently, during the formation of the semiconductor layer 620, the semiconductor layer 620 can be directly connected to the gate layer 320 through the hole at the location of the second dielectric layer 522, resulting in leakage in the second channel structure 520.

[0116] The semiconductor structure 200 provided in this embodiment includes a stacked structure 300 and a channel structure 500 penetrating the stacked structure 300. The stacked structure 300 includes an array region CA and a connection region SS. The channel structure 500 includes a first channel structure 510 located in the array region CA and a second channel structure 520 located in the connection region SS. The semiconductor structure 200 also includes a first insulating isolation layer 610 covering the stacked structure 300, and a semiconductor layer 620 located on the side of the first insulating isolation layer 610 facing away from the stacked structure 300. The first channel structure 510... The first semiconductor pillar 511 passes through the first insulating isolation layer 610 and connects to the semiconductor layer 620. The second semiconductor pillar 521 of the second channel structure 520 is located inside the first insulating isolation layer 610, so that the first insulating isolation layer 610 can fill the hole formed at the position of the second dielectric layer 522. That is, the first insulating isolation layer 610 can prevent the semiconductor layer 620 from being directly connected to the gate line layer 320 at the second channel structure 520, thereby avoiding the leakage current of the second channel structure 520 from affecting the storage function of the first channel structure 510 and improving the yield of the semiconductor structure 200.

[0117] In the above implementation, both the first semiconductor pillar 511 and the second semiconductor pillar 521 may include at least one of polycrystalline silicon or monocrystalline silicon.

[0118] In the above implementation, the first semiconductor pillar 511 can be a solid pillar or a hollow pillar. When the first semiconductor pillar 511 is a hollow pillar, it can further include a support portion, which can be located inside the first semiconductor pillar 511, i.e., the first semiconductor pillar 511 surrounds the support portion. The support portion can provide support for the channel structure 500. The support portion can include an insulating material, such as silicon oxide. It should be noted that the structure of the second semiconductor pillar 521 is similar to that of the first semiconductor pillar.

[0119] Referring again to Figure 5, in the implementation of the semiconductor structure 200 including the first insulating isolation layer 610, the first insulating isolation layer 610 can cover the entire stacked structure 300. That is, the first insulating isolation layer 610 can cover the connection area SS and the array area CA of the stacked structure 300. The semiconductor layer 620 is located on the side of the first insulating isolation layer 610 away from the stacked structure 300. The semiconductor layer 620 can also cover the entire or part of the stacked structure 300. For example, the semiconductor layer 620 can only cover the array area CA of the stacked structure 300; or the semiconductor layer 620 can cover the connection area SS and the array area CA of the stacked structure 300. That is, the projection of the semiconductor layer 620 onto the stacked structure 300 covers the first insulating isolation layer 610. Compared with the embodiment where the semiconductor layer 620 only covers the array area CA of the stacked structure 300, the embodiment where the semiconductor layer 620 covers the entire stacked structure 300 simplifies the process of forming the semiconductor layer 620.

[0120] In the above implementation, the end of the first semiconductor pillar 511 away from the wafer layer 280 passes through the first insulating isolation layer 610, and the portion of the first semiconductor pillar 511 located on the side of the first insulating isolation layer 610 away from the stacked structure 300 is connected to the semiconductor layer 620.

[0121] Referring again to Figure 5, in this embodiment, the semiconductor structure 200 further includes a connection structure 400. The connection structure 400 is located in the connection region SS and on the side of the channel structure 500 away from the array region CA. The connection structure 400 penetrates the stacked structure 300. The connection structure 400 may include a through-array contact (TAC). A through-array barrier (TAB) is provided between the TAC and the gate line layer in the stacked structure. The TAB is used to achieve insulation between the TAC and the gate line layer 320 in the stacked structure 300. The TAC is used to electrically connect the stacked structure and the surrounding circuitry.

[0122] Referring again to FIG5, in the above implementation, the first dielectric layer 512 may include a barrier layer, a storage layer and a tunneling layer. The barrier layer, storage layer and tunneling layer are arranged sequentially in the direction from the first semiconductor pillar 511 to the stacked structure 300. The tunneling layer covers the sidewall of the first semiconductor pillar 511, the storage layer is located between the tunneling layer and the barrier layer, and the barrier layer is located between the storage layer and the stacked structure 300.

[0123] It should be noted that the structure of the second dielectric layer 522 is similar to that of the first dielectric layer 512. The second dielectric layer 522 may include a barrier layer, a storage layer and a tunneling layer, which are arranged sequentially from the second semiconductor pillar 521 toward the stacked structure 300.

[0124] For example, the barrier layer may include at least one of silicon oxide and metal oxide; the storage layer may include at least one of silicon nitride and silicon oxynitride; and the tunneling layer may include at least one of silicon oxide and metal oxide.

[0125] Referring again to Figure 5, in this embodiment, the semiconductor structure 200 may further include an insulating capping layer 710. The insulating capping layer covers the semiconductor layer 620 to form a flat surface. A contact pad 720 is formed at the end of the insulating capping layer 710 away from the stacked structure 300, facilitating the connection of the semiconductor layer 620 to peripheral circuits. The semiconductor structure 200 also includes a first conductive post 730, which penetrates the insulating capping layer 710. One end of the first conductive post 730 extends to and connects to the semiconductor layer 620, while the other end connects to the contact pad 720, facilitating the connection between the semiconductor layer 620 and peripheral circuits.

[0126] In the above implementation, the first conductive post 730 is located in the array region CA, and the first conductive post 730 is connected to a portion of the semiconductor layer 620 located in the array region CA. This arrangement shortens the length of current flow from the first conductive post 730 to the first semiconductor post 511, thereby reducing resistance.

[0127] Referring again to Figure 5, in this embodiment, the semiconductor structure 200 may further include an isolation structure 800. Multiple isolation structures 800 may be provided, and these structures may extend through the connection region SS, the array region CA, or be spaced apart between the connection region SS and the array region CA. The isolation structure 800 can support the stacked structure 300 to improve the stability of the semiconductor structure 200.

[0128] In the above embodiment, the isolation structure 800 includes a filler pillar 810 and a second insulating isolation layer 820. The filler pillar 810 can support the semiconductor structure 200 and may include at least one of a metal (e.g., tungsten, copper, aluminum, etc.), a metal silicide, a metal nitride, or doped polysilicon. The second insulating isolation layer 820 is disposed between the filler pillar 810 and the sidewall of the stacked structure 300. The second insulating isolation layer 820 may include at least one of silicon oxide or a metal oxide. The filler pillar 810 penetrates the stacked structure 300, and one end of the filler pillar 810 away from the stacked structure 300 passes through the first insulating isolation layer 610. A portion of the filler pillar 810 located on the side of the first insulating isolation layer 610 away from the stacked structure 300 is located within the semiconductor layer 620 and connected to the semiconductor layer 620 to improve the stability of the semiconductor layer 620.

[0129] Referring again to Figure 5, in the implementation of the semiconductor structure 200 including the first conductive pillar 730, the diameter of the first semiconductor pillar 511 is smaller than the diameter of the filling pillar 810. Therefore, the top area of ​​the isolation structure 800 is larger, and the area of ​​the semiconductor layer 620 corresponding to the isolation structure 800 is larger. The first conductive pillar 730 is connected to the semiconductor layer 620 corresponding to the isolation structure 800, which increases the connection area between the first conductive pillar 730 and the semiconductor layer 620 and improves the stability of the connection between the first conductive pillar 730 and the semiconductor layer 620.

[0130] Referring again to Figure 5, in this embodiment, the semiconductor structure 200 may further include a second conductive post 740. The second conductive post 740 penetrates the insulating cover layer 710 and the semiconductor layer 620. A third insulating isolation layer 770 is provided between the second conductive post 740 and the semiconductor layer 620. The third insulating isolation layer 770 can achieve insulation between the second conductive post 740 and the semiconductor layer 620. One end of the second conductive post 740 passes through the semiconductor layer 620 and is connected to the connection structure 400. The other end of the second conductive post 740 is connected to the contact pad 720, which facilitates the connection between the semiconductor layer 620 and the peripheral circuit.

[0131] This invention also provides a method for fabricating a semiconductor structure. Referring to Figure 6, the fabrication method may include steps S100-S400:

[0132] S100: A stacked structure is formed, the stacked structure including an array region and a connection region, the array region and the connection region being arranged adjacent to each other; a first channel structure and a second channel structure are provided on the stacked structure, the first channel structure being located in the array region and the second channel structure being located in the connection region; the first channel structure includes a first semiconductor pillar and a first dielectric layer enclosing the first semiconductor pillar; the second channel structure includes a second semiconductor pillar and a second dielectric layer enclosing the second semiconductor pillar.

[0133] Referring to Figure 7A, in step S100, forming the stacked structure 300 may include:

[0134] Multiple dielectric layers 310 and multiple sacrificial layers are alternately stacked on a substrate using a thin film deposition process to form a stacked structure.

[0135] The thin film deposition process may include one or more of the following combinations: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electroplating.

[0136] "Alternating layering" refers to forming a dielectric layer 310 on a substrate, then forming a sacrificial layer on the dielectric layer 310, and then forming another dielectric layer 310 on the sacrificial layer, and then repeating the above steps.

[0137] After forming the stacked structure, the process also includes forming channel holes on the stacked structure. The channel holes can be formed in the array region CA or in the connection region SS. The channel holes can be formed by etching. The etched channel holes extend into the substrate to ensure that the channel structure 500 formed in the channel holes can penetrate the initial stacked structure 300.

[0138] During the formation of the first channel structure 510 within the channel aperture located in the array region CA, a first dielectric layer 512 is formed on the aperture wall, and a first semiconductor pillar 511 is formed on the first dielectric layer 512, the first semiconductor pillar 511 surrounding the aperture. A support portion is then filled within the aperture. The support portion supports the channel structure 500, improving its stability. Similarly, during the formation of the second channel structure 520 within the channel aperture located in the connection region SS, a second dielectric layer 522 is formed on the aperture wall, and a second semiconductor pillar 521 is formed on the second dielectric layer 522.

[0139] After forming the channel structure 500, multiple gate slots can be formed on the stacked structure. Some of the gate slots are located in the array region CA, and some are located in the connection region SS. The gate slots penetrate multiple alternately stacked dielectric layers 310 and multiple sacrificial layers, and all extend into the substrate.

[0140] The sacrificial layer is replaced with a gate line layer 320 through the gate gap to form a stacked structure 300.

[0141] After the stacked structure 300 is formed, an isolation structure 800 is formed in the gate gap. Since the gate gap penetrates the multiple alternately stacked dielectric layers 310 and multiple sacrificial layers and extends into the substrate, one end of the isolation structure 800 is located in the substrate.

[0142] After forming the stacked structure 300, a connecting structure 400 may also be formed within the stacked structure 300, and the connecting structure 400 extends through the stacked structure 300.

[0143] After the stacked structure 300 is formed, the stacked structure 300 can be coupled to the wafer layer 280, so that the substrate is on top and the stacked structure 300 is located between the substrate and the wafer layer 280.

[0144] Referring again to Figure 7A, after forming the stacked structure 300, a portion of the substrate is removed, and the remaining portion of the substrate serves as the first intermediate layer 750, exposing one end of the first channel structure extending into the substrate and one end of the second channel structure extending into the substrate. Simultaneously, one end of the isolation structure extending into the substrate is also exposed.

[0145] After removing the substrate, the method provided in this application embodiment may further include:

[0146] S200: Remove a portion of the first dielectric layer at the end of the first channel structure away from the stacked structure and a portion of the second dielectric layer at the end of the second channel structure away from the stacked structure.

[0147] In step S200, a portion of the first dielectric layer 512 and a portion of the second dielectric layer 522 can be removed by etching. Please refer to Figures 7A and 7B for comparison. The etching direction is parallel to the stacked structure 300. In some embodiments, etching may include ONO RM to remove oxides, nitrides, and oxides in sequence.

[0148] For example, etching may include:

[0149] The first step of oxide removal can remove a portion of the barrier layer in the first intermediate layer 750, the first dielectric layer 512, and the second dielectric layer 522. In an implementation where the semiconductor structure 200 includes an isolation structure 800, the first step of oxide removal can also remove a portion of the second insulating isolation layer 820 to expose the end of the fill pillar 810 facing away from the stacked structure 300 and the sidewall near the end of the fill pillar 810 facing away from the stacked structure 300.

[0150] The second step, nitride removal, can remove a portion of the storage layer in the first dielectric layer 512 and a portion of the storage layer in the second dielectric layer 522.

[0151] The third step, oxide removal, can remove part of the tunneling layer in the first dielectric layer 512 and part of the tunneling layer in the second dielectric layer 522.

[0152] After removing a portion of the first dielectric layer 512 and a portion of the second dielectric layer 522, a portion of the first semiconductor pillar 511 and a portion of the second semiconductor pillar 521 are exposed on the side of the stacked structure 300 away from the wafer layer 280. The method provided in this application embodiment may further include:

[0153] S300: An intermediate insulating isolation layer is formed on the stacked structure, a portion of the intermediate insulating isolation layer is removed to form a first insulating isolation layer, and one end of the first semiconductor pillar away from the stacked structure is located on the side of the first insulating isolation layer away from the stacked structure.

[0154] Referring to Figure 7C, step S300 may include: forming an intermediate insulating isolation layer 611 on the stacked structure 300, the intermediate insulating isolation layer 611 covering the array region CA and the connection region SS. After forming the intermediate insulating isolation layer 611, the intermediate insulating isolation layer 611 covers the first semiconductor pillar 511 located in the array region CA and the second semiconductor pillar 521 located in the connection region SS, so as to cover the leakage current of the second channel structure 520.

[0155] Referring to Figure 7D, after forming the intermediate insulating isolation layer 611, a mask 760 can be formed on the intermediate insulating isolation layer 611, and the formed mask 760 covers the connection area SS.

[0156] Referring to Figure 7E, after forming the mask 760, a portion of the intermediate insulating isolation layer 611 is removed. Since the mask 760 only covers the connection area SS, the intermediate insulating isolation layer 611 located in the connection area SS will not be removed. After removing the portion of the intermediate insulating isolation layer located in the array area, the remaining portion of the intermediate insulating isolation layer 611 serves as the first insulating isolation layer 610, so that the end of the first semiconductor pillar 511 away from the stacked structure 300 is located on the side of the first insulating isolation layer 610 away from the stacked structure 300, which facilitates the connection between the first semiconductor pillars 511.

[0157] S400: A semiconductor layer is formed on the first insulating isolation layer, and the semiconductor layer covers the end of the first semiconductor pillar away from the stacked structure.

[0158] Referring to Figure 7F, in some embodiments, after removing part of the intermediate insulating isolation layer 611 located in the array region CA, the semiconductor layer 620 can be formed only in the array region CA. With the above arrangement, the material used to form the semiconductor layer 620 is reduced while still enabling interconnection between multiple first channel structures 510.

[0159] Referring to Figure 7G, in the above implementation, an insulating cover layer 710 is formed on the semiconductor layer 620, and a first conductive hole is formed on the insulating cover layer 710, with the bottom of the first conductive hole located on the semiconductor layer.

[0160] A first conductive post 730 is formed in the first conductive hole, and the first conductive post 730 is connected to the semiconductor layer 620.

[0161] A second conductive hole is formed in the connection area; the second conductive hole penetrates the insulating cover layer 710 and the semiconductor layer 620 to the connection structure 400, so that the second conductive post 740 formed in the second conductive hole can be connected to the connection structure 400.

[0162] Referring to Figure 7H, in some embodiments, after removing a portion of the intermediate insulating isolation layer 611 located in the array region CA, the mask 760 may be removed first to expose the first insulating isolation layer 610.

[0163] Referring to Figure 7I, a semiconductor layer 620 is formed on the first insulating isolation layer 610, covering the array region CA and the connection region SS. Since the end of a portion of the first semiconductor pillar 511 away from the stacked structure 300 is located on the side of the first insulating isolation layer 610 away from the stacked structure 300, during the formation of the semiconductor layer 620, a portion of the first semiconductor pillar 511 is located within the semiconductor layer 620. Both the first semiconductor pillar 511 and the semiconductor layer 620 can include monocrystalline silicon or polycrystalline silicon, thus realizing the connection between the first semiconductor pillar 511 and the semiconductor layer 620.

[0164] Compared to the implementation where the semiconductor layer 620 is formed only in the array region CA, the implementation where the semiconductor layer 620 is formed in both the array region CA and the connection region SS after removing the mask 760 does not require limiting the formation location of the semiconductor layer 620, thus simplifying the steps for forming the semiconductor layer 620.

[0165] In an implementation of the semiconductor structure 200 including the isolation structure 800, forming the semiconductor layer 620 on the first insulating isolation layer 610 further includes covering one end of the filler pillar 810 away from the stacked structure 300 and the sidewall near the end of the filler pillar 810 away from the stacked structure 300. This allows a portion of the filler pillar 810 to be located within and connected to the semiconductor layer 620, thereby improving the stability of the semiconductor layer 620.

[0166] The semiconductor structure 200 prepared according to the semiconductor structure preparation method provided in the embodiments of this application includes a stacked structure 300 and a channel structure 500 penetrating the stacked structure 300. The stacked structure 300 includes an array region CA and a connection region SS. The channel structure 500 includes a first channel structure 510 located in the array region CA and a second channel structure 520 located in the connection region SS. The semiconductor structure 200 also includes a first insulating isolation layer 610 covering the stacked structure 300 and a semiconductor layer 620 located on the side of the first insulating isolation layer 610 facing away from the stacked structure 300. The first semiconductor pillar 511 of the channel structure 510 passes through the first insulating isolation layer 610 and connects to the semiconductor layer 620. The second semiconductor pillar 521 of the second channel structure 520 is located inside the first insulating isolation layer 610, so that the first insulating isolation layer 610 can fill the hole formed at the position of the second dielectric layer 522. That is, the first insulating isolation layer 610 can prevent the semiconductor layer 620 from being directly connected to the gate line layer 320 at the second channel structure 520, thereby avoiding the leakage of the second channel structure 520 from affecting the storage function of the first channel structure 510 and improving the yield of the semiconductor structure 200.

[0167] After forming the semiconductor layer 620, the semiconductor structure fabrication method also includes:

[0168] Referring to Figures 7J and 7K, an insulating capping layer 710 is formed on the semiconductor layer 620, and a first conductive hole is formed on the insulating capping layer 710, with the bottom of the first conductive hole located on the semiconductor layer.

[0169] A first conductive post 730 is formed in the first conductive hole, and the first conductive post 730 is connected to the semiconductor layer 620.

[0170] With the above configuration, one end of the first conductive post 730 extends to and connects to the semiconductor layer 620, and the other end of the first conductive post 730 is connected to the contact pad 720, which facilitates the connection between the semiconductor layer 620 and the peripheral circuit.

[0171] Referring again to Figure 7K, in the implementation of the semiconductor structure 200 including the isolation structure 800, the step of forming a first conductive hole on the insulating cover layer 710 may include: forming a first conductive hole on the insulating cover layer 710 corresponding to the isolation structure 800. Through this arrangement, the first conductive post 730 formed within the first conductive hole can be connected to the semiconductor layer 620 corresponding to the isolation structure 800. Compared to the connection between the first conductive post 730 and the semiconductor layer 620 corresponding to the first semiconductor post 511, the diameter of the filling post 810 is larger than the diameter of the first semiconductor post 511. Therefore, the connection between the first conductive post 730 and the semiconductor layer 620 corresponding to the isolation structure 800 can increase the connection area between the first conductive post 730 and the semiconductor layer 620, thereby improving the stability of the connection between the first conductive post 730 and the semiconductor layer 620.

[0172] Referring again to Figure 7K, the method for fabricating the semiconductor structure provided in this application embodiment may further include:

[0173] A second conductive hole is formed in the connection area; the second conductive hole penetrates the insulating cover layer 710 and the semiconductor layer 620 to the connection structure 400, so that the second conductive post 740 formed in the second conductive hole can be connected to the connection structure 400.

[0174] A second conductive post 740 is formed in the second conductive hole, and a third insulating layer 770 is formed between the second conductive post 740 and the semiconductor layer 620.

[0175] With the above configuration, the third insulating isolation layer 770 can achieve insulation between the second conductive post 740 and the semiconductor layer 620. One end of the second conductive post 740 passes through the semiconductor layer 620 and is connected to the connection structure 400. The other end of the second conductive post 740 is connected to the contact pad 720, which facilitates the connection between the semiconductor layer 620 and the peripheral circuit.

[0176] Referring to Figures 8 and 9, some embodiments of the present invention also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the three-dimensional memory 10 may include the semiconductor structure 200 as described above, and the controller 20 is coupled to the three-dimensional memory 10 to control the storage of data in the three-dimensional memory 10.

[0177] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0178] In some embodiments, referring to FIG8, the storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0179] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0180] In other embodiments, referring to FIG9, the storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, the storage system 1000 being integrated into solid state drives (SSDs).

[0181] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0182] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0183] In some embodiments, controller 20 may be configured to manage data stored in 3D memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of 3D memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to 3D memory 10.

[0184] Of course, controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0185] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0186] Some embodiments of the present invention also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0187] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0188] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A stacked structure, the stacked structure including an array area and a connection area, the array area and the connection area being arranged adjacent to each other; A channel structure, comprising a first channel structure and a second channel structure, both penetrating the stacked structure, wherein the first channel structure is located in the array region and the second channel structure is located in the connection region; the first channel structure includes a first semiconductor pillar; the second channel structure includes a second semiconductor pillar; a first insulating isolation layer, covering the stacked structure, wherein one end of the first semiconductor pillar away from the stacked structure passes through the first insulating isolation layer, and one end of the second semiconductor pillar away from the stacked structure is located within the first insulating isolation layer; A semiconductor layer, the semiconductor layer being connected to a portion of the first semiconductor pillar located on the side of the first insulating isolation layer opposite to the stacked structure.

2. The semiconductor structure according to claim 1, characterized in that, The projection of the semiconductor layer onto the stacked structure covers the first insulating isolation layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The semiconductor structure further includes: an insulating capping layer covering the semiconductor layer; and a first conductive pillar penetrating the insulating capping layer and connected to the semiconductor layer.

4. The semiconductor structure according to claim 3, characterized in that, The first conductive pillar is connected to a portion of the semiconductor layer located in the array region.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure further includes an isolation structure that extends through the array region; the first conductive pillar is connected to the semiconductor layer corresponding to the isolation structure.

6. The semiconductor structure according to claim 5, characterized in that, The isolation structure includes a filler pillar and a second insulating isolation layer covering the filler pillar, with one end of the filler pillar facing away from the stacked structure connected to the semiconductor layer.

7. The semiconductor structure according to claim 1 or 2, characterized in that, The semiconductor structure further includes a second conductive pillar that penetrates the semiconductor layer, and a third insulating layer is disposed between the second conductive pillar and the semiconductor layer.

8. The semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes a connection structure that extends through the stacked structure and is located in the connection region, and the second conductive post is connected to the connection structure.

9. The semiconductor structure according to claim 1 or 2, characterized in that, The first channel structure further includes a first dielectric layer located between the first semiconductor pillar and the stacked structure; the second channel structure further includes a second dielectric layer located between the second semiconductor pillar and the stacked structure.

10. A method for fabricating a semiconductor structure, characterized in that, include: A stacked structure is formed, the stacked structure including an array area and a connection area, the array area and the connection area being arranged adjacent to each other; The stacked structure is provided with a first channel structure and a second channel structure that penetrate the stacked structure. The first channel structure is located in the array region, and the second channel structure is located in the connection region. The first channel structure includes a first semiconductor pillar and a first dielectric layer that encloses the first semiconductor pillar. The second channel structure includes a second semiconductor pillar and a second dielectric layer that encloses the second semiconductor pillar. Remove a portion of the first dielectric layer of the first channel structure away from the end of the stacked structure and a portion of the second dielectric layer of the second channel structure away from the end of the stacked structure; An intermediate insulating isolation layer is formed on the stacked structure, a portion of the intermediate insulating isolation layer is removed to form a first insulating isolation layer, and one end of the first semiconductor pillar away from the stacked structure is located on the side of the first insulating isolation layer away from the stacked structure; a semiconductor layer is formed on the first insulating isolation layer, and the semiconductor layer covers the end of the first semiconductor pillar away from the stacked structure.

11. The method according to claim 10, characterized in that, The step of forming an intermediate insulating isolation layer on the stacked structure, removing a portion of the intermediate insulating isolation layer to form a first insulating isolation layer, and placing the end of the first semiconductor pillar away from the stacked structure on the side of the first insulating isolation layer away from the stacked structure includes: forming an intermediate insulating isolation layer on the stacked structure, the intermediate insulating isolation layer covering the array region and the connection region; forming a mask on the intermediate insulating isolation layer, the mask covering the connection region; and removing a portion of the intermediate insulating isolation layer located in the array region, so that the end of the first semiconductor pillar away from the stacked structure is placed on the side of the first insulating isolation layer away from the stacked structure.

12. The method according to claim 11, characterized in that, The step of forming a semiconductor layer on the first insulating isolation layer, the semiconductor layer covering one end of the first semiconductor pillar away from the stacked structure, includes: forming the semiconductor layer in the array region after removing a portion of the intermediate insulating isolation layer located in the array region.

13. The method according to claim 11, characterized in that, The step of forming a semiconductor layer on the first insulating isolation layer, the semiconductor layer covering one end of the first semiconductor pillar away from the stacked structure, includes: removing the mask after removing a portion of the intermediate insulating isolation layer located in the array region; forming the semiconductor layer, the semiconductor layer covering the array region and the connection region.

14. The method according to any one of claims 10-13, characterized in that, After forming the semiconductor layer, the semiconductor structure fabrication method further includes: forming an insulating capping layer on the semiconductor layer, and forming a first conductive hole on the insulating capping layer, wherein the bottom of the first conductive hole is located on the semiconductor layer; forming a first conductive pillar in the first conductive hole, wherein the first conductive pillar is connected to the semiconductor layer.

15. The method according to claim 14, characterized in that, Forming the stacked structure further includes: forming an isolation structure on the array region; forming a first conductive hole on the insulating cover layer includes: forming a first conductive hole on the insulating cover layer corresponding to the isolation structure.

16. The method according to claim 15, characterized in that, The isolation structure includes a filler column and a second insulating isolation layer covering the filler column; Before forming a semiconductor layer on the stacked structure, the method further includes: removing a portion of the second insulating isolation layer to expose one end of the filler pillar away from the stacked structure and the sidewall near the one end of the filler pillar away from the stacked structure; forming a semiconductor layer on the stacked structure further includes: the semiconductor layer also covering one end of the filler pillar away from the stacked structure and the sidewall near the one end of the filler pillar away from the stacked structure.

17. The method according to any one of claims 10-13, characterized in that, After forming the semiconductor layer, the method further includes: forming a second conductive hole on the connection region; forming a second conductive pillar in the second conductive hole; and forming a third insulating layer between the second conductive hole and the hole wall of the second conductive hole.

18. A storage system, characterized in that, include: The semiconductor structure as described in any one of claims 1-9; A controller coupled to the semiconductor structure to control the semiconductor structure to store data.

19. An electronic device, characterized in that, Including the storage system as described in claim 18.

Images