Thin film transistor and display device including the same

Abstract

A thin film transistor and a display device including the same are provided. A thin film transistor for a display device may include: an active layer disposed on a substrate; a gate electrode overlapping the active layer; a source electrode electrically connected to the active layer; a drain electrode electrically connected to the active layer; and at least one hole in the active layer, where the at least one hole at least partially overlaps an edge of the gate electrode. Further, the at least one hole in the active layer may control or block diffusion of dopants within the active layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0118794, filed on September 7, 2023, which is hereby incorporated by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin film transistor and a display device including the thin film transistor. Background Art

[0004] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since thin film transistors can be manufactured on glass substrates or plastic substrates, thin film transistors are widely used as switching devices of display devices such as liquid crystal display devices or organic light emitting display devices.

[0005] Based on the material constituting the active layer, thin film transistors can be divided into amorphous silicon thin film transistors using amorphous silicon as an active layer, polycrystalline silicon thin film transistors using polycrystalline silicon as an active layer, and oxide semiconductor thin film transistors using oxide semiconductors as an active layer.

[0006] Amorphous silicon thin film transistors (a-Si TFTs) have the advantages of short manufacturing process time and low production cost because amorphous silicon can be deposited in a short time to form an active layer, but amorphous silicon thin film transistors (a-Si TFTs) have the disadvantage of limited use in active matrix organic light-emitting devices (AMOLEDs) due to low mobility and poor current driving capability as well as variations in threshold voltage.

[0007] Polycrystalline silicon thin film transistors (poly-Si TFTs) are made by crystallizing amorphous silicon after depositing it. Since a process of crystallizing amorphous silicon is required in the manufacturing process of polycrystalline silicon thin film transistors, the manufacturing cost increases as the number of processes increases, and since the crystallization process is performed at a high process temperature, it is difficult to apply polycrystalline silicon thin film transistors to large-area devices. In addition, due to its polycrystalline characteristics, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors.

[0008] In an oxide semiconductor thin film transistor (TFT), since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the oxygen content, it is easy to obtain the desired physical properties. In addition, due to the properties of the oxide, since the oxide semiconductor is transparent, it is also advantageous for realizing a transparent display.

[0009] In oxide semiconductors, as the width of an active layer changes, conductive diffusion occurs differently due to differences in oxygen compensation capabilities of surrounding layers. As a result, there may be difficulty in optimizing the threshold voltage (Vth) of a thin film transistor in the same process.

[0010] In addition, in oxide semiconductors, when the width of the active layer increases, the conductive penetration depth increases and the length of the effective channel decreases, which reduces the driving stability of the thin film device. In other words, when the active layer is made wide, it is difficult to control the diffusion of dopants, and the conductive layer may extend too deep or even under the gate electrode, which reduces the channel area and impairs the driving stability. Therefore, technology for controlling the conductive layer penetration depth is being continuously studied.

[0011] There is a need for a thin film transistor having a configuration that can provide a wide active layer while also controlling conductive diffusion, and can provide excellent mobility and improved driving stability. Summary of the invention

[0012] An embodiment of the present invention is to provide a thin film transistor in which conductive diffusion is controlled or prevented even when the width of a channel region increases by including one or more holes in an active layer.

[0013] An embodiment of the present invention seeks to provide a thin film transistor in which conductive diffusion is controlled or prevented and excellent mobility is ensured by configuring holes in an active layer.

[0014] Embodiments of the present invention seek to provide a thin film transistor including an active hole, such as a hole in an active layer, having improved reliability.

[0015] Another embodiment of the present invention seeks to provide a display device including such a thin film transistor.

[0016] In addition to the objects of the present disclosure as mentioned above, additional objects and features of the present disclosure will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0017] According to one aspect of the present disclosure, the above and other purposes can be achieved by providing a thin film transistor, which includes: an active layer; a gate electrode, which is spaced apart from the active layer and at least partially overlaps with the active layer, wherein the active layer includes: a channel region, which at least partially overlaps with the gate electrode in a plan view; a source region, which is connected to one side of the channel region in a plan view; and a drain region, which is connected to the other side of the channel region in a plan view, an active hole without an active layer is provided in an area whose edge is defined by the active layer, and the active hole includes a first active hole, at least a portion of which overlaps with the gate electrode, and the first active hole includes: a first region, which overlaps with the gate electrode; and a second region, which does not overlap with the gate electrode, and the area of ​​the second region is greater than or equal to the area of ​​the first region.

[0018] When a direction parallel to the shortest line connecting the source region and the drain region is a first direction and a direction perpendicular to the first direction is a second direction, the length of an area where an arbitrary straight line parallel to the second direction overlaps with the first region in a plane may decrease as the distance from the second region with respect to the first direction increases.

[0019] When a direction parallel to the shortest line connecting the source region and the drain region is a first direction and a direction perpendicular to the first direction is a second direction, the first active hole includes: a first source active hole, the first source active hole is arranged in a plane along the first direction from the gate electrode toward the source region; and a first drain active hole, the first drain active hole is arranged in a plane along the first direction from the gate electrode toward the drain region; and the first source active hole and the first drain active hole can be spaced apart from each other.

[0020] A straight line passing through at least a portion of the first source active hole among any straight lines parallel to the first direction may pass through the first drain active hole.

[0021] A straight line passing through at least a portion of the first source active hole among any straight lines parallel to the first direction may not pass through the first drain active hole.

[0022] The first source active hole may include a first sub-active hole and a second sub-active hole spaced apart from each other, and the first drain active hole may include a first sub-active hole and a second sub-active hole spaced apart from each other.

[0023] Among any straight lines parallel to the first direction, a straight line passing through the first sub-active hole of the first source active hole may pass through the first sub-active hole of the first drain active hole, and among any straight lines parallel to the first direction, a straight line passing through the second sub-active hole of the first source active hole may pass through the second sub-active hole of the first drain active hole.

[0024] A straight line passing through at least a portion of the first source active hole among any straight lines parallel to the first direction may not pass through the first drain active hole.

[0025] The first source active hole and the first drain active hole may further include a protrusion portion disposed in a direction not parallel to the first direction.

[0026] The protruding portion may not overlap with the gate electrode.

[0027] The first source active hole may include a first sub-active hole and a second sub-active hole spaced apart from each other, and the first drain active hole may include a first sub-active hole and a second sub-active hole spaced apart from each other.

[0028] The first sub-active hole and the second sub-active hole of the first source active hole may contact each other, and the first sub-active hole and the second sub-active hole of the first drain active hole may contact each other.

[0029] The active hole may further include a second active hole spaced apart from the first active hole, the second active hole may not overlap the gate electrode, and a length of the second active hole in the second direction may be longer than a length in the first direction.

[0030] Among any straight lines parallel to the first direction, a straight line passing through the first active hole may pass through the second active hole.

[0031] The second active holes may include: a second source active hole disposed in a plane along the first direction from the gate electrode toward the source region; and a second drain active hole disposed in a plane along the first direction from the gate electrode toward the drain region.

[0032] The thin film transistor may further include: a source electrode contacting the source region through the contact hole; and a drain electrode spaced apart from the source electrode and contacting the drain region through the contact hole.

[0033] Another configuration of the present invention provides a display device including a thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 is a plan view of a thin film transistor according to an embodiment of the present invention.

[0036] Figure 2 According to an embodiment of the present invention, Figure 1 A cross-sectional view taken along line II'.

[0037] Figure 3 According to an embodiment of the present invention, Figure 1 A cross-sectional view taken along line II-II'.

[0038] Figure 4 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0039] Figure 5 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0040] Figure 6 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0041] Figure 7 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0042] Figure 8 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0043] Fig. 9 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0044] Fig.10 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0045] Fig.11 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0046] Fig.12 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0047] Fig.13 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0048] Fig.14 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0049] Fig.15 is a plan view of a thin film transistor according to another embodiment of the present invention.

[0050] Fig.16A is a plan view of a thin film transistor according to another embodiment of the present invention.

[0051] Fig. 16B is a plan view of a thin film transistor according to a comparative example.

[0052] Fig.17is a graph obtained by measuring the threshold voltage Vth of thin film transistors according to the embodiment of the present invention and a comparative example.

[0053] Fig.18 is a schematic diagram of a display device according to an embodiment of the present invention.

[0054] Fig.19 is a schematic diagram of a shift register according to an embodiment of the present invention.

[0055] Fig. 20 According to an embodiment of the present invention Fig.18 The circuit diagram of any pixel.

[0056] Fig.21 According to an embodiment of the present invention Fig. 20 A floor plan of pixels.

[0057] Fig. 22 According to an embodiment of the present invention, Fig.21 A cross-sectional view taken along line III-III'.

[0058] Fig.23 is a circuit diagram of any one pixel of a display device according to another embodiment of the present invention.

[0059] Fig.24 is a circuit diagram of any one pixel of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The advantages and features of the present disclosure and their implementation methods will be explained by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.

[0061] The shapes, sizes, ratios, angles, and numbers disclosed in the drawings used to describe the embodiments of the present disclosure are examples only, and therefore the present disclosure is not limited to the details shown. Throughout the specification, similar reference numerals refer to similar elements. In the following description, when it is determined that the detailed description of related known functions or configurations unnecessarily obscures the main points of the present disclosure, the detailed description will be omitted.

[0062] In the case where “including,” “having,” and “comprising” described in the present disclosure are used, another part may be added unless “only to” is used. Terms in the singular form may include plural forms unless indicated otherwise.

[0063] When constituting an element, the element is interpreted as including an error band although there is no explicit description.

[0064] When describing a positional relationship, for example, when the positional relationship is described as "on," "above," "below," and "adjacent to," one or more parts may be set between two other parts unless "immediately" or "directly" is used.

[0065] Spatially relative terms such as "below," "beneath," "below," "above," and "above" may be used herein to easily describe the relationship of one element or elements to another element or elements as shown in the accompanying drawings. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the accompanying drawings. For example, if the device shown in the figure is inverted, a device described as being disposed "below" or "below" another device may be disposed "above" the other device. Thus, the exemplary terms "below or below" may include both "below or below" and "above" orientations. Similarly, the exemplary terms "above" or "above" may include both "above" and "below or below" orientations.

[0066] When describing a time relationship, for example, when a time sequence is described as “after,” “subsequently,” “next,” and “before,” discontinuous cases may be included unless “immediately” or “directly” is used.

[0067] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0068] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, and each element of the first element, the second element, and the third element.

[0069] The features of the various embodiments of the present disclosure may be coupled or combined with each other in part or in whole, and may interoperate and be technically driven with each other in various ways, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0070] When adding reference numerals to components of each of the drawings describing embodiments of the present disclosure, the same components may have the same numerals as may be displayed on other drawings.

[0071] In the embodiments of the present disclosure, the source electrode and the drain electrode are distinguished for ease of description, and the source electrode and the drain electrode can be interchanged. The source electrode can be a drain electrode, and vice versa. In addition, the source electrode of any embodiment can be a drain electrode in another embodiment, and the drain electrode of any embodiment can be a source electrode in another embodiment.

[0072] In some embodiments of the present disclosure, for ease of description, the source region is separated from the source electrode region, and the drain region is separated from the drain electrode region, but the embodiments of the present disclosure are not limited thereto. The source region may be a source electrode, and the drain region may be a drain electrode. In addition, the source region may be a drain electrode, and the drain region may be a source electrode.

[0073] Figure 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional view taken along line II′. Figure 3 According to an embodiment of the present invention, Figure 1 A cross-sectional view taken along line II-II′.

[0074] Specifically, refer to Figure 1 , Figure 2 and Figure 3 , may include an active layer 130 on a base substrate 110 and a gate electrode 150 spaced apart from and partially overlapping the active layer 130 .

[0075] According to an embodiment of the present invention, the thin film transistor 100 may further include a base substrate 110. Figure 2 and Figure 3 , an active layer 130 is disposed on the base substrate 110 .

[0076] According to an embodiment of the present invention, the thin film transistor 100 may further include a buffer layer 120. Figure 2 and Figure 3 , the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the base substrate 110 and the active layer 130.

[0077] According to an embodiment of the present invention, the thin film transistor 100 may further include a gate insulating layer 140. Figure 2 and Figure 3, the gate insulating layer 140 is disposed on the active layer 130 . Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150 .

[0078] According to an embodiment of the present invention, the thin film transistor 100 may further include another layer disposed on the gate electrode 150. In detail, the thin film transistor 100 may further include an interlayer insulating layer 180. Figure 3 , the interlayer insulating layer 180 is disposed on the gate electrode 150. In detail, the gate electrode 150 is disposed between the gate insulating layer 140 and the interlayer insulating layer 180.

[0079] According to an embodiment of the present invention, the thin film transistor 100 may further include a source electrode 160 and a drain electrode 170. Figure 1 , Figure 2 and Figure 3 , a source electrode 160 and a drain electrode 170 are disposed on the gate insulating layer 140 .

[0080] Hereinafter, components of the thin film transistor 100 according to an embodiment of the present invention will be described in more detail.

[0081] Glass or plastic may be used as the base substrate 110. As the plastic, a transparent plastic having a flexible property, such as polyimide, may be used.

[0082] When polyimide is used as the base substrate 110, heat-resistant polyimide that can withstand high temperatures may be used in consideration of performing a high-temperature deposition process on the base substrate 110. In this case, in order to form a thin film transistor, processes such as deposition, etching, etc. may be performed in a state where a polyimide substrate is disposed on a carrier substrate made of a highly durable material such as glass.

[0083] Reference Figure 2 and Figure 3 , a buffer layer 120 may be disposed on the base substrate 110 .

[0084] The buffer layer 120 may be formed on the base substrate 110 and may be formed of an inorganic material or an organic material. For example, an insulating oxide such as silicon oxide (SiOx), aluminum oxide (Al2O3), etc. may be included.

[0085] The buffer layer 120 blocks impurities such as moisture and oxygen from flowing out of the base substrate 110 to protect the active layer 130 , planarizes an upper portion of the base substrate 110 , and may be formed as a single layer or a multi-layer.

[0086] Reference Figure 2 and Figure 3 , an active layer 130 may be disposed on the buffer layer 120 .

[0087] The active layer 130 may include a channel region 130 n , a source region 130 a , and a drain region 130 b .

[0088] The channel region 130n overlaps the gate electrode 150. The channel region 130n functions as a channel of the thin film transistor 100.

[0089] Specifically, the active layer 130 may include a channel region 130n partially overlapping with the gate electrode 150 in a plane or in a plan view, a source region 130a connected to one side of the channel region 130n in a plane or in a plan view without overlapping with the gate electrode 150, and a drain region 130b connected to the other side of the channel region 130n in a plane or in a plan view without overlapping with the gate electrode 150.

[0090] According to an embodiment of the present invention, the source region 130 a and the drain region 130 b are spaced apart from each other, wherein the channel region 130 n is interposed between the source region 130 a and the drain region 130 b .

[0091] According to the configuration of the present invention, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0092] The oxide semiconductor material may include at least one of an oxide semiconductor material based on IZO (InZnO), an oxide semiconductor material based on IGO (InGaO), an oxide semiconductor material based on ITO (InSnO), an oxide semiconductor material based on IGZO (InGaZnO), an oxide semiconductor material based on IGZTO (InGaZnSnO), an oxide semiconductor material based on GZTO (GaZnSnO), an oxide semiconductor material based on GZO (GaZnO), an oxide semiconductor material based on ITZO (InSnZnO), and an oxide semiconductor material based on FIZO (FeInZnO). However, the embodiments of the present invention are not limited thereto, and the active layer 130 may be made of another oxide semiconductor material known in the art.

[0093] For the active layer 130 made of semiconductor material, the source region 130a and the drain region 130b can be formed by selectively conducting. According to an embodiment of the present invention, imparting conductivity to a specific portion of the active layer 130 so that the portion can be used as a conductor is called selective conduction. The portion imparted with conductivity by selective conduction is converted into a conductor, while the portion not imparted with conductivity is not converted into a conductor.

[0094] Figure 1 , Figure 2 and Figure 3The source region 130 a and the drain region 130 b shown are portions rendered conductive by selective conductivity.

[0095] According to an embodiment of the present invention, selective conductivity may be formed by doping with a dopant. In addition, selective conductivity may be formed by plasma treatment.

[0096] Selective conduction of the active layer 130 may be performed by doping with a dopant using the gate electrode 150 or a photoresist as a mask. The dopant may include, for example, at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0097] When the active layer 130 is selectively conductive by doping the dopant, the region of the active layer 130 doped with the dopant is selectively conductive to become the source region 130a or the drain region 130b. The region of the active layer 130 not doped with the dopant may not be conductive and may become the channel region 130n.

[0098] Alternatively, the active layer 130 may be selectively conductive by a plasma treatment applied to the process of patterning the gate insulating layer 140. For example, plasma may be used in the process of patterning the gate insulating layer 140, and a portion of the active layer 130 in contact with the plasma may be selectively conductive to become a source region 130a or a drain region 130b of the active layer 130. A portion of the active layer 130 protected by the gate insulating layer 140 and not in contact with the plasma may be a channel region 130n that is not conductive.

[0099] exist Figure 1 , Figure 2 and Figure 3 , the configuration in which the active layer 130 is formed of one layer is disclosed, but the configuration of the present invention is not limited thereto. The active layer 130 may have a single layer structure or a multi-layer structure.

[0100] Reference Figure 1 , Figure 2 and Figure 3 , the active hole 135 (e.g., one or more holes in the active layer) where the active layer 130 is not provided is provided in a region where the edge is defined by the active layer 130. According to an embodiment of the present invention, the active hole 135 is provided on a plane or in a region defined by the active layer 130 in a plan view. Specifically, the active hole 135 may be formed by removing a portion of the active layer 130 by patterning.

[0101] Reference Figure 1 and Figure 2, the active hole 135 may be a region formed by removing a portion of the active layer 130. Since the active hole 135 may be referred to as a hole formed in the active layer 130 by removing a portion of the active layer 130, the hole is referred to as an "active hole" according to an embodiment of the present invention.

[0102] According to an embodiment of the present invention, the active hole 135 may include a first active hole 136 partially overlapping the gate electrode 150. Specifically, the active hole 135 includes the first active hole 136, and at least a portion of the first active hole 136 may overlap the gate electrode 150.

[0103] Figure 1 and Figure 2 A configuration in which a portion of the first active hole 136 overlaps the gate electrode 150 is shown.

[0104] A gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 protects the channel region 130n.

[0105] The gate insulating layer 140 has insulating properties. The gate insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0106] Reference Figure 2 and Figure 3 , the gate insulating layer 140 is not patterned, and may be disposed on the entire surface of the base substrate 110. However, the embodiments of the present invention are not limited thereto, and the gate insulating layer 140 may have a patterned structure.

[0107] A gate electrode 150 is disposed on the gate insulating layer 140 . The gate electrode 150 overlaps the channel region 130 n of the active layer 130 .

[0108] The gate electrode 150 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, silver-based metals such as silver (Ag) or silver alloys, copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, and chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multilayer structure including at least two conductive layers, each having different physical properties. For example, the gate electrode 150 may include at least one of molybdenum (Mo) and titanium (Ti).

[0109] According to an embodiment of the present invention, the gate insulating layer 140 may be patterned by etching using the gate electrode 150 as a mask, and in this process, the active layer 130 may be selectively conductive to form the source region 130a and the drain region 130b. Specifically, according to an embodiment of the present invention, a region of the active layer 130 overlapping with the gate electrode 150 is not conductive to form a channel region 130n having semiconductor characteristics, while a region not overlapping with the gate electrode 150 may be conductive to form the source region 130a and the drain region 130b.

[0110] Reference Figure 2 and Figure 3 An interlayer insulating layer 180 may be disposed on the gate electrode 150. The interlayer insulating layer 180 may be formed of an organic insulating material or an inorganic insulating material. The interlayer insulating layer 180 may be formed of a composite layer of an organic layer and an inorganic layer.

[0111] According to an embodiment of the present invention, the thin film transistor 100 may include a source electrode 160 and a drain electrode 170 disposed on the interlayer insulating layer 180. The position of the source electrode 160 and the position of the drain electrode 170 may be inverted. However, the embodiment of the present invention is not limited thereto, and the source region 130a and the drain region 130b may be used as the source electrode and the drain electrode, respectively.

[0112] Reference Figure 1 , Figure 2 and Figure 3 , the source electrode 160 and the drain electrode 170 may be connected to the active layer 130 through the contact holes, respectively. Specifically, the source electrode 160 may contact the source region 130a through the contact hole. The drain electrode 170 may be spaced apart from the source electrode 160 and may contact the drain region 130b through the contact hole.

[0113] Reference Figure 1 , Figure 2 and Figure 3 , a light blocking layer 111 may be disposed on the base substrate 110. Specifically, the light blocking layer 111 may be disposed between the base substrate 110 and the active layer 130. The light blocking layer 111 overlaps the channel region 130n. The light blocking layer 111 blocks light incident from the outside, thereby protecting the channel region 130n.

[0114] The light blocking layer 111 may be formed of a material having light blocking properties. The light blocking layer 111 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to an embodiment of the present invention, the light blocking layer 111 may have electrical conductivity.

[0115] The light blocking layer 111 may be omitted. In addition, a buffer layer may be additionally disposed between the base substrate 110 and the light blocking layer 111. The light blocking layer 111 may be electrically connected to one of the source electrode 160 and the drain electrode 170. Figure 2 A configuration in which the light blocking layer 111 is electrically connected to the source electrode 160 is shown.

[0116] According to an embodiment of the present invention, a portion of the first active hole 136 may not overlap with the gate electrode 150 . Figure 1 The following configuration is shown in the plan view: a portion of the active hole 136 overlaps with a portion of the gate electrode 150, and another portion of the first active hole 136 is arranged along the first direction X away from the gate electrode 150 (for example, another portion of the active hole 136 may not overlap with the gate electrode 150) and toward the source region 130a or the drain region 130b.

[0117] Specifically, according to an embodiment of the present invention, the first active hole 136 may include a first region A1 overlapping the gate electrode 150 and a second region A2 not overlapping the gate electrode 150. More specifically, the second region A2 may be disposed away from the gate electrode 150 (e.g., not overlapping) along the first direction X toward the source region 130a or the drain region 130b.

[0118] According to an embodiment of the present invention, if a direction parallel to the shortest line connecting the source region 130a and the drain region 130b is defined as a first direction X, the length of the channel region 130n along the first direction X can be defined as the length of the channel region, and if a direction perpendicular to the first direction X is defined as a second direction Y, the width of the channel region 130n along the second direction Y can be defined as the width of the channel region.

[0119] In the case where the channel region 130n has a large width, when the conduction is performed relative to the source region 130a and the drain region 130b, the interface between the channel region 130n and the conduction portion increases, and thus the conduction diffusion toward the channel region 130n may be greatly performed. When the conduction diffusion toward the channel region 130n is greatly performed, the threshold voltage Vth of the thin film transistor 100 may move in the negative (-) direction, and the driving stability of the thin film transistor 100 may be deteriorated. For example, when the channel region 130n is wide, more dopants may be concentrated at the central area at the edge of the gate electrode 150, and the dopants may penetrate deeper and may extend laterally to penetrate under the gate electrode 150. In other words, the conduction diffusion may extend farther and deeper, which may be undesirable in some cases and may cause non-uniformity.

[0120] On the other hand, when the channel region (130n) has a small width, the interface between the channel region (130n) and the conductive portion is reduced, thereby suppressing conductive diffusion toward the channel region (130n), while excessive oxygen flows into the channel region (130n) and reliability degradation occurs.

[0121] According to an embodiment of the present invention, Figure 1 As shown, the first active hole 136 is formed in the boundary region between the channel region 130n and the source region 130a and the boundary region between the channel region 130n and the drain region 130b. For example, the first active hole 136 may include two holes in the active layer 130 disposed on opposite sides of the gate electrode 150. Therefore, the boundary surface between the channel region 130n and the source region 130a and the boundary surface between the channel region 130n and the drain region 130b are reduced, and thus the conductive diffusion toward the channel region 130n can be suppressed. For example, the holes in the active layer 130 can be used to block or control the penetration or absorption of dopants into the active layer 130.

[0122] Therefore, even if the channel region 130n has a large width, the movement of the threshold voltage (Vth) of the thin film transistor 100 in the negative (-) direction is suppressed, thereby improving the driving stability of the thin film transistor 100. In this way, when many thin film transistors are manufactured, their characteristics can be uniformly controlled, which can improve image quality, produce more uniform display images, and reduce defects.

[0123] According to an embodiment of the present invention, the first active hole 136 may include a first region A1 overlapping the gate electrode 150 and a second region A2 not overlapping the gate electrode 150. In this case, the area of ​​the second region A2 of the first active hole 136 may be greater than or equal to the area of ​​the first region A1 of the first active hole 136. For example, the hole in the active layer 130 may have a square shape and a portion of the square hole overlapping the gate electrode 150 may have a triangular shape, but the embodiment is not limited thereto. For example, the hole in the active layer 130 for controlling the diffusion of the conductive material may have various shapes, such as square, circular, oval, polygonal, triangular, etc., which are discussed in more detail below with respect to various embodiments.

[0124] The area of ​​the first region A1 and the area of ​​the second region A2 mean an area occupied by the first region A1 and an area occupied by the second region A2 when viewed in a plan view.

[0125] According to an embodiment of the present invention, as the area of ​​the second region A2 not overlapping the gate electrode 150 increases, when the conduction with respect to the source region 130a and the drain region 130b is performed, the conduction diffusion toward the channel region 130n can be suppressed. Therefore, the movement of the threshold voltage Vth of the thin film transistor 100 in the negative (-) direction is suppressed, and thus the driving stability of the thin film transistor 100 can be improved. In other words, the portion of the hole in the active layer 130 that does not overlap the gate electrode 150 can be larger than the portion of the hole that overlaps the gate electrode 150.

[0126] In addition, according to the embodiment of the present invention, since the area of ​​the first region A1 overlapping the gate electrode 150 is small, the area of ​​the channel region 130n is prevented from being reduced, so that a sufficient area of ​​the channel region 130n can be ensured. In other words, the channel region 130n can be made as large as possible while still optimally managing the amount of conductive diffusion. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured.

[0127] According to an embodiment of the present invention, when a direction parallel to the shortest line connecting the source region 130a and the drain region 130b is referred to as a first direction X and a direction perpendicular to the first direction X is referred to as a second direction Y, a length L1 of an area where an arbitrary straight line LNY parallel to the second direction Y overlaps the first region A1 in a plane may decrease as the distance from the second region A2 with respect to the first direction X increases.

[0128] More specifically, the length of the region where an arbitrary straight line LNY parallel to the second direction Y and the first area A1 overlap each other in a plan view means the length L1 of a line segment where the arbitrary straight line LNY parallel to the second direction Y and the first area A1 overlap each other. More specifically, when the length of the first active hole 136 in the second direction Y is defined as the length of the first active hole 136 , the length of the first area A1 of the first active hole 136 decreases toward the inside of the gate electrode 150 .

[0129] exist Figure 1 , a configuration is shown in which the length L1 of the region where the arbitrary straight line LNY parallel to the second direction Y overlaps the first region A1 decreases toward the inside of the gate electrode 150. Therefore, the area of ​​the channel region 130n can be prevented from being reduced, and thus a sufficient area of ​​the channel region 130n can be ensured. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured.

[0130] In addition, Figure 1 , a configuration is shown in which the length L1 of the region where the arbitrary straight line LNY parallel to the second direction Y overlaps the first area A1 is constantly reduced toward the inside of the gate electrode 150. However, embodiments of the present invention are not limited thereto, and may be rapidly or gradually reduced toward the inside of the gate electrode 150.

[0131] According to an embodiment of the present invention, the first active hole 136 may include a first source active hole 136s disposed on one side of the gate electrode 150 toward the source region 130a along the first direction X in the plane, and a first drain active hole 136d disposed on the other side of the gate electrode 150 toward the drain region 130b in the plane along the first direction X. In other words, the first source active hole 136s and the first drain active hole 136d may overlap opposite edges of the gate electrode 150.

[0132] Figure 1 A configuration is shown in which the first source active hole 136 s and the first drain active hole 136 d are disposed along the first direction X from the gate electrode 150 toward the source region 130 a and the drain region 130 b , respectively.

[0133] According to an embodiment of the present invention, the first source active hole 136 s and the first drain active hole 136 d are disposed to be spaced apart from each other.

[0134] Figure 1 A configuration is shown in which the first source active hole (136s) and the first drain active hole (136d) are spaced apart from each other and the gate electrode (150) is interposed between the first source active hole (136s) and the first drain active hole (136d).

[0135] According to an embodiment of the present invention, a straight line LNX passing through at least a portion of the first source active hole 136s among any straight lines parallel to the first direction X may pass through the first drain active hole 136d.

[0136] exist Figure 1 , a configuration is shown in which the first source active hole 136s and the first drain active hole 136d are arranged on any straight line parallel to the first direction X. Specifically, in Figure 1 , a configuration is shown in which the first source active hole 136s and the first drain active hole 136d overlap each other with respect to the first direction X. However, embodiments of the present invention are not limited thereto, and at least a portion of the first source active hole 136s may overlap at least a portion of the first drain active hole 136d with respect to the first direction X.

[0137] According to the embodiment of the present invention, even when the first source active hole 136s and the first drain active hole 136d are disposed on any straight line parallel to the first direction X, the area of ​​the channel region 130n can be prevented from being reduced, and thus a sufficient area of ​​the channel region 130n can be ensured. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured.

[0138] Figure 4is a plan view of a thin film transistor 200 according to another embodiment of the present invention.

[0139] According to an embodiment of the present invention, a straight line LNX passing through at least a portion of the first source active hole 136s among any straight lines parallel to the first direction X may not pass through the first drain active hole 136d.

[0140] Figure 4 The configuration in which the first source active hole 136s and the first drain active hole 136d are not arranged together on any straight line parallel to the first direction X is shown. Specifically, Figure 4 A configuration is shown in which the first source active hole 136 s and the first drain active hole 136 d are spaced apart from each other with respect to the first direction X. For example, the first source active hole 136 s and the first drain active hole 136 d may be “catty-cornered” with respect to each of the opposite sides of the gate electrode 150 .

[0141] According to the embodiment of the present invention, even when the first source active hole 136s and the first drain active hole 136d are not disposed together on any straight line parallel to the first direction X, the area of ​​the channel region 130n can be prevented from being reduced, and thus a sufficient area of ​​the channel region 130n can be ensured. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured.

[0142] According to an embodiment of the present invention, the first active hole 136 may have a shape such as a semicircular shape, a fan shape, an arc shape, and a polygonal shape. However, the embodiment of the present invention is not limited thereto, and the first active hole 136 may have various shapes.

[0143] Figure 5 is a plan view of a thin film transistor 300 according to another embodiment of the present invention. Figure 6 is a plan view of a thin film transistor 400 according to another embodiment of the present invention.

[0144] Reference Figure 5 , the first active hole 136 may have a triangular shape among polygons. Specifically, Figure 5A configuration is shown in which each of the first source active hole 136s and the first drain active hole 136d has an isosceles triangle shape. Even in the case where the shapes of the first source active hole 136s and the first drain active hole 136d are triangles, when the second area A2 of the first source active hole 136s and the first drain active hole 136d is greater than or equal to the first area A1, the reduction of the channel region 130n can be prevented, and thus a sufficient area of ​​the channel region 130n can be ensured. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured. For example, the first source active hole 136s and the first drain active hole 136d may have a triangular shape disposed on opposite sides of the gate electrode pointing to each other, but the embodiment is not limited thereto.

[0145] Reference Figure 6 , the first active hole 136 may have an arcuate shape in a polygonal shape. Specifically, Figure 6 A configuration in which each of the first source active hole 136s and the first drain active hole 136d has an arcuate shape is shown. For example, each of the first source active hole 136s and the first drain active hole 136d may have a semi-oval shape or a semi-elliptical shape. Even in the case where the shapes of the first source active hole 136s and the first drain active hole 136d are arcuate shapes, when the second area A2 of the first source active hole 136s and the first drain active hole 136d is greater than or equal to the first area A1, the area of ​​the channel region 130n is prevented from being reduced, and thus a sufficient area of ​​the channel region 130n can be ensured. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured.

[0146] Figure 7 is a plan view of a thin film transistor 500 according to another embodiment of the present invention. Figure 8 is a plan view of a thin film transistor 600 according to another embodiment of the present invention.

[0147] According to an embodiment of the present invention, the first source active hole 136s may include a first sub-active hole 136s1 and a second sub-active hole 136s2 spaced apart from each other, and the first drain active hole 136d may include a first sub-active hole 136d1 and a second sub-active hole 136d2 spaced apart from each other. For example, the plurality of holes in the active layer 130 may be arranged on opposite sides of the gate electrode 150 in a grid pattern (e.g., 2×2, 3×2, 4×2, 4×4, etc.). In addition, the plurality of holes in the active layer 130 may all have the same size, but the embodiment is not limited thereto. For example, according to an embodiment, the plurality of holes in the active layer 130 may have different sizes or mixed shapes and mixed sizes.

[0148] Specifically, refer to Figure 7, the first source active hole 136s and the first drain active hole 136d are spaced apart from each other and the gate electrode 150 is interposed between the first source active hole 136s and the first drain active hole 136d, and the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s are arranged from the gate electrode 150 toward the source region 130a and at a predetermined interval along the first direction X. In addition, the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d are arranged from the gate electrode 150 toward the drain region 130b at a predetermined interval.

[0149] In addition, the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s respectively include a first area A1 overlapping the gate electrode 150 and a second area A2 not overlapping the gate electrode 150, and the second area A2 may be greater than or equal to the first area A1. The first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d also include a first area A1 overlapping the gate electrode 150 and a second area A2 not overlapping the gate electrode 150, and the second area A2 may be greater than or equal to the first area A1.

[0150] Figure 7 and Figure 8 Only four holes in the active layer are shown, but the embodiments of the present invention are not limited thereto, and the first source active hole 136s and the first drain active hole 136d may further include third sub-active holes 136s3 and 136d3 and fourth sub-active holes 136s4 and 136d4, respectively, and may further include five or more sub-active holes.

[0151] According to an embodiment of the present invention, a straight line LNX1 passing through the first sub-active hole 136s1 of the first source active hole 136s among any straight lines parallel to the first direction X may pass through the first sub-active hole 136d1 of the first drain active hole 136d, and a straight line LNX2 passing through the second sub-active hole 136s2 of the first source active hole 136s among any straight lines parallel to the first direction X may pass through the second sub-active hole 136d2 of the first drain active hole 136d.

[0152] Figure 7 A configuration is shown in which the first sub-active hole 136s1 of the first source active hole 136s and the first sub-active hole 136d1 of the first drain active hole 136d are arranged on an arbitrary straight line LNX1 parallel to the first direction X. In addition, a configuration is shown in which the second sub-active hole 136s2 in the first source active hole 136s and the second sub-active hole 136d2 in the first drain active hole 136d are arranged on an arbitrary straight line LNX2 parallel to the first direction X.

[0153] However, the embodiments of the present invention are not limited thereto, and the positions of the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s may be exchanged or offset with each other, and the positions of the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d may also be exchanged or offset with each other.

[0154] According to an embodiment of the present invention, a straight line passing through at least a portion of the first source active hole 136 s among any straight lines parallel to the first direction X may not pass through the first drain active hole 136 d .

[0155] Reference Figure 8 , a straight line LNX1 passing through at least a portion of the first sub-active hole 136s1 of the first source active hole 136s among any straight lines parallel to the first direction X does not pass through any of the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d, and a straight line LNX2 passing through at least a portion of the second sub-active hole 136s2 of the first source active hole 136s among any straight lines parallel to the first direction X does not pass through any of the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d.

[0156] However, the embodiments of the present invention are not limited thereto, and the positions of the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s may be exchanged or offset with each other, and the positions of the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d may also be exchanged or offset with each other.

[0157] Fig. 9 is a plan view of a thin film transistor 700 according to another embodiment of the present invention. Fig.10 is a plan view of a thin film transistor 800 according to another embodiment of the present invention. Fig.11 is a plan view of a thin film transistor 900 according to another embodiment of the present invention. Fig.12 is a view of a thin film transistor 1000 according to another embodiment of the present invention. Fig.13 is a plan view of a thin film transistor 1100 according to another embodiment of the present invention. Fig.14 is a plan view of a thin film transistor 1200 according to another embodiment of the present invention. Fig.15 is a plan view of a thin film transistor 1300 according to another embodiment of the present invention.

[0158] According to an embodiment of the present invention, the first source active hole 136s and the first drain active hole 136d may further include a protrusion P disposed in a direction not parallel to the first direction X. For example, each of the first source active hole 136s and the first drain active hole 136d may have a "cross shape", a "lowercase letter t" shape, or a "plus sign" shape.

[0159] Since the first source active hole 136s and the first drain active hole 136d each further include a protruding portion P disposed in a direction not parallel to the first direction X, when conducting with respect to the source region 130a and the drain region 130b is performed, the conducting diffusion path to the channel region 130n is blocked by the protruding portion P, and thus the conducting diffusion toward the channel region 130n can be greatly suppressed. Therefore, the movement of the threshold voltage (Vth) of the thin film transistor 700 in the negative (-) direction is suppressed, and thus the driving stability of the thin film transistor 700 can be improved.

[0160] Fig. 9 A configuration is shown in which the first source active hole 136s and the first drain active hole 136d are spaced apart from each other and include a protruding portion P disposed in a direction not parallel to the first direction X. For example, each of the first source active hole 136s and the first drain active hole 136d may have a "cross shape," a "lowercase letter t" shape, or a "plus sign" shape, in which a cross member is disposed diagonally or not perpendicular to a base.

[0161] According to an embodiment of the present invention, the protruding portion P of the first source active hole 136s and the first drain active hole 136d may not overlap with the gate electrode 150. In addition, even when the first source active hole 136s and the first drain active hole 136d further include the protruding portion P, respectively, the second area A2 not overlapping with the gate electrode 150 is greater than or equal to the first area A1 overlapping with the gate electrode 150, and the area of ​​the channel region 130n can be prevented from being reduced, and thus a sufficient area of ​​the channel region 130n can be ensured. Therefore, conductive diffusion can be controlled or prevented, and excellent mobility can be ensured.

[0162] According to an embodiment of the present invention, the protruding portions P of the first source active hole 136 s and the first drain active hole 136 d may be disposed in a direction parallel to the second direction Y. As shown in FIG.

[0163] exist Fig. 9, a configuration is shown in which the protruding portion P of the first source active hole 136s and the first drain active hole 136d is disposed in a direction parallel to the second direction Y. Specifically, the protruding portion P may be disposed in a vertical direction relative to some regions of the first source active hole 136s and the first drain active hole 136d, and the first source active hole 136s and the first drain active hole 136d are disposed in a direction parallel to the first direction X. However, the embodiments of the present invention are not limited thereto, and the protruding portion P of the first source active hole 136s and the protruding portion P of the first drain active hole 136d may be disposed in a direction not parallel to the second direction Y (see Fig.10 ), the protrusion portion P may be disposed in only one of the first source active hole 136s and the first drain active hole 136d in the second direction Y (see Fig.11 ), and the protrusion portion P may be disposed in both directions in the second direction Y in the first source active hole 136s and the first drain active hole 136d (see Fig.12 ). For example, each of the first source active hole 136s and the first drain active hole 136d may have a "capital T letter shape" or an "L" shape. In addition, each of the first source active hole 136s and the first drain active hole 136d may have point symmetry with respect to a center point between the first source active hole 136s and the first drain active hole 136d, but the embodiment is not limited thereto. For example, each of the first source active hole 136s and the first drain active hole 136d may have mirror symmetry, or be arranged symmetrically with respect to a center point between the first source active hole 136s and the first drain active hole 136d.

[0164] According to an embodiment of the present invention, the first source active hole 136s may include a first sub-active hole 136s1 and a second sub-active hole 136s2 spaced apart from each other, and the first drain active hole 136d may include a first sub-active hole 136d1 and a second sub-active hole 136d2 spaced apart from each other. For example, a plurality of "cross-shaped" holes may be provided in the active layer 130 at opposite sides of the gate electrode 150, and the holes may be arranged in a grid (e.g., 2×2, 3×2, 4×2, 4×4, etc.), but the embodiment is not limited thereto.

[0165] Specifically, refer to Fig.13, the first source active hole 136s and the first drain active hole 136d are respectively spaced apart from each other, wherein the gate electrode 150 is inserted between the first source active hole 136s and the first drain active hole 136d, and the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s are arranged at a predetermined interval while protruding from the gate electrode 150 toward the source region 130a in the first direction X. In addition, the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d protrude from the gate electrode 150 toward the drain region 130b in the first direction X and are arranged at a predetermined interval.

[0166] exist Fig.13 , only the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s and the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d are shown, but the embodiments of the present invention are not limited thereto, and the first source active hole 136s and the first drain active hole 136d may further include third sub-active holes 136s3 and 136d3 and fourth sub-active holes 136s4 and 136d4, respectively, and may further include five or more sub-active holes.

[0167] According to an embodiment of the present invention, the first sub-active hole 136s1 and the second sub-active hole 136s2 of the first source active hole 136s may contact or communicate with each other, and the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d may contact or communicate with each other.

[0168] More specifically, refer to Fig.14 , the protruding portion P of each of the first sub-active hole 136s1 and the second sub-active hole 136s2 may contact each other (for example, two connected crosses or connected "t" shapes). In addition, the protruding portion P of each of the first sub-active hole 136d1 and the second sub-active hole 136d2 of the first drain active hole 136d may contact each other. More specifically, when the first source active hole 136s and the first drain active hole 136d include a plurality of sub-active holes, the protruding portions P of the plurality of sub-active holes may be connected to the protruding portions P of other adjacent sub-active holes. Even in this case, when the conduction with respect to the source region 130a and the drain region 130b is performed, the conduction diffusion path to the channel region 130n is blocked by the protruding portion P, and thus the conduction diffusion toward the channel region 130n may be greatly suppressed. Therefore, movement of the threshold voltage (Vth) of the thin film transistor 700 in the negative (−) direction is suppressed, and thus driving stability of the thin film transistor 700 can be improved.

[0169] According to an embodiment of the present invention, the active hole 135 may further include a second active hole 137 spaced apart from the first active hole 136. For example, the active layer 130 may include a plurality of holes on opposite sides of the gate electrode 150, and the holes may include a mixture of different shapes, sizes, and different orientations.

[0170] Specifically, refer to Fig.15 In addition to the first active hole 136 partially overlapping the gate electrode 150 , the active hole 135 may further include a second active hole 137 spaced apart from the first active hole 136 and not overlapping the gate electrode 150 .

[0171] According to an embodiment of the present invention, the second active hole 137 may have a length in the second direction Y longer than that in the first direction X, and a straight line LNX passing through the first active hole 136 among any straight lines parallel to the first direction X may pass through the second active hole 137 .

[0172] According to an embodiment of the present invention, the second active hole 137 may include a second source active hole 137s disposed in a plane or along the first direction X in a plan view from the gate electrode 150 toward the source region 130a, and a second drain active hole 137d disposed in a plane or along the first direction X in a plan view from the gate electrode 150 toward the drain region 130b.

[0173] Specifically, refer to Fig.15 , shows a configuration in which the first source active hole 136s and the first drain active hole 136d of the first active hole 136 are arranged in a straight line with the second source active hole 137s and the second drain active hole 137d parallel to the second active hole 137 and an arbitrary straight line LNX in the first direction X. However, the embodiments of the present invention are not limited thereto, and the first source active hole 136s and the second source active hole 137s of the first active hole 136 and the second source active hole 137 are arranged in a straight line with an arbitrary straight line LNX parallel to the first direction X, or the first drain active hole 136d and the second drain active hole 137d of the first active hole 136 and the second drain active hole 137d are arranged in a straight line with an arbitrary straight line LNX parallel to the first direction X, but the source active holes 136s and 137s and the drain active holes 136d and 137d are not necessarily arranged in a straight line with the arbitrary straight line LNX parallel to the first direction X.

[0174] Fig.16A is a plan view of a thin film transistor according to an embodiment of the present invention. Fig. 16B is a plan view of a thin film transistor according to a comparative example in which the active layer 130 does not include any active hole. Fig.17 is a graph measuring threshold voltages Vth of thin film transistors according to example embodiments and comparative examples.

[0175] Reference Fig.17 , graph "a" shows the Fig.16A The threshold voltage Vth measurement result of the thin film transistor of the embodiment of the present invention is shown in the curve "b". Fig. 16B The threshold voltage Vth measurement result of the thin film transistor of the comparative example.

[0176] exist Fig.17 In the graph, the horizontal axis represents the gate voltage V GS , and the vertical axis represents the logarithmic value of the drain-source current IDS.

[0177] Reference Fig.16A , the thin film transistor according to the embodiment may include the first active hole 136, and the thin film transistor according to the embodiment may be Figures 1 to 15 Any one of the thin film transistors 100, 200, 300, 400, 500, 600, 800, 900, 1000, 1100, 1200 and 1300. In contrast, referring to Fig. 16B , the thin film transistor according to the comparative example does not include the active hole 135 .

[0178] Reference Fig.17 , in the case corresponding to the graph "a" of the embodiment including the first active hole 136, when the conductive is performed relative to the source region 130a and the drain region 130b, the diffusion of the conductive toward the channel region 130n can be suppressed. Therefore, the movement of the threshold voltage (Vth) of the thin film transistor 100 in the negative (-) direction can be suppressed, and therefore, the driving stability of the thin film transistor 100 can be improved. In addition, the area of ​​the channel region 130n can be prevented from being reduced, so that a sufficient area of ​​the channel region 130n can be ensured. Therefore, the diffusion of the conductive can be controlled or prevented, and excellent mobility can be ensured.

[0179] On the other hand, in the case corresponding to the graph "b" of the comparative example B not including the first active hole 136, the conductivity of the source region 130a and the drain region 130b can continue and penetrate under the gate electrode, and therefore, the conductivity diffusion toward the channel region 130n can be performed to a large extent, which reduces the size of the channel region. Therefore, it can be confirmed that the threshold voltage Vth of the thin film transistor moves in the negative (-) direction, which may impair the driving stability.

[0180] Fig.18 is a schematic diagram illustrating a display device 2000 according to still another embodiment of the present disclosure.

[0181] like Fig.18As shown, a display device 2000 according to still another embodiment of the present disclosure may include a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0182] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in intersection regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on a base substrate 110 .

[0183] The controller 340 controls the gate driver 320 and the data driver 330 .

[0184] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using a signal supplied from an external system (not shown). In addition, the controller 340 samples input image data input from the external system, realigns the sampled data, and supplies the realigned digital image data RGB to the data driver 330.

[0185] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, a control signal for controlling a shift register may be included in the gate control signal GCS.

[0186] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0187] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. In detail, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0188] According to one embodiment of the present disclosure, the gate driver 320 may be packaged on the display panel 310. In this manner, a structure in which the gate driver 320 is directly packaged on the display panel 310 will be referred to as a gate-in-panel (GIP) structure. In detail, in the gate-in-panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0189] The display device 2000 according to one embodiment of the present disclosure may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200 and 1300. According to one embodiment of the present disclosure, the gate driver 320 may include the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200 and 1300.

[0190] The gate driver 320 may include a shift register 350 .

[0191] The shift register 350 sequentially supplies gate pulses to the gate lines GL within one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame means a period of time during which one image is output through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0192] In addition, the shift register 350 supplies a gate-off signal capable of turning off the switching device to the gate line GL during another frame period during which no gate pulse is supplied. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0193] The shift register 350 may include the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , 1100 , 1200 , and 1300 described above.

[0194] Fig.19 is a schematic diagram showing the shift register 350 .

[0195] Reference Fig.19 , the shift register 350 may include g number of stages 351 (ST1 to STg).

[0196] The shift register 350 transmits one scan signal SS to the pixel P connected to one gate line GL through one gate line GL. Each of the stages 351 may be connected to one gate line GL. When g number of gate lines GL are formed in the display panel 110, the shift register 350 may include g number of stages 351 (ST1 to STg), and may generate g number of scan signals SS1 to SSg.

[0197] Generally, each stage 351 outputs the gate pulse GP once during one frame, and the gate pulse GP is sequentially output from each stage 351 .

[0198] Fig. 20 It is shown Fig.18 Circuit diagram of any pixel P in .

[0199] Fig. 20 The circuit diagram of FIG. 7 is an equivalent circuit diagram of a pixel P of a display device 2000 including an organic light emitting diode (OLED) as a display element 710 .

[0200] Reference Fig. 20 , the pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. In detail, the display device 2000 according to one embodiment of the present disclosure may include a pixel driving circuit PDC on a base substrate 110.

[0201] Fig. 20 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. A display device 2000 according to another embodiment of the present disclosure may include at least one of the above-mentioned thin film transistors 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000, 1100, 1200 and 1300.

[0202] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied via the gate line GL.

[0203] The data line DL supplies a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0204] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0205] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0206] The amount of current supplied to the organic light emitting diode (OLED) as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray scale of light output from the display element 710 may be controlled.

[0207] Fig.21 According to the embodiments of the present disclosure Fig. 20 The pixel plane diagram, and Fig. 22 According to the embodiments of the present disclosure Fig.21 A cross-sectional view taken along line III-III'.

[0208] Reference Fig.21 and Fig. 22 , a first thin film transistor TR1 and a second thin film transistor TR2 are disposed on a base substrate 110 .

[0209] The base substrate 110 may be made of glass or plastic. As the base substrate 110, plastic having flexible properties such as polyimide (PI) may be used.

[0210] The light blocking layer 111 is disposed on the base substrate 110. The light blocking layer 111 may have a light blocking property. The light blocking layer 111 may block light incident from the outside to protect the active layers A1 and A2 from damage or degradation.

[0211] The buffer layer 120 is disposed on the light blocking layer 111. The buffer layer 120 is made of an insulating material, and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside.

[0212] A first active layer A1 of the first thin film transistor TR1 and a second active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 120 .

[0213] The first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0214] In the first thin film transistor TR1, the first active layer A1 may include a channel region, a source region, and a drain region. The channel region of the first active layer A1 overlaps the gate electrode G1. According to another embodiment of the present invention, the source region may be referred to as a source electrode S1, and the drain region may be referred to as a drain electrode D1.

[0215] In the second thin film transistor TR1, the second active layer A2 may include a channel region, a source region, and a drain region. The channel region of the second active layer A2 overlaps the gate electrode G2. According to another embodiment of the present invention, the source region may be referred to as a source electrode S2, and the drain region may be referred to as a drain electrode D2.

[0216] In the first thin film transistor TR1, an active hole 135 in which the first active layer A1 is not disposed is disposed in a region in which an edge thereof is defined by the first active layer A1. The active hole 135 may be a region formed by removing the active layers A1 and A2.

[0217] The active holes 135 include a first active hole 136, and at least a portion of the first active hole 136 may overlap the gate electrodes G1 and G2. Specifically, the first active hole 136 includes a first source active hole 136s and a first drain active hole 136d disposed from the gate electrodes G1 and G2, and at least a portion of each of the first source active hole 136s and the first drain active hole 136d may overlap the gate electrodes G1 and G2.

[0218] A gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 covers upper surfaces of the active layers A1 and A2.

[0219] The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140 .

[0220] Although not shown in the drawings, a gate line GL may be disposed on the gate insulating layer 140. The gate electrode G1 of the first thin film transistor TR1 may extend from the gate line GL or may be a part of the gate line GL.

[0221] Reference Fig.21 and Fig. 22 , a first capacitor electrode CE1 of the storage capacitor Cst is formed on the gate insulating layer 140. The first capacitor electrode CE1 may be formed of the same material as the gate electrodes G1 and G2 through the same process.

[0222] An interlayer insulating layer 180 is disposed on the gate electrodes G1 and G2 and the first capacitor electrode CE1 .

[0223] The data line DL and the driving power line PL are disposed on the interlayer insulating layer 180. In addition, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 and the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are disposed on the interlayer insulating layer 180.

[0224] The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL, and may have a structure extending from the data line DL.

[0225] The source electrode S1 of the first thin film transistor TR1 may make contact with a side surface of the active layer A1 of the first thin film transistor TR1 through the first contact hole H1 .

[0226] The drain electrode D1 of the first thin film transistor TR1 contacts the other side surface of the active layer A1 of the first thin film transistor TR1 through the second contact hole H2. In addition, the drain electrode D1 of the first thin film transistor TR1 is connected to the first capacitor electrode CE1 through the third contact hole H3. Therefore, the first capacitor electrode CE1 can be connected to the first thin film transistor TR1.

[0227] The drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL, and may have a structure extending from the driving power line PL.

[0228] The drain electrode D2 of the second thin film transistor TR2 may contact the side surface of the active layer A2 of the second thin film transistor TR2 through the sixth contact hole H6.

[0229] The source electrode S2 of the second thin film transistor TR2 contacts the other side surface of the active layer A2 of the second thin film transistor TR2 through the fifth contact hole H5. In addition, the source electrode S2 of the second thin film transistor TR2 is connected to the light blocking layer 111 through the fourth contact hole H4. The same voltage as the source electrode S2 of the second thin film transistor TR2 may be applied to the light blocking layer 111 overlapping the second thin film transistor TR2.

[0230] The source electrode S2 of the second thin film transistor TR2 may extend onto the interlayer insulating layer 180 to form a second capacitor electrode CE2 of the storage capacitor Cst.

[0231] According to an embodiment of the present invention, the first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap each other to form a storage capacitor Cst.

[0232] Reference Fig.21 and Fig. 22 A planarization layer 190 is disposed on the data line DL, the driving power line PL, the source electrodes S1 and S2, the drain electrodes D1 and D2, and the second capacitor electrode CE2. The planarization layer 190 planarizes the upper portion of the first thin film transistor TR1 and the upper portion of the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2. The planarization layer 190 serves as a protective layer.

[0233] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 contacts the second capacitor electrode CE2 through the seventh contact hole H7 formed in the planarization layer 180. Therefore, the first electrode 711 of the display element 710 may be connected to the source electrode S2 of the second thin film transistor TR2.

[0234] A bank layer 750 is disposed at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0235] An organic light emitting layer 712 is provided on the first electrode 711, and a second electrode 713 is provided on the organic light emitting layer 712. Thus, the display element 710 is completed. Fig. 20 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 2000 according to the embodiment of the present invention is an organic light emitting display device.

[0236] Fig.23 is a circuit diagram of any pixel of a display device 2100 according to another embodiment of the present invention.

[0237] Fig.23 is an equivalent circuit diagram of a pixel P of an organic light emitting display device.

[0238] Fig.23 The pixel P of the illustrated display device 2100 includes an organic light emitting diode OLED as a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0239] In the pixel P, signal lines DL, GL, PL, RL, and SCL for supplying signals to the pixel driving circuit PDC are arranged.

[0240] The data voltage Vdata is supplied to the data line DL, the scan signal SS is supplied to the gate line GL, the driving voltage Vdd for driving pixels is supplied to the driving power line PL, the reference voltage Vref is supplied to the reference line RL, and the sensing control signal SCS is supplied to the sensing control line SCL.

[0241] The pixel driving circuit PDC includes, for example, a first thin film transistor TR1 (switching transistor), which is connected to the gate line GL and the data line DL; a second thin film transistor TR2 (driving transistor), which controls the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1; and a third thin film transistor TR3 (sensing transistor), which is used to sense the characteristics of the second thin film transistor TR2.

[0242] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2 .

[0243] The third thin film transistor TR3 is connected to the first node n1 and the reference line RL between the second thin film transistor TR2 and the display element 710, is turned on or off by the sensing control signal SCS, and detects characteristics of the second thin film transistor TR2 which is a driving transistor during sensing.

[0244] The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1. The storage capacitor Cst is formed between the second node n2 and the first node n1.

[0245] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged in the storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0246] When the second thin film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin film transistor TR2 by the driving voltage Vdd that drives the pixel, and light is output from the display element 710 .

[0247] A display device 2100 according to another embodiment of the present invention may include at least one of the thin film transistors 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , 1000 , 1100 , 1200 , and 1300 .

[0248] Fig.24 is a circuit diagram of any pixel P of a display device 2200 according to another embodiment of the present invention.

[0249] Fig.24 The pixel P of the illustrated display device 2200 includes an organic light emitting diode OLED as a display element 710, and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0250] The pixel driving circuit PDC includes thin film transistors TR1 , TR2 , TR3 , and TR4 .

[0251] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL that supply drive signals to the pixel drive circuit PDC are arranged.

[0252] and Fig.23 Compared with the pixel P, Fig.24 The pixel P further includes an emission control line EL. An emission control signal EM is supplied to the emission control line EL. Fig.23 Compared with the pixel driving circuit PDC, Fig.24The pixel driving circuit PDC further includes a fourth thin film transistor TR4, which is a light emission control transistor for controlling a light emission time point of the second thin film transistor TR2.

[0253] The first thin film transistor TR1 is turned on by the scan signal SS supplied to the gate line GL, and transmits the data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2 .

[0254] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710 .

[0255] The third thin film transistor TR3 is connected to the reference line RL, is turned on or off by the sensing control signal SCS, and detects characteristics of the third thin film transistor TR3 which is a driving transistor during sensing.

[0256] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the emission control signal EM. When the fourth thin film transistor TR4 is turned on, current is supplied to the second thin film transistor TR2 to output light from the display element 710 .

[0257] A pixel driving circuit PDC according to another exemplary configuration of the present invention may be formed in various structures other than the above-described structure. The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0258] According to the present disclosure, the following advantageous effects can be obtained.

[0259] The thin film transistor according to the embodiment of the present invention includes the active hole, and even if the width of the channel region is increased, conductive diffusion can be controlled or prevented.

[0260] The thin film transistor according to the embodiment of the present invention can control or prevent conductive diffusion by controlling active holes and ensure excellent mobility.

[0261] A thin film transistor including an active hole according to the configuration of the present invention has excellent reliability.

[0262] In addition to the above-mentioned effects, other features and advantages of the present invention will be described below or will be clearly understood by a person having ordinary skill in the art to which the present invention pertains based on such technology and description.

[0263] It will be apparent to those skilled in the art that the above disclosure is not limited to the above embodiments and drawings, and that various substitutions, modifications and variations may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims, and it is intended that all changes or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the present disclosure.

Claims

1. A thin film transistor, comprising: Active layer; as well as a gate electrode, the gate electrode being spaced apart from the active layer, the gate electrode at least partially overlapping the active layer, Wherein, the active layer comprises: a channel region at least partially overlapping the gate electrode in a plan view; a source region connected to one side of the channel region; a drain region connected to the other side of the channel region; and active holes penetrating opposite sides of the active layer, the active holes comprising a first active hole, wherein at least a portion of the first active hole overlaps with the gate electrode, Wherein, the first active hole comprises: a first region overlapping the gate electrode; and a second region, the second region not overlapping the gate electrode, and The area of ​​the second zone is greater than or equal to the area of ​​the first zone.

2. The thin film transistor according to claim 1, wherein: A direction parallel to the shortest line connecting the source region and the drain region is a first direction, and a direction perpendicular to the first direction is a second direction, and The width of the first active hole in the second direction decreases as the distance from the second region in the first direction increases.

3. The thin film transistor according to claim 1, wherein: A direction parallel to the shortest line connecting the source region and the drain region is a first direction, and a direction perpendicular to the first direction is a second direction, Wherein, the first active hole comprises: a first source active hole, the first source active hole extending along the first direction away from the gate electrode and toward the source region; and A first drain active hole is provided, the first drain active hole extending along the first direction away from the gate electrode and toward the drain region, and The first source active hole and the first drain active hole are spaced apart from each other.

4. The thin film transistor according to claim 3, wherein: A straight line parallel to the first direction passes through at least a portion of the first source active hole and also passes through at least a portion of the first drain active hole.

5. The thin film transistor according to claim 3, wherein: A straight line parallel to the first direction passes through at least a portion of the first source active hole and does not pass through the first drain active hole.

6. The thin film transistor according to claim 3, wherein: The first source active hole includes a first sub-active hole and a second sub-active hole spaced apart from each other, and The first drain active hole includes a first sub-active hole and a second sub-active hole which are spaced apart from each other.

7. The thin film transistor according to claim 6, wherein: A straight line parallel to the first direction passes through the first sub-active hole of the first source active hole and passes through the first sub-active hole of the first drain active hole, and Wherein, a straight line parallel to the first direction passes through the second sub-active hole of the first source active hole and passes through the second sub-active hole of the first drain active hole.

8. The thin film transistor according to claim 6, wherein: A straight line parallel to the first direction passes through at least a portion of the first source active hole and does not pass through the first drain active hole.

9. The thin film transistor according to claim 3, wherein: Each of the first source active hole and the first drain active hole further includes a protruding portion disposed in a direction not parallel to the first direction.

10. The thin film transistor according to claim 9, wherein: The protruding portion does not overlap the gate electrode.

11. The thin film transistor according to claim 9, wherein: The first source active hole includes a first sub-active hole and a second sub-active hole spaced apart from each other, and The first drain active hole includes a first sub-active hole and a second sub-active hole which are spaced apart from each other.

12. The thin film transistor according to claim 11, wherein: The first sub-active hole and the second sub-active hole of the first source active hole are in contact with each other or are connected to each other, and The first sub-active hole and the second sub-active hole of the first drain active hole are in contact with each other or connected with each other.

13. The thin film transistor according to claim 3, wherein: The active hole further includes a second active hole spaced apart from the first active hole, wherein the second active hole does not overlap with the gate electrode, and Wherein, a length of the second active hole in the second direction is longer than a length of the second active hole in the first direction.

14. The thin film transistor according to claim 13, wherein: A straight line parallel to the first direction passes through the first active hole and passes through the second active hole.

15. The thin film transistor according to claim 13, wherein: The second active hole comprises: a second source active hole, the second source active hole extending along the first direction away from the gate electrode and toward the source region; and The second drain active hole extends along the first direction away from the gate electrode and toward the drain region.

16. The thin film transistor according to claim 1, further comprising: A source electrode, the source electrode being in contact with the source region through a contact hole; as well as A drain electrode is spaced apart from the source electrode and contacts the drain region through a contact hole.

17. A display device comprising the thin film transistor according to any one of claims 1 to 16.

18. A thin film transistor, comprising: An active layer, wherein the active layer is disposed on a substrate; a gate electrode, the gate electrode overlapping the active layer; a source electrode electrically connected to the active layer; a drain electrode electrically connected to the active layer; as well as at least one hole in the active layer, wherein the at least one hole at least partially overlaps an edge of the gate electrode; wherein the at least one hole comprises two holes penetrating the active layer, wherein the two holes overlap with opposite edges of the gate electrode, and Therein, the two holes have a conical shape pointing towards each other.

19. The thin film transistor according to claim 18, wherein: The two holes have mirror symmetry.

20. The thin film transistor according to claim 18, wherein: The at least one hole comprises a plurality of holes having different sizes or different shapes, and Wherein, each hole of the plurality of holes at least partially overlaps with the gate electrode.

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