Semiconductor device, display panel and chip

Abstract

The semiconductor device, the display panel and the chip disclosed by the embodiments of the present application adopt a first conductor part, a channel part and a second conductor part to be stacked to form a vertical active structure layer, so as to realize a narrow channel; and the growth direction of the crystal grains of the channel part is consistent with the movement of the carriers, so that a structure of a single-crystal-like channel can be realized, thereby improving the mobility of the carriers.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a semiconductor device, a display panel and a chip. BACKGROUND

[0002] Current product chips are made by manufacturers, which are costly. Integrating MUX, source driving circuit (SOURCE), timing control circuit (TCON) and the like of chip circuit on a glass substrate (System On Glass, SOG) can greatly improve the integration of display panel, reduce the dependence on chips and reduce costs. Realizing SOG requires improving the integration, maximum working frequency and current density of existing thin film transistors (TFTs). These all require the TFTs to have shorter channel length, higher mobility and smaller volume.

[0003] Current thin film transistors are mostly amorphous silicon, metal oxide semiconductor and polycrystalline silicon, among which polycrystalline silicon is mostly used in mobile phones, VR and the like due to its high mobility and small device size. However, the mobility and size of polycrystalline silicon used for chip manufacturing cannot meet the requirements. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device, a display panel and a chip, which can realize short channel of thin film transistor while improving carrier mobility.

[0005] Embodiments of the present application provide a semiconductor device, which comprises:

[0006] a substrate; and

[0007] at least one thin film transistor disposed on the substrate; the thin film transistor comprises:

[0008] an active structure layer disposed on the substrate, the active structure layer comprising a first conductor portion, a channel portion and a second conductor portion, the first conductor portion being disposed on the substrate, the channel portion being disposed on a side of the first conductor portion away from the substrate, and the second conductor portion being disposed on a side of the channel portion away from the substrate;

[0009] a first insulating layer covering the active structure layer and the substrate;

[0010] a gate electrode disposed on the first insulating layer and located at least one side of the active structure layer, the gate electrode being at least overlapped with a side surface of the channel portion in a direction parallel to the extension direction of the substrate; and

[0011] a first electrode connected to the first conductor portion and a second electrode connected to the second conductor portion.

[0012] The material of the channel portion is polysilicon, and the growth direction of the crystal grains of the polysilicon is consistent with the moving direction of the carriers.

[0013] Optionally, in some embodiments of the present application, the slope angle of the active structure layer is between 80 degrees and 90 degrees.

[0014] Optionally, in some embodiments of the present application, the thickness of the channel portion is between 5 nanometers and 1 micrometer.

[0015] Optionally, in some embodiments of the present application, the gate electrode includes a first gate electrode and a second gate electrode, the first gate electrode is located on one side of the active structure layer, and the second gate electrode is located on the other side of the active structure layer.

[0016] In the extension direction parallel to the substrate, one side surface of the first conductor portion, one side surface of the channel portion, and one side surface of the second conductor portion are all arranged to overlap the first gate electrode, and the other side surface of the first conductor portion, the other side surface of the channel portion, and the other side surface of the second conductor portion are all arranged to overlap the second gate electrode.

[0017] Optionally, in some embodiments of the present application, the thickness of the first insulating layer is less than the thickness of the first conductor portion.

[0018] Optionally, in some embodiments of the present application, on both sides of the active structure layer, the first gate electrode and the second gate electrode are not arranged to overlap the first conductor portion on the side close to the substrate.

[0019] Optionally, in some embodiments of the present application, the active structure layer includes oppositely arranged first and second side surfaces, the first gate electrode is arranged to cover the side of the first insulating layer opposite to the first side surface, and the second gate electrode is arranged to cover the side of the first insulating layer opposite to the second side surface. The first insulating layer includes a top portion arranged to cover the side of the active structure layer away from the substrate.

[0020] In the orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are both flush with the side of the top portion away from the substrate.

[0021] Optionally, in some embodiments of the present application, the number of thin film transistors is at least two, and in the orthographic projection pattern of the semiconductor device, the gate electrodes and the active structure layers are alternately and spacedly arranged along a first direction, and the first direction is perpendicular to the long axis direction of the channel portion.

[0022] Each of the thin film transistors includes two of the gates, one of the gates is disposed on one side of the active structure layer, and the other of the gates is disposed on the other side of the active structure layer.

[0023] The first electrode, the second electrode and one of the gates are shared between two adjacent thin film transistors.

[0024] Optionally, in some embodiments of the present application, the semiconductor device further includes a first connecting portion disposed in the same layer as the first conductor portion, the first connecting portion is connected to one side of the first conductor portion of at least two of the thin film transistors, and the first electrode is connected to the first connecting portion through a first via hole.

[0025] The semiconductor device further includes a second connecting portion disposed in the same layer as the second conductor portion, the second connecting portion is connected to one side of the second conductor portion of at least two of the thin film transistors, and the second electrode is connected to the second connecting portion through a second via hole.

[0026] Optionally, in some embodiments of the present application, the semiconductor device further includes a third connecting portion disposed in the same layer as the gate, the third connecting portion is connected to one side of the gate of at least two of the thin film transistors.

[0027] In the projection direction of the semiconductor device, a second insulating layer is disposed between the first connecting portion and the third connecting portion, the second insulating layer covers the first connecting portion and exposes the first conductor portion, and the third connecting portion is disposed on the side of the second insulating layer away from the substrate.

[0028] Optionally, in some embodiments of the present application, the semiconductor device further includes a fourth connecting portion and a fifth connecting portion, the fourth connecting portion is disposed in the same layer as the first conductor portion, and the fourth connecting portion is connected to the other side of the first conductor portion of at least two of the thin film transistors.

[0029] The fifth connecting portion is disposed in the same layer as the channel portion, and the fifth connecting portion is connected to one side of the channel portion of at least two of the thin film transistors.

[0030] The second connecting portion, the fourth connecting portion and the fifth connecting portion all extend along the first direction, and in the projection direction of the semiconductor device, the second connecting portion, the fourth connecting portion and the fifth connecting portion are arranged in an overlapping manner.

[0031] Optionally, in some embodiments of the present application, the channel portion and the second conductor portion extend along the long axis direction of the channel portion and cover part of the second insulating layer.

[0032] Optionally, in some embodiments of the present application, the first connecting part, the fourth connecting part and the first conductor part are integrally formed of the same material, the second connecting part and the second conductor part are integrally formed of the same material, the third connecting part and the gate are integrally formed of the same material, and the fifth connecting part and the channel part are integrally formed of the same material.

[0033] Correspondingly, the present application also provides a display panel comprising the semiconductor device according to any one of the above embodiments.

[0034] Correspondingly, the present application also provides a chip comprising the semiconductor device according to any one of the above embodiments.

[0035] The semiconductor device provided by the embodiments of the present application adopts the first conductor part, the channel part and the second conductor part to be stacked to form a vertical active structure layer, so as to realize a narrow channel; and the growth direction of the crystal grain of the channel part is consistent with the movement of the carrier, so as to realize a structure of a single-crystal-like channel, thereby improving the mobility of the carrier. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic diagram of a top view structure of the semiconductor device provided by the embodiments of the present application;

[0037] Figure 2 is a schematic diagram of a cross-sectional view along the AA line in the semiconductor device provided by the embodiments of the present application; Figure 1

[0038] Figure 3 is a schematic diagram of a cross-sectional view along the BB line in the semiconductor device provided by the embodiments of the present application; Figure 1

[0039] Figure 4 is a schematic diagram of a structure of step B1 of the preparation method of the semiconductor device provided by the embodiments of the present application;

[0040] Figure 5 is a schematic diagram of a structure of step B2 of the preparation method of the semiconductor device provided by the embodiments of the present application;

[0041] Figure 6 is a schematic diagram of a structure of step B3 of the preparation method of the semiconductor device provided by the embodiments of the present application;

[0042] Figure 7 is a schematic diagram of a structure of step B4 of the preparation method of the semiconductor device provided by the embodiments of the present application;

[0043] Figure 8 is a schematic diagram of a structure of step B5 of the preparation method of the semiconductor device provided by the embodiments of the present application;

[0044] ​​Figure 9 is a structural schematic diagram of step B6 of the preparation method of the semiconductor device provided in the embodiments of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, but not to limit the present application. In the present application, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, and specifically refer to the direction of the drawing surface in the drawings; and "inner" and "outer" refer to the contour of the device; the words "first", "second", "third" and the like are only used as labels, and do not impose numerical requirements or establish sequences.

[0046] The embodiments of the present application provide a semiconductor device, a display panel and a chip, which are described in detail below. It should be noted that the description order of the following embodiments is not limited as the preferred order of the embodiments.

[0047] Please refer to Figures 1 to 3 The embodiments of the present application provide a semiconductor device 100, which includes a substrate 11 and at least one thin film transistor TFT. The thin film transistor TFT is arranged on the substrate 11.

[0048] The thin film transistor TFT includes an active structure layer 12, a first insulating layer 13, a gate 14, a first electrode 151 and a second electrode 152.

[0049] The active structure layer 12 is arranged on the substrate 11. The active structure layer 12 includes a first conductor part 121, a channel part 122 and a second conductor part 123. The first conductor part 121 is arranged on the substrate 11. The channel part 122 is arranged on the side of the first conductor part 121 away from the substrate 11. The second conductor part 123 is arranged on the side of the channel part 122 away from the substrate 11.

[0050] The first insulating layer 13 covers the active structure layer 12 and the substrate 11. The gate 14 is arranged on the first insulating layer 13 and located on at least one side of the active structure layer 12. In the direction z perpendicular to the orthographic projection direction of the semiconductor device 100, the gate 14 is arranged to overlap at least the side surface of the channel part 122. The first electrode 151 is connected to the first conductor part 121. The second electrode 152 is connected to the second conductor part 123.

[0051] The material of the channel portion 122 is polysilicon, and the growth direction of the crystal grains of the polysilicon is consistent with the moving direction of the carriers.

[0052] The semiconductor device 100 of the embodiment of the present application adopts the first conductor portion 121, the channel portion 122, and the second conductor portion 123 to be stacked to form a vertical active structure layer 12, that is, to take the thickness of the channel portion 122 as the length of the channel, so as to realize a narrow channel. In addition, since the growth direction of the crystal grains of the channel portion 122 is from the first conductor portion 121 to the second conductor portion 123 (the thickness direction of the channel portion 122), the crystal grains of the channel portion 122 are single grains in the thickness direction of the channel portion 122. By arranging the growth direction of the crystal grains of the channel portion 122 to be consistent with the moving direction of the carriers, a structure of a single-crystal-like channel can be realized, so as to improve the mobility of the carriers.

[0053] The crystal grains of the channel portion 122 are arranged in multiple grains in the extension direction parallel to the substrate 11.

[0054] It is to be noted that the extension direction parallel to the substrate 11 is the first direction x. The projection direction z of the semiconductor device 100 is also the thickness direction of each film layer. The long axis direction of the channel portion 122 is the second direction y. The first direction x and the second direction y intersect. Optionally, the first direction x is perpendicular to the second direction y. In some embodiments, the included angle between the first direction x and the second direction y is an acute angle.

[0055] Optionally, the slope angle a of the active structure layer 12 is between 80 degrees and 90 degrees. Such arrangement makes the inversion carriers of the active structure layer mainly concentrate on the surface, and the current from the source to the drain also flows on the surface. Therefore, by controlling the slope angle a to be between 80 degrees and 90 degrees, the moving direction of the carriers can be ensured to move along the growth direction of the crystal grains of the channel portion 122.

[0056] It is to be understood that when the slope angle a is too large or too small, the carriers will cross the grain boundaries, resulting in a reduced mobility.

[0057] Optionally, the slope angle a can be 80 degrees, 81 degrees, 82 degrees, 83 degrees, 84 degrees, 85 degrees, 86 degrees, 87 degrees, 88 degrees, 89 degrees, or 90 degrees. Among them, when the slope angle a is 90 degrees, the mobility of the carriers is the best.

[0058] Optionally, the thickness of the channel portion 122 is between 5 nanometers and 1 micrometer. It is to be understood that if the thickness of the channel portion 122 is too small, the short channel effect cannot be overcome, and if the thickness is too large, the film crystallization is difficult. Therefore, by selecting the thickness of the channel portion 122 to be between 5 nanometers and 1 micrometer, the short channel effect can be overcome, and the difficulty of film crystallization can be reduced.

[0059] Optionally, the thickness of the channel portion 122 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 50 nm, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1 μm.

[0060] Optionally, the material of the first conductor portion 121 and the second conductor portion 123 can be a polysilicon layer doped or implanted with conductive ions, which can be N-type or P-type doping ions, such as phosphorus ions, boron ions, gallium ions, or indium ions, etc.

[0061] Of course, the material of the first conductor portion 121 and the second conductor portion 123 can also be a conductive material, but is not limited thereto.

[0062] Optionally, the thickness of the first conductor portion 121 and the second conductor portion 123 can each be between 30 nm and 300 nm, such as 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 150 nm, 200 nm, 250 nm, or 300 nm.

[0063] The thickness of the first conductor portion 121 and the second conductor portion 123 is selected to be between 30 nm and 300 nm, which avoids excessive resistance of the first conductor portion 121 and the second conductor portion 123, and also avoids excessive film formation time and serious particle diffusion.

[0064] Optionally, in some embodiments, the material of the channel portion 122 can also be other semiconductor materials, such as metal oxides.

[0065] Optionally, one of the first electrode 151 and the second electrode 152 is a source electrode, and the other of the first electrode 151 and the second electrode 152 is a drain electrode.

[0066] The gate electrode 14, the first electrode 151, and the second electrode 152 can be formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, an alloy containing any of the above metal elements, or an alloy combining any of the above metal elements, etc. In addition, the gate electrode 14, the first electrode 151, and the second electrode 152 can have a single-layer structure or a laminated structure of two or more layers.

[0067] Optionally, the semiconductor device 100 can further include a buffer layer 16 disposed between the substrate 11 and the first conductor portion 121.

[0068] The material of the first insulating layer 13 and the buffer layer 16 can be formed by a plurality of inorganic layers stacked in an alternating manner. For example, the first insulating layer 13 can be formed as a double layer formed by stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide, magnesium oxide, and titanium oxide, or a multi-layer formed by alternately stacking inorganic layers including at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide, magnesium oxide, and titanium oxide. However, the present disclosure is not limited thereto, and the first insulating layer 13 and the buffer layer 16 can be formed as a single-layer inorganic layer containing the above-described insulating material.

[0069] Optionally, the substrate 11 can be a hard substrate or a flexible substrate. The material of the substrate 11 includes one of glass, sapphire, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, aromatic fluorine-containing toluene containing polyarylate, polycyclic olefin, polyimide, or polyurethane.

[0070] Optionally, the gate 14 includes a first gate 141 and a second gate 142. The first gate 141 is located on one side of the active structure layer 12, and the second gate 142 is located on the other side of the active structure layer 12.

[0071] The thin film transistor TFT adopts double-gate control, has strong ability to control short channel effect and suppress leakage current, and has strong electrostatic control ability for the inversion channel.

[0072] In the direction perpendicular to the orthographic projection direction z of the semiconductor device 100, that is, in the first direction x, one side surface of the first conductor portion 121, one side surface of the channel portion 122, and one side surface of the second conductor portion 123 are all arranged to overlap the first gate 141. The other side surface of the first conductor portion 121, the other side surface of the channel portion 122, and the other side surface of the second conductor portion 123 are all arranged to overlap the second gate 142.

[0073] In addition to overlapping the channel portion 122, the first gate 141 and the second gate 142 also overlap the first conductor portion 121 and the second conductor portion 123, so as to improve the control ability of the gate 14.

[0074] Optionally, the active structure layer 12 includes a first side surface 12a and a second side surface 12b arranged opposite to each other. The first gate 141 covers one side of the first insulating layer 13 opposite to the first side surface 12a. The second gate 142 covers one side of the first insulating layer 13 opposite to the second side surface 12b. The first insulating layer 13 includes a top portion 131 covering one side of the active structure layer 12 away from the substrate 11.

[0075] In the orthogonal projection direction z of the semiconductor device 100, the first gate 141 and the second gate 142 are flush with the side of the top 131 away from the substrate 11. Such an arrangement can improve the control ability of the first gate 141 and the second gate 142.

[0076] Optionally, the thickness of the first insulating layer 13 is less than the thickness of the first conductor portion 121. Such an arrangement allows the gate 14 to overlap the side of the first conductor portion 121 in the first direction x, so as to ensure that the gate 14 has a stronger control ability.

[0077] In some embodiments, a recess or opening can also be provided on the buffer layer 16, which is located on both sides of the active structure layer 12, so that the first insulating layer 13 covers in the recess or opening, so that the gate 14 can overlap the side of the first conductor portion 121 in the first direction x, or even completely overlap the side of the first conductor portion 121.

[0078] Optionally, on both sides of the active structure layer 12, the side of the gate 14 close to the substrate 11 is not provided with the first conductor portion 121. Such an arrangement avoids the generation of parasitic capacitance between the gate 14 and the first conductor portion 121, and further avoids the GIDL (Gate-induced Drain Leakage) effect.

[0079] Optionally, the number of thin film transistors TFT is at least two. In the orthogonal projection pattern of the semiconductor device 100 (as shown in Figure 1 The gate 14 and the active structure layer 12 are alternately and spacedly arranged along the first direction x, and the first direction x is perpendicular to the long axis direction y of the channel portion 122.

[0080] Each thin film transistor TFT includes two gates 14. In the same thin film transistor TFT, one gate 14 is arranged on one side of the active structure layer 12, and the other gate 14 is arranged on the other side of the active structure layer 12.

[0081] The first electrode 151, the second electrode 152 and one gate 14 are shared between two adjacent thin film transistors TFT; such an arrangement can save material and layout space and reduce process difficulty.

[0082] Since the active structure layer 12 is prepared first and then the first insulating layer 13 is formed, the first insulating layer 13 forms a recess ax between adjacent active structure layers 12, and the gate 14 can be directly formed in the recess ax, and the up-down position of the gate 14 is determined by the depth of the recess ax, so as to realize the effect of self-aligned gate and further reduce the process difficulty.

[0083] Optionally, the semiconductor device 100 further comprises a first connecting portion 171, which is arranged in the same layer as the first conductor portion 121. The first connecting portion 171 is connected to one side of the first conductor portion 121 of at least two thin film transistors TFT. The first electrode 151 is connected to the first connecting portion 171 through a first via hole k1.

[0084] The semiconductor device 100 further comprises a second connecting portion 172, which is arranged in the same layer as the second conductor portion 123. The second connecting portion 172 is connected to one side of the second conductor portion 123 of at least two thin film transistors TFT. The second electrode 152 is connected to the second connecting portion 172 through a second via hole k2.

[0085] The first conductor portion 121 and the first connecting portion 171 are arranged in the same layer and connected, and the materials of the two can be the same, and the two can be prepared and formed by using the same photomask; that is, the first connecting portion 171 is integrally formed with the first conductor portion 121 and made of the same material. In some embodiments, the first connecting portion 171 and the first conductor portion 121 can also be arranged in different layers, and the materials of the two can also be different.

[0086] Secondly, the first via hole k1 is located at the center position of the first connecting portion 171, so that the distance from the center of the first via hole k1 to each first conductor portion 121 is equal, improving the synchronization of signal transmission.

[0087] The second conductor portion 123 and the second connecting portion 172 are arranged in the same layer and connected, and the materials of the two can be the same, and the two can be prepared and formed by using the same photomask. The second connecting portion 172 is integrally formed with the second conductor portion 123 and made of the same material. In some embodiments, the second connecting portion 172 and the second conductor portion 123 can also be arranged in different layers, and the materials of the two can also be different.

[0088] Secondly, the second via hole k2 is located at the center position of the second connecting portion 172, so that the distance from the center of the second via hole k2 to each second conductor portion 123 is equal, improving the synchronization of signal transmission.

[0089] Optionally, in the orthographic projection pattern of the semiconductor device 100, the pattern of the first via hole k1 and the pattern of the second via hole k2 are arranged symmetrically about the first direction x axis, which can shorten the distance of signal transmission and improve the transmission rate of signals.

[0090] Optionally, the first connecting portion 171 and the second connecting portion 172 are both arranged along the first direction x, and the first conductor portion 121 and the second conductor portion 123 are both arranged along the second direction y, and the first direction x is perpendicular to the second direction y, which can reduce the layout space.

[0091] Optionally, the semiconductor device 100 further comprises a third connecting part 173, which is arranged in the same layer as the gate electrode 14. The third connecting part 173 is connected to one side of the gate electrode 14 of at least two thin film transistors TFT.

[0092] In the projection direction z of the semiconductor device 100, the second insulating layer 18 is arranged between the first connecting part 171 and the third connecting part 173. The second insulating layer 18 covers the first connecting part 171 and exposes the first conductor part 121, and the third connecting part 173 is arranged on the side of the second insulating layer 18 away from the substrate 11.

[0093] Optionally, the third connecting part 173 is made of the same material as the gate electrode 14 and is integrated with the gate electrode 14. In some embodiments, the third connecting part 173 and the gate electrode 14 can also be arranged in different layers, and the materials of the two can also be different.

[0094] Optionally, the semiconductor device 100 further comprises a fourth connecting part 174 and a fifth connecting part 175. The fourth connecting part 174 is arranged in the same layer as the first conductor part 121. The fourth connecting part 174 is connected to the other side of the first conductor part 121 of at least two thin film transistors TFT.

[0095] That is, the first connecting part 171 and the fourth connecting part 174 are located on opposite sides of the first conductor part 121.

[0096] The fifth connecting part 175 is arranged in the same layer as the channel part 122. The fifth connecting part 175 is connected to one side of the channel part 122 of at least two thin film transistors TFT.

[0097] The second connecting part 172, the fourth connecting part 174, and the fifth connecting part 175 all extend along the first direction x. In the projection direction z of the semiconductor device 100, the second connecting part 172, the fourth connecting part 174, and the fifth connecting part 175 are arranged in an overlapping manner.

[0098] The overlapping arrangement of the second connecting part 172, the fourth connecting part 174, and the fifth connecting part 175 can improve the flatness and stability of the second connecting part 172, and avoid the risk of the second connecting part 172 being disconnected due to the step difference.

[0099] The fifth connecting part 175 is made of the same material as the channel part 122 and is integrated with the channel part 122. The first connecting part 171 and the fourth connecting part 174 are made of the same material as the first conductor part 121 and are integrated with the first conductor part 121.

[0100] Optionally, the channel part 122 and the second conductor part 123 extend along the long axis direction y of the channel part 122 and cover part of the second insulating layer 18.

[0101] It needs to be understood that the channel portion 122 and the second conductor portion 123 are patterned by a photolithography process. Due to the error of mask alignment and the error of exposure machine, the pattern of the channel portion 122 and the second conductor portion 123 will be offset. If the design pattern is located at the boundary of the second insulating layer 18, due to the error, the actual pattern of the channel portion 122 and the second conductor portion 123 will be moved downward to the boundary of the second insulating layer 18, and when the pattern is etched, the etching liquid will continue to etch the first conductor portion after etching the channel portion and the second conductor layer, resulting in the disconnection of the first conductor portion 121 and the first connecting portion 171.

[0102] The channel portion 122 and the second conductor portion 123 overlap the second insulating layer 18, which is to overcome the error and ensure the effective connection of the first conductor portion 121 and the first connecting portion 171.

[0103] The preparation method of the semiconductor device 100 of the embodiment is as follows:

[0104] Please refer to Figure 4 , step B1, a buffer layer 16 and a patterned first conductor layer NP1 are sequentially formed on the substrate 11. The first conductor layer NP1 includes the first conductor portion 121, the first connecting portion 171, and the fourth connecting portion 174. The first connecting portion 171 and the fourth connecting portion 174 are connected to the first conductor portion 121 arranged oppositely in the second direction y.

[0105] Please refer to Figure 5 , step B2, a patterned second insulating layer 18 is formed on the first conductor layer NP1. The second insulating layer 18 covers the first connecting portion 171 and exposes the first conductor portion 121 and the fourth connecting portion 174.

[0106] Please refer to Figure 6 , step B3, a channel layer Pl and a second conductor layer NP2 are sequentially formed on the buffer layer 16, and then the channel layer Pl and the second conductor layer NP2 are patterned by using the same mask. The channel layer Pl includes the channel portion 122 and the fifth connecting portion 175. The second conductor layer NP2 includes the second conductor portion 123 and the second connecting portion 172. The first conductor portion 121, the channel portion 122, and the second conductor portion 123 are stacked to form an active structure layer 12.

[0107] Please refer to Figure 7 , step B4, a first insulating layer 13 is formed on the second conductor layer NP2. The first insulating layer 13 covers the active structure layer 12, the buffer layer 16, and the second insulating layer 18.

[0108] Please refer to Figure 8, step B5, forming a patterned gate layer Ga on the second insulating layer 18. The gate layer Ga includes the gate 14 and a third connecting part 173. The third connecting part 173 is arranged in overlapping with the first connecting part 171.

[0109] Optionally, a full-area gate layer Ga can be formed on the second insulating layer 18 first, and then the gate layer Ga on the side away from the substrate 11 of the active structure layer 12 is removed by using a chemical mechanical polishing (CMP) technique, and then a photolithography process is performed on the gate layer Ga to form the gate 14 and the third connecting part 173.

[0110] Please refer to Figure 9 , step B6, sequentially forming a third insulating layer 19 and a source-drain metal layer SD on the gate layer Ga, and the third insulating layer 19 covers the gate layer Ga and the first insulating layer 13. The third insulating layer 19 is provided with a first via hole k1 and a second via hole k2, the first via hole k1 penetrates through the third insulating layer 19, the first insulating layer 13 and the second insulating layer 18, and the second via hole k2 penetrates through the third insulating layer 19 and the first insulating layer 13.

[0111] The source-drain metal layer SD includes a first electrode 151 and a second electrode 152, the first electrode 151 is connected to the first connecting part 171 through the first via hole k1, and the second electrode 152 is connected to the second connecting part 172 through the second via hole k2.

[0112] The above is the step process of the preparation method of the semiconductor device 100 of the embodiment of the application. Optionally, in some embodiments, the first conductor layer NP1, the channel layer Pl and the second conductor layer NP2 can be sequentially formed and then a photomask process is performed once.

[0113] Correspondingly, the embodiment of the application also provides a display panel including the semiconductor device 100 of any one of the above embodiments. That is, the structure of the semiconductor device of the display panel of the embodiment is similar or identical to the structure of the semiconductor device 100 of the above embodiment.

[0114] The display panel of the embodiment of the application includes the semiconductor device 100, the semiconductor device 100 stacks the first conductor part, the channel part and the second conductor part to form a vertical active structure layer, realizes a narrow channel, and the growth direction of the crystal grain of the channel part is consistent with the movement of the carrier, so that a structure of a single-crystal channel-like can be realized, thereby improving the mobility of the carrier.

[0115] Correspondingly, the embodiment of the application also provides a chip including the semiconductor device 100 of any one of the above embodiments. That is, the structure of the semiconductor device of the chip of the embodiment is similar or identical to the structure of the semiconductor device 100 of the above embodiment.

[0116] The chip of the embodiment of the present application comprises a semiconductor device 100, the semiconductor device 100 adopts a first conductor part, a channel part and a second conductor part to be stacked to form an active structure layer of a vertical type, narrow channel is realized; and the growth direction of the crystal grain of the channel part is consistent with the movement of the carrier, the structure of a single crystal channel can be realized, thereby the mobility of the carrier is improved.

[0117] The above describes in detail a semiconductor device, a display panel and a chip provided by the embodiment of the present application, specific examples are applied in the text to describe the principle and implementation mode of the present application, the above embodiment is only used to help understand the method and the core idea of the present application; meanwhile, for the person skilled in the art, according to the idea of the present application, the specific implementation mode and the application range will be changed, and the above is described, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate; at least one thin film transistor disposed on the substrate, the thin film transistor comprising: an active structure layer disposed on the substrate, the active structure layer comprising a first conductor portion, a channel portion and a second conductor portion, the first conductor portion being disposed on the substrate, the channel portion being disposed on a side of the first conductor portion away from the substrate, the second conductor portion being disposed on a side of the channel portion away from the substrate; a first insulating layer covering the active structure layer and the substrate; a gate electrode comprising a first gate electrode and a second gate electrode, the first gate electrode being located on one side of the active structure layer, the second gate electrode being located on the other side of the active structure layer, the gate electrode at least overlapping a side surface of the channel portion in a direction parallel to the extension direction of the substrate; and a first electrode connected to the first conductor portion and a second electrode connected to the second conductor portion; wherein the material of the channel portion is polysilicon, the growth direction of the crystal grains of the polysilicon being consistent with the moving direction of the carriers; the active structure layer comprises a first side surface and a second side surface disposed oppositely, the first gate electrode being covered on a side of the first insulating layer facing the first side surface, the second gate electrode being covered on a side of the first insulating layer facing the second side surface, the first insulating layer comprising a top portion, the top portion being covered on a side of the active structure layer away from the substrate; in the semiconductor device in a top view, a hollow region is formed between the first gate electrode and the second gate electrode, the hollow region overlapping the second conductor portion; in the orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with one side of the top portion away from the substrate. The slope angle of the active structure layer is between 80 degrees and 90 degrees.

2. The semiconductor device according to claim 1, wherein The thickness of the channel portion is between 5 nanometers and 1 micrometer.

3. The semiconductor device according to claim 1 or 2, wherein In the direction parallel to the extension direction of the substrate, a side surface of the first conductor portion, a side surface of the channel portion and a side surface of the second conductor portion all overlap the first gate electrode; the other side surface of the first conductor portion, the other side surface of the channel portion and the other side surface of the second conductor portion all overlap the second gate electrode.

4. The semiconductor device of claim 2, wherein The thickness of the first insulating layer is less than the thickness of the first conductor portion.

5. The semiconductor device of claim 4, wherein, The number of the thin film transistors is at least two, in the orthographic projection pattern of the semiconductor device, the gate electrodes and the active structure layers are alternately and spacedly arranged along a first direction, the first direction being perpendicular to the long axis direction of the channel portion; 6. The semiconductor device according to any one of Claims 1-2, 4-5, wherein each of the thin film transistors comprises two gate electrodes, in the same thin film transistor, one gate electrode is disposed on one side of the active structure layer, and the other gate electrode is disposed on the other side of the active structure layer; the first electrode, the second electrode and one gate electrode are shared between two adjacent thin film transistors. ​ 7. The semiconductor device of claim 6, wherein, The semiconductor device further comprises a first connecting portion disposed in the same layer as the first conductor portion, the first connecting portion being connected to one side of the first conductor portion of at least two of the thin film transistors, the first electrode being connected to the first connecting portion through a first via hole; The semiconductor device further comprises a second connecting portion disposed in the same layer as the second conductor portion, the second connecting portion being connected to one side of the second conductor portion of at least two of the thin film transistors, the second electrode being connected to the second connecting portion through a second via hole.

8. The semiconductor device of claim 7, wherein, The semiconductor device further comprises a third connecting portion disposed in the same layer as the gate electrode, the third connecting portion being connected to one side of the gate electrode of at least two of the thin film transistors; In the direction of the orthographic projection of the semiconductor device, a second insulating layer is disposed between the first connecting portion and the third connecting portion, the second insulating layer covering the first connecting portion and exposing the first conductor portion, the third connecting portion being disposed on the side of the second insulating layer away from the substrate.

9. The semiconductor device of claim 8, wherein, The semiconductor device further comprises a fourth connecting portion and a fifth connecting portion, the fourth connecting portion being disposed in the same layer as the first conductor portion, the fourth connecting portion being connected to the other side of the first conductor portion of at least two of the thin film transistors; The fifth connecting portion is disposed in the same layer as the channel portion, the fifth connecting portion being connected to one side of the channel portion of at least two of the thin film transistors; The second connecting portion, the fourth connecting portion and the fifth connecting portion all extend along the first direction, in the direction of the orthographic projection of the semiconductor device, the second connecting portion, the fourth connecting portion and the fifth connecting portion being disposed in overlap.

10. The semiconductor device of claim 8, wherein, The channel portion and the second conductor portion extend along the long axis direction of the channel portion and cover the part of the second insulating layer.

11. The semiconductor device of claim 9, wherein, The first connecting portion, the fourth connecting portion and the first conductor portion are made of the same material and are integrally formed, the second connecting portion and the second conductor portion are made of the same material and are integrally formed, the third connecting portion and the gate electrode are made of the same material and are integrally formed, and the fifth connecting portion and the channel portion are made of the same material and are integrally formed.

12. A display panel, characterized by The semiconductor device comprises the semiconductor device according to any one of claims 1-11.

13. A chip, characterized by The semiconductor device comprises the semiconductor device according to any one of claims 1-11.

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