High sustaining voltage unidirectional thyristor electrostatic discharge protection device and its fabrication method

Abstract

This invention discloses a high sustaining voltage unidirectional thyristor electrostatic discharge (ESD) device and its fabrication method. A forward-biased diode, a gate-grounded NMOS transistor, and a reverse-biased diode are embedded in the transistor (PW). The N+ region of the forward-biased diode D1 is the drain N+ region of the gate-grounded NMOS transistor, and the N+ region of the reverse-biased diode D2 is the source N+ region of the gate-grounded NMOS transistor. This device adds a surface ESD current discharge path to the traditional unidirectional thyristor ESD device, shunting the SCR path and effectively suppressing the positive feedback effect of the SCR discharge path. The ESD device of this invention features high sustaining voltage and high failure current, achieving a high protection level while effectively avoiding latch-up effects.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and in particular to a unidirectional thyristor ESD protection device with high sustaining voltage and its manufacturing method. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, the failure of integrated circuit chips and electronic products due to ESD (electrostatic discharge) has become increasingly severe. Providing ESD protection for electronic products and integrated circuit chips has become one of the major challenges faced by ESD engineers.

[0003] A cross-sectional view of a traditional unidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is shown below. Figure 1 Its equivalent circuit diagram is shown in Figure 2 When an ESD pulse is applied to the anode of a unidirectional SCR, the first N-well and the first P-well form a reverse-biased PN junction. When the ESD pulse voltage exceeds the avalanche breakdown voltage of this PN junction, a large avalanche current is generated inside the device. This current flows through the first P-well and through the parasitic resistance to the cathode. The voltage drop across the parasitic resistance of the first P-well is equivalent to the base voltage drop of an NPN transistor. When this voltage exceeds the forward turn-on voltage of the vertical NPN transistor, the transistor turns on. After this transistor turns on, it provides base current to the horizontal PNP transistor. The horizontal PNP transistor, in turn, further provides base current to the vertical NPN transistor, forming a positive feedback mechanism that fully turns on the SCR path. However, due to its PNPN structure, positive feedback mechanism, high current gain, and low parasitic resistance, its sustaining voltage is too low, resulting in a high latch-up risk when applied to ESD protection in I / O circuits. Therefore, it is necessary to increase its sustaining voltage. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a unidirectional thyristor electrostatic discharge (ESD) protection device with high sustaining voltage and its fabrication method, which is applied to the design of an ESD protection network with a 12V operating voltage.

[0005] The technical solution of the present invention to solve the above problems is:

[0006] In a first aspect, embodiments of the present invention provide a unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage, comprising a P-type substrate; an N-type buried layer and a P-type epitaxial layer are disposed in the P-type substrate; a first high-voltage N-type well and a second high-voltage N-type well are disposed above the N-type buried layer; a first N-type deep well is disposed above the first high-voltage N-type well; a second N-type deep well is disposed above the second high-voltage N-type well; a first N-well is disposed on the first N-type deep well; a first P-well is disposed on the P-type epitaxial layer; a second N-well is disposed on the second N-type deep well; a first N+ implant and a first P+ implant are disposed sequentially from left to right on the first N-well; a second P+ implant, a second N+ implant, a first gate, a third N+ implant, a third P+ implant, a fourth N+ implant, and a fourth P+ implant are disposed sequentially from left to right on the first P-well; the first gate is located between the second N+ implant and the third N+ implant.

[0007] The first N+ injection and the first P+ injection electrodes in the first N-well are connected together and serve as the anode of the device; the fourth N+ injection and the fourth P+ injection electrodes in the first P-well are connected together and serve as the cathode of the device; the second P+ and the second N+ injection in the first P-well are connected together by a metal wire and are not connected to any potential; the first gate in the first P-well is connected to ground by a metal wire; the third N+ and the third P+ injection in the first P-well are connected together by a metal wire and are not connected to any potential.

[0008] Preferably, there are eight field oxygen isolation regions; the first field oxygen isolation region is between the left side of the first N+ injection and the first N-type well; the second field oxygen isolation region is between the first N+ injection and the first P+ injection; the third field oxygen isolation region is between the first P+ injection and the second P+ injection; the fourth field oxygen isolation region is between the second P+ injection and the second N+ injection; the fifth field oxygen isolation region is between the third N+ injection and the third P+ injection; the sixth field oxygen isolation region is between the third P+ injection and the fourth N+ injection; the seventh field oxygen isolation region is between the fourth N+ injection and the fourth P+ injection; and the eighth field oxygen isolation region is between the right side of the fourth P+ injection and the second N-type well.

[0009] Preferably, the first and second field oxygen isolation regions are located on the surface of the first N-well; the third field oxygen isolation region is located on the surface of the first N-well, the surface of the P-type epitaxial layer, and the surface of the first P-well; the fourth, fifth, sixth, and seventh field oxygen isolation regions are located on the surface of the first P-well; and the eighth field oxygen isolation region is located on the surface of the first P-well, the surface of the P-type epitaxial layer, and the surface of the second N-well.

[0010] Preferably, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well; at this time, the second P+ injection and the second N+ injection form a forward-biased diode D1, and the third N+ injection and the third P+ injection form a reverse-biased diode D2. The second N+ injection, the first gate, and the third N+ injection form an NMOS. When D1 is turned on, it will form an additional shunt path with the NMOS and D2.

[0011] Preferably, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first P+ injection, the first N-well / first deep N-well / first high-voltage N-well / N-type buried layer and the first P-well constitute a parasitic transistor PNP. The first N-well / first deep N-well / first high-voltage N-well / N-type buried layer, the first P-well and the fourth N+ injection constitute a parasitic transistor NPN. When its voltage drop reaches 0.7V, the parasitic transistor NPN on the right side conducts and provides base current to the parasitic transistor PNP on the left side, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a positive SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well.

[0012] Preferably, when the high-voltage ESD pulse reaches the anode of the device and the cathode is grounded, after the first N-well / P-type epitaxial layer and the first P-well junction are broken down, the ESD current in the first N-well will converge to the second P+ injection region, flow into the drain N+ region of the NMOS through the forward-biased diode D1, flow out from the source N+ region of the NMOS, and finally flow back into the SCR path through the reverse-biased diode D2. By introducing an additional shunt path, the positive feedback of the SCR can be suppressed on the one hand, and after D1, NMOS and D2 form a new shunt path, the hot spots inside the device are dispersed, which can improve the failure current of the device to a certain extent.

[0013] Preferably, the widths S1, S2, and S3 of the second P+ injection are adjustable. When S1 and S2 increase, the sustaining voltage increases. When S3 increases, the triggering voltage increases, and the sustaining voltage also increases.

[0014] Secondly, embodiments of the present invention provide a method for fabricating a unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage, comprising the following steps:

[0015] Step 1: Form an N-type buried layer and a P-type epitaxial layer on a P-type substrate;

[0016] Step 2: Generate a first high-pressure N-type well and a second high-pressure N-type well above the N-type buried layer;

[0017] Step 3: Generate a first N-type deep well in the first high-pressure N-type well, and generate a second N-type deep well in the second high-pressure N-type well;

[0018] Step 4: Generate the first N-well in the first N-type deep well, generate the second N-well in the second N-type deep well, and generate the first P-well in the P-type epitaxial layer;

[0019] Step 5: Generate the first N+ implant and the first P+ implant in the first N-well from left to right; generate the second P+ implant, the second N+ implant, the first gate, the third N+ implant, the third P+ implant, the fourth N+ implant, and the fourth P+ implant in the first P-well from left to right.

[0020] Step 6: A first field oxygen isolation region is formed to the left of the first N+ injection on the first N-well; a second field oxygen is generated between the first N+ injection and the first P+ injection on the first N-well; a third field oxygen is generated between the first P+ injection on the first N-well and the second P+ injection on the first P-well; a fourth field oxygen is generated between the second P+ injection and the second N+ injection on the first P-well; a fifth field oxygen is generated between the third N+ injection and the third P+ injection on the first P-well; a sixth field oxygen is generated between the third P+ injection and the fourth N+ injection on the first P-well; a seventh field oxygen is generated between the fourth N+ injection and the fourth P+ injection on the first P-well; and an eighth field oxygen is generated to the right of the fourth P+ injection on the first P-well.

[0021] Step 7: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0022] Step 8: Connect the first N+ implant and the first P+ implant together as the anode of the device; connect the second P+ implant and the second N+ implant together without applying a potential; connect the third P+ implant and the third N+ implant together without applying a potential; connect the first gate and the fourth N+ implant and the fourth P+ implant together as the cathode of the device.

[0023] Preferably, the formation of the N-type buried layer and the P-type epitaxial layer on the P-type substrate further includes:

[0024] A silicon dioxide thin film is grown on a P-type substrate, followed by the deposition of a silicon nitride layer. A photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop the wafer to form a shallow isolation trench. The silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, and a silicon dioxide layer is deposited. Then, chemical mechanical polishing is performed until the silicon nitride layer is removed.

[0025] The beneficial effects of this invention are as follows:

[0026] 1. The present invention can adjust the trigger voltage by adjusting the width of the breakdown surface. Based on the traditional unidirectional thyristor electrostatic discharge protection device, the breakdown surface is changed from well breakdown between the first N-well and the first P-well to well breakdown between the first N-well and the P-type epitaxial layer and the first P-well. The trigger voltage and the sustaining voltage can be adjusted by adjusting the width of the breakdown surface.

[0027] 2. To further improve the performance of the unidirectional thyristor, this invention introduces two diodes and one NMOS structure without increasing the device layout area. The second P+ injection and the second N+ injection in the first P-well together form a forward-biased diode D1, and the third N+ injection and the third P+ injection in the first P-well together form a reverse-biased diode D2. The second N+ injection, the first gate, the third N+ injection, and the fourth P+ injection in the first P-well constitute an NMOS. When the first N-well / P-type epitaxial layer and the first P-well junction are broken down... Afterwards, the ESD current in the first N-well will converge to the second P+ injection region, flow into the drain N+ region of the NMOS through the forward-biased diode D1, flow out from the source N+ region of the NMOS, and finally flow back into the SCR path through the reverse-biased diode D2. By introducing an additional shunt path, on the one hand, the positive feedback of the SCR can be suppressed, thereby suppressing the latch-up effect and thus improving the device's sustaining voltage. On the other hand, after D1, NMOS, and D2 form a new shunt path, the hot spots inside the device are dispersed, which can improve the device's failure current to a certain extent.

[0028] 3. In this invention, the widths S1, S2, and S3 of the second P+ injection are adjustable. When S1 and S2 increase, the diode area increases, and the current transmission capability of the path formed by D1, NMOS, and D2 improves, allowing more current to pass through the path. At the same time, the effective base region widths of the two parasitic transistors increase, suppressing SCR positive feedback and increasing the sustaining voltage. When S3 increases, the trigger voltage increases, and the sustaining voltage also increases. Attached Figure Description

[0029] Figure 1 This is a cross-sectional view of a traditional unidirectional SCR electrostatic discharge protection device.

[0030] Figure 2 This is the equivalent circuit diagram of a traditional unidirectional SCR electrostatic discharge protection device.

[0031] Figure 3 This is a cross-sectional view of an embodiment of the present invention.

[0032] Figure 4 This is an equivalent circuit diagram of an embodiment of the present invention.

[0033] Figure 5The simulation diagram shows the total current density distribution of a unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage, provided as an embodiment of the present invention. Detailed Implementation

[0034] The following description, in conjunction with the accompanying drawings and embodiments, further illustrates the ESD protection design of the I / O port of a 12V DC power interface chip based on the present invention.

[0035] like Figure 3 As shown, a high sustaining voltage unidirectional thyristor electrostatic discharge (ESD) device includes a P-type substrate 101; an N-type buried layer 201 and a P-type epitaxial layer 301 are disposed in the substrate; a first high-voltage N-type well 401 and a second high-voltage N-type well 402 are disposed above the N-type buried layer 201; a first N-type deep well 501 and a second N-type deep well 502 are disposed on the high-voltage N-type wells 401 and 402; a first N-well 601, a first P-well 603, and a second N-well 602 are disposed on the N-type deep wells 501 and 502; the first N-well 601 has a first N+ implantation 801 and a first P+ implantation 802 arranged sequentially from left to right; the first P-well 603 has a second P+ implantation 803, a second N+ implantation 804, a first gate 901, a third N+ implantation 805, a third P+ implantation 806, a fourth N+ implantation 807, and a fourth P+ implantation 808 arranged sequentially from left to right; the first Gate 901 is located between the second N+ injection 804 and the third N+ injection 805; the first N+ injection 801 and the first P+ injection 802 in the first N-well 601 are connected together and serve as the anode of the device; the first gate 901, the fourth N+ injection 807, and the fourth P+ injection 808 in the first P-well 603 are connected together and serve as the cathode of the device; the second P+ injection 803 and the second N+ injection 804 in the first P-well are connected together by a metal wire and are not connected to any potential; the third N+ injection 805 and the third P+ injection 806 in the first P-well are connected together by a metal wire and are not connected to any potential. Thus, when D1 is turned on, it will form an additional shunt path with the NMOS and D2, which will discharge a portion of the current in the SCR path through this path. This will suppress the positive feedback effect in the original SCR path, thereby improving the holding voltage.

[0036] In one embodiment, the high sustaining voltage unidirectional thyristor electrostatic discharge (ESD) device has eight field oxygen isolation regions: a first field oxygen isolation region 701 is located between the left side of the first N+ injection 801 and the first N-well 601; a second field oxygen isolation region 702 is located between the first N+ injection 801 and the first P+ injection 802; a third field oxygen isolation region 703 is located between the first P+ injection 802 and the second P+ injection 803; a fourth field oxygen isolation region 704 is located between the second P+ injection 803 and the second N+ injection 804; a fifth field oxygen isolation region 705 is located between the third N+ injection 805 and the third P+ injection 806; a sixth field oxygen isolation region 706 is located between the third P+ injection 806 and the fourth N+ injection 807; a seventh field oxygen isolation region 707 is located between the fourth N+ injection 807 and the fourth P+ injection 808; and an eighth field oxygen isolation region 708 is located to the right of the fourth P+ injection 808 and between the second N-well 602.

[0037] In one embodiment, the first field oxygen isolation region 701 and the second field oxygen isolation region 702 are located on the surface of the first N-well 601; the third field oxygen isolation region 703 is located on the surface of the first N-well 601, the surface of the P-type epitaxial layer 301, and the surface of the first P-well 603; the fourth field oxygen isolation region 704, the fifth field oxygen isolation region 705, the sixth field oxygen isolation region 706, and the seventh field oxygen isolation region 707 are located on the surface of the first P-well 603; and the eighth field oxygen isolation region 708 is located on the surface of the first P-well 603, the surface of the P-type epitaxial layer 301, and the surface of the second N-well 602.

[0038] In one implementation, such as Figure 5 As shown, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, its breakdown surface is between the first N-well 601 and the P-type epitaxial layer 301 and the first P-well 303; at this time, the second P+ injection 803 and the second N+ injection 804 form a forward-biased diode D1, and the third N+ injection 805 and the third P+ injection 806 form a reverse-biased diode D2. The second N+ injection 804, the first gate 901, and the third N+ injection 805 form an NMOS. When D1 is turned on, it will form an additional shunt path with the NMOS and D2.

[0039] When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the first P+ injection 802, the first N-well 601 / first deep N-well 501 / first high-voltage N-well 401 / N-type buried layer 201 and the first P-well 603 form a parasitic transistor PNP. The first N-well 601 / first deep N-well 501 / first high-voltage N-well 401 / N-type buried layer 201, the first P-well 603 and the fourth N+ injection 807 form a parasitic transistor NPN. When its voltage drop reaches 0.7V, the parasitic transistor NPN on the right side conducts and provides base current to the parasitic transistor PNP on the left side, thereby promoting its conduction. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a positive SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and its breakdown surface is between the first N-well 601 and the P-type epitaxial layer 301 and the first P-well 603.

[0040] When a high-voltage ESD pulse reaches the anode of the device and the cathode is grounded, after the junction of the first N-well 601 / P-type epitaxial layer 301 and the first P-well 603 is broken down, the ESD current in the first N-well 601 will converge to the second P+ injection region 803, flow into the drain N+ region 804 of the NMOS through the forward-biased diode D1, flow out from the source N+ region 805 of the NMOS, and finally flow back into the SCR path through the reverse-biased diode D2. By introducing an additional shunt path, the positive feedback of the SCR can be suppressed on the one hand, and after D1, NMOS and D2 form a new shunt path, the hot spots inside the device are dispersed, which can improve the failure current of the device to a certain extent.

[0041] This device can be customized according to the ESD design window requirements of different application scenarios by controlling the width S1 of the second P+ injection 803 and the third P+ injection 806. When S1 increases, the holding voltage increases. The width S2 of the second N+ injection 804 and the third N+ injection 805 is also adjustable. Increasing their width can effectively suppress the current saturation effect and improve the current conduction capability of the NMOS, thereby further improving the holding voltage and failure current, and reducing the on-resistance. As S1 and S2 increase, the base region width of the parasitic transistor also increases, thereby reducing the current gain coefficient β and thus improving the holding voltage. The width S3 is also adjustable. By adjusting the distance between the first N-well 601 and the first P-well 603, the trigger voltage can be adjusted. Increasing the width of S3 increases both the trigger voltage and the holding voltage.

[0042] This invention also provides a method for fabricating a unidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device with high sustaining voltage, comprising the following steps:

[0043] Step 1: Form an N-type buried layer 201 in a P-type substrate 101;

[0044] Step 2: Generate a first high-pressure N-type trap 401 and a second high-pressure N-type trap 402 above the N-type buried layer 201;

[0045] Step 3: Generate a first N-type deep well 501 in the first high-pressure N-type well 401, and generate a second N-type deep well 502 in the second high-pressure N-type well 402;

[0046] Step 4: Generate a first N-well 601 in the first N-type deep well 501, generate a second N-well 602 in the second N-type deep well 502, and generate a first P-well 603 in the P-type epitaxial layer 301.

[0047] Step 5: Generate the first N+ implant 801 and the first P+ implant 802 sequentially from left to right on the first N-well 601; generate the second P+ implant 803, the second N+ implant 804, the first gate 901, the third N+ implant 805, the third P+ implant 806, the fourth N+ implant 807, and the fourth P+ implant 808 sequentially from left to right on the first P-well 603.

[0048] Step Six: A first field oxygen isolation region 701 is formed to the left of the first N+ injection 801 on the first N-well 601. A second field oxygen isolation region 702 is generated between the first N+ injection 801 and the first P+ injection 802 on the first N-well 601. A third field oxygen isolation region 703 is generated between the first P+ injection 802 on the first N-well 601 and the second P+ injection 803 on the first P-well 603. A fourth field oxygen isolation region 703 is generated between the second P+ injection 803 and the second N+ injection 804 on the first P-well 603. In region 704, a fifth field oxygen isolation region 705 is generated between the third N+ injection 805 and the third P+ injection 806 on the first P-well 603; a sixth field oxygen isolation region 706 is generated between the third P+ injection 805 and the fourth N+ injection 807 on the first P-well 603; a seventh field oxygen isolation region 707 is generated between the fourth N+ injection 807 and the fourth P+ injection 808 on the first P-well 603; and an eighth field oxygen isolation region 708 is generated to the right of the fourth P+ injection 808 on the first P-well 603.

[0049] Step 7: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0050] Step 8: Connect the first N+ injection 801 and the first P+ injection 802 together as the anode of the device; connect the second P+ injection 803 and the second N+ injection 804 together without applying a potential; connect the third N+ injection 805 and the third P+ injection 806 together without applying a potential; and connect the first gate 901 and the fourth N+ injection 807 and the fourth P+ injection 808 together as the cathode of the device.

[0051] The fabrication method of the high-holding-voltage unidirectional thyristor electrostatic discharge (ESD) protection device of this invention is simple and easy to operate. To further improve the performance of the unidirectional thyristor, this invention introduces two diodes and an NMOS structure without increasing the device layout area. This generates a completely new shunt path, which weakens the positive feedback effect of the SCR path, thereby suppressing latch-up and effectively improving the device's protection performance and failure level. This device can be used in the ESD protection design of the I / O ports of 12V DC power interface chips. The device in this example uses a 0.18μm BCDMOS process.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage, characterized in that, include: A P-type substrate; the P-type substrate has an N-type buried layer and a P-type epitaxial layer; a first P-well is provided on the P-type epitaxial layer; Above the N-type buried layer are a first high-pressure N-type trap and a second high-pressure N-type trap; above the first high-pressure N-type trap is a first N-type deep trap; above the second high-pressure N-type trap is a second N-type deep trap. The first N-type deep well is provided with a first N-well; the second N-type deep well is provided with a second N-well; the N-type deep well is provided with a first N-well, a first P-well, and a second N-well from left to right; the first N-well is provided with a first N+ injection and a first P+ injection from left to right; The first P-well is provided with a second P+ implant, a second N+ implant, a first gate, a third N+ implant, a third P+ implant, a fourth N+ implant, and a fourth P+ implant from left to right; The first gate is located between the second N+ injection and the third N+ injection; The first N+ injection and the first P+ injection electrodes in the first N-well are connected together and serve as the anode of the device; The fourth N+ injection electrode in the first P-well is connected to the fourth P+ injection electrode and serves as the cathode of the device. The second P+ injection and the second N+ injection in the first P-well are connected together by a metal wire, but are not connected to a potential. The first gate in the first P-well is connected to ground via a metal wire; The third N+ injection in the first P-well is connected to the third P+ injection via a metal wire, but is not connected to a potential.

2. The unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 1, characterized in that, Also includes: Eight oxygen isolation zones; The first oxygen isolation region is between the left side of the first N+ injection and the first N-well; the second oxygen isolation region is between the first N+ injection and the first P+ injection; the third oxygen isolation region is between the first P+ injection and the second P+ injection; the fourth oxygen isolation region is between the second P+ injection and the second N+ injection; the fifth oxygen isolation region is between the third N+ injection and the third P+ injection; the sixth oxygen isolation region is between the third P+ injection and the fourth N+ injection; the seventh oxygen isolation region is between the fourth N+ injection and the fourth P+ injection; and the eighth oxygen isolation region is between the right side of the fourth P+ injection and the second N-well.

3. The unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 2, characterized in that, The first and second field oxygen isolation regions are located on the surface of the first N-well; the third field oxygen isolation region is located on the surface of the first N-well, the surface of the P-type epitaxial layer, and the surface of the first P-well; the fourth, fifth, sixth, and seventh field oxygen isolation regions are located on the surface of the first P-well; and the eighth field oxygen isolation region is located on the surface of the first P-well, the surface of the P-type epitaxial layer, and the surface of the second N-well.

4. The unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 1, characterized in that, When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well. At this time, the second P+ injection and the second N+ injection form a forward-biased diode D1, and the third N+ injection and the third P+ injection form a reverse-biased diode D2. The second N+ injection, the first gate, and the third N+ injection form an NMOS. When D1 is turned on, it will form an additional shunt path with the NMOS and D2.

5. The unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 1, characterized in that, When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the first P+ injection, the first N-well / first deep N-well / first high-voltage N-well / N-type buried layer and the first P-well constitute a parasitic transistor PNP. The first N-well / first deep N-well / first high-voltage N-well / N-type buried layer, the first P-well and the fourth N+ injection constitute a parasitic transistor NPN. When the voltage drop between the first P-well and the fourth N+ injection reaches 0.7V, the parasitic transistor NPN on the right turns on and provides base current to the parasitic transistor PNP on the left, thereby causing the parasitic transistor PNP to turn on. When the parasitic transistor PNP and the parasitic transistor NPN are turned on, a positive SCR path is formed, forming a positive feedback effect. At this time, the device is successfully triggered, and the breakdown surface is between the first N-well and the P-type epitaxial layer and the first P-well.

6. The unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 1, characterized in that, When a high-voltage ESD pulse reaches the anode of the device and the cathode is grounded, after the first N-well / P-type epitaxial layer and the first P-well junction are broken down, the ESD current in the first N-well will converge to the second P+ injection region, flow into the drain N+ region of the NMOS through the forward-biased diode D1, flow out from the source N+ region of the NMOS, and finally flow back into the SCR path through the reverse-biased diode D2.

7. The unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 1, characterized in that, The widths S1, S2, and S3 of the second P+ injection are adjustable. When S1 and S2 increase, the sustaining voltage increases. When S3 increases, the triggering voltage increases, and the sustaining voltage increases.

8. A method for manufacturing a unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to any one of claims 1-7, comprising the following steps: Step 1: Form an N-type buried layer and a P-type epitaxial layer on a P-type substrate; Step 2: Generate a first high-pressure N-type well and a second high-pressure N-type well above the N-type buried layer; Step 3: Generate a first N-type deep well in the first high-pressure N-type well, and generate a second N-type deep well in the second high-pressure N-type well; Step 4: Generate the first N-well in the first N-type deep well, generate the second N-well in the second N-type deep well, and generate the first P-well in the P-type epitaxial layer; Step 5: Generate the first N+ injection and the first P+ injection sequentially from left to right on the first N-well; A second P+ implant, a second N+ implant, a first gate, a third N+ implant, a third P+ implant, a fourth N+ implant, and a fourth P+ implant are sequentially generated on the first P-well from left to right. Step 6: A first field oxygen isolation region is formed to the left of the first N+ injection on the first N-well; a second field oxygen is generated between the first N+ injection and the first P+ injection on the first N-well; a third field oxygen is generated between the first P+ injection on the first N-well and the second P+ injection on the first P-well; a fourth field oxygen is generated between the second P+ injection and the second N+ injection on the first P-well; a fifth field oxygen is generated between the third N+ injection and the third P+ injection on the first P-well; a sixth field oxygen is generated between the third P+ injection and the fourth N+ injection on the first P-well; a seventh field oxygen is generated between the fourth N+ injection and the fourth P+ injection on the first P-well; and an eighth field oxygen is generated to the right of the fourth P+ injection on the first P-well. Step 7: Anneal all injection zones to eliminate the migration of impurities within the injection zones; Step 8: Connect the first N+ implant and the first P+ implant together as the anode of the device; connect the second P+ implant and the second N+ implant together without applying a potential; connect the third P+ implant and the third N+ implant together without applying a potential; connect the first gate and the fourth N+ implant and the fourth P+ implant together as the cathode of the device.

9. The method for manufacturing a unidirectional thyristor electrostatic discharge (ESD) device with high sustaining voltage according to claim 8, characterized in that, Before step one, the following steps are also included: growing a silicon dioxide thin film on a P-type substrate, followed by depositing a silicon nitride layer; spin-coating a photoresist layer onto a wafer, exposing and developing the photoresist with a mask to form a shallow isolation trench; etching the silicon dioxide, silicon nitride, and shallow isolation trench to remove the photoresist layer, depositing a silicon dioxide layer, and then performing chemical polishing until the silicon nitride layer is removed.

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