A method for fabricating a selective electrode contact heterojunction cell and a heterojunction cell

Abstract

The application relates to the technical field of heterojunction solar cells, and particularly discloses a preparation method of a selective electrode contact heterojunction cell and the heterojunction cell. The method comprises the following steps: first texturing a silicon wafer substrate, preparing a mask layer after the texturing, first patterning the silicon wafer, slotting the two surfaces of the silicon wafer based on picosecond laser, second texturing the silicon wafer, placing the cleaned silicon wafer in a second texturing mixed solution, so that a large-textured pyramid structure is generated on the bottom surface of the groove on the two surfaces of the silicon wafer, removing the first mask layer from the silicon wafer after the second texturing, and sequentially depositing a plurality of layers including an intrinsic amorphous silicon layer on the two surfaces of the silicon wafer, aligning and printing a second mask layer on other regions of the silicon wafer which are not provided with the groove in the first patterning based on exposure and development, electroplating copper grid lines on the silicon wafer, and sequentially removing the second mask layer and a copper seed layer from the silicon wafer after the electroplating of the grid lines, so as to obtain a selective electrode contact copper grid line heterojunction solar cell, thereby improving the copper grid line stripping problem and improving the cell efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of heterojunction solar cells, and in particular to a method for preparing a selective electrode contact heterojunction cell and a heterojunction cell. Background Art

[0002] In recent years, heterojunction solar cells have attracted widespread attention in the industry due to their excellent performance such as high efficiency and low attenuation.

[0003] In the related technologies, for the grid lines of heterojunction solar cells, the most cutting-edge technology is to use copper electroplating technology instead of screen printing, and to completely replace silver paste with metallic copper as the grid line electrode. This method fundamentally solves the problem of high silver paste cost. At the same time, the copper and the transparent conductive film TCO are tightly adhered, the contact resistance is smaller, the power loss is also smaller, and the conversion efficiency of the battery cell is higher. In addition, the copper grid lines made by copper electroplating are thinner and have better morphology than the silver grid lines made by screen printing, further improving the photoelectric conversion efficiency.

[0004] However, in actual applications, it has been found that both copper and silver grid lines have the problem of grid detachment. Moreover, in the existing copper electroplating process technology, the copper grid lines formed by electroplating are more prone to grid detachment than the silver grid lines, which affects the production yield of the battery cells and directly increases the difficulty of mass production. At the same time, the high string resistance leads to large current loss, thereby reducing the overall photoelectric conversion efficiency of the battery. Summary of the Invention

[0005] The present application aims to at least solve the problem of grid delamination in heterojunction batteries in the prior art, especially the problem that the copper grid lines electroplated in the copper electroplating process are prone to grid delamination and high string resistance, which increases the difficulty of mass production and reduces the overall conversion efficiency of the battery. Therefore, the present application proposes a preparation method for a selective electrode contact heterojunction battery and a heterojunction battery.

[0006] To achieve the above objectives, in a first aspect, the present application provides a method for preparing a selective electrode contact heterojunction battery, comprising:

[0007] Step S10: First texturing of the silicon wafer substrate, placing the silicon wafer substrate in a first texturing mixture to form small textured pyramid structures on both sides of the silicon wafer substrate, wherein the size of the pyramid structures is between 0.5um and 4um;

[0008] Step S20: preparing a mask layer for the silicon wafer, depositing a first mask layer for the second texturing on both sides of the silicon wafer after the first texturing, wherein the thickness of the first mask layer is 50nm-250nm, and the refractive index is between 1.5-2.6;

[0009] Step S30: first patterning of the silicon wafer, based on picosecond laser, groove processing is performed on both sides of the silicon wafer according to the position of the electrode grid line, wherein the depth of the groove is completely ablated to expose the surface of the silicon wafer substrate;

[0010] Step S40: second texturing of the silicon wafer, pre-cleaning is performed on the silicon wafer after grooving, and the cleaned silicon wafer is placed in a second texturing mixed solution to form a large-textured pyramid structure on the inner bottom surface of the groove on both sides of the silicon wafer, wherein the size of the pyramid structure is between 4um and 10um;

[0011] Step S50: removing the first mask layer from the silicon wafer after the second texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, a TCO layer, and a copper plating seed layer on both sides of the silicon wafer;

[0012] Step S60: second patterning of the silicon wafer, based on exposure and development, a second mask layer is printed on the other areas of the silicon wafer after the first patterning groove, wherein the second mask layer is an ink mask layer;

[0013] Step S70: copper grid line plating on the silicon wafer, and sequentially removing the second mask layer and the copper seed layer from the silicon wafer after the copper grid line plating to obtain a selective electrode contact copper grid line heterojunction solar cell.

[0014] According to some embodiments of the present application, in the step S10, the first texturing mixed solution is composed of at least an alkaline solution, a small-textured special additive, and ultrapure water, and the alkaline solution includes one or more combinations of potassium hydroxide or sodium hydroxide solution.

[0015] According to some embodiments of the present application, in the step S20, the first mask layer includes one or more combinations of silicon nitride film, silicon oxide film, and silicon oxynitride film.

[0016] According to some embodiments of the present application, in the step S30, based on a picosecond laser, the mask layer on the front and back surfaces of the silicon wafer is grooved according to the position of the preset electrode grid line, wherein the wavelength range of the picosecond laser is 325nm-532nm, the width range of the front main grid groove is 50um-80um, the width range of the front auxiliary grid groove is 10um-40um, the width range of the back main grid groove is 50um-250um, and the width range of the back auxiliary grid groove is 20-80um.

[0017] According to some embodiments of the present application, in the step S40, a potassium hydroxide solution is used to clean the laser damage layer at the grooved position on the front and back surfaces of the silicon wafer, and the cleaned silicon wafer is placed in a second texturing mixed solution for texturing, wherein the second texturing mixed solution is composed of at least an alkaline solution, a large-textured special additive, and ultrapure water, and the alkaline solution includes one or more combinations of potassium hydroxide or sodium hydroxide solution.

[0018] According to some embodiments of the present application, in the step S50, comprising:

[0019] Step S51: depositing an intrinsic amorphous silicon layer on the double sides of the silicon wafer after the secondary texturing, and the thickness of the intrinsic amorphous silicon layer ranges from 4nm to 10nm;

[0020] Step S52: depositing an emitter layer on the surface of the intrinsic amorphous silicon layer on the double sides of the silicon wafer, wherein the emitter layer is one of a doped amorphous silicon layer or a nanocrystalline silicon layer;

[0021] Step S53: sputtering a high-transmittance TCO layer on the surface of the emitter layer on the double sides of the silicon wafer;

[0022] Step S54: depositing a seed layer on the surface of the TCO layer on the double sides of the silicon wafer, wherein the thickness of the seed layer ranges from 10nm to 150nm.

[0023] According to some embodiments of the present application, in the step S52, comprising:

[0024] depositing a phosphorus-doped amorphous silicon layer or a phosphorus-doped nanocrystalline silicon layer on the surface of the intrinsic amorphous silicon layer on the light-receiving side of the silicon wafer to form a front-side emitter, and the thickness of the phosphorus-doped amorphous silicon layer or the phosphorus-doped nanocrystalline silicon layer ranges from 5nm to 40nm;

[0025] depositing a boron-doped amorphous silicon layer or a boron-doped nanocrystalline silicon layer on the surface of the intrinsic amorphous silicon layer on the back side of the silicon wafer to form a back-side emitter, and the thickness of the boron-doped amorphous silicon layer or the boron-doped nanocrystalline silicon layer ranges from 5nm to 60nm.

[0026] According to some embodiments of the present application, in the step S70, further comprising:

[0027] immersing the electroplated silicon wafer in an alkaline mixed solution to remove the second mask layer, wherein the alkaline mixed solution comprises a combination of one or more of a potassium hydroxide solution or a sodium hydroxide solution, and the immersion time ranges from 30s to 200s;

[0028] immersing the silicon wafer with the removed mask in an acid mixed solution to remove the copper seed layer except for the copper grid lines, wherein the acid mixed solution comprises a combination of one or more of a dilute sulfuric acid solution or a dilute nitric acid solution.

[0029] According to some embodiments of the present application, when the battery electrode is a silver grid line, the step S40 further comprises:

[0030] Step S51: removing the first mask layer from the silicon wafer after the secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, and a TCO layer on the double sides of the silicon wafer;

[0031] Step S61: printing electrodes, according to the position of the first time patterned slot, selecting the corresponding screen printing, using the way of screen printing in the front and back of the silicon wafer printing silver grid line, and then curing to get the selective electrode contact silver grid heterojunction solar cell.

[0032] Compared with the prior art, the above-mentioned first aspect of the present application provides technical solutions which at least include the following beneficial effects:

[0033] 1) By small velvet texturing on the silicon wafer, the silicon wafer is formed with small velvet pyramid structure on both sides, and the size of the pyramid structure is controlled within 0.5um-4um, so that the light absorption of the heterojunction cell is increased and the efficiency of the cell is improved. Different from the existing heterojunction cell production process, after the first texturing, a mask layer is deposited on both sides of the silicon wafer, the mask layer is one of silicon nitride film, silicon oxide film and silicon oxynitride film layer, and then a grid slot is opened based on a 325nm-532nm wavelength picosecond laser to complete the first time patterned processing. Through the laser of a specific wavelength and frequency, the copper grid line width is flexibly adjustable and more fine during the slotting process. After cleaning the laser damage layer at the slotting position, the second texturing is performed. Due to the existence of the mask layer, the second texturing produces large velvet pyramid structure in the slot, and the size of the pyramid is controlled within 4um-10um. After depositing multiple layers and electroplating copper grid lines or printing silver grid lines, the contact specific surface area of the copper electroplating process copper grid line or silver grid line and the transparent conductive oxide TCO layer is increased to reduce the series resistance and increase the pulling force, thereby improving the cell efficiency and improving the grid line off-grid problem.

[0034] 2) The heterojunction solar cell prepared by the method of the present application effectively increases the contact specific surface area of the grid line and the body of the heterojunction solar cell without increasing the width of the grid line, thereby reducing the series resistance, improving the fill factor efficiency gain, in addition, the battery structure can effectively increase the bonding force between the copper grid line or silver grid line and the TCO layer, thereby effectively improving the off-grid problem and improving the yield of the heterojunction solar cell. At the same time, for the copper grid silicon heterojunction solar cell, two different processes are used when preparing the mask layer before and after, which further simplifies the preparation process of the selective electrode contact silicon heterojunction solar cell under the premise of improving the off-grid and improving the yield, and improves the production efficiency of the heterojunction solar cell.

[0035] Secondly, the present application also provides a copper electroplating back contact heterojunction cell prepared by the preparation method of the selective electrode contact heterojunction cell provided in any one of the above-mentioned first aspect.

[0036] It can be understood that the beneficial effects of the above-mentioned second aspect can be referred to the related description in the above-mentioned first aspect, which will not be repeated here.

[0037] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0039] Figure 1 is a flow chart of a preparation method of a selective electrode contact copper grid heterojunction cell according to an embodiment of the present application;

[0040] Figure 2 is a first cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0041] Figure 3 is a second cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0042] Figure 4 is a third cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0043] Figure 5 is a fourth cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0044] Figure 6 is a fifth cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0045] Figure 7 is a sixth cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0046] Figure 8 is a seventh cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0047] Figure 9 is an eighth cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0048] Figure 10 is a ninth cell structure schematic diagram in a preparation flow of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0049] Figure 11is a tenth cell structure schematic diagram in a preparation procedure of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0050] Figure 12 is an eleventh cell structure schematic diagram in a preparation procedure of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0051] Figure 13 is a twelfth cell structure schematic diagram in a preparation procedure of a copper grid line heterojunction solar cell according to an embodiment of the present application;

[0052] Reference signs:

[0053] 100, silicon wafer substrate; 101, first texturing; 102, second texturing; 110, first mask layer; 111, first line groove; 112, second texturing; 120, intrinsic amorphous silicon layer, 130a, phosphorus-doped silicon layer; 130b, boron-doped silicon layer; 140, TCO layer; 150, electroplating seed layer; 160, second mask layer; 161, second line groove; 170, copper grid line electrode. DETAILED DESCRIPTION

[0054] The embodiments of the present application will be described in detail with reference to the drawings, the embodiments described with reference to the drawings are exemplary, and it should be understood that the specific embodiments described herein are only used to explain the present application, and are not intended to limit the present application.

[0055] It should be noted that when an element is referred to as being "fixed" to another element, it can be directly on the other element or there can be an intervening element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or there can be an intervening element.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] Please refer to Figures 1 to 13 The embodiment provides a preparation method of a selective electrode contact heterojunction cell, which comprises the following steps:

[0058] Step S10: first texturing of the silicon wafer substrate, the silicon wafer substrate is placed in a first texturing mixed solution, so that small textured pyramid structures are generated on both sides of the silicon wafer substrate, wherein the size of the pyramid structure is between 0.5um and 4um;

[0059] In this step, the first texturing is performed on the silicon wafer substrate cleaned by pre-cleaning, and the silicon wafer is placed in a specially prepared first texturing mixed solution, wherein the first texturing mixed solution is composed of at least an alkaline solution, a small-textured surface special additive and ultrapure water, the alkaline solution includes one or more combinations of potassium hydroxide or sodium hydroxide solution, the main component of the small-textured surface special additive is potassium sorbate, and the solution is 1%-5%; the first texturing is to form a pyramid light-trapping structure on the surface of the single crystal silicon, increase the light absorption, and the reaction time can be controlled within 200s-1800s, so that the front and back (light receiving and back light) surfaces of the silicon wafer substrate form a pre-set pyramid structure, and the size of the pyramid structure is controlled within 0.5um-4um.

[0060] In some examples, as shown in Figure 2 The double sides of the silicon wafer substrate 100 form the first textured surface 101 structure, through the setting of the first textured surface 101, the effective area of the battery surface can be increased, so that more light is absorbed, thereby improving the photoelectric conversion efficiency, at the same time, through the formation of micron-level texture on the battery surface, the reflection of light can be effectively reduced, further enhancing the absorption of light, and the textured structure can optimize the motion path of the carriers, reduce the recombination of the carriers, and improve the current output of the battery.

[0061] It can be understood that the thickness and specific material of the silicon wafer substrate 100 and other parameters in the texturing process and the required equipment can be selected according to actual needs, which are not limited here, for example, the silicon wafer substrate 100 is an N-type doped single crystal or polycrystalline silicon wafer with a thickness of 80um-160um, and the pre-cleaning of the silicon wafer substrate is a conventional process, which is not described here.

[0062] Step S20: Mask layer preparation of the silicon wafer, the first mask layer for the second texturing is deposited on the double sides of the silicon wafer after the first texturing, wherein the thickness of the first mask layer is 50nm-250nm, and the refractive index is between 1.5-2.6;

[0063] In this step, after the silicon wafer substrate is textured for the first time, PECVD is used to deposit 50nm-250nm silicon nitride film, silicon oxide film or silicon oxynitride film on the front and back sides of the silicon wafer substrate as the first mask layer for the secondary texture. At the same time, the refractive index is between 1.5-2.6. The deposition material for the first mask layer can be selected according to actual needs and is not restricted here. The specific value of the thickness of the first mask layer and the specific value of the refractive index are within the above range. For example, the thickness is 100nm and the refractive index is 2. The specific selection is based on actual needs. It can be understood that the restriction of the refractive index can help achieve good optical matching between different materials, reduce light reflection loss, ensure that more light can enter the battery, reduce light reflection between different layers, increase light penetration and absorption, and thus improve photoelectric conversion efficiency.

[0064] In some examples, such as Figure 3 As shown, the first mask layer 110 deposited on both sides of the silicon wafer substrate 100 completely covers its surface. Due to the small thickness of the mask layer, its surface will still maintain a pyramid-shaped velvet surface after deposition. Of course, it should be noted that the PECVD technology and the corresponding equipment are existing technologies, and the deposition principle and related parameter settings can be selected according to actual needs, which will not be elaborated here.

[0065] Step S30: The first patterning process of the silicon wafer is to perform grooves on both sides of the silicon wafer according to the positions of the electrode gate lines using a picosecond laser, wherein the grooves are completely ablated to expose the surface of the silicon wafer substrate;

[0066] In this step, a picosecond laser with a wavelength of 325nm-532nm is used to groove the mask layers on the front and back sides according to the position of the electrode grid lines. The width of the front main gate groove is 50-80um, the width of the front auxiliary gate groove is 10um-40um, the width of the back main gate groove is 50um-250um, and the width of the back auxiliary gate groove is 20-80um; the first mask layer at the groove position is completely etched away, that is, the depth of the groove is completely ablated to expose the surface of the silicon wafer substrate.

[0067] It should be noted that, in order to increase the specific surface area of ​​contact between the grid line and the heterojunction solar cell, in this method,

[0068] The setting of the first mask layer can effectively limit the reaction of the mixed texturing solution to the silicon wafer surface area outside the set line groove area during the second texturing, so as to reduce the reflection of light between different layers, increase the penetration and absorption of light, and improve the photoelectric conversion efficiency. In this step, the use of picosecond laser can cooperate well with the first mask layer, so that the copper grid line width can be flexibly adjusted and more refined during the slotting process through the laser of specific wavelength and frequency.

[0069] Meanwhile, the picosecond laser with a wavelength of 325nm-532nm is used for patterning in this step, which can accurately cut and carve at the micron or sub-micron level, and combined with the setting of the first mask layer, so that the slot size is more accurate.

[0070] In some examples, as shown in Figure 4 It is noted that the number and position of the first linear grooves 111 are selected according to actual needs, and are not limited herein. The bottom of the first linear groove 111 formed by the picosecond laser extends to the surface of the silicon wafer substrate 100, and the small fiber surface of the silicon wafer substrate 100 in the first linear groove 111 is etched completely, that is, the silicon nitride at the slot position is etched completely, so that the pyramid structure with a large fiber surface is formed at the bottom of the first linear groove 111 during the second texturing.

[0071] Step S40: second texturing of the silicon wafer. The silicon wafer after slotting is pre-cleaned, and the cleaned silicon wafer is placed in a second texturing mixed solution to form a pyramid structure with a large fiber surface at the bottom of the groove on both sides of the silicon wafer, wherein the size of the pyramid structure is between 4um and 10um;

[0072] In this step, the silicon wafer after slotting is pre-cleaned. The pre-cleaning can be cleaning the laser damage layer at the slot position of the front and back surfaces of the silicon wafer using KOH solution. The cleaned silicon wafer is subjected to second texturing by a texturing process. Specifically, the silicon wafer is placed in a specially prepared second texturing mixed solution, wherein the second texturing mixed solution is composed of at least an alkaline solution, a large fiber surface special additive and ultrapure water. The alkaline solution includes one or more combinations of potassium hydroxide or sodium hydroxide solution. The main component of the large fiber surface special additive is 1%-5% potassium sorbate solution. Other components are selected according to actual needs. The purpose of the second texturing is to form a pyramid structure with a larger size at the gate line position, which is to increase the contact area with the copper gate line and reduce the contact resistance, thereby improving the FF and cell efficiency. The reaction time can be controlled within 200s-1800s. Due to the setting of the first mask layer, a pyramid structure with a large fiber surface is formed on the bottom surface of the linear groove on the front and back (light receiving and backlight) of the silicon wafer substrate, and the size of the pyramid structure is controlled within 3um-10um.

[0073] Step S50: removing the first mask layer from the silicon wafer after the second texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, a TCO layer and an electroplating seed layer on both sides of the silicon wafer;

[0074] In this step, after the second texturing of the front and back surfaces of the silicon wafer, the silicon nitride mask layer on the front and back surfaces is etched by placing the silicon wafer in an aqueous HF solution. In this way, a large-textured pyramid structure is formed at the position corresponding to the line groove of the silicon wafer substrate, and the other areas at the position corresponding to the line groove of the silicon wafer substrate retain a small-textured pyramid structure. Then, an intrinsic amorphous silicon layer, an emitter layer, a TCO layer, and an electroplating seed layer are sequentially deposited on the front and back surfaces of the silicon wafer, which specifically includes the following steps:

[0075] Step S51: An intrinsic amorphous silicon layer is deposited on the front and back surfaces of the silicon wafer after the second texturing, and the thickness of the intrinsic amorphous silicon layer is in the range of 4 nm to 10 nm.

[0076] In this step, an intrinsic amorphous silicon layer is deposited on the front and back surfaces of the silicon wafer using PECVD, with a thickness of 4 nm to 10 nm, which passivates the silicon interface. Optionally, the process gas of the intrinsic amorphous silicon layer is a combination of silane (SiH4), hydrogen (H2), and carbon dioxide (CO2), with a refractive index of 3.2 to 4.8. The intrinsic amorphous silicon layer can passivate the dangling bonds on the surface of the silicon wafer and reduce the surface defect state density.

[0077] Step S52: An emitter layer is deposited on the surface of the intrinsic amorphous silicon layer on the front and back surfaces of the silicon wafer, wherein the emitter layer is one of a doped amorphous silicon layer or a nanocrystalline silicon layer.

[0078] In this step, an emitter layer is deposited on the front and back surfaces of the silicon wafer using PECVD. Specifically, a phosphorus-doped amorphous / nanocrystalline silicon layer is deposited on the front and back surfaces of the silicon wafer, with a thickness of 5 nm to 40 nm, forming an nn+ high-low heterojunction with crystalline silicon. A boron-doped amorphous / nanocrystalline silicon layer is deposited on the back surface of the silicon wafer, with a thickness of 5 nm to 60 nm, forming an np heterojunction as the back emitter of the cell.

[0079] Step S53: A high-transmittance TCO layer is sputtered on the surface of the emitter layer on the front and back surfaces of the silicon wafer.

[0080] In this step, a high-transmittance conductive thin film is sputtered on the front and back surfaces of the cell using PVD or RPD to form a TCO layer for collecting carriers. It should be understood that the thickness of the TCO layer is 80 to 120 nm, and the TCO layer is a conventional setting for heterojunction solar cells. The specific implementation conditions and principles can be achieved by existing technologies, and will not be described here.

[0081] Step S54: A seed layer is deposited on the surface of the TCO layer on the front and back surfaces of the silicon wafer, and the thickness of the seed layer is in the range of 10 nm to 150 nm.

[0082] In this step, electroplating seed layers are prepared on both surfaces of the silicon wafer, and PVD is used to deposit a 10nm-150nm seed layer on the front and back sides of the battery respectively. The seed layer can be roughly divided into three types: copper, nickel and copper-nickel alloy by using different target materials in the PVD sputtering process. The main function of the seed layer is to enhance the bonding force between the copper grid line and the TCO, which helps the heterojunction battery to achieve double-sided electroplating. If the copper grid line is directly grown on the silicon surface, the sintering link is reduced, which is easy to cause grid delamination problems.

[0083] In some examples, such as Figures 5 to 9 As shown, after the first mask layer 110 is removed from the silicon wafer substrate 100, a second velvet surface 112 is formed at the bottom of the double-surface surface grooves, and a first velvet surface 101 is formed in other areas of the grooves. At the same time, an intrinsic amorphous silicon layer 120, a phosphorus-doped silicon layer 130a, a TCO layer 140 and an electroplating seed layer 150 are sequentially deposited on the front side, and an intrinsic amorphous silicon layer 120, a boron-doped silicon layer 130b, a TCO layer 140 and an electroplating seed layer 150 are sequentially deposited on the back side.

[0084] Step S60: performing a second patterning process on the silicon wafer, and printing a second mask layer based on exposure and development on other areas of the silicon wafer where the grooves were opened by the first patterning, wherein the second mask layer is an ink mask layer;

[0085] In this step, the deposited multi-layer structure silicon wafer is patterned for the second time, and the exposure and development method is used to perform alignment masking on other areas outside the patterned grooves in the third step; first, ink is printed on the front and back sides of the battery with the electroplating seed layer, then exposed, and finally developed, leaving the ink in the mask area to form the gate line groove. It should be noted that the exposure and development process is a prior art, and its principles and related parameter settings will not be elaborated here.

[0086] It should be noted that this step uses exposure and development for patterning, taking into full consideration that the battery's passivation film, PN junction, and TCO film layers have all been prepared before this step. These film layers are all at the nanoscale, and laser grooving will cause damage to these film layers, resulting in reduced efficiency.

[0087] Step S70: electroplating copper gate lines on the silicon wafer, and removing the second mask layer and the copper seed layer from the silicon wafer after the gate line electroplating in sequence to obtain a selective electrode contact copper gate line heterojunction solar cell.

[0088] In the step, the copper plating process is performed on the battery, and the vertical continuous plating is used to electroplate the copper grid line at the double-sided grid line groove of the silicon wafer, wherein the width of the front main grid ranges from 50 um to 80 um, the width of the front auxiliary grid ranges from 10 um to 40 um, and the height ranges from 5 um to 20 um; the width of the back main grid ranges from 50 um to 250 um, the width of the back auxiliary grid ranges from 20 um to 80 um, and the height ranges from 5 um to 20 um.

[0089] After the copper grid line is electroplated, the electroplated silicon wafer is soaked in an alkaline mixed solution to remove the second mask layer, wherein the alkaline mixed solution includes one or more combinations of potassium hydroxide or sodium hydroxide solution, and the soaking time ranges from 30 s to 200 s; the silicon wafer with the removed mask is soaked in an acid mixed solution to remove the copper seed layer except the copper grid line, wherein the acid mixed solution includes one or more combinations of dilute sulfuric acid or dilute nitric acid solution, and then the silicon wafer is cleaned with ultrapure water and dried to obtain a selective electrode contact copper grid line silicon-based heterojunction solar cell, wherein the concentration of the potassium hydroxide or sodium hydroxide solution is about 4% to 15%, and the concentration of the dilute sulfuric acid or dilute nitric acid solution is about 0.5% to 1.5%.

[0090] In some examples, as Figures 10 to 13 , the second mask layer 160 made of ink is formed on the surface of the electroplating seed layer 150 by exposure and development, and the second line groove 161 is formed on the surface of the second mask layer 160 at the corresponding position of the first line groove 111, and after electroplating, the copper grid line electrode 170 is formed in the second line groove 161, and finally the electroplating seed layer 150 and the second mask layer 160 are removed, wherein part of the electroplating seed layer 150 remains at the bottom of the copper grid line electrode 170, and a selective electrode contact copper grid line silicon-based heterojunction solar cell is obtained.

[0091] In some embodiments, a selective electrode contact silver grid line silicon-based heterojunction solar cell preparation method is also provided, and it is noted that the difference between the method steps of the selective electrode contact silver grid line silicon-based heterojunction solar cell preparation method and the selective electrode contact copper grid line silicon-based heterojunction solar cell preparation method is that the following steps are included after the step S40 of secondary texturing in the selective electrode contact silver grid line silicon-based heterojunction solar cell preparation method:

[0092] Step S51: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, and a TCO layer on both sides of the silicon wafer;

[0093] In this step, the deposition of the intrinsic amorphous silicon layer, the emitter layer, and the TCO layer can refer to the description in the above embodiments, which will not be described here.

[0094] Step S61: printing electrodes, according to the position of the first patterned slot, selecting the corresponding screen printing, using the method of screen printing silver grid line on the front and back of the silicon wafer, and then curing to obtain a selective electrode contact silver grid heterojunction solar cell.

[0095] In the above process, small velvet texturing is performed on the silicon wafer to form a small velvet pyramid structure on both sides of the silicon wafer, and the size of the pyramid structure is controlled within 0.5um-4um, thereby increasing the light absorption of the heterojunction solar cell and improving the efficiency of the solar cell. Different from the existing heterojunction solar cell production process, after the first texturing, a mask layer is deposited on both sides of the silicon wafer, the mask layer is one of silicon nitride film, silicon oxide film and silicon oxynitride film, and then a grid slot is opened by a 325nm-532nm wavelength picosecond laser to complete the first patterning process. By using a laser with a specific wavelength and frequency, the copper grid line width can be flexibly adjusted and more precise during the slotting process. After cleaning the laser damage layer at the slotting position, the second texturing is performed. Due to the presence of the mask layer, the second texturing produces a large velvet pyramid structure in the slot, and the size of the pyramid is controlled within 4um-10um. After depositing multiple layers and electroplating copper grid lines or printing silver grid lines, the contact specific surface area of the copper electroplating process copper grid line or silver grid line and the transparent conductive oxide (TCO) layer is improved to reduce the series resistance and increase the pulling force, thereby improving the efficiency of the solar cell and improving the grid line detachment problem.

[0096] At the same time, without increasing the width of the grid line, the specific surface area of the contact between the grid line and the heterojunction solar cell body is effectively increased, thereby reducing the series resistance and improving the fill factor efficiency gain. In addition, the battery structure can effectively increase the bonding force between the copper grid line or silver grid line and the TCO layer, thereby effectively improving the grid line detachment problem and improving the yield of the heterojunction solar cell. At the same time, for the copper grid silicon heterojunction solar cell, two different processes are used when the mask layer is prepared before and after the second time. Under the premise of improving the grid detachment and improving the yield, the preparation process of the selective electrode contact silicon heterojunction solar cell is further simplified, and the production efficiency of the heterojunction solar cell is improved.

[0097] In some embodiments, the copper grid heterojunction solar cell prepared by the above method is compared with the experimental data of the ordinary copper grid heterojunction solar cell, as shown in the following table (1), wherein the copper grid control group is the ordinary copper grid heterojunction solar cell, and the copper grid experimental groups 1-3 are the copper grid heterojunction solar cells prepared by the above method. The grid line pull-off force of the copper grid experimental group 2 is 0.9N greater than that of the copper grid control group, and at the same time, the efficiency and FF of the solar cell are effectively improved, and the series resistance is effectively reduced.

[0098] Table (1) is a comparison of experimental data of the copper grid heterojunction solar cell prepared by the above method and the ordinary copper grid heterojunction solar cell

[0099]

[0100] In some embodiments, there is also provided a heterojunction solar cell prepared by the method of preparing a selective electrode contact heterojunction solar cell according to any of the above embodiments.

[0101] It can be understood that the beneficial effects of the technical solutions of the embodiments can refer to the above-mentioned related descriptions of the beneficial effects of the selective electrode contact silicon heterojunction solar cell, which will not be described here.

[0102] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application.

[0103] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example.

[0104] Obviously, the described embodiments are only a part of the embodiments of the present application, not all. In this paper, "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification is not necessarily the same embodiment, nor is it independent or alternative to other embodiments or alternative embodiments. It is obvious to those skilled in the art that the embodiments described herein can be combined with other embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0105] While the embodiments of the application have been shown and described, it is to be understood that the embodiments can be varied, modified, substituted and changed by those skilled in the art without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for preparing a selective electrode contact heterojunction battery, characterized in that: include: Step S10: First texturing of the silicon wafer substrate, placing the silicon wafer substrate in a first texturing mixture to form small textured pyramid structures on both sides of the silicon wafer substrate, wherein the size of the pyramid structures is between 0.5um and 4um; Step S20: preparing a mask layer for the silicon wafer, depositing a first mask layer for the second texturing on both sides of the silicon wafer after the first texturing, wherein the thickness of the first mask layer is 50nm-250nm, and the refractive index is between 1.5-2.6; Step S30: The first patterning process of the silicon wafer is to perform grooves on both sides of the silicon wafer according to the positions of the electrode gate lines using a picosecond laser, wherein the grooves are completely ablated to expose the surface of the silicon wafer substrate; Step S40: Second texturing of the silicon wafer, pre-cleaning the grooved silicon wafer, and placing the cleaned silicon wafer in a second texturing mixture to form a large textured pyramid structure on the bottom surface of the double-sided groove of the silicon wafer, wherein the size of the pyramid structure is between 4um and 10um; Step S50: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, a TCO layer, and an electroplating seed layer on both sides of the silicon wafer; Step S60: performing a second patterning process on the silicon wafer, and printing a second mask layer based on exposure and development on other areas of the silicon wafer where the grooves were opened by the first patterning, wherein the second mask layer is an ink mask layer; Step S70: electroplating copper gate lines on the silicon wafer, and removing the second mask layer and the copper seed layer from the silicon wafer after the gate line electroplating in sequence to obtain a selective electrode contact copper gate line heterojunction solar cell.

2. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In step S10, the first texturing mixture is composed of at least an alkaline solution, a small-texture additive, and ultrapure water, wherein the alkaline solution includes a combination of one or more of potassium hydroxide solution and sodium hydroxide solution.

3. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S20, the first mask layer includes one or more of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film.

4. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In step S30, the mask layer on the front and back sides of the silicon wafer is grooved according to the position of the preset electrode grid line based on a picosecond laser, wherein the wavelength range of the picosecond laser is 325nm-532nm, the front main gate groove width range is 50um-80um, the front sub-gate groove width range is 10um-40um, the back main gate groove width range is 50um-250um, and the back sub-gate groove width range is 20-80um.

5. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In step S40, a potassium hydroxide solution is used to clean the laser damaged layer at the grooved position on the front and back sides of the silicon wafer, and the cleaned silicon wafer is placed in a second texturing mixture for texturing, wherein the second texturing mixture is composed of at least an alkaline solution, a special additive for large texturing surfaces and ultrapure water, and the alkaline solution includes a combination of one or more potassium hydroxide or sodium hydroxide solutions.

6. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S50, it includes: Step S51: depositing an intrinsic amorphous silicon layer on both sides of the silicon wafer after secondary texturing, wherein the thickness of the intrinsic amorphous silicon layer is in the range of 4 nm to 10 nm; Step S52: depositing emitter layers on the surfaces of the intrinsic amorphous silicon layer on both sides of the silicon wafer, wherein the emitter layer is one of a doped amorphous silicon layer and a nanocrystalline silicon layer; Step S53: sputtering a high-transmittance TCO layer on the emitter layer surface on both sides of the silicon wafer; Step S54: depositing a seed layer on the surface of the TCO layer on both sides of the silicon wafer, wherein the thickness of the seed layer is in the range of 10 nm to 150 nm.

7. The method for preparing a selective electrode contact heterojunction battery according to claim 6, characterized in that: In the step S52, it specifically includes: Depositing a phosphorus-doped amorphous silicon or a phosphorus-doped nanocrystalline silicon layer on the surface of the intrinsic amorphous silicon layer on the light-receiving side of the silicon wafer to form a front emitter, wherein the phosphorus-doped amorphous silicon or phosphorus-doped nanocrystalline silicon layer has a thickness ranging from 5 nm to 40 nm; A boron-doped amorphous silicon or boron-doped nanocrystalline silicon layer is deposited on the surface of the intrinsic amorphous silicon layer on the backlight side of the silicon wafer to form a back emitter. The boron-doped amorphous silicon or boron-doped nanocrystalline silicon layer has a thickness of 5nm-60nm.

8. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: In the step S70, the following is further included: Immersing the electroplated silicon wafer in an alkaline mixed solution to remove the second mask layer, wherein the alkaline mixed solution includes a combination of one or more potassium hydroxide solutions or sodium hydroxide solutions, and the immersion time ranges from 30 seconds to 200 seconds; The silicon wafer with the mask removed is immersed in an acidic mixed solution to remove the copper seed layer except the copper grid line, wherein the acidic mixed solution includes a combination of one or more of dilute sulfuric acid solution and dilute nitric acid solution.

9. The method for preparing a selective electrode contact heterojunction battery according to claim 1, characterized in that: When the battery electrodes are silver grid lines, the step S40 includes: Step S51: removing the first mask layer from the silicon wafer after secondary texturing, and sequentially depositing an intrinsic amorphous silicon layer, an emitter layer, and a TCO layer on both sides of the silicon wafer; Step S61: printing electrodes. According to the position of the first patterned groove, a corresponding screen is selected, and silver grid lines are printed on the front and back of the silicon wafer using screen printing. After curing, a selective electrode contact silver grid heterojunction solar cell is obtained.

10. A heterojunction solar cell, characterized in that: The heterojunction solar cell is prepared by the method for preparing a selective electrode contact heterojunction cell as claimed in any one of claims 1 to 9.

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