Display panel and method of providing display panel

Abstract

The invention relates to a display panel and a method for providing the same. The display panel includes: a pixel defining layer in which a first light emitting opening and a second light emitting opening are defined; a partition wall in which a first partition wall opening and a second partition wall opening are defined; a first light emitting element in the first partition wall opening; a second light emitting element in the second partition wall opening; a first lower inorganic encapsulation pattern covering the first light emitting element; and a second lower inorganic encapsulation pattern spaced apart from the first lower inorganic encapsulation pattern and covering the second light emitting element. A thickness of the first lower inorganic encapsulation pattern is less than a thickness of the second lower inorganic encapsulation pattern.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2023-0119942 filed on September 8, 2023 and all benefits arising from the Korean Patent Application, the entire contents of which are incorporated herein by reference. Background Art

[0002] The present disclosure relates to a display panel and a method of providing a display panel. More particularly, the present disclosure relates to a display panel with improved display quality. Technical Field

[0003] Display devices such as televisions, monitors, smart phones, and tablet computers that provide images to users include display panels for displaying images. Various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels are being developed.

[0004] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern in a light emitting element in a light emitting region. The light emitting pattern may be separated for each light emitting region, and the cathode may provide a common voltage to the light emitting region. Summary of the invention

[0005] The present disclosure provides a display panel having improved display quality and a method for providing (or manufacturing) a display panel in which a light emitting element is provided (or formed) without using a metal mask.

[0006] An embodiment of the present invention provides a display panel, comprising: a base layer; a pixel defining layer, which is arranged on the base layer and defines a first light-emitting opening and a second light-emitting opening in the pixel defining layer; a partition wall, which is on the pixel defining layer and defines a first partition wall opening overlapping with the first light-emitting opening and a second partition wall opening overlapping with the second light-emitting opening in the partition wall; a first light-emitting element, which is arranged in the first partition wall opening and includes a first anode, a first light-emitting pattern and a first cathode; a second light-emitting element, which is arranged in the second partition wall opening and includes a second anode, a second light-emitting pattern and a second cathode; a first lower inorganic encapsulation pattern, which covers the first light-emitting element; and a second lower inorganic encapsulation pattern, which is spaced apart from the first lower inorganic encapsulation pattern and covers the second light-emitting element, wherein the thickness of the first lower inorganic encapsulation pattern is less than the thickness of the second lower inorganic encapsulation pattern.

[0007] In an embodiment, the first light emitting element may emit blue light, and the second light emitting element may emit green light.

[0008] In an implementation, the first lower inorganic encapsulation pattern may have a thickness of about 0.2 μm (micrometers) to about 1.0 μm.

[0009] In an implementation, the second lower inorganic encapsulation pattern may have a thickness of about 1.0 μm to about 1.5 micrometers (μm).

[0010] In an embodiment, a first dummy region may be defined between the first lower inorganic encapsulation pattern and a partition wall defining the first partition wall opening, and a second dummy region may be defined between the second lower inorganic encapsulation pattern and a partition wall defining the second partition wall opening.

[0011] In an implementation, a height of the first virtual area may be smaller than a height of the second virtual area.

[0012] In an embodiment, a third light emitting opening may be further defined in the pixel defining film, and a third partition wall opening overlapping the third light emitting opening may be further defined in the partition wall. The display panel may further include: a third light emitting element disposed in the third partition wall opening and including a third anode, a third light emitting pattern, and a third cathode; and a third lower inorganic encapsulation pattern covering the third light emitting element.

[0013] In an implementation, a thickness of the third lower inorganic encapsulation pattern may be equal to or greater than a thickness of the second lower inorganic encapsulation pattern.

[0014] In an embodiment, the third light emitting element may emit red light.

[0015] In an implementation, the third lower inorganic encapsulation pattern may have a thickness of about 1.0 μm to about 1.7 μm.

[0016] In an implementation, a third dummy region may be defined between the third lower inorganic encapsulation pattern and a partition wall defining the third partition wall opening.

[0017] In an implementation, a height of the third virtual area may be greater than a height of the second virtual area.

[0018] In an embodiment of the present invention, a manufacturing method for a display panel includes: providing a preliminary display panel, the preliminary display panel including a base layer, a pixel defining film arranged on the base layer, a first preliminary partition wall layer arranged on the pixel defining film, and a second preliminary partition wall layer arranged on the first preliminary partition wall layer; etching the first preliminary partition wall layer and the second preliminary partition wall layer to form a partition wall, in which a first partition wall opening, a second partition wall opening, and a third partition wall opening are defined; forming a first light-emitting element in the first partition wall opening; forming a first lower inorganic packaging pattern covering the first light-emitting element; forming a second light-emitting element in the second partition wall opening; forming a second lower inorganic packaging pattern covering the second light-emitting element; forming a third light-emitting element in the third partition wall opening; and forming a third lower inorganic packaging pattern covering the third light-emitting element, and the thickness of the first lower inorganic packaging pattern is less than the thickness of the second lower inorganic packaging pattern.

[0019] In an implementation, a thickness of the third lower inorganic encapsulation pattern may be equal to or greater than a thickness of the second lower inorganic encapsulation pattern.

[0020] In an embodiment, forming the first light emitting element in the first partition wall opening may include forming a first dummy layer inside the second partition wall opening and the third partition wall opening and on the partition walls.

[0021] In an embodiment, forming a first lower inorganic packaging pattern covering a first light emitting element may include: depositing a first lower inorganic packaging layer to cover the first partition wall opening, the second partition wall opening, the third partition wall opening and the partition wall and having a thickness of about 0.2 μm to about 1.0 μm; removing a portion of the first lower inorganic packaging layer that does not overlap with the first light emitting element; and removing the first dummy layer to form a first dummy region between the first lower inorganic packaging pattern and the partition wall defining the first partition wall opening.

[0022] In an embodiment, forming the second light emitting element in the second partition wall opening may include forming a second dummy layer inside the first partition wall opening and the third partition wall opening and on the partition walls.

[0023] In an embodiment, forming a second lower inorganic packaging pattern covering a second light emitting element may include: depositing a second lower inorganic packaging layer to cover the first partition wall opening, the second partition wall opening, the third partition wall opening and the partition wall and having a thickness of about 1.0 μm to about 1.5 μm; removing a portion of the second lower inorganic packaging layer that does not overlap with the second light emitting element; and removing the second virtual layer to form a second virtual region between the second lower inorganic packaging pattern and the partition wall defining the second partition wall opening.

[0024] In an embodiment, forming the third light emitting element in the third partition wall opening may include forming a third dummy layer inside the first partition wall opening and the second partition wall opening and on the partition wall.

[0025] In an embodiment, forming a third lower inorganic packaging pattern covering a third light emitting element may include: depositing a third lower inorganic packaging layer to cover the first partition wall opening, the second partition wall opening, the third partition wall opening and the partition wall and having a thickness of about 1.0 μm to about 1.7 μm; removing a portion of the third lower inorganic packaging layer that does not overlap with the third light emitting element; and removing the third dummy layer to form a third dummy region between the third lower inorganic packaging pattern and the partition wall defining the third partition wall opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention. In the drawings:

[0027] Figure 1A is a perspective view of a display device according to an embodiment of the present invention;

[0028] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present invention;

[0029] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention;

[0030] Figure 3 is a plan view of a display panel according to an embodiment of the present invention;

[0031] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention;

[0032] Figure 5 is an enlarged plan view showing a portion of a display area of ​​a display panel according to an embodiment of the present invention;

[0033] Figure 6 is a display panel according to an embodiment of the present invention. Figure 3 A cross-sectional view taken along line II';

[0034] Figure 7 is along Figure 5 A cross-sectional view taken along line II-II'; and

[0035] FIG. 8A to FIG. 8I , 9A to 9D , FIG. 10A to FIG. 10D and Fig.11 are cross-sectional views showing processes of a method of manufacturing (or providing) a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In this specification, it should be understood that when an element (or region, layer, part, etc.) is referred to as being associated with another element, such as being "on" another element, "connected to" another element, "coupled to" another element, it can be directly disposed on the other element, directly connected or directly coupled to the other element, or an intervening element can be disposed between the element and the other element. Conversely, when an element (or region, layer, part, etc.) is referred to as being associated with another element, such as being "directly on" another element, "directly connected to" another element, "directly coupled to" another element, no intervening element is disposed between the element and the other element. As used herein, elements that are in contact with each other can form an interface therebetween.

[0037] The same reference numerals or symbols refer to the same elements throughout the text. In the drawings and text of the present disclosure, reference numerals indicating elements in the singular form may also be used to refer to multiple singular elements. In the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the elements are exaggerated.

[0038] It should be understood that although the terms first, second, etc. can be used to describe various elements, components, areas, layers and / or sections herein, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms are only used to distinguish an element, component, area, layer or section from another element, component, area, layer or section. Therefore, without departing from the scope of the present invention, the first element, first component, first area, first layer or first section discussed below can be referred to as the second element, second component, second area, second layer or second section. Similarly, the second element, second component, second area, second layer or second section can be referred to as the first element, first component, first area, first layer or first section.

[0039] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are intended to also include plural forms. Therefore, mentioning "an" element after mentioning "the" element in the claims includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0040] In addition, terms such as "below", "on the lower side", "above", "on the upper side" and the like may be used to describe the relationship of elements illustrated in the drawings. These terms have relative concepts and are described based on directions indicated in the drawings.

[0041] It should be further understood that the terms “including” and / or “having” when used in this specification specify the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0042] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art in view of the relevant measurements and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It should be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0044] Hereinafter, embodiments of the present invention are described with reference to the accompanying drawings.

[0045] Figure 1A is a perspective view of a display device DD according to an embodiment of the present invention, and Figure 1B is an exploded perspective view of a display device DD according to an embodiment of the present invention.

[0046] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or a billboard. In addition, the display device DD may be a small electronic device or a medium-sized electronic device such as a personal computer, a laptop computer, a personal digital assistant, a car navigation unit, a game console, a smart phone, a tablet computer, and a camera. However, this is an example, and another display device may also be adopted unless it departs from the idea of ​​the present invention. Figure 1A and Figure 1B A display device DD is shown as an example as a smartphone.

[0047] refer to Figure 1A and Figure 1B, the display device DD may display an image IM on a display surface FS disposed on a plane. The display surface FS may be parallel to a plane defined by a first direction DR1 and a second direction DR2 intersecting each other. The display surface FS may be visible along a third direction DR3, so that the image IM may be displayed toward the third direction DR3. The thickness of the display device DD and / or its various components or layers may be defined along the third direction DR3 as a thickness direction.

[0048] The image IM may include a still image as well as a dynamic image. Figure 1A A clock and an icon are shown as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0049] In the present embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each component are defined based on the direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. As used herein, the directions represented by the first direction DR1, the second direction DR2, and the third direction DR3 may be relative concepts and may therefore be changed to other directions. In the present specification, "on a plane" or "in a plan view" may refer to a state when observed from the third direction DR3.

[0050] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP may be coupled to the housing HAU to form an exterior of the display device DD.

[0051] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may have a visible light transmittance of about 90% or more.

[0052] The border area BZA may be an area (or a plane area) having a transmittance relatively lower than that of the transmission area TA. The border area BZA may define the shape (e.g., a plane shape) of the transmission area TA. The border area BZA may be adjacent to the transmission area TA, for example, closer to the outer edge of the display device DD than the transmission area TA. In an embodiment, the border area BZA may surround the transmission area TA. However, this is shown as an example, and the border area BZA of the window WP may be omitted. The window WP may include at least any one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment of the present invention.

[0053] The display module DM may be disposed under the window WP. The display module DM may be essentially a component that generates an image IM. The image IM generated in the display module DM is displayed on the display surface IS of the display module DM and is observable to the outside of the display device DD, such as to a user of the display device DD, through the transmissive area TA.

[0054] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be covered by the bezel area BZA and thus may not be visible from the outside (e.g., outside the display device DD).

[0055] The housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0056] The housing HAU may include a relatively high rigidity material. For example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the components of the display device DD housed in the internal space from external impact.

[0057] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0058] refer to Figure 2 The display module DM may include a display panel DP as an imaging display layer and an input sensor INS as an input sensing layer. Although not shown separately in the drawings, according to an embodiment of the present invention, the display device DD (see Figure 1A ) may further include a protection member disposed on the lower surface of the display panel DP or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0059] The display panel DP may be an emissive display panel. However, this is an example, and the embodiments of the present invention are not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0060] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE as an encapsulation layer. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. In this specification, "component A is directly disposed on component B" means that no intervening adhesive layer is disposed between component A and component B.

[0061] The base layer BL may include at least one plastic film. The base layer BL as a flexible substrate may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, etc. Figure 1B The described display area DA and non-display area NDA may be similarly defined in the base layer BL. That is, various layers or components of the display device DD may include the display area DA, non-display area NDA, etc. corresponding to the above-described components.

[0062] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixels PX (see Figure 3 ) driving circuit, etc.

[0063] The display element layer DP-OLED may include partition walls and light emitting elements ED (see Figure 6 ). The light emitting element ED may include an anode AE ​​(see Figure 6 ), intermediate layer and cathode CE (see Figure 6 ). The light emitting element ED may be electrically connected to the circuit element layer DP-CL.

[0064] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be provided for improving optical efficiency, and other thin films may be provided for protecting the organic light emitting diode.

[0065] The input sensor INS acquires coordinate information of an external input to the display device DD. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. In addition, the input sensor INS may include a single layer or multiple layers of insulating layers. The input sensor INS may detect the external input in a capacitive manner. However, this is an example, and embodiments of the present invention are not limited thereto. For example, in an embodiment, the input sensor INS may also detect the external input in an electromagnetic induction or pressure sensing manner. According to another embodiment of the present invention, the input sensor INS may be omitted.

[0066] Figure 3 is a plan view of a display panel DP according to an embodiment of the present invention.

[0067] refer to Figure 3, a display area DA and a non-display area NDA surrounding the display area DA may be defined in the display panel DP. The display area DA and the non-display area NDA may be distinguished according to whether pixels PX are disposed therein. The pixels PX may be disposed in the display area DA, and the pixels PX may not be disposed in the non-display area NDA.

[0068] The display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, first control lines CSL1 and second control lines CSL2, driving voltage lines PL, scan drivers SDV, data drivers, emission drivers EDV, driving chips DIC, and pads PD. Here, "m" and "n" are natural numbers of at least 2. The data driver may be a partial circuit configured in the driving chip DIC.

[0069] The pixels PX may be connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0070] Initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, and black scan lines GBL1 to GBLm may extend in a first direction DR1 to be electrically connected to a scan driver SDV. Data lines DL1 to DLn may extend in a second direction DR2 to be electrically connected to a drive chip DIC. Emission control lines ECL1 to ECLm may extend in a first direction DR1 to be electrically connected to an emission driver EDV.

[0071] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion of the driving voltage line PL extending in the first direction DR1 and the portion extending in the second direction DR2 may be disposed on different layers from each other within the display panel DP. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0072] The first control line CSL1 may be connected to the scan driver SDV. The second control line CSL2 may be connected to the emission driver EDV.

[0073] The driving chip DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD. A flexible circuit film FCB such as a circuit board may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a terminal pad for connecting the flexible circuit film FCB to the display panel DP. That is, the display panel DP may be electrically connected to an external component such as a circuit board at the pad PD of the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0074] In addition, the pad PD may also include an input pad. The input pad may be used to connect the flexible circuit film FCB to the input sensor INS (see Figure 2 ) of the input sensor INS. That is, the external component may be connected to the input pad at the input sensor INS. However, the embodiments of the present invention are not limited thereto, and the input pad may be provided on the input sensor INS and connected to the circuit board separately from the pad PD. In addition, the input sensor INS may be omitted, and the input pad may not be included.

[0075] Figure 4 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present invention.

[0076] Figure 4 A plurality of pixels PX are shown as an example (see Figure 3 ) is an equivalent circuit diagram of a pixel PXij in FIG. Since each of the plurality of pixels PX has the same circuit structure, the description of the circuit structure of the pixel PXij can be equally applicable to the remaining pixels PX, and thus the detailed description of the remaining pixels PX will be omitted.

[0077] refer to Figure 3 and Figure 4 , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th emission control line ECLj among the emission control lines ECL1 to ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4. Here, i is an integer from 1 to n, and j is an integer from 1 to m.

[0078] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present invention, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but the embodiments of the present invention are not particularly limited thereto. The pixel circuit PDC may control the amount of current (e.g., current) flowing through the light emitting element ED in response to the data signal Di. The light emitting element ED may emit light of a predetermined brightness in response to the amount of current provided from the pixel circuit PDC.

[0079] The pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. The configuration of the pixel circuit PDC according to an embodiment of the present invention is not limited to Figure 4 The embodiment shown in FIG. Figure 4 The pixel circuit PDC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PDC may be variously set.

[0080] At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0081] In particular, the first transistor T1 that directly affects the brightness of the light-emitting element ED can be configured to include a semiconductor layer composed of high-reliability polysilicon, thereby realizing a high-resolution display device. Since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not significant despite the long operating time. That is, since the color change of the image IM caused by the voltage drop is not significant even during low-frequency driving, low-frequency driving is possible. As previously described, since the oxide semiconductor has the advantage of low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 is used as an oxide semiconductor. It can prevent leakage current from flowing into the gate electrode, and at the same time, power consumption can be reduced.

[0082] Some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the others may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0083] The configuration of the pixel circuit PDC according to the embodiment of the present invention is not limited to Figure 4 The embodiment shown in FIG. Figure 4 The pixel circuit PDC shown in the figure is only an example, and the configuration of the pixel circuit PDC may be set differently. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type transistors.

[0084] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj may transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a voltage level corresponding to an image signal input to the display device DD (see FIG. 1 ).

[0085] The first and second driving voltage lines VL1 and VL2 may transmit first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0086] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5 and a second electrode connected to a pixel electrode (or referred to as an anode AE) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 can receive the i-th data signal Di transmitted through the i-th data line DLi according to the switching operation of the second transistor T2, and provide a driving current to the light emitting element ED.

[0087] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on in response to a write scan signal GWj received through the j-th write scan line GWLj, and transmit an i-th data signal Di transmitted through the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst may be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst may be connected to the first node N1.

[0088] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 may be turned on in response to the j-th compensation scan signal GCj transmitted through the j-th compensation scan line GCLj, and the third electrode of the first transistor T1 and the second electrode of the first transistor T1 are connected to each other so that the first transistor T1 is diode-connected. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst may be connected to the first node N1.

[0089] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 through which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on in response to the j-th initialization scan signal GIj transmitted through the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1, and thus initializes the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0090] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode (e.g., the second node N2) of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0091] The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the jth emission control signal EMj transmitted through the jth emission control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the diode-connected first transistor T1 and then transmitted to the light emitting element ED through the sixth transistor T6.

[0092] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 through which a second initialization voltage VAINT is transmitted, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to a voltage level of the first initialization voltage VINT.

[0093] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. Figure 6 ) may be connected to a second driving voltage line VL2 through which a second driving voltage ELVSS is transmitted. The second driving voltage ELVSS may have a voltage level lower than that of the first driving voltage ELVDD.

[0094] Figure 5 FIG. 2 is a diagram showing a display panel DP (see FIG. 2 ) according to an embodiment of the present invention. Figure 2 ) is an enlarged plan view of a portion of the display area DA. Figure 5 shows when the display module DM (see Figure 1B ) of the display surface IS (see Figure 1B ) is a plan view of the display module DM when viewed from above, and shows the arrangement of the light emitting areas PXA-B, PXA-G and PXA-R.

[0095] refer to Figure 5 , the display area DA may include a light-emitting area and a non-light-emitting area adjacent to the light-emitting area. The light-emitting area may be set to include a plurality of light-emitting areas including a first light-emitting area PXA-B, a second light-emitting area PXA-G, and a third light-emitting area PXA-R, and the non-light-emitting area may include a peripheral area NPXA surrounding the first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R. The first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R may respectively correspond to an area (or a plane area) in which light provided by the light-emitting element ED is emitted. The first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R may be arranged according to the direction toward the display module DM (see Figure 2 ) is distinguished by the color of the externally emitted light.

[0096] The first light emitting area PXA-B, the second light emitting area PXA-G, and the third light emitting area PXA-R may respectively provide first to third color lights having colors different from each other. For example, the first color light may be blue light, the second color light may be green light, and the third color light may be red light. However, the examples of the first to third color lights are not necessarily limited to the embodiments of the present invention.

[0097] The first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R may each be defined as an area in which the upper surface of the anode AE ​​is exposed by the light-emitting opening OP-E to be described later. That is, the plane area of ​​the corresponding light-emitting area may correspond to the plane area of ​​the anode AE ​​exposed to the outside of the pixel defining layer. The peripheral area NPXA may set the boundaries of the first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R, and prevent color mixing between the first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R.

[0098] The first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R may each be provided in plural numbers and repeatedly provided in a predetermined arrangement within the display area DA. For example, the first light-emitting area PXA-B and the third light-emitting area PXA-R may be alternately arranged along the first direction DR1 to form a "first group". The second light-emitting area PXA-G may be arranged along the first direction DR1 to form a "second group". The "first group" and the "second group" may each be provided in plural numbers, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0099] A second light emitting area PXA-G may be spaced apart from a first light emitting area PXA-B or a third light emitting area PXA-R in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2, for example, a direction inclined relative to the first direction DR1 or the second direction DR2.

[0100] Figure 5 The arrangement of the first light emitting area PXA-B, the second light emitting area PXA-G, and the third light emitting area PXA-R is shown as an example, the embodiments of the present invention are not limited thereto, and the arrangement may have various forms. In an embodiment, the first light emitting area PXA-B, the second light emitting area PXA-G, and the third light emitting area PXA-R may have a configuration as follows: Figure 5 As shown in Alternatively, the first light-emitting area PXA-B, the second light-emitting area PXA-G and the third light-emitting area PXA-R may also have a stripe arrangement or a diamond arrangement. Layout form.

[0101] The first light emitting area PXA-B, the second light emitting area PXA-G and the third light emitting area PXA-R may have various shapes on a plane. For example, the first light emitting area PXA-B, the second light emitting area PXA-G and the third light emitting area PXA-R may have a polygonal, circular, elliptical or other plane shape. Figure 5 The first and third light emitting regions PXA-B and PXA-R which are quadrilaterals (eg, rhombuses) on a plane and the second light emitting region PXA-G which is an octagon are exemplarily shown.

[0102] The first light emitting region PXA-B, the second light emitting region PXA-G, and the third light emitting region PXA-R may have the same shape on a plane, and optionally, at least some may have different shapes. Figure 5 The first and third light emitting regions PXA-B and PXA-R having the same shape on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-B and PXA-R are exemplarily shown.

[0103] At least some of the first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R may have different areas on a plane. In an embodiment, the area of ​​the third light-emitting area PXA-R emitting red light may be larger than the area of ​​the second light-emitting area PXA-G emitting green light, and smaller than the area of ​​the first light-emitting area PXA-B emitting blue light. However, the size relationship between the areas of the first light-emitting area PXA-B, the second light-emitting area PXA-G, and the third light-emitting area PXA-R according to the light-emitting color is not limited thereto, and may be selected according to the display module DM (see Figure 2 In addition, the embodiments of the present invention are not limited thereto, and the first light emitting area PXA-B, the second light emitting area PXA-G, and the third light emitting area PXA-R may have the same area on a plane.

[0104] According to an embodiment of the present invention, the display module DM (see Figure 2 The shapes, areas, arrangements, etc. of the first light emitting area PXA-B, the second light emitting area PXA-G, and the third light emitting area PXA-R can be determined according to the color of the emitted light, the display module DM (see Figure 2 )'s size and composition can be variously designed, and are not limited to Figure 5 The embodiment shown in FIG.

[0105] Figure 6 According to an embodiment of the present invention, Figure 3 A cross-sectional view of the display panel DP taken along line II'. Figure 2 describe Figure 6 , and descriptions of the same figure numerals or symbols will be omitted.

[0106] Figure 6 is the display area DA (see Figure 5 ), and Figure 6 The light emitting area PXA in may correspond to Figure 5 Any one of the first light emitting area PXA-B, the second light emitting area PXA-G and the third light emitting area PXA-R in the reference Figure 6 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0107] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. on the base layer BL. The material layers of the insulating layers, semiconductor layers, and conductive layers are formed (or provided) by coating, deposition, etc. Thereafter, the material layers forming the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this way, the semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed as corresponding patterns of the material layers.

[0108] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission line SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0109] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0110] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the embodiments of the present invention are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 6 A partial semiconductor pattern is shown only as an example, and the semiconductor pattern may be further provided in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 5 ). The semiconductor pattern may be arranged across a plurality of light emitting regions PXA-B, PXA-G, and PXA-R according to certain rules. The semiconductor pattern may differ in electrical characteristics depending on whether its region is doped. The semiconductor pattern may include a first region doped with a high concentration and a second region doped with a low concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0111] The first region may have a higher conductivity (e.g., electrical conductivity) than that of the second region and may be substantially used as a conductive electrode or an electrical signal line. The second region may substantially correspond to an active portion (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active portion of a transistor, another portion of the semiconductor pattern may be a source or drain of the transistor, and another portion of the semiconductor pattern may be a conductive region.

[0112] The source S, the active portion A, and the drain D of the transistor TR1 may be formed of the same semiconductor pattern. Figure 6A portion of a signal transmission line SCL formed by a semiconductor pattern is shown. Although not shown separately in the drawings, the signal transmission line SCL may be connected to the drain D of the transistor TR1 on a plane. That is, the source S, the active portion A, the drain D, and the signal transmission line SCL may be in the same layer as each other. Because in the same layer, the elements may be formed in the same process and / or include the same material as each other, the elements may be corresponding portions or patterns of the same material layer, the elements may be on the same layer by forming an interface with the same layer located below or above, etc., but are not limited thereto.

[0113] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be disposed on the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may each be an inorganic layer or an organic layer.

[0114] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active portion A, and the drain D of the transistor TR1 disposed on the buffer layer BFL, and the signal transmission line SCL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 and cover the electrode EE.

[0115] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission line SCL through a contact hole CNT-1 passing through the first insulating layer 10, the first insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0116] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0117] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining layer PDL as a pixel defining layer, and a partition wall PW of a bank layer.

[0118] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode).

[0119] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined through the fifth insulating layer 50. Thus, the anode AE ​​may be electrically connected to the signal transmission line SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus electrically connected to the corresponding circuit element.

[0120] The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers containing ITO and Ag. For example, the anode AE ​​may include a layer containing ITO (hereinafter, lower ITO layer), a layer containing Ag disposed on the lower ITO layer (hereinafter, Ag layer), and a layer containing ITO disposed on the Ag layer (hereinafter, upper ITO layer).

[0121] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel defining film PDL. A sacrificial opening OP-S defined by a portion of the sacrificial pattern SP may be defined in the sacrificial pattern SP, wherein the sacrificial opening OP-S exposes a portion of the upper surface of the anode AE ​​outside the sacrificial pattern SP. The sacrificial opening OP-S may overlap with a light emitting opening OP-E of a pixel defining layer to be described later.

[0122] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening OP-E may be defined in (or by) the pixel defining film PDL. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​to the outside of the pixel defining film PDL through the light emitting opening OP-E.

[0123] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to this embodiment, the upper surface of the anode AE ​​may be spaced apart from the pixel defining layer PDL in the cross section and along the third direction DR3 and the sacrificial pattern SP is between the anode AE ​​and the pixel defining layer PDL. Therefore, it may be possible to protect the anode AE ​​from damage in the process of forming the light emitting opening OP-E.

[0124] On a plane, the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner side surface of the pixel defining film PDL defining the light-emitting opening OP-E may be closer (e.g., closer) to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the embodiments of the present invention are not limited thereto, and the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S may also be substantially aligned with the inner side surface of the pixel defining film PDL defining the light-emitting opening OP-E. At this time, the light-emitting area PXA may also be considered as the area of ​​the anode AE ​​exposed by the corresponding sacrificial opening OP-S.

[0125] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x ). The pixel defining film PDL may be disposed between the anode AE ​​and the partition wall PW, and thus may prevent the anode AE ​​and the partition wall PW from being electrically connected to each other.

[0126] The light emitting pattern EP may be disposed on the anode AE. The light emitting pattern EP may include a light emitting layer containing a light emitting material. The light emitting pattern EP may also include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the light emitting layer, and may also include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light emitting layer. The light emitting pattern EP may also be referred to as an "organic layer" or an "intermediate layer".

[0127] The light-emitting pattern EP may have a discrete shape. The discrete shape may be provided by a material layer of the light-emitting pattern EP, and the material layer of the light-emitting pattern EP is disconnected by a stacked structure on which such a material layer is applied. In an embodiment of providing a display panel DP, the material providing the light-emitting pattern EP may be patterned (or disconnected) by a pointed portion defined by an inner side wall of a partition wall PW, wherein the disconnected portion provides the light-emitting pattern EP in a corresponding opening at the light-emitting area PXA. The light-emitting pattern EP may be arranged inside the sacrificial opening OP-S at the sacrificial pattern layer, inside the light-emitting opening OP-E at the pixel defining layer, and inside the partition wall opening OP-P at the embankment layer. The above-mentioned openings may together form a light-emitting opening at the light-emitting area PXA. The light-emitting pattern EP may extend from the anode AE ​​to cover a portion of the upper surface of the pixel defining film PDL that is exposed at the light-emitting opening through the partition wall opening OP-P.

[0128] The cathode CE may be disposed on the light emitting pattern EP. Similar to the above description, the material providing the cathode CE may be patterned by a pointed portion defined by the partition wall PW. At least a portion of the cathode CE may be disposed in the partition wall opening OP-P. The cathode CE may be in contact with the first inner surface S-L1 of the first partition wall layer L1, wherein the first inner surface S-L1 defines the lower portion of the embankment opening. The cathode CE may have electrical conductivity. As long as it has electrical conductivity, the cathode CE may be formed of various materials such as metals, transparent conductive oxides (TCOs), or conductive polymer materials. For example, the cathode CE may contain silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0129] According to an embodiment of the present invention, the display element layer DP-OLED may further include a capping pattern (not shown). The capping pattern may be disposed in the partition wall opening OP-P and disposed on the cathode CE. Here, the material layer providing the capping pattern may be patterned by a sharp portion formed by the partition wall PW.

[0130] The partition wall PW may be disposed on the pixel definition film PDL. The partition wall opening OP-P may be defined in the partition wall PW by a continuous portion of the partition wall PW. The partition wall opening OP-P may correspond to the light emitting opening OP-E defined by a continuous portion of the pixel definition layer, and may expose at least a portion of the anode AE ​​to the outside of the bank layer.

[0131] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of layers stacked in sequence, and at least one of the plurality of layers may be recessed compared to another layer, thereby forming an undercut structure. Therefore, the partition wall PW may include or define a pointed portion.

[0132] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition film PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 6 , the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2 , but the embodiments of the present invention are not limited thereto.

[0133] The first partition wall layer L1 may be relatively recessed at the light emitting area PXA compared to the second partition wall layer L2. The first partition wall layer L1 may be formed by recessing the sidewall of the first partition wall layer L1 relative to the sidewall of the second partition wall layer L2. A portion of the second partition wall layer L2 that protrudes further toward the light emitting area PXA than the sidewall of the first partition wall layer L1 may be defined as a pointed portion of the partition wall PW.

[0134] The partition wall opening OP-P defined in the partition wall PW may include a first area A1 as a first thickness portion (or a lower volume portion) and a second area A2 as a second thickness portion (or an upper volume portion). The first partition wall layer L1 may include a first inner surface S-L1 at which the first area A1 of the partition wall opening OP-P is defined, and the second partition wall layer L2 may include a second inner surface S-L2 at which the second area A2 is defined.

[0135] In cross section, due to the undercut structure of the bank layer at the light emitting region PXA, the second inner surface S-L2 of the second partition wall layer L2 may be closer to the center of the anode AE ​​than the first inner surface S-L1 of the first partition wall layer L1. The first inner surface S-L1 may be recessed relative to the second inner surface S-L2 in a direction away from the center of the anode AE. Therefore, the second partition wall layer L2 protruding toward the light emitting region PXA may include or define a pointed portion.

[0136] In a direction along the circuit element layer DP-CL, such as in a direction along the first direction DR1 and / or the second direction DR2, the width of the first area A1 may be different from the width of the second area A2. The width of the first area A1 may be greater than the width of the second area A2. In this case, the second area A2 of the partition wall opening OP-P may be an area defining a tip portion.

[0137] The first partition wall layer L1 and the second partition wall layer L2 may each include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0138] Figure 6 The first inner surface S-L1 and the second inner surface S-L2 are exemplarily shown to be perpendicular to the upper surface of the pixel definition layer PDL, but the embodiments of the present invention are not limited thereto. For example, the partition wall PW may have a tapered shape or an inverted tapered shape, in which case the inner surface of the partition wall PW may be inclined relative to the upper surface of the pixel definition layer.

[0139] The partition wall PW may receive the second driving voltage ELVSS (see Figure 4 ), and thus, the cathode CE may be electrically connected to the partition wall PW to receive the second driving voltage ELVSS (see Figure 4 ).

[0140] The dummy area DMA may be formed on the partition wall PW. In particular, the dummy area DMA may be formed between the partition wall PW and the lower inorganic encapsulation pattern LIL in cross section. The dummy area DMA may be defined as a first dummy layer DMP1-I, a second dummy layer DMP2-I, and a third dummy layer DMP3-I formed and removed during a method of providing a display panel DP to be described later (see Fig.8F , Fig. 9A or Fig. 10A ) area.

[0141] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE as an encapsulation layer may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0142] The lower inorganic encapsulation pattern LIL may correspond to the light emitting opening OP-E. The lower inorganic encapsulation pattern LIL may be disposed on the cathode CE. In particular, a portion of the lower inorganic encapsulation pattern LIL may be formed in the partition wall opening OP-P, and another portion of the lower inorganic encapsulation pattern LIL may be formed on the partition wall PW. That is, the lower inorganic encapsulation pattern LIL in the partition wall opening OP-P may extend from the partition wall opening OP-P and extend along the upper surface of the partition wall PW.

[0143] The organic encapsulation film OL may cover the lower inorganic encapsulation pattern LIL and provide a flat upper surface. A portion of the organic encapsulation film OL may extend into a gap between an upper surface of the partition wall PW and a lower surface of the lower inorganic encapsulation pattern LIL spaced apart from the partition wall PW to fill the dummy area DMA. An upper inorganic encapsulation film UIL may be disposed on the organic encapsulation film OL.

[0144] The lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0145] Figure 7 is along Figure 5 A cross-sectional view taken along line II-II'. Figure 7 is an enlarged view showing a first light emitting area PXA-B, a second light emitting area PXA-G and a third light emitting area PXA-R, and refers to Figure 6 The description of the luminous area PXA can be applied to Figure 7 Each of the first light emitting area PXA-B, the second light emitting area PXA-G and the third light emitting area PXA-R in.

[0146] refer to Figure 7The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, and a partition wall PW.

[0147] The light emitting elements ED1, ED2 and ED3 may include a first light emitting element ED1, a second light emitting element ED2 and a third light emitting element ED3. The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1 and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2 and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3 and a third cathode CE3. The first anode AE1, the second anode AE2 and the third anode AE3 may be arranged in a variety of patterns. In an embodiment, the first light emitting pattern EP1 may provide blue light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide red light.

[0148] The first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E may be defined in the pixel defining film PDL. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0149] In this embodiment, the first light emitting region PXA-B may be defined as a region of the upper surface of the first anode AE1 exposed by the first light emitting opening OP1-E. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second light emitting opening OP2-E. The third light emitting region PXA-R may be defined as a region of the upper surface of the third anode AE3 exposed by the third light emitting opening OP3-E.

[0150] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be disposed on upper surfaces of the first anode AE1, the second anode AE2, and the third anode AE3, respectively. The first sacrificial pattern opening OP1-S, the second sacrificial pattern opening OP2-S, and the third sacrificial pattern opening OP3-S respectively overlapping the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E may be defined in the first sacrificial pattern SP1, the third sacrificial pattern SP2, and the third sacrificial pattern SP3, respectively.

[0151] In this embodiment, the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P, which overlap the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the partition wall PW. The first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P may each include the previously referenced Figure 6 The first area A1 described (see Figure 6 ) and the second area A2 (see Figure 6 ). The first partition wall layer L1 may include a first inner side surface S-L1 of a first area A1 defining a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P (see Figure 6 ), and the second partition wall layer L2 may include a second inner side surface S-L2 of the second area A2 defining the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P (see Figure 6 ).

[0152] The first light emitting pattern EP1 and the first cathode CE1 may be disposed in the first partition wall opening OP1-P, the second light emitting pattern EP2 and the second cathode CE2 may be disposed in the second partition wall opening OP2-P, and the third light emitting pattern EP3 and the third cathode CE3 may be disposed in the third partition wall opening OP3-P.

[0153] In this embodiment, the material layers of the first light-emitting pattern EP1, the second light-emitting pattern EP2 and the third light-emitting pattern EP3 and the material layers of the first cathode CE1, the second cathode CE2 and the third cathode CE3 can be physically separated by the second partition wall layer L2 forming a pointed portion, so that the first light-emitting pattern EP1, the second light-emitting pattern EP2 and the third light-emitting pattern EP3 and the first cathode CE1, the second cathode CE2 and the third cathode CE3 can be formed as patterns in the light-emitting openings OP1-E, OP2-E and OP3-E, respectively, or as patterns in the partition wall openings OP1-P, OP2-P and OP3-P.

[0154] According to an embodiment of the present invention, a plurality of first light emitting patterns EP1 may be deposited by patterning on a pixel-by-pixel basis by a sharp portion defined on a partition wall PW that disconnects the light emitting material layer forming the light emitting pattern. That is, the first light emitting patterns EP1 may be formed together as a single material layer using an open mask, but may be easily divided by the partition wall PW in pixels PX.

[0155] On the other hand, in the case of patterning the first light emitting pattern EP1 using a fine metal mask (FMM), a support spacer protruding from a conventional conductive partition wall may be provided in order to support the fine metal mask. In addition, since the fine metal mask is spaced apart from the base surface on which patterning is performed by the height of the conventional partition wall and the spacer, there may be limitations in achieving high resolution of the formed pattern. In addition, since the fine metal mask is in contact with the spacer, foreign matter may remain on the spacer after the patterning process of the first light emitting pattern EP1, or the spacer may be damaged due to the imprinting of the fine metal mask. Therefore, a conventional display panel with defects may be formed.

[0156] According to this embodiment of the present invention, since the partition wall PW is included, the corresponding material layers of the light emitting elements ED1, ED2 and ED3 can be easily physically separated. Therefore, leakage current, driving errors, etc. that may occur between adjacent light emitting regions PXA-B, PXA-G and PXA-R can be reduced or effectively prevented, and independent operation of each of the light emitting elements ED1, ED2 and ED3 can be possible.

[0157] In particular, since the plurality of first light emitting patterns EP1 are not aligned with the display area DA (see Figure 1B ) is patterned without contacting the components inside, so the defect rate can be reduced, so that a display panel DP with improved process reliability can be provided. Since patterning of the material layer can be possible even without providing a separate supporting spacer protruding from the partition wall PW, the area of ​​the light-emitting areas PXA-B, PXA-G, and PXA-R can be miniaturized, thereby providing a display panel DP that facilitates high-resolution realization.

[0158] In addition, when manufacturing a large-area display panel DP, manufacturing a large-area mask can be omitted, thereby reducing process costs, and since the process may not be affected by defects that may occur on the large-area mask, a display panel DP with improved process reliability can be provided. The description of the plurality of first light emitting patterns EP1 can be similarly applied to the plurality of second light emitting patterns EP2 and the third light emitting patterns EP3.

[0159] The thin film encapsulation layer TFE may include lower inorganic encapsulation patterns LIL1 , LIL2 , and LIL3 , an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0160] In this embodiment, the lower inorganic encapsulation patterns LIL1, LIL2 and LIL3 may include a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2 and a third lower inorganic encapsulation pattern LIL3. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2 and the third lower inorganic encapsulation pattern LIL3 may overlap with the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E, respectively. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2 and the third lower inorganic encapsulation pattern LIL3 may be arranged in the form of a pattern spaced apart from each other.

[0161] The first lower inorganic encapsulation pattern LIL1 may cover the first light emitting element ED1. A portion of the first lower inorganic encapsulation pattern LIL1 may be formed in the first partition wall opening OP1-P, and another portion of the first lower inorganic encapsulation pattern LIL1 may be formed on an upper surface of the partition wall PW extending from a side wall of the partition wall PW defining the first partition wall opening OP1-P. In a cross section, the first dummy area DMA1 may be formed as a first gap between the first lower inorganic encapsulation pattern LIL1 and the partition wall PW defining the first partition wall opening OP1-P.

[0162] The second lower inorganic encapsulation pattern LIL2 may cover the second light emitting element ED2. A portion of the second lower inorganic encapsulation pattern LIL2 may be formed in the second partition wall opening OP2-P, and another portion of the second lower inorganic encapsulation pattern LIL2 may be formed on an upper surface of the partition wall PW extending from a side wall of the partition wall PW defining the second partition wall opening OP2-P. In cross section, the second virtual area DMA2 may be formed as a second gap between the second lower inorganic encapsulation pattern LIL2 and the partition wall PW defining the second partition wall opening OP2-P.

[0163] The third lower inorganic encapsulation pattern LIL3 may cover the third light emitting element ED3. A portion of the third lower inorganic encapsulation pattern LIL3 may be formed in the third partition wall opening OP3-P, and another portion of the third lower inorganic encapsulation pattern LIL3 may be formed on an upper surface of the partition wall PW extending from a side wall of the partition wall PW defining the third partition wall opening OP3-P. In cross section, the third virtual area DMA3 may be formed as a third gap between the third lower inorganic encapsulation pattern LIL3 and the partition wall PW defining the third partition wall opening OP3-P.

[0164] The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2, and the third lower inorganic encapsulation pattern LIL3 may be different in thickness from each other. The thickness of the corresponding lower inorganic encapsulation pattern may be defined in a direction perpendicular to the surface along which the corresponding lower inorganic encapsulation pattern is defined. Figure 7, for example, the thickness may be defined not only along the third direction DR3 but also along a horizontal direction (eg, the first direction DR1 and / or the second direction DR2).

[0165] The thickness TT1 of the first lower inorganic encapsulation pattern LIL1 may be less than the thickness TT2 of the second lower inorganic encapsulation pattern LIL2, and the thickness TT3 of the third lower inorganic encapsulation pattern LIL3 may be equal to or greater than the thickness TT2 of the second lower inorganic encapsulation pattern LIL2. For example, the thickness TT1 of the first lower inorganic encapsulation pattern LIL1 may be about 0.2 micrometers (μm) to about 1.0 μm, the thickness TT2 of the second lower inorganic encapsulation pattern LIL2 may be about 1.0 μm to about 1.5 micrometers (μm), and the thickness TT3 of the third lower inorganic encapsulation pattern LIL3 may be about 1.0 μm to about 1.7 μm.

[0166] The height of the gap at the corresponding virtual area can be defined along the third direction DR3. The corresponding height can be the minimum distance between the facing surfaces. The facing surfaces can be defined by the upper surface of the partition wall PW at the second partition wall layer L2 and the lower surface of the lower inorganic encapsulation pattern LIL at its extended portion. The extended portion of the lower inorganic encapsulation pattern LIL of the corresponding light-emitting area can extend from the light-emitting area and in a direction toward the adjacent light-emitting area. The gap is opened in a direction away from the corresponding light-emitting area by being spaced apart from the uppermost surface of the partition wall PW by the extended portion.

[0167] During a process of providing the display panel DP described later, a height H1 of the first dummy area DMA1 may correspond to a height H1 of the first dummy layer DMP1-I (see Fig.8F ), and the thickness of the first dummy layer DMP1-I may correspond to the sum of the thicknesses of the first light emitting pattern EP1 and the first cathode CE1. During a process of providing the display panel DP described later, the height H2 of the second dummy area DMA2 may correspond to the second dummy layer DMP2-I (see Fig. 9A ), and the thickness of the second dummy layer DMP2-I may correspond to the sum of the thicknesses of the second light emitting pattern EP2 and the second cathode CE2. During a process of providing the display panel DP described later, the height H3 of the third dummy area DMA3 may correspond to the third dummy layer DMP3-I (see Fig. 10A ), and the thickness of the third virtual layer DMP3-I may correspond to the sum of the thicknesses of the third light emitting pattern EP3 and the third cathode CE3. That is, the height of the gap adjacent to the corresponding light emitting area is directly related to the thickness of the light emitting pattern in the corresponding light emitting area.

[0168] The thicknesses of the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 may be different from each other. Similar to the above description, the thickness of the corresponding light emitting pattern may be defined in a direction perpendicular to the surface along which the corresponding pattern is defined. For example, the thickness of the first light emitting pattern EP1 may be less than the thickness of the second light emitting pattern EP2, and the thickness of the third light emitting pattern EP3 may be greater than the thickness of the second light emitting pattern EP2. Therefore, due to the different thicknesses of the light emitting patterns, while the thickness of the cathode electrode may be substantially the same, the corresponding heights H1, H2, and H3 of the first virtual area DMA1, the second virtual area DMA2, and the third virtual area DMA3 may be different from each other. For example, the height H1 of the first virtual area DMA1 may be less than the height H2 of the second virtual area DMA2, and the height H3 of the third virtual area DMA3 may be greater than the height H2 of the second virtual area DMA2.

[0169] FIG. 8A to FIG. 11 1 is a cross-sectional view showing a process and a structure of an operation of a method of manufacturing (or providing) a display panel DP according to an embodiment of the present invention. FIG. 8A to FIG. 11 When describing, Figure 7 The same / similar components in the drawings will be denoted by the same / similar reference numerals or symbols, and repeated description thereof will be omitted.

[0170] According to an embodiment of the present invention, a method for manufacturing (or providing) a display panel DP may include providing a preliminary display panel DP-I including a base layer BL, a pixel defining film PDL disposed on the base layer BL, a first preliminary partition wall layer L1-I disposed on the pixel defining film PDL, and a second preliminary partition wall layer L2-I disposed on the first preliminary partition wall layer L1-I; etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I to form a partition wall PW defining a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P therein; forming a first light-emitting element ED1 in the first partition wall opening OP1-P; forming a first lower inorganic encapsulation pattern LIL1 covering the first light-emitting element ED1; forming a second light-emitting element ED2 in the second partition wall opening OP2-P; forming a second lower inorganic encapsulation pattern LIL2 covering the second light-emitting element ED2; forming a third light-emitting element ED3 in the third partition wall opening OP3-P; forming a third lower inorganic encapsulation pattern LIL3 covering the third light-emitting element ED3.

[0171] In the following, reference FIG. 8A to FIG. 8I The formation of the first light emitting element ED1 and the formation of the first lower inorganic encapsulation pattern LIL1 covering the first light emitting element ED1 are described, and reference is made to 9A to 9DThe formation of the second light emitting element ED2 and the formation of the second lower inorganic encapsulation pattern LIL2 covering the second light emitting element ED2 are described. FIG. 10A to FIG. 10D The formation of the third light emitting element ED3 and the formation of the third lower inorganic encapsulation pattern LIL3 covering the third light emitting element ED3 are described, and reference is made to Fig.11 The formation of the organic encapsulation film OL and the upper inorganic encapsulation film UIL is described. FIG. 8A to FIG. 11 The display panel DP provided (or formed) by the operation shown in Figure 7 The display panel DP in.

[0172] Reference Fig. 8A , the method for providing a display panel DP according to an embodiment of the present invention may include providing a preliminary display panel DP-I. The preliminary display panel DP-I provided according to the present embodiment may include a base layer BL, a circuit element layer DP-CL, a first anode AE1, a second anode AE2, and a third anode AE3, a first sacrificial layer SP1-I, a second sacrificial layer SP2-I, and a third sacrificial layer SP3-I, a pixel defining film PDL, a first preliminary partition wall layer L1-I, and a second preliminary partition wall layer L2-I.

[0173] The circuit element layer DP-CL can be formed by a conventional circuit element manufacturing process, wherein the insulating layer, the semiconductor layer and the conductive layer are formed by coating, deposition, etc., and the insulating layer, the semiconductor layer and the conductive layer are selectively patterned by photolithography and etching processes to form semiconductor patterns, conductive patterns, signal lines, etc.

[0174] The first anode AE1 and the first sacrificial layer SP1-I may be formed by the same patterning process, the second anode AE2 and the second sacrificial layer SP2-I may be formed by the same patterning process, and the third anode AE3 and the third sacrificial layer SP3-I may be formed by the same patterning process. Here, the ends or end surfaces of the corresponding anodes and sacrificial layers may be aligned with each other (such as coplanar), but are not limited thereto.

[0175] The pixel defining layer PDL may be disposed on the base layer BL. The pixel defining layer PDL as a pixel defining layer may cover all of the first, second, and third anodes AE1, AE2, and AE3 and all of the first, second, and third sacrificial layers SP1-I, SP2-I, and SP3-I.

[0176] The first preliminary partition wall layer L1-I may be disposed on the pixel definition film PDL. The first preliminary partition wall layer L1-I may be formed by a deposition process of a conductive material. The second preliminary partition wall layer L2-I may be disposed on the first preliminary partition wall layer L1-I. The second preliminary partition wall layer L2-I may also be formed by a deposition process of a conductive material. In the present embodiment, the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may each contain a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO) or aluminum zinc oxide. However, the materials of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are not limited thereto. The first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may form a preliminary partition wall PW-I.

[0177] refer to Figure 8B According to an embodiment of the present invention, a method for providing a display panel DP may include forming a first photoresist layer PR1 on a preliminary partition wall PW-I. After forming the preliminary photoresist layer on the preliminary partition wall PW-I, the preliminary photoresist layer is patterned using a photomask to form the first photoresist layer PR1. Through the patterning process, a continuous portion of the first photoresist layer PR1 defines therein a first light opening OP1-PR overlapping the first anode AE1, a second light opening OP2-PR overlapping the second anode AE2, and a third light opening OP3-PR overlapping the third anode AE3.

[0178] refer to Figure 8C and Fig.8D According to an embodiment of the present invention, a method for providing a display panel DP may include etching a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I using a first photoresist layer PR1 as a mask to form a partition wall PW defining a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P therein, so that the preliminary partition wall PW-I (see Figure 8B ) to form a partition wall PW. Here, an opening portion (e.g., a thickness portion) of the partition wall PW may be defined at the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, respectively, and the opening portions corresponding to the corresponding anodes may together form one partition wall opening (or bank opening).

[0179] like Figure 8CAs shown in , performing a first etching on the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include using the first photoresist layer PR1 as a mask and performing dry etching on the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I to form preliminary partition wall openings OP1-PI, OP2-PI, and OP3-PI in the preliminary partition wall PW-I. The preliminary partition wall openings OP1-PI, OP2-PI, and OP3-PI may include a first preliminary partition wall opening OP1-PI, a second preliminary partition wall opening OP2-PI, and a third preliminary partition wall opening OP3-PI. The first preliminary partition wall opening OP1-PI may be formed overlapping with the first anode AE1, the second preliminary partition wall opening OP2-PI may be formed overlapping with the second anode AE2, and the third preliminary partition wall opening OP3-PI may be formed overlapping with the third anode AE3.

[0180] The first etching (e.g., dry etching) process according to the present embodiment can be performed under etching conditions where the etching selectivity between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is substantially the same. Therefore, the inner side surface of the first preliminary partition wall layer L1-I that defines the preliminary partition wall openings OP1-PI, OP2-PI, and OP3-PI, respectively, and the corresponding inner side surface of the second preliminary partition wall layer L2-I can be substantially aligned. When aligned, the inner side surfaces can be coplanar with each other.

[0181] like Fig.8D As shown in FIG. 1 , the first preliminary partition wall layer L1-I (see Figure 8C ) performing the second etching may include using the first photoresist layer PR1 as a mask and wet etching the first preliminary partition wall layer L1-I at each preliminary partition wall opening to form a plurality of first preliminary partition wall openings OP1-PI, OP2-PI, and OP3-PI, respectively (see Figure 8C ) form partition wall openings OP1-P, OP2-P, and OP3-P. The partition wall openings OP1-P, OP2-P, and OP3-P may include a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P. The first partition wall opening OP1-P may be formed overlapping with the first anode AE1, the second partition wall opening OP2-P may be formed overlapping with the second anode AE2, and the third partition wall opening OP3-P may be formed overlapping with the third anode AE3.

[0182] The partition wall openings OP1-P, OP2-P, and OP3-P may each include a first region A1 (e.g., a lower volume) and a second region A2 (e.g., an upper volume) sequentially formed in the thickness direction (i.e., the third direction DR3). The first partition wall layer L1 may include a first inner side surface S-L1 defining the first region A1 of each of the partition wall openings OP1-P, OP2-P, and OP3-P, and the second partition wall layer L2 may include a second inner side surface S-L2 defining the second region A2.

[0183] The second etching (e.g., wet etching) process according to the present embodiment can be performed under the condition that the difference in etching selectivity between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is large. Therefore, the inner surface of the partition wall PW defining the partition wall openings OP1-P, OP2-P, and OP3-P can have an undercut shape in cross section. In particular, since the etching rate of the first partition wall layer L1 is greater than the etching rate of the second partition wall layer L2 for the etching solution, the first partition wall layer L1 can be mainly etched more than the second partition wall layer L2. Therefore, the first inner surface S-L1 of the first partition wall layer L1 can be recessed inward from the second inner surface S-L2 of the second partition wall layer L2 to provide an undercut structure. The pointed portion of the partition wall PW can be formed by a portion of the second partition wall layer L2 that protrudes further than the first partition wall layer L1.

[0184] At the partition wall openings OP1 -P, OP2 -P, and OP3 -P of the partition wall PW having an undercut shape, the pixel defining film PDL is exposed to the outside of the partition wall PW.

[0185] refer to Fig. 8E According to an embodiment of the present invention, a method for providing a display panel DP may include etching a pixel definition film PDL exposed at the partition wall openings OP1-P, OP2-P, and OP3-P, and etching a first sacrificial layer SP1-I, a second sacrificial layer SP2-I, and a third sacrificial layer SP3-I subsequently exposed at the partition wall openings OP1-P, OP2-P, and OP3-P after etching the pixel definition film PDL (see Fig.8D ). The etching process of the pixel defining film PDL may be performed by dry etching using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as a mask. The first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E corresponding to the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P, respectively, may be formed in the pixel defining film PDL through the sidewall or inner surface of the pixel defining film PDL.

[0186] The first light emitting opening OP1 -E may overlap with the first partition wall opening OP1 -P, the second light emitting opening OP2 -E may overlap with the second partition wall opening OP2 -P, and the third light emitting opening OP3 -E may overlap with the third partition wall opening OP3 -P.

[0187] The etching process of the sacrificial layers SP1-I, SP2-I, and SP3-I may be performed by wet etching using the first photoresist layer PR1 and the partition wall PW (e.g., the second partition wall layer L2) as a mask. Sacrificial pattern openings OP1-S, OP2-S, and OP3-S respectively overlapping with the light-emitting openings OP1-E, OP2-E, and OP3-E may be formed in the sacrificial patterns SP1, SP2, and SP3 formed by etching the sacrificial layers SP1-I, SP2-I, and SP3-I. The sacrificial pattern openings OP1-S, OP2-S, and OP3-S may include a first sacrificial pattern opening OP1-S overlapping with the first light-emitting opening OP1-E, a second sacrificial pattern opening OP2-S overlapping with the second light-emitting opening OP2-E, and a third sacrificial pattern opening OP3-S overlapping with the third light-emitting opening OP3-E. At least a portion of the anodes AE1, AE2, and AE3 may be exposed to the outside of the sacrificial patterns SP1, SP2, and SP3, respectively, and to the outside of the pixel defining film PDL through the sacrificial pattern openings OP1-S, OP2-S, and OP3-S, and to the outside of the partition wall PW through the light emitting openings OP1-E, OP2-E, and OP3-E.

[0188] The etching process of the sacrificial patterns SP1, SP2, and SP3 may be performed under the condition that the difference in etching selectivity between the preliminary sacrificial layers SP1-I, SP2-I, and SP3-I and the anodes AE1, AE2, and AE3 is large, thereby preventing the anodes AE1, AE2, and AE3 from being etched together with the etching of the preliminary sacrificial layers SP1-I, SP2-I, and SP3-I. That is, since the preliminary sacrificial layers SP1-I, SP2-I, and SP3-I having a higher etching rate than the anodes AE1, AE2, and AE3 are disposed between the pixel defining film PDL and the anodes AE1, AE2, and AE3, the anodes AE1, AE2, and AE3 may be prevented from being etched together and damaged during the etching process.

[0189] refer to Fig.8F According to an embodiment of the present invention, the method for providing a display panel DP may include removing the first photoresist layer PR1 (see Fig. 8E) and then forming a first light emitting element ED1 in the first partition wall opening OP1-P. Forming the first light emitting element ED1 in the first partition wall opening OP1-P may include forming a first light emitting pattern EP1 and forming a first cathode CE1. In addition, forming the first light emitting element ED1 in the first partition wall opening OP1-P may include forming a first dummy layer DMP1-I inside the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW.

[0190] Forming the first light emitting pattern EP1 may include a deposition process of the first light emitting layer. In an embodiment, the deposition process of the first light emitting layer may be a thermal evaporation process. However, this is an example, and the deposition process of the first light emitting layer is not limited to the above example. The first light emitting layer may be separated by a sharp portion formed on the partition wall PW to form the first light emitting pattern EP1 and the (1-1)th virtual layer D11-I. The first light emitting pattern EP1 may be formed on the first anode AE1 in the first light emitting opening OP1-E and the first partition wall opening OP1-P. A portion of the (1-1)th virtual layer D11-I may be formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P (or the second light emitting opening OP2-E and the third light emitting opening OP3-E), and another portion of the (1-1)th virtual layer D11-I may be formed on the partition wall PW.

[0191] That is, when forming the first light emitting pattern EP1, a (1-1)th virtual layer D11-I spaced apart from the first light emitting pattern EP1 may also be formed. The (1-1)th virtual layer D11-I may include an organic material. For example, the (1-1)th virtual layer D11-I may include the same material as the first light emitting pattern EP1. The (1-1)th virtual layer D11-I may be formed simultaneously with the first light emitting pattern EP1 through one process, and may be formed separately from the first light emitting pattern EP1 due to the undercut shape of the partition wall PW. That is, the first light emitting pattern EP1 and the (1-1)th virtual layer D11-I may be in the same layer as each other, such as by being corresponding patterns of the same material layer (for example, a first light emitting layer as a first light emitting material layer).

[0192] Forming the first cathode CE1 may include a deposition process for a first cathode layer. In an embodiment, the deposition process for the first cathode layer may be a sputtering process. However, this is an example, and the deposition process for the first cathode layer is not limited to the above example. The first cathode layer may be separated by a sharp portion formed on the partition wall PW to form the first cathode CE1 and the (2-1)th virtual layer D21-I. The first cathode CE1 may be formed on the first light emitting pattern EP1 in the first light emitting opening OP1-E and the first partition wall opening OP1-P. A portion of the (2-1)th virtual layer D21-I may be formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P (or the second light emitting opening OP2-E and the third light emitting opening OP3-E), and another portion of the (2-1)th virtual layer D21-I may be formed on the partition wall PW.

[0193] That is, when forming the first cathode CE1, a (2-1)th virtual layer D21-I spaced apart from the first cathode CE1 may also be formed. The (2-1)th virtual layer D21-I may include a conductive material. For example, the (2-1)th virtual layer D21-I may include the same material as that of the first cathode CE1. The (2-1)th virtual layer D21-I may be formed simultaneously with the first cathode CE1 through one process, and may be formed separately from the first cathode CE1 due to the undercut shape of the partition wall PW. That is, the first cathode CE1 and the (2-1)th virtual layer D21-I may be in the same layer as each other, such as by corresponding patterns being the same material layer (e.g., a first cathode layer being a first cathode material layer).

[0194] The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may be sequentially stacked along the third direction DR3. The first anode AE1, the first light emitting pattern EP1, and the first cathode CE1 may form a first light emitting element ED1.

[0195] The (1-1)th virtual layer D11-I and the (2-1)th virtual layer D21-I may be stacked in sequence along the third direction DR3. The (1-1)th virtual layer D11-I and the (2-1)th virtual layer D21-I may form a first virtual layer DMP1-I, and a virtual opening may be formed in the first virtual layer DMP1-I. Here, providing the first light emitting element ED1 in the first partition wall opening OP1-P includes providing a first material layer of the first light emitting element ED1, the first material layer of the first light emitting element ED1 including: a first material layer pattern (EP1 and / or CE1) in the first partition wall opening OP1-P; and a first virtual layer (D11-I and / or D21-I) of the first material layer inside the second partition wall opening OP2-P, inside the third partition wall opening OP3-P and on the partition wall PW.

[0196] According to an embodiment of the present invention, the method for providing a display panel DP may include forming a capping pattern (not shown). For example, forming the capping pattern may include forming a capping pattern layer on the Fig.8F The deposition process on the stacked structure of the capping pattern layer may be a thermal evaporation process. The capping pattern layer may be separated by a sharp portion formed on the partition wall PW to form a capping pattern and a (3-1)th virtual layer. The capping pattern may be formed on the first cathode CE1 in the first partition wall opening OP1-P. A portion of the (3-1)th virtual layer may be formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P, and another portion of the (3-1)th virtual layer may be formed on the partition wall PW.

[0197] That is, when forming the capping pattern, a (3-1)th virtual layer spaced apart from the capping pattern may also be formed. The (3-1)th virtual layer may include a conductive material. For example, the (3-1)th virtual layer may include the same material as the capping pattern. The (3-1)th virtual layer may be formed simultaneously with the capping pattern through a process, and may be formed separately from the capping pattern due to the undercut shape of the partition wall PW. In this case, the first virtual layer DMP1-I may include the (1-1)th virtual layer D11-I, the (2-1)th virtual layer D21-I, and the (3-1)th virtual layer.

[0198] refer to FIG. 8G to FIG. 8I , the method for providing a display panel DP according to an embodiment of the present invention may include forming a first lower inorganic encapsulation pattern LIL1 covering the first light emitting element ED1. Forming the first lower inorganic encapsulation pattern LIL1 may include depositing a first lower inorganic encapsulation layer LIL1-I, removing a portion of the first lower inorganic encapsulation layer LIL1-I that does not overlap the first light emitting element ED1, and removing the first dummy layer DMP1-I to form a first dummy area DMA1.

[0199] refer to Figure 8G , forming the first lower inorganic encapsulation pattern LIL1 may include depositing a first lower inorganic encapsulation layer LIL1-I. The first lower inorganic encapsulation layer LIL1-I may be formed by a deposition process. In an embodiment, the first lower inorganic encapsulation layer LIL1-I may be formed by a chemical vapor deposition (CVD) process. The first lower inorganic encapsulation layer LIL1-I may be formed to cover the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P and the partition wall PW and have a thickness TT1 of about 0.2 μm to about 1.0 μm.

[0200] refer to Figure 8H, forming the first lower inorganic encapsulation pattern LIL1 may include forming a second photoresist layer PR2 corresponding to the first light emitting element ED1 and removing a portion of the first lower inorganic encapsulation layer LIL1-I that does not overlap the first light emitting element ED1.

[0201] When forming the second photoresist layer PR2, after forming the preliminary photoresist layer, the preliminary photoresist layer can be patterned by using a photomask to form the second photoresist layer PR2. Through the patterning process, the second photoresist layer PR2 can be formed into a pattern corresponding to the first light-emitting element ED1. Here, the second photoresist layer PR2 corresponds to the first light-emitting element ED1 by being arranged at the first partition wall opening OP1-P and the region adjacent to the first partition wall opening OP1-P along the upper surface of the partition wall PW.

[0202] When removing the portion of the first lower inorganic encapsulation layer LIL1-I that does not overlap with the first light-emitting element ED1 (for example, except for the area corresponding to the first light-emitting element ED1 as described above), the first lower inorganic encapsulation layer LIL1-I may be patterned by dry etching using the second photoresist layer PR2 as a mask, thereby removing the portion of the first lower inorganic encapsulation layer LIL1-I that does not overlap with the first light-emitting element ED1. The first lower inorganic encapsulation pattern LIL1 that overlaps with the first light-emitting element ED1 (for example, at the first partition wall opening OP1-P and the area adjacent to the first partition wall opening OP1-P) may be formed by the patterned first lower inorganic encapsulation layer LIL1-I. The first lower inorganic encapsulation pattern LIL1 may be the remaining portion of the first lower inorganic encapsulation layer LIL1-I.

[0203] Since the first lower inorganic encapsulation layer LIL1-I has a small thickness TT1 (e.g., about 0.2 μm to about 1.0 μm), the process time for dry etching can be minimized. Therefore, when patterning is performed to remove the portion of the first lower inorganic encapsulation layer LIL1-I that does not overlap with the first light-emitting element ED1, over-etching occurring in the area to be removed can be reduced or eliminated.

[0204] refer to Figure 8I , forming the first lower inorganic encapsulation pattern LIL1 may include removing the first dummy layer DMP1-I (see Figure 8H ) to form a first virtual area DMA1.

[0205] The (2-1)th dummy layer D21-I of the first dummy layer DMP1-I formed inside the second partition wall opening OP2-P and the third partition wall opening OP3-P and on the partition wall PW may be removed by performing wet etching to expose the first dummy layer DMP1-I, and the exposed (1-1)th dummy layer D11-I of the first dummy layer DMP1-I may be removed by using a stripper. Thereafter, the second photoresist layer PR2 (see Figure 8H ). That is, we can Figure 8H Remove from the stacking structure Figure 8H The entire first virtual layer DMP1-I in.

[0206] By removing the first dummy layer DMP1-I, the first dummy area DMA1 may be formed as a gap between an extension portion of the first lower inorganic encapsulation pattern LIL1 and an upper surface of the partition wall PW facing the extension portion adjacent to the first partition wall opening OP1-P. A height H1 of the gap at the first dummy area DMA1 may correspond to the height H2 of the first dummy layer DMP1-I (see Fig.8F ), that is, the sum of the thicknesses of the (2-1)th virtual layer D21-I and the (1-1)th virtual layer D11-I. Here, the total thickness of the first virtual layer DMP1-I may correspond to the sum of the thicknesses of the first light emitting pattern EP1 in the same layer (and having the same thickness) as the (1-1)th virtual layer D11-I and the first cathode CE1 in the same layer (and having the same thickness) as the (2-1)th virtual layer D21-I.

[0207] By Figure 8H The entire first dummy layer DMP1-I is removed from the stacked structure, various anode electrodes, sacrificial patterns, continuous portions of the pixel defining film, and continuous portions of the partition wall PW are exposed at the light emitting area PXA except for the light emitting area PXA to which the first light emitting element ED1 corresponds.

[0208] refer to Fig. 9A , the method for providing a display panel DP according to an embodiment of the present invention may include forming a second light emitting element ED2 in the second partition wall opening OP2-P. Forming the second light emitting element ED2 in the second partition wall opening OP2-P may include forming a second light emitting pattern EP2 and forming a second cathode CE2. In addition, forming the second light emitting element ED2 in the second partition wall opening OP2-P may include forming a second dummy layer DMP2-I inside the first partition wall opening OP1-P and the third partition wall opening OP3-P and on the partition wall PW.

[0209] Forming the second light emitting pattern EP2 may include a deposition process for a second light emitting layer. In an embodiment, the deposition process for the second light emitting layer may be a thermal evaporation process. However, this is an example, and the deposition process for the second light emitting layer is not limited to the above-mentioned example. The second light emitting layer may be separated by a sharp portion formed on the partition wall PW to form a second light emitting pattern EP2 and a (1-2) virtual layer D12-I. The second light emitting pattern EP2 may be formed on the second anode AE2 in the second light emitting opening OP2-E and the second partition wall opening OP2-P. A portion of the (1-2) virtual layer D12-I may be formed inside the first partition wall opening OP1-P and the third partition wall opening OP3-P (or the first light emitting opening OP1-E and the third light emitting opening OP3-E), and another portion of the (1-2) virtual layer D12-I may be formed on the partition wall PW.

[0210] That is, when forming the second light emitting pattern EP2, the (1-2)th virtual layer D12-I spaced apart from the second light emitting pattern EP2 may also be formed. The (1-2)th virtual layer D12-I may include an organic material. For example, the (1-2)th virtual layer D12-I may include the same material as that of the second light emitting pattern EP2. The (1-2)th virtual layer D12-I may be formed simultaneously with the second light emitting pattern EP2 through one process, and is formed separately from the second light emitting pattern EP2 due to the undercut shape of the partition wall PW.

[0211] Forming the second cathode CE2 may include a deposition process for a second cathode layer. In an embodiment, the deposition process for the second cathode layer may be a sputtering process. However, this is an example, and the deposition process for the second cathode layer is not limited to the above-mentioned example. The second cathode layer may be separated by a sharp portion formed on the partition wall PW to form the second cathode CE2 and the (2-2)th virtual layer D22-I. The second cathode CE2 may be formed on the second light emitting pattern EP2 in the second light emitting opening OP2-E and the second partition wall opening OP2-P. A portion of the (2-2)th virtual layer D22-I may be formed inside the first partition wall opening OP1-P and the third partition wall opening OP3-P (or the first light emitting opening OP1-E and the third light emitting opening OP3-E), and another portion of the (2-2)th virtual layer D22-I may be formed on the partition wall PW.

[0212] That is, when forming the second cathode CE2, a (2-2)th virtual layer D22-I spaced apart from the second cathode CE2 may also be formed. The (2-2)th virtual layer D22-I may include a conductive material. For example, the (2-2)th virtual layer D22-I may include the same material as that of the second cathode CE2. The (2-2)th virtual layer D22-I may be formed simultaneously with the second cathode CE2 through one process, and may be formed separately from the second cathode CE2 due to the undercut shape of the partition wall PW.

[0213] The second anode AE2, the second light emitting pattern EP2, and the second cathode CE2 may be sequentially stacked along the third direction DR3. The second anode AE2, the second light emitting pattern EP2, and the second cathode CE2 may form a second light emitting element ED2.

[0214] The (1-2)th virtual layer D12-I and the (2-2)th virtual layer D22-I may be stacked in sequence along the third direction DR3. The (1-2)th virtual layer D12-I and the (2-2)th virtual layer D22-I may form a second virtual layer DMP2-I, and a virtual opening may be formed in the second virtual layer DMP2-I. Here, providing a second light emitting element ED2 in the second partition wall opening OP2-P includes providing a second material layer of the second light emitting element ED2, the second material layer of the second light emitting element ED2 including: a second material layer pattern (EP2 and / or CE2) in the second partition wall opening OP2-P; and a second virtual layer (D12-I and / or D22-I) of the second material layer inside the first partition wall opening OP1-P, inside the third partition wall opening OP3-P and on the partition wall PW.

[0215] According to an embodiment of the present invention, similar to the method discussed above, for example, the method for providing a display panel DP may further include: Fig. 9A A capping pattern is formed on the stacked structure. Forming the capping pattern may include a deposition process of the capping pattern layer. The deposition process of the capping pattern layer may be a thermal evaporation process. The capping pattern layer may be separated by a sharp portion formed on the partition wall PW to form a capping pattern and a (3-2)th virtual layer. The capping pattern may be formed on the second cathode CE2 in the second partition wall opening OP2-P. A portion of the (3-2)th virtual layer may be formed inside the first partition wall opening OP1-P and the third partition wall opening OP3-P, and another portion of the (3-2)th virtual layer may be formed on the partition wall PW.

[0216] That is, when forming the capping pattern, a (3-2)th virtual layer spaced apart from the capping pattern may also be formed. The (3-2)th virtual layer may include a conductive material. For example, the (3-2)th virtual layer may include the same material as the capping pattern. The (3-2)th virtual layer may be formed simultaneously with the capping pattern through a process, and may be formed separately from the capping pattern due to the undercut shape of the partition wall PW. In this case, the second virtual layer DMP2-I may include the (1-2)th virtual layer D12-I, the (2-2)th virtual layer D22-I, and the (3-2)th virtual layer.

[0217] refer to FIG. 9B to FIG. 9D , the method for providing a display panel DP according to an embodiment of the present invention may include forming a second lower inorganic encapsulation pattern LIL2 covering the second light emitting element ED2. Forming the second lower inorganic encapsulation pattern LIL2 may include depositing a second lower inorganic encapsulation layer LIL2-I, removing a portion of the second lower inorganic encapsulation layer LIL2-I that does not overlap with the second light emitting element ED2, and removing the second dummy layer DMP2-I to form a second dummy area DMA2.

[0218] refer to Fig. 9B , forming the second lower inorganic encapsulation pattern LIL2 may include depositing a second lower inorganic encapsulation layer LIL2-I. The second lower inorganic encapsulation layer LIL2-I may be formed by a deposition process. In an embodiment, the second lower inorganic encapsulation layer LIL2-I may be formed by a chemical vapor deposition (CVD) process. The second lower inorganic encapsulation layer LIL2-I may be formed to cover the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P and the partition wall PW and have a thickness TT2 of about 1.0 μm to about 1.5 μm. That is, the thickness TT2 of the second lower inorganic encapsulation layer LIL2-I may be greater than the thickness TT1 of the first lower inorganic encapsulation layer LIL1-I.

[0219] Fig. 9B It is exemplarily shown that the second lower inorganic encapsulation layer LIL2-I is formed separately from the first dummy area DMA1, but the embodiments of the present invention are not limited thereto. For example, the second lower inorganic encapsulation layer LIL2-I may fill a portion of the first dummy area DMA1 or fill the entire first dummy area DMA1.

[0220] refer to Fig. 9C, forming the second lower inorganic encapsulation pattern LIL2 may include forming a third photoresist layer PR3, and removing a portion of the second lower inorganic encapsulation layer LIL2-I that does not overlap with the second light emitting element ED2. Here, the third photoresist layer PR3 corresponds to the second light emitting element ED2 by being disposed at the second partition wall opening OP2-P and a region adjacent to the second partition wall opening OP2-P along the upper surface of the partition wall PW.

[0221] When forming the third photoresist layer PR3, after forming the preliminary photoresist layer, the preliminary photoresist layer may be patterned using a photomask to form the third photoresist layer PR3. Through the patterning process, the third photoresist layer PR3 may be formed into a pattern corresponding to the second light emitting element ED2.

[0222] When removing the portion of the second lower inorganic encapsulation layer LIL2-I that does not overlap with the second light-emitting element ED2, the second lower inorganic encapsulation layer LIL2-I may be patterned by dry etching using the third photoresist layer PR3 as a mask, thereby removing the portion of the second lower inorganic encapsulation layer LIL2-I that does not overlap with the second light-emitting element ED2. The second lower inorganic encapsulation pattern LIL2 overlapping with the second light-emitting element ED2 may be formed by the patterned second lower inorganic encapsulation layer LIL2-I.

[0223] refer to Fig.9D , forming the second lower inorganic encapsulation pattern LIL2 may include removing the second dummy layer DMP2-I (see Fig. 9C ) to form a second virtual area DMA2.

[0224] The (2-2)th dummy layer D22-I of the second dummy layer DMP2-I formed inside the first partition wall opening OP1-P and the third partition wall opening OP3-P and on the partition wall PW may be removed by performing wet etching, and the (1-2)th dummy layer D12-I of the second dummy layer DMP2-I may be removed by using a stripper. Thereafter, the third photoresist layer PR3 (see Fig. 9C ). That is, we can Fig. 9C Remove from the stacking structure Fig. 9C The entire second virtual layer DMP2-I in.

[0225] By removing the second dummy layer DMP2-I, the second dummy area DMA2 may be formed as a gap between the second lower inorganic encapsulation pattern LIL2 and the partition wall PW defining the second partition wall opening OP2-P. The height H2 of the second dummy area DMA2 may correspond to the second dummy layer DMP2-I (see Fig. 9A ), and the thickness of the second dummy layer DMP2-I may correspond to the sum of the thicknesses of the second light emitting pattern EP2 and the second cathode CE2.

[0226] The gap at the virtual area is an inlet where a gas for etching flows. Fig. 9C and Fig.9D Since the height of the gap at the dummy area (or dummy layer) is large during the process in the method of providing the display panel DP, since the volume or space into which the gas for dry etching can flow is large, the inflow of the gas becomes easier, so that the etching speed becomes higher. For example, since the height H2 of the second dummy area DMA2 (or the second dummy layer DMP2-I) is greater than that of the first dummy area DMA1 (or the first dummy layer DMP1-I (see Figure 8H )) of the height H1, so as to remove the second lower inorganic encapsulation layer LIL2-I (see Fig. 9B ) that does not overlap with the second light emitting element ED2 may be etched at a higher speed than that for removing the first lower inorganic encapsulation layer LIL1-I (see Figure 8G ) of the portion that does not overlap with the first light emitting element ED1.

[0227] In the case of a larger etching rate at a larger height gap, over-etching may occur undesirably. According to an embodiment of the present invention, since the thickness TT2 of the second lower inorganic encapsulation layer LIL2-I etched at the larger height gap is greater than the thickness TT1 of the first lower inorganic encapsulation layer LIL1-I, the over-etching phenomenon occurring on the second lower inorganic encapsulation layer LIL2-I can be reduced or eliminated.

[0228] refer to Fig. 10A , the method for providing a display panel DP according to an embodiment of the present invention may include forming a third light emitting element ED3 in the third partition wall opening OP3-P. Forming the third light emitting element ED3 in the third partition wall opening OP3-P may include forming a third light emitting pattern EP3 and forming a third cathode CE3. In addition, forming the third light emitting element ED3 in the third partition wall opening OP3-P may include forming a third dummy layer DMP3-I inside the first partition wall opening OP1-P and the second partition wall opening OP2-P and on the partition wall PW.

[0229] Forming the third light emitting pattern EP3 may include a deposition process of a third light emitting layer. In an embodiment, the deposition process of the third light emitting layer may be a thermal evaporation process. However, this is an example, and the deposition process of the third light emitting layer is not limited to the above-mentioned example. The third light emitting layer may be separated by a sharp portion formed on the partition wall PW to form a third light emitting pattern EP3 and a (1-3)th virtual layer D13-I. The third light emitting pattern EP3 may be formed on the third anode AE3 in the third light emitting opening OP3-E and the third partition wall opening OP3-P. A portion of the (1-3)th virtual layer D13-I may be formed inside the first partition wall opening OP1-P and the second partition wall opening OP2-P (or the first light emitting opening OP1-E and the second light emitting opening OP2-E), and another portion of the (1-3)th virtual layer D13-I may be formed on the partition wall PW.

[0230] That is, when forming the third light emitting pattern EP3, a (1-3)th virtual layer D13-I spaced apart from the third light emitting pattern EP3 may also be formed. The (1-3)th virtual layer D13-I may include an organic material. For example, the (1-3)th virtual layer D13-I may include the same material as that of the third light emitting pattern EP3. The (1-3)th virtual layer D13-I may be formed simultaneously with the third light emitting pattern EP3 through one process, and may be formed separately from the third light emitting pattern EP3 due to the undercut shape of the partition wall PW.

[0231] Forming the third cathode CE3 may include a deposition process for a third cathode layer. In an embodiment, the deposition process for the third cathode layer may be a sputtering process. However, this is an example, and the deposition process for the third cathode layer is not limited to the above-mentioned example. The third cathode layer may be separated by a sharp portion formed on the partition wall PW to form the third cathode CE3 and the (2-3)th virtual layer D23-I. The third cathode CE3 may be formed on the third light emitting pattern EP3 in the third light emitting opening OP3-E and the third partition wall opening OP3-P. A portion of the (2-3)th virtual layer D23-I may be formed inside the first partition wall opening OP1-P and the second partition wall opening OP2-P (or the first light emitting opening OP1-E and the second light emitting opening OP2-E), and another portion of the (2-3)th virtual layer D23-I may be formed on the partition wall PW.

[0232] That is, when forming the third cathode CE3, a (2-3)th virtual layer D23-I spaced apart from the third cathode CE3 may also be formed. The (2-3)th virtual layer D23-I may include a conductive material. For example, the (2-3)th virtual layer D23-I may include the same material as that of the third cathode CE3. The (2-3)th virtual layer D23-I may be formed simultaneously with the third cathode CE3 through one process, and may be formed separately from the third cathode CE3 due to the undercut shape of the partition wall PW.

[0233] The third anode AE3, the third light emitting pattern EP3, and the third cathode CE3 may be sequentially stacked along the third direction DR3. The third anode AE3, the third light emitting pattern EP3, and the third cathode CE3 may form a third light emitting element ED3.

[0234] The (1-3)th virtual layer D13-I and the (2-3)th virtual layer D23-I may be stacked in sequence along the third direction DR3. The (1-3)th virtual layer D13-I and the (2-3)th virtual layer D23-I may form a third virtual layer DMP3-I, and a virtual opening may be formed in the third virtual layer DMP3-I. Here, providing a third light emitting element ED3 in the third partition wall opening OP3-P includes providing a third material layer of the third light emitting element ED3, and the third material layer of the third light emitting element ED3 includes: a third material layer pattern (EP3 and / or CE3), in the third partition wall opening OP3-P; and a third virtual layer (D13-I and / or D23-I) of the third material layer, inside the first partition wall opening OP1-P, inside the second partition wall opening OP2-P and on the partition wall PW.

[0235] According to an embodiment of the present invention, similar to the method discussed above, for example, the method for providing a display panel DP may further include: Fig. 10A A capping pattern is formed on the stacked structure. Forming the capping pattern may include a deposition process of the capping pattern layer. The deposition process of the capping pattern layer may be a thermal evaporation process. The capping pattern layer may be separated by a sharp portion formed on the partition wall PW to form a capping pattern and a (3-3)th virtual layer. The capping pattern may be formed on the third cathode CE3 in the third partition wall opening OP3-P. A portion of the (3-3)th virtual layer may be formed inside the first partition wall opening OP1-P and the second partition wall opening OP2-P, and another portion of the (3-3)th virtual layer may be formed on the partition wall PW.

[0236] That is, when forming the capping pattern, a (3-3)th virtual layer spaced apart from the capping pattern may also be formed. The (3-3)th virtual layer may include a conductive material. For example, the (3-3)th virtual layer may include the same material as the capping pattern. The (3-3)th virtual layer may be formed simultaneously with the capping pattern through a process, and may be formed separately from the capping pattern due to the undercut shape of the partition wall PW. In this case, the third virtual layer DMP3-I may include the (1-3)th virtual layer D13-I, the (2-3)th virtual layer D23-I, and the (3-3)th virtual layer.

[0237] refer to FIG. 10B to FIG. 10D , the method for providing a display panel DP according to an embodiment of the present invention may include forming a third lower inorganic encapsulation pattern LIL3 covering the third light emitting element ED3. Forming the third lower inorganic encapsulation pattern LIL3 may include depositing a third lower inorganic encapsulation layer LIL3-I, removing a portion of the third lower inorganic encapsulation layer LIL3-I that does not overlap the third light emitting element ED3, and removing the third dummy layer DMP3-I to form a third dummy area DMA3.

[0238] refer to Fig. 10B , forming the third lower inorganic encapsulation pattern LIL3 may include depositing a third lower inorganic encapsulation layer LIL3-I. The third lower inorganic encapsulation layer LIL3-I may be formed by a deposition process. In an embodiment, the third lower inorganic encapsulation layer LIL3-I may be formed by a chemical vapor deposition (CVD) process. The third lower inorganic encapsulation layer LIL3-I may be formed to cover the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P and the partition wall PW and have a thickness TT3 of about 1.0 μm to about 1.7 μm. That is, the thickness TT3 of the third lower inorganic encapsulation layer LIL3-I may be equal to or greater than the second lower inorganic encapsulation layer LIL2-I (see Fig. 9B ) thickness TT2 (see Fig. 9B ).

[0239] Fig. 10B It is exemplarily shown that the third lower inorganic encapsulation layer LIL3-I is formed separately from the first virtual area DMA1 and the second virtual area DMA2, but the embodiments of the present invention are not limited thereto. For example, the third lower inorganic encapsulation layer LIL3-I may fill a portion of the first virtual area DMA1 and / or a portion of the second virtual area DMA2, or fill the entire first virtual area DMA1 and / or the entire second virtual area DMA2.

[0240] refer to Fig. 10C, forming the third lower inorganic encapsulation pattern LIL3 may include forming a fourth photoresist layer PR4, and removing a portion of the third lower inorganic encapsulation layer LIL3-I that does not overlap with the third light emitting element ED3. Here, the fourth photoresist layer PR4 corresponds to the third light emitting element ED3 by being disposed at the third partition wall opening OP3-P and a region adjacent to the third partition wall opening OP3-P along the upper surface of the partition wall PW.

[0241] When forming the fourth photoresist layer PR4, after forming the preliminary photoresist layer, the fourth photoresist layer PR4 may be formed by patterning the preliminary photoresist layer using a photomask. Through the patterning process, the fourth photoresist layer PR4 may be formed into a pattern corresponding to the third light emitting element ED3.

[0242] When removing the portion of the third lower inorganic encapsulation layer LIL3-I that does not overlap with the third light-emitting element ED3, the third lower inorganic encapsulation layer LIL3-I may be patterned by dry etching using the fourth photoresist layer PR4 as a mask, thereby removing the portion of the third lower inorganic encapsulation layer LIL3-I that does not overlap with the third light-emitting element ED3. The third lower inorganic encapsulation pattern LIL3 overlapping with the third light-emitting element ED3 may be formed by the patterned third lower inorganic encapsulation layer LIL3-I.

[0243] refer to Fig. 10D , forming the third lower inorganic encapsulation pattern LIL3 may include removing the third dummy layer DMP3-I (see Fig. 10C ) to form a third virtual area DMA3.

[0244] The (2-3)th dummy layer D23-I of the third dummy layer DMP3-I formed inside the first partition wall opening OP1-P and the second partition wall opening OP2-P and on the partition wall PW may be removed by performing wet etching, and the (1-3)th dummy layer D13-I of the third dummy layer DMP3-I may be removed by using a stripper. Thereafter, the fourth photoresist layer PR4 (see Fig. 10C ). That is, we can Fig. 10C Remove from the stacking structure Fig. 10C The entire third virtual layer DMP3-I in.

[0245] By removing the third dummy layer DMP3-I, the third dummy area DMA3 may be formed as a gap between the third lower inorganic encapsulation pattern LIL3 and the partition wall PW defining the third partition wall opening OP3-P. The height H3 of the third dummy area DMA3 may correspond to the height H3 of the third dummy layer DMP3-I (see Fig. 10A ), and the thickness of the third dummy layer DMP3-I may correspond to the sum of the thicknesses of the third light emitting pattern EP3 and the third cathode CE3.

[0246] refer to Fig. 10C and Fig. 10D Since the height of the gap at the dummy area (or dummy layer) is large during the process in the method of providing the display panel DP, the inflow of the gas for dry etching becomes easier, so that the etching speed becomes higher. For example, since the height H3 of the third dummy area DMA3 (or the third dummy layer DMP3-I) is greater than that of the second dummy area DMA2 (or the second dummy layer DMP2-I (see Fig. 9C )) of the height H2, so for removing the third lower inorganic encapsulation layer LIL3-I (see Fig. 10B ) that does not overlap with the third light emitting element ED3 may be etched at a higher speed than that for removing the second lower inorganic encapsulation layer LIL2-I (see Fig. 9B ) of the portion that does not overlap with the second light-emitting element ED2.

[0247] In the case of a larger etching rate at a larger height gap, over-etching may occur undesirably. According to an embodiment of the present invention, since the thickness TT3 of the third lower inorganic encapsulation layer LIL3-I is equal to or greater than the thickness TT2 of the second lower inorganic encapsulation layer LIL2-I, the over-etching phenomenon occurring on the third lower inorganic encapsulation layer LIL3-I can be reduced or eliminated.

[0248] refer to Fig.11 According to an embodiment of the present invention, a method for providing a display panel DP may include forming an organic encapsulation film OL and an upper inorganic encapsulation film UIL to complete the formation of the display panel DP. The organic encapsulation film OL may be formed by applying an organic material by inkjet, but the embodiments of the present invention are not limited thereto. The organic encapsulation film OL provides a planarized upper surface. Thereafter, an upper inorganic encapsulation film UIL may be formed by depositing an inorganic material. Thus, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE may be formed.

[0249] As has been described previously, since the thickness of the second lower inorganic encapsulation layer LIL2-I is greater than the thickness of the first lower inorganic encapsulation layer LIL1-I, the over-etching phenomenon of the second lower inorganic encapsulation layer LIL2-I can be reduced or eliminated. In addition, since the thickness of the third lower inorganic encapsulation layer LIL3-I is equal to or greater than the thickness of the second lower inorganic encapsulation layer LIL2-I, the over-etching phenomenon of the third lower inorganic encapsulation layer LIL3-I can be reduced or eliminated.

[0250] Although the embodiments of the present invention have been described, it should be understood that the present invention should not be limited to these embodiments, but various changes and modifications can be made by those of ordinary skill in the art within the spirit and scope of the present invention as claimed. Therefore, the technical scope of the present invention should not be limited to the contents described in the specific embodiments of the specification, but should be defined by the claims.

Claims

1. Display panel, including: a pixel defining layer, wherein a first light emitting opening and a second light emitting opening are defined in the pixel defining layer; a partition wall on the pixel defining layer, wherein a first partition wall opening overlapping the first light emitting opening and a second partition wall opening overlapping the second light emitting opening are defined in the partition wall; a first light emitting element in the first partition wall opening and including a first anode, a first light emitting pattern and a first cathode; a second light emitting element in the second partition wall opening and including a second anode, a second light emitting pattern, and a second cathode; a first lower inorganic packaging pattern, covering the first light-emitting element; as well as a second lower inorganic encapsulation pattern, spaced apart from the first lower inorganic encapsulation pattern and covering the second light emitting element, Wherein, a thickness of the first lower inorganic encapsulation pattern is smaller than a thickness of the second lower inorganic encapsulation pattern.

2. The display panel according to claim 1, wherein: The first light emitting element emits blue light, and The second light emitting element emits green light.

3. The display panel according to claim 1, wherein: The thickness of the first lower inorganic encapsulation pattern is 0.2 micrometers to 1.0 micrometers.

4. The display panel according to claim 1, wherein: The thickness of the second lower inorganic encapsulation pattern is 1.0 micrometer to 1.5 micrometer.

5. The display panel according to claim 1, wherein: adjacent to the first partition wall opening, the first lower inorganic encapsulation pattern is spaced apart from the partition wall and has a first gap therebetween to define a first dummy region, and Adjacent to the second partition wall opening, the second lower inorganic encapsulation pattern is spaced apart from the partition wall with a second gap therebetween to define a second dummy region.

6. The display panel according to claim 5, wherein: Along the thickness direction of the partition wall: The first gap and the second gap define a height of the first virtual area and a height of the second virtual area, respectively, and The height of the first virtual area is smaller than the height of the second virtual area.

7. The display panel according to claim 5, further comprising: a third light emitting opening defined in the pixel defining layer; a third partition wall opening defined in the partition wall and overlapping the third light emitting opening; a third light emitting element in the third partition wall opening and including a third anode, a third light emitting pattern and a third cathode; as well as A third lower inorganic encapsulation pattern is spaced apart from the first and second lower inorganic encapsulation patterns and covers the third light emitting element.

8. The display panel according to claim 7, wherein: A thickness of the third lower inorganic encapsulation pattern is equal to or greater than the thickness of the second lower inorganic encapsulation pattern.

9. The display panel according to claim 7, wherein: The third light emitting element emits red light.

10. The display panel according to claim 7, wherein: The third lower inorganic encapsulation pattern has a thickness of 1.0 micrometer to 1.7 micrometers.

11. The display panel according to claim 7, wherein: Adjacent to the third partition wall opening, the third lower inorganic encapsulation pattern is spaced apart from the partition wall with a third gap therebetween to define a third dummy region.

12. The display panel according to claim 11, wherein: Along the thickness direction of the partition wall: The second gap and the third gap define a height of the second virtual area and a height of the third virtual area, respectively, and The height of the third virtual area is greater than the height of the second virtual area.

13. A method for providing a display panel, the method comprising: providing a preliminary display panel, the preliminary display panel including a pixel defining layer having a light emitting opening defined therein, a first preliminary partition wall layer on the pixel defining layer, and a second preliminary partition wall layer on the first preliminary partition wall layer; etching the first preliminary partition wall layer and the second preliminary partition wall layer to form a partition wall in which a first partition wall opening, a second partition wall opening, and a third partition wall opening are defined corresponding to the light emitting openings, respectively; providing a first light emitting element in the first partition wall opening; Providing a first lower inorganic packaging pattern covering the first light emitting element; providing a second light emitting element in the second partition wall opening; providing a second lower inorganic encapsulation pattern spaced apart from the first lower inorganic encapsulation pattern and covering the second light emitting element; providing a third light emitting element in the third partition wall opening; as well as providing a third lower inorganic encapsulation pattern spaced apart from the first lower inorganic encapsulation pattern and the second lower inorganic encapsulation pattern and covering the third light emitting element, Wherein, a thickness of the first lower inorganic encapsulation pattern is smaller than a thickness of the second lower inorganic encapsulation pattern.

14. The method of claim 13, wherein: A thickness of the third lower inorganic encapsulation pattern is equal to or greater than the thickness of the second lower inorganic encapsulation pattern.

15. The method of claim 13, wherein: Providing the first light emitting element in the first partition wall opening includes providing a first material layer of the first light emitting element, the first material layer including: a first material layer pattern in the first partition wall opening, and The first virtual layer of the first material layer is inside the second partition wall opening, inside the third partition wall opening, and on the partition wall.

16. The method of claim 15, wherein: Providing the first lower inorganic packaging pattern includes: depositing a first lower inorganic encapsulation layer having a thickness of 0.2 micrometers to 1.0 micrometers, the first lower inorganic encapsulation layer covering each of the first material layer, the first partition wall opening, the second partition wall opening, the third partition wall opening, and the partition wall of the first light emitting element; removing a portion of the first lower inorganic encapsulation layer that does not overlap with the first light emitting element; and The first dummy layer is removed to form a first gap between the first lower inorganic encapsulation pattern and the partition wall and adjacent to the first partition wall opening.

17. The method of claim 13, wherein: Providing the second light emitting element in the second partition wall opening includes providing a second material layer of the second light emitting element, the second material layer including: a second material layer pattern in the second partition wall opening, and The second dummy layer of the second material layer is inside the first partition wall opening, inside the third partition wall opening, and on the partition wall.

18. The method of claim 17, wherein: Providing the second lower inorganic packaging pattern includes: depositing a second lower inorganic encapsulation layer having a thickness of 1.0 micrometer to 1.5 micrometer, the second lower inorganic encapsulation layer covering each of the second material layer, the first partition wall opening, the second partition wall opening, the third partition wall opening, and the partition wall of the second light emitting element; removing a portion of the second lower inorganic encapsulation layer that does not overlap with the second light emitting element; and The second dummy layer is removed to form a second gap between the second lower inorganic encapsulation pattern and the partition wall and adjacent to the second partition wall opening.

19. The method of claim 13, wherein: Providing the third light emitting element in the third partition wall opening includes providing a third material layer of the third light emitting element, the third material layer including: a third material layer pattern in the third partition wall opening, and The third dummy layer of the third material layer is inside the first partition wall opening, inside the second partition wall opening, and on the partition wall.

20. The method of claim 19, wherein: Providing the third lower inorganic encapsulation pattern comprises: depositing a third lower inorganic encapsulation layer having a thickness of 1.0 micrometer to 1.7 micrometer, the third lower inorganic encapsulation layer covering each of the third material layer, the first partition wall opening, the second partition wall opening, the third partition wall opening, and the partition wall of the third light emitting element; removing a portion of the third lower inorganic encapsulation layer that does not overlap with the third light emitting element; and The third dummy layer is removed to form a third gap between the third lower inorganic encapsulation pattern and the partition wall and adjacent to the third partition wall opening.

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