Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of pixel circuits distributed in an array mode, each pixel circuit comprises a plurality of transistors, a first capacitor (C1) and a second capacitor (C2), and each transistor comprises a driving transistor (T3), a write-in transistor (T4), a light-emitting control transistor (T5), a first reset transistor (T1), a second reset transistor (T2) and a third reset transistor (T7). A substrate (SU), a semiconductor layer (sE) provided on the substrate (SU) side and including an active portion of each transistor, and a plurality of light emitting devices (LD); the light-emitting device (LD) is arranged on one side, far away from the substrate (SU), of the semiconductor layer (sE), and the light-emitting device (LD) is connected with a first pole of a driving transistor (T3) of a pixel circuit; one of a first pole plate (C11) and a second pole plate (C12) of the first capacitor (C1) and one of a first pole plate (C21) and a second pole plate (C22) of the second capacitor (C2) are arranged on the same layer; one of the first capacitance (C1) and the second capacitance (C2) overlaps an active portion (ACT3) of the driving transistor (T3).

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202310628545.6 filed on May 30, 2023, entitled “Display device, display panel, pixel circuit and driving method thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] OLED (organic light-emitting diode) display panels offer a wide range of applications thanks to their advantages, including self-luminescence, wide color gamut, high contrast, flexibility, and high responsiveness. However, the brightness uniformity of current display panels still needs to be improved, and display anomalies are prone to occur.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] The present disclosure provides a display panel and a display device.

[0008] According to one aspect of the present disclosure, a display panel is provided, comprising a plurality of pixel circuits arranged in an array along row and column directions, the pixel circuits comprising a plurality of transistors, a first capacitor and a second capacitor, wherein each of the transistors comprises a drive transistor, a write transistor, a light emission control transistor, a first reset transistor, a second reset transistor, and a third reset transistor;

[0009] The first electrode of the light-emitting control transistor is used to receive a first power supply signal, and the second electrode of the light-emitting control transistor is connected to the second electrode of the driving transistor; the first electrode of the write transistor is used to receive a data signal, and the second electrode of the write transistor is connected to the gate of the driving transistor and the first plate of the first capacitor, the second plate of the first capacitor is connected to the first plate of the second capacitor, and the second plate of the second capacitor is connected to the first electrode of the driving transistor;

[0010] The first electrode of the first reset transistor and the first electrode of the second reset transistor are used to receive a reference signal, and the second electrode of the first reset transistor is connected to the gate of the driving transistor; the second electrode of the second reset transistor is connected to the second plate of the first capacitor and the first plate of the second capacitor; the first electrode of the third reset transistor is used to receive a reset signal, and the second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second plate of the second capacitor;

[0011] The display panel includes:

[0012] substrate;

[0013] a semiconductor layer, provided on one side of the substrate and including an active portion of each of the transistors;

[0014] A plurality of light-emitting devices are provided on a side of the semiconductor layer away from the substrate, and one of the light-emitting devices is connected to a first electrode of a driving transistor of the pixel circuit;

[0015] One of the first plate and the second plate of the first capacitor is arranged in the same layer as one of the first plate and the second plate of the second capacitor; and one of the first capacitor and the second capacitor overlaps with the active portion of the driving transistor.

[0016] In an exemplary embodiment of the present disclosure, the first plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer and distributed along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer and are an integrated structure; the first plate and the second plate of the second capacitor overlap with the active part of the driving transistor.

[0017] In an exemplary embodiment of the present disclosure, the pixel circuit further includes a data control transistor, a first electrode of the data control transistor being connected to the second electrode of the write transistor and the first plate of the first capacitor, and a second electrode of the data control transistor being connected to the gate of the drive transistor.

[0018] In an exemplary embodiment of the present disclosure, the semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion spaced apart along the row direction; the second semiconductor portion is located between the first semiconductor portion and the third semiconductor portion, and the first semiconductor portion is connected to the second semiconductor portion;

[0019] The active parts of the write transistor, the data control transistor and the first reset transistor are all located in the first semiconductor part and are connected in sequence along the column direction; the active part of the second reset transistor is located in the second semiconductor part; the active parts of the light emitting control transistor, the drive transistor and the third reset transistor are located in the third semiconductor part and are connected in sequence along the column direction.

[0020] In an exemplary embodiment of the present disclosure, the third semiconductor portion includes a first semiconductor segment and a second semiconductor segment distributed along the column direction; the active portion of the driving transistor is connected between the first semiconductor segment and the second semiconductor segment;

[0021] The width of the active portion of the driving transistor in the row direction is greater than the width of the first semiconductor segment and the second semiconductor segment in the row direction.

[0022] In an exemplary embodiment of the present disclosure, a width of the active portion of the driving transistor in the row direction is not less than 6 μm and not more than 20 μm.

[0023] In an exemplary embodiment of the present disclosure, the third semiconductor portion includes a first semiconductor segment and a second semiconductor segment distributed along the column direction; the active portion of the driving transistor is connected between the first semiconductor segment and the second semiconductor segment;

[0024] The active portion of the driving transistor is bent toward the first semiconductor segment along the row direction.

[0025] In an exemplary embodiment of the present disclosure, a length of the active portion of the driving transistor in the column direction is not less than 20 μm and not more than 30 μm.

[0026] In an exemplary embodiment of the present disclosure, a width-to-length ratio of the driving transistor is not greater than 20 / 6 and not less than 4 / 30.

[0027] In an exemplary embodiment of the present disclosure, the first plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer and distributed along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer and are an integrated structure; the first plate and the second plate of the second capacitor overlap with the active part of the driving transistor.

[0028] In an exemplary embodiment of the present disclosure, the first plate and the second plate of the first capacitor overlap with the third semiconductor portion and the first semiconductor portion.

[0029] In an exemplary embodiment of the present disclosure, the capacitance of the second capacitor is greater than the capacitance of the first capacitor.

[0030] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0031] a light emitting control line extending along the row direction and overlapping with the active portion of the light emitting control transistor, for transmitting a light emitting control signal;

[0032] a first reset control line extending along the row direction and overlapping the active portion of the third reset transistor, for transmitting a reset control signal;

[0033] a second reset control line connected to the gates of the first reset transistor and the second reset transistor, and configured to transmit a reference control signal;

[0034] a scan line extending along the row direction and connected to the gate of the write transistor for transmitting a scan signal;

[0035] a data control line extending along the row direction and connected to the gate of the data control transistor for transmitting a data control signal;

[0036] a first reset line extending along the row direction and connected to the first electrode of the first reset transistor and the first electrode of the second reset transistor, for transmitting the reference signal;

[0037] The second reset line extends along the row direction and is connected to the first electrode of the third reset transistor for transmitting the reset signal.

[0038] In an exemplary embodiment of the present disclosure, the light emitting control line, the scan line, the data control line, the second reset control line, the first reset control line, and the second reset line are sequentially spaced apart in their orthographic projections on the substrate along the column direction; the first reset line overlaps the first reset control line;

[0039] An orthographic projection of the active portion of the driving transistor on the substrate is located between an orthographic projection of the data control line and an orthographic projection of the second reset control line on the substrate;

[0040] The orthographic projections of the active portion of the write transistor and the first capacitor on the substrate are at least partially located between the orthographic projections of the light emitting control line and the data control line on the substrate;

[0041] Orthographic projections of active portions of the first reset transistor and the second reset transistor on the substrate are located between orthographic projections of the data control line and the first reset control line on the substrate.

[0042] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0043] a plurality of first auxiliary power lines extending along the row direction and distributed along the column direction; a first auxiliary power line is provided between two adjacent rows of pixel circuits; the first auxiliary power line is connected to the first electrode of the light emitting control transistor of the pixel circuit on one side thereof;

[0044] a plurality of first power lines, arranged on a side of the first auxiliary power line away from the substrate, each of the first power lines extending along the column direction and spaced apart along the row direction; a first power line connected to each of the first auxiliary power lines and overlapping with a column of the pixel circuits;

[0045] A plurality of data lines are arranged on a side of the first auxiliary power line away from the substrate, each of the data lines extending along the column direction and spaced apart along the row direction; one of the data lines overlaps with a column of the pixel circuits and is connected to the first electrode of the write transistor for transmitting the data signal.

[0046] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0047] a plurality of second power lines, a first auxiliary reset line, and a second auxiliary reset line extending along the column direction and distributed along the row direction, the first auxiliary reset line being arranged on a side of the first auxiliary power line away from the substrate; the second power line being used to transmit a second power signal, the first auxiliary reset line being connected to the first reset line, and the second auxiliary reset line being connected to the second reset line;

[0048] The first power line and the data line connected to the pixel circuits in the same column are defined as a line group, and the second power line, one of the first auxiliary reset line and the second auxiliary reset line is provided between two adjacent line groups;

[0049] The light emitting device includes a first electrode and a second electrode. The first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the second power line.

[0050] In an exemplary embodiment of the present disclosure, the light emission control line includes a first sub-light emission control line and a second sub-light emission control line arranged in a direction away from the substrate, and the first sub-light emission control line and the second sub-light emission control line both extend along the row direction and are connected;

[0051] The first reset control line includes a first sub-reset control line and a second sub-reset control line arranged in a direction away from the substrate, and the first sub-reset control line and the second sub-reset control line are both extended and connected in the row direction.

[0052] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0053] a light shielding layer, provided on one side of the substrate, and comprising the second plate of the first capacitor and the first plate of the second capacitor;

[0054] a first gate layer, disposed on a side of the light shielding layer away from the substrate, and comprising a first plate of the first capacitor, a second plate of the second capacitor, the first sub-light emitting control line, and the first sub-reset control line; and the semiconductor layer is disposed on a side of the first gate layer away from the substrate;

[0055] a second gate layer, provided on a side of the semiconductor layer away from the substrate, and comprising the second sub-light emitting control line and the second sub-reset control line;

[0056] a first source-drain layer, provided on a side of the second gate layer away from the substrate, and comprising the first auxiliary power line, the scan line, the data control line, the second reset control line, the first reset line, and the second reset line;

[0057] The second source-drain layer is provided on a side of the first source-drain layer away from the substrate, and includes the data line, the first power line, the second power line, the first auxiliary reset line and the second auxiliary reset line.

[0058] In an exemplary embodiment of the present disclosure, the first gate layer further includes:

[0059] a first gate portion overlapping the active portion of the write transistor to form a gate of the write transistor;

[0060] a second gate portion overlapping the active portion of the data control transistor to form a gate of the data control transistor; a first plate of the second capacitor including a third gate portion;

[0061] The fourth gate portion overlaps the active portions of the first reset transistor and the second reset transistor to form gates of the first reset transistor and the second reset transistor.

[0062] In an exemplary embodiment of the present disclosure, the second gate layer includes:

[0063] a fifth gate portion overlapping the active portion of the write transistor and connected to the first gate portion to form a gate of the write transistor;

[0064] a sixth gate portion overlapping the active portion of the data control transistor and connected to the second gate portion to form a gate of the data control transistor;

[0065] a seventh gate portion overlapping the active portion of the driving transistor and overlapping the third gate portion to form a gate of the driving transistor;

[0066] An eighth gate portion overlaps the active portions of the first reset transistor and the second reset transistor and is connected to the fourth gate portion to form gates of the first reset transistor and the second reset transistor.

[0067] In an exemplary embodiment of the present disclosure, the first source-drain layer includes:

[0068] a first connecting portion, located between the first auxiliary power line and the scan line, and connected to the data line and the first electrode of the write transistor;

[0069] a second connecting portion located between the scan line and the data control line and connected to the first plate of the first capacitor and a region of the first semiconductor portion located between the active portion of the write transistor and the active portion of the data control transistor;

[0070] a third connecting portion located between the data control line and the second reset control line and connected to the sixth gate portion and a region of the first semiconductor portion located between an active portion of the first reset transistor and an active portion of the data control transistor;

[0071] a fourth connecting portion, located between the third connecting portion and the second reset control line, and connected to the first plate of the second capacitor and an end of the second semiconductor portion close to the active portion of the driving transistor; and an end of the second semiconductor portion away from the active portion of the driving transistor is connected to the first semiconductor portion;

[0072] The fifth connection portion is located between the first reset control line and the second reset control line and is connected to the second plate of the second capacitor and a region of the third semiconductor portion located between the active portion of the drive transistor and the active portion of the third reset transistor.

[0073] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer includes metal oxide.

[0074] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0075] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0077] FIG1 is a top view of an embodiment of a display panel disclosed herein.

[0078] FIG2 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.

[0079] FIG3 is a timing diagram of an embodiment of a driving method for a pixel circuit disclosed herein.

[0080] FIG4 is a partial cross-sectional schematic diagram of an embodiment of a display panel disclosed herein.

[0081] FIG5 is a partial top view of the light shielding layer to the second source and drain layer in the first embodiment of the display panel disclosed herein.

[0082] FIG6 is a partial top view of the light shielding layer to the first source and drain layer of a single pixel circuit in the first embodiment of the display panel disclosed herein.

[0083] FIG7 is a partial top view of the light shielding layer to the second gate layer of a single pixel circuit in the first embodiment of the display panel disclosed herein.

[0084] FIG8 is a partial top view of the light shielding layer to the semiconductor layer gate layer of a single pixel circuit in the first embodiment of the display panel disclosed herein.

[0085] FIG9 is a partial top view of the light shielding layer to the first gate layer of a single pixel circuit in the first embodiment of the display panel disclosed herein.

[0086] 10 to 15 are partial top views of each layer from the light shielding layer to the second source and drain layer of a single pixel circuit in the first embodiment of the display panel disclosed herein.

[0087] FIG16 is a partial top view of the light shielding layer to the second source and drain layer of a single pixel circuit in the second embodiment of the display panel disclosed herein.

[0088] FIG17 is a partial top view of the light shielding layer to the first source and drain layer of a single pixel circuit in the second embodiment of the display panel disclosed herein.

[0089] FIG18 is a partial top view of the light shielding layer to the second gate layer of a single pixel circuit in the second embodiment of the display panel disclosed herein.

[0090] FIG19 is a partial top view of the light shielding layer to the semiconductor layer gate layer of a single pixel circuit in the second embodiment of the display panel disclosed herein.

[0091] FIG20 is a partial top view of the light shielding layer to the first gate layer of a single pixel circuit in the second embodiment of the display panel disclosed herein.

[0092] 21 to 26 are partial top views of each layer from the light shielding layer to the second source and drain layer of a single pixel circuit in the second embodiment of the display panel disclosed herein.

[0093] FIG27 is a partial top view of the light shielding layer to the second source and drain layer of multiple pixel circuits in the first embodiment of the display panel disclosed herein.

[0094] FIG28 is a partial top view of the light shielding layer to the first source and drain layer of multiple pixel circuits in the first embodiment of the display panel disclosed herein.

[0095] FIG29 is a partial top view of the light shielding layer to the second gate layer of multiple pixel circuits in the first embodiment of the display panel of the present disclosure.

[0096] FIG30 is a partial top view of the light shielding layer to the semiconductor layer gate layer of multiple pixel circuits in the first embodiment of the display panel disclosed herein.

[0097] FIG31 is a partial top view of the light shielding layer to the first gate layer of multiple pixel circuits in the first embodiment of the display panel disclosed herein.

[0098] 32 to 37 are partial top views of each layer from the light shielding layer to the second source and drain layer of multiple pixel circuits in the first embodiment of the display panel disclosed herein.

[0099] FIG38 is a partial top view of the light shielding layer to the second source and drain layer of multiple pixel circuits in the second embodiment of the display panel disclosed herein.

[0100] FIG39 is a partial top view of the light shielding layer to the first source and drain layer of multiple pixel circuits in the second embodiment of the display panel disclosed herein.

[0101] FIG40 is a partial top view of the light shielding layer to the second gate layer of multiple pixel circuits in the second embodiment of the display panel disclosed herein.

[0102] FIG41 is a partial top view of the light shielding layer to the semiconductor layer gate layer of multiple pixel circuits in the second embodiment of the display panel disclosed herein.

[0103] FIG42 is a partial top view of the light shielding layer to the first gate layer of multiple pixel circuits in the second embodiment of the display panel disclosed herein.

[0104] 43 to 48 are partial top views of each layer from the light shielding layer to the second source and drain layer of multiple pixel circuits in the second embodiment of the display panel disclosed herein. DETAILED DESCRIPTION

[0105] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0106] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0107] The row direction X and column direction Y herein are two intersecting directions. In the drawings of this disclosure, the row direction X may be horizontal and the column direction Y may be vertical, with the two directions being perpendicular to each other. However, this is not limiting. The row direction X and the column direction Y may also be non-perpendicular. Furthermore, those skilled in the art will appreciate that, as the display panel rotates, the actual orientations of the row direction X and the column direction Y may change, but their relative positions remain unchanged.

[0108] In this article, "overlap" of feature A and feature B means that the orthographic projection of feature A on a plane and the orthographic projection of feature B on the same plane at least partially overlap; the plane can be the surface of the substrate or other plane parallel to the substrate.

[0109] In this article, A and B are "set in the same layer" means that A and B belong to different continuous or disconnected regions in the same film layer, and the film layer can be a single-layer structure; or, the film layer can be a multi-layer structure, in which case A and B can be located in the same layer or different layers in the multi-layer structure.

[0110] As shown in FIG1 , the present disclosure provides a display panel, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA.

[0111] As shown in FIG4 , the display panel may include a driving backplane BP and a plurality of light-emitting devices LD arranged on one side of the driving backplane BP. The light-emitting devices LD are arrayed along the row direction X and the column direction Y. The driving circuit in the driving backplane BP can drive the light-emitting devices LD to emit light to display images.

[0112] As shown in Figure 4, the light-emitting device LD can be located in the display area AA. It can be an OLED (organic light-emitting diode) using organic light-emitting materials; it can also be an LED (light-emitting diode) using inorganic light-emitting materials, such as Micro LED (micrometer light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); it can also be a device such as QLED (quantum dot diode). There is no special limitation on the specific structure of the light-emitting device LD here, as long as it can display images.

[0113] As shown in Figure 4, taking the light-emitting device LD using OLED as an example, it may include a first electrode ANO, a light-emitting layer EL and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying an electrical signal to the first electrode ANO and the second electrode CAT, the light-emitting layer EL can be stimulated to emit light. The specific light-emitting principle will not be described in detail here.

[0114] The driving circuit may include pixel circuits located within the display area AA and peripheral circuits located in the peripheral area WA. The pixel circuits may be distributed along the row direction X and the column direction Y. One pixel circuit may be connected to the first electrode ANO of one light-emitting device LD, and a row of pixel circuits may be connected to the first electrode ANO of each light-emitting device LD in the row. Of course, the same pixel circuit may also be connected to the first electrodes ANO of multiple light-emitting devices LD. Furthermore, some pixel circuits may be located in the peripheral area WA.

[0115] The peripheral circuit can be connected to the light-emitting device LD through the pixel circuit and apply a first power signal VDD to the first electrode ANO of the light-emitting device LD. On the other hand, the peripheral circuit can also be connected to the second electrode CAT of the light-emitting device LD and apply a second power signal VSS to the second electrode CAT. The current passing through the light-emitting device LD can be controlled through the pixel circuit, thereby controlling the brightness of the light-emitting device LD.

[0116] Taking a pixel circuit as an example, as shown in FIG2 , the pixel circuit may include a driving transistor T3, a storage circuit RU, a writing circuit DU, and a light emitting control circuit EU, wherein:

[0117] The gate of the driving transistor T3 is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU, and the first electrode of the driving transistor T3 is used to be connected to the light-emitting device LD. The second electrode of the driving transistor T3 is connected to the light-emitting control circuit EU, and the light-emitting control circuit EU is used to receive the first power supply signal VDD;

[0118] The write circuit DU is connected to the first electrode of the driving transistor T3 through the energy storage circuit RU; the write circuit DU is used to write the data signal Data into the energy storage circuit RU; the energy storage circuit RU is used to store the data signal Data and the voltage of the first electrode of the driving transistor T3.

[0119] The energy storage circuit RU can store the data signal Data and the voltage of the first electrode of the driving transistor T3 respectively, so as to stabilize the voltage difference between the first electrode and the gate of the driving transistor T3 and prevent mutual interference between the two. The write circuit DU can control the writing and shutting off of the data signal Data.

[0120] The energy storage circuit RU can be implemented by multiple capacitors, and the write circuit DU can be implemented by transistors. For example:

[0121] As shown in FIG2 , in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series; the write circuit DU may include a write transistor T4 ; and the light emission control circuit EU may include a light emission control transistor T5 .

[0122] The first electrode of the write transistor T4 is used to input the data signal Data. The second electrode of the write transistor T4 is connected to the gate of the drive transistor T3 and the first plate C11 of the first capacitor C1. The second plate C12 of the first capacitor C1 is connected to the first plate C21 of the second capacitor C2. The second plate C22 of the second capacitor C2 is connected to the first electrode of the drive transistor T3. The first electrode of the light-emitting control transistor T5 is used to receive the first power supply signal VDD, and the second electrode can be connected to the second electrode of the drive transistor T3. The first electrode of the drive transistor T3 and the second plate C22 of the second capacitor C2 can be connected to the first electrode ANO of the light-emitting device LD.

[0123] Furthermore, in some embodiments, the display panel may further include a data control circuit CU. The data control circuit CU may be connected to the gate and first electrode of the driving transistor T3, and the second electrode of the write circuit DU may be connected to the gate of the driving transistor T3 and the energy storage circuit RU through the data control circuit CU. The data control circuit CU can turn the gate of the driving transistor T3 and the write circuit DU on and off, and can also turn the gate of the driving transistor T3 and the energy storage circuit RU on and off. This prevents the data signal Data from being directly written to the gate of the driving transistor T3 and interfering with the voltage of its first electrode, thereby preventing a significant difference between the actual brightness of the light-emitting device LD and the designed brightness due to different levels of interference between different data signals Data, thereby improving image quality.

[0124] The data control circuit CU can also be implemented by transistors; for example:

[0125] As shown in FIG. 2 , in some embodiments of the present disclosure, the energy storage circuit RU may include a first capacitor C1 and a second capacitor C2 connected in series; the data control circuit CU includes a data control transistor T6 ; and the write circuit DU may include a write transistor T4 .

[0126] The first electrode of the write transistor T4 is used to input the data signal Data, the second electrode of the write transistor T4 is connected to the first electrode of the data control transistor T6 and the first plate C11 of the first capacitor C1, and can be connected to the N5 node; the second electrode of the data control transistor T6 is connected to the gate of the drive transistor T3 and can be connected to the N1 node; the second plate C12 of the first capacitor C1 is connected to the first plate C21 of the second capacitor C2 and can be connected to the N4 node; the second plate C22 of the second capacitor C2 is connected to the first electrode of the drive transistor T3 and can be connected to the N3 node.

[0127] The gate of the write transistor T4 can receive a scan signal Gate and be turned on or off under the control of the scan signal Gate. The gate of the data control transistor T6 can receive a data control signal DC and be turned on or off under the control of the data control signal DC.

[0128] In addition, the light emitting control circuit EU can control the connection and disconnection of the first power supply signal VDD, which can also be achieved by transistors. For example:

[0129] As shown in Figure 2, in some embodiments of the present disclosure, the light-emitting control circuit EU may include a light-emitting control transistor T5, whose first electrode is used to receive the first power supply signal VDD, and the second electrode can be connected to the second electrode of the driving transistor T3, and the second electrode can be connected to the second electrode of the driving transistor T3 at the N2 node.

[0130] The gate of the light emitting control transistor T5 may receive the light emitting control signal EM and be turned on or off under the control of the light emitting control signal EM.

[0131] In order to eliminate the influence of the signal of the previous frame image, before displaying the signal input of the current frame, the gate and the first electrode of the driving transistor T3 may be reset. At the same time, the energy storage circuit RU may also be reset. As shown in FIG2 , in some embodiments of the present disclosure, the pixel circuit may further include a first reset transistor T1 and a second reset transistor T2, wherein:

[0132] The first electrode of the first reset transistor T1 is used to receive the reference signal Vref, and the second electrode is connected to the gate of the driving transistor T3 and the second electrode of the data control transistor T6. As shown in Figure 2, the second electrode of the first reset transistor T1 is connected to the gate of the driving transistor T3 and the second electrode of the data control transistor T6 at the N1 node.

[0133] A first electrode of the second reset transistor T2 is used to receive a reference signal Vref, and a second electrode of the second reset transistor T2 is connected to the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. As shown in FIG2 , the second electrode of the second reset transistor T2 and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are connected to the N4 node.

[0134] The gates of the first reset transistor T1 and the second reset transistor T2 can receive a reference control signal RE2 and be turned on or off under the control of the reference control signal RE2. In other words, the first reset transistor T1 and the second reset transistor T2 can be turned on or off synchronously and can be controlled by the same signal. Of course, the gates of the first reset transistor T1 and the second reset transistor T2 can receive the reference control signal RE2 via the same or different signal lines.

[0135] The reference signal Vref can be input to the N1 and N4 nodes through the first reset transistor T1 and the second reset transistor T2 to eliminate the influence of the signal when displaying the previous frame image.

[0136] Furthermore, as shown in FIG2 , the pixel circuit further includes a third reset transistor T7, a first electrode of which is used to receive a reset signal Vinit, and a second electrode is connected to the first electrode of the driving transistor T3 and the second electrode plate C22 of the second capacitor C2. As shown in FIG2 , the second electrode of the third reset transistor T7 is connected to the first electrode of the driving transistor T3 and the second electrode plate C22 of the second capacitor C2 at the N3 node. The gate of the third reset transistor T7 can receive a reset control signal RE1 and be turned on or off under the control of the reset control signal RE1. The reset signal Vinit can be input to the N3 node through the third reset transistor T7, resetting the first electrode of the driving transistor T3, the second electrode plate C22 of the second capacitor C2, and the first electrode ANO of the light-emitting device LD, thereby eliminating the influence of the signal of the previous frame image.

[0137] In some embodiments of the present disclosure, at least one of the transistors in the pixel circuit may be an oxide transistor, that is, the material of the active portion of the transistor may be a crystalline oxide semiconductor or an amorphous oxide semiconductor. For example, the material of the active portion of the transistor may be an oxide of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or a mixture of oxides of at least one metal selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti). Oxide semiconductors, within the spirit and scope of the disclosure, may include metal oxides such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc gallium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), and zinc tin oxide (ZTO).

[0138] Accordingly, the transistors can be N-type transistors. As shown in FIG2 , if each transistor can be an N-type transistor, the first electrode of each transistor is a source electrode, and the second electrode is a drain electrode. The transistor is turned on when the gate electrode receives a high level and turned off when the gate electrode receives a low level. For example, as shown in FIG2 , the drive transistor T3, the data control transistor T6, the write transistor T4, the first reset transistor T1, the second reset transistor T2, the third reset transistor T7, and the light-emitting control transistor T5 are all metal oxide transistors, that is, the transistors of the pixel circuit are all metal oxide transistors to reduce leakage current. Of course, only some of the transistors can also be metal oxide transistors.

[0139] The following describes the structure of the pixel circuit based on the above embodiment and its driving method:

[0140] As shown in FIG2 and FIG3 , the driving method of the pixel circuit according to the embodiment of the present disclosure may include:

[0141] In the compensation phase t2 , the data control circuit CU is turned off, and the light emitting control circuit EU is turned on, so as to write the threshold voltage of the driving transistor T3 into the energy storage circuit RU.

[0142] Different voltages can be input to the gate and first electrode of the driving transistor T3 to turn on the driving transistor T3. When the light-emitting control circuit EU is turned on, the voltage at the first electrode of the driving transistor T3 gradually increases, and the threshold voltage of the driving transistor T3 begins to be written into the energy storage circuit RU. The compensation phase begins to write the threshold voltage into the energy storage circuit RU, but is not limited to completing the writing of the threshold voltage.

[0143] In the writing phase t3, the writing circuit DU and the light emitting control circuit EU are turned on, and the data control circuit CU is turned off. The data signal Data is written into the energy storage circuit RU through the writing circuit DU, and the threshold voltage of the driving transistor T3 is written into the energy storage circuit RU.

[0144] The data signal Data is written to the tank circuit RU via the write circuit DU. At this time, the data control circuit CU remains off, preventing the data signal Data from being written to the gate of the drive transistor T3. Simultaneously, when the voltage at the first electrode of the drive transistor T3 reaches a value equal to the difference between the voltage at its gate and the threshold voltage, the drive transistor T3 is turned off, allowing the threshold voltage of the drive transistor T3 to be written into the tank circuit RU. In other words, the threshold voltage and the data signal Data can be written simultaneously.

[0145] In the light emitting stage t4, the light emitting control circuit EU and the data control circuit CU are turned on, the writing circuit DU is turned off, and the voltage difference between the gate and the first electrode of the driving transistor T3 is controlled by the energy storage circuit RU to make the light emitting device LD emit light.

[0146] The voltage difference between the gate and the first electrode of the driving transistor T3 is stably controlled by the energy storage circuit RU. During this process, the data signal Data at the gate does not interfere with the voltage of the first electrode.

[0147] Furthermore, as shown in FIG2 and FIG3 , in some embodiments of the present disclosure, the driving method may further include:

[0148] In the reset phase t1, the first reset transistor T1, the second reset transistor T2 and the third reset transistor T7 are turned on, and the write circuit DU, the data control circuit CU and the light emitting control circuit EU are turned off; the gate of the driving transistor T3 is reset by the reference signal Vref, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are reset; the first electrode of the driving transistor T3 and the second plate C22 of the second capacitor C2 are reset by the reset signal Vinit; at the same time, the driving transistor T3 can be turned on by the voltage difference between the reset signal Vinit and the reference signal Vref.

[0149] The pixel circuit and driving method of the disclosed embodiment include a data control circuit CU disposed between the gate and first electrode of the driving transistor T3. This allows the writing of the data signal Data to be divided into two phases: the first phase, a writing phase t3, during which the data signal Data is stored separately via the energy storage circuit RU while the data control circuit CU is turned off, thereby preventing the data signal Data from being directly written to the gate of the driving transistor T3. The second phase, a light-emitting phase t4, is a light-emitting phase t4, during which the data control circuit CU is turned on and the data signal Data is applied to the gate of the driving transistor T3 via the energy storage circuit RU. During the compensation phase t2, the threshold voltage of the driving transistor T3 can also be written into the energy storage circuit RU (independent of the storage of the data signal Data).

[0150] The energy storage circuit RU does not interfere with the storage of the threshold voltage when storing the data signal Data. In the light-emitting stage t4, the energy storage circuit RU can ensure that the differential voltage between the data signal Data and the first electrode of the driving transistor T3 is stable, thereby preventing a large difference between the actual brightness of the light-emitting device LD and the designed brightness due to different levels of interference of different data signals Data, thereby improving picture quality.

[0151] The following is an exemplary description of the driving method of the pixel circuit by taking the pixel circuit of the embodiment in FIG2 (each transistor is an N-type metal oxide transistor) as an example:

[0152] During reset phase t1, the reference control signal RE2 received by the gates of the first and second reset transistors T1 and T2 is at a high level, turning on the first and second reset transistors T1 and T2. The reference signal Vref, which can be 2.5V, resets nodes N1 and N4. The reset control signal RE1 received by the gate of the third reset transistor T7 is at a high level, turning on the third reset transistor T7. The reset signal Vinit, which can be 1.5V, resets node N3. At this point, a voltage difference exists between the gate and the first electrode of the driving transistor T3, turning it on.

[0153] At the same time, the light control signal EM received by the gate of the light control transistor T5 is at a low level, so that the light control transistor T5 is turned off; the scanning signal Gate received by the gate of the write transistor T4 is at a low level, so that the write transistor T4 is turned off; the data control signal DC received by the gate of the data control transistor T6 is at a low level, so that the data control transistor T6 is turned off.

[0154] The reset of nodes N1 and N4 and the reset of node N3 can be performed in stages. For example, the reference control signal RE2 first changes from a low level to a high level, and then the reset control signal RE1 changes from a low level to a high level. Of course, the two can also be performed simultaneously.

[0155] During compensation phase t2, the light control signal EM received by the gate of light control transistor T5 is at a high level, turning on light control transistor T5. The voltage at node N2 is equal to the voltage of the first power signal VDD. Since driving transistor T3 is turned on, the voltage at node N3 gradually increases. The voltage of the first power signal VDD can be 11.5V.

[0156] At the same time, the reference control signal RE2 is at a high level, the first reset transistor T1 and the second reset transistor T2 are turned on; the reset control signal RE1 is at a low level, the third reset transistor T7 is turned off; the data control signal DC is at a low level, the data control transistor T6 is turned off; the scan signal Gate is at a low level, and the write transistor T4 is turned off.

[0157] In the writing phase t3, the scanning signal Gate is high, the writing transistor T4 is turned on, and the data signal Data is written to the N5 node through the writing transistor T4, that is, stored in the first capacitor C1; the data control signal DC is low, and the data control transistor T6 is turned off.

[0158] At the same time, the emission control signal EM can remain high, turning on the emission control transistor T5. The voltage at node N3 gradually increases until it reaches Vref-Vth, causing the voltage difference between the gate and the first electrode of the driving transistor T3 to equal the threshold voltage, i.e., gate-source voltage difference Vgs=Vth. At this point, the driving transistor T3 is turned off; Vth is the threshold voltage of the driving transistor T3. Consequently, the threshold voltage Vth is written to node N3 and stored in the second capacitor C2. That is, the writing of the threshold voltage begins in compensation phase t2 and is completed in writing phase t3. The writing of the threshold voltage continues from compensation phase t2 to writing phase t3. The emission control signal EM can continue until the driving transistor T3 is turned off, i.e., until the writing of the threshold voltage is completed. For example, the emission control signal EM can continue until the scanning signal Gate is turned off, i.e., after the writing of the data signal Data is completed.

[0159] In addition, the reference control signal RE2 is low, the first reset transistor T1 and the second reset transistor T2 are turned off; the reset control signal RE1 is low, the third reset transistor T7 is turned off; the data control signal DC is low, the data control transistor T6 is turned off.

[0160] During light-emitting phase t4, the light-emitting control signal EM is high, turning on the light-emitting control transistor T5; the data control signal DC is high, turning on the data control transistor T6; the reference control signal RE2 is low, turning off the first and second reset transistors T1 and T2; the reset control signal RE1 is low, turning off the third reset transistor T7; the scan signal Gate is low, turning off the write transistor T4; and under the action of the first capacitor C1, the data signal Data begins to be written to point N1. At this time, the voltage at node N1, i.e., the gate voltage of the driving transistor T3, Vg, is Vdata + Vld + VSS - (Vref - Vth); the voltage at node N3, i.e., the voltage at the first electrode of the driving transistor T3, Vs, is Vld + VSS. Therefore, the gate-source voltage difference Vgs of the driving transistor T3 is Vdata - Vref + Vth. Vld is the voltage of the light-emitting device LD, VSS is the voltage of the second power supply signal VSS input to the second electrode CAT of the light-emitting device LD, and Vdata is the voltage of the data signal Data.

[0161] The output current of the driving transistor T3 satisfies the following formula: I=(μWCox / 2L)(Vgs-Vth) 2 ;

[0162] I is the output current of the driving transistor T3; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the channel of the driving transistor T3, and L is the channel length of the driving transistor T3.

[0163] According to the above formula for the output current of the driving transistor T3, the gate-source voltage difference Vgs of the driving transistor T3 in the above pixel circuit is substituted into the above formula to obtain: the output current of the driving transistor T3 I = (μWCox / 2L)(Vdata-Vref) 2 It can be seen that the output current of the pixel circuit is independent of the threshold voltage Vth of the driving transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor T3 on its output current. The output current can be controlled by controlling the voltage Vdata of the data signal Data, so as to control the brightness of the light-emitting device LD.

[0164] In the above pixel circuit, the second capacitor C2 is used to store the threshold voltage Vth, and its capacitance affects the speed and effectiveness of the compensation of the threshold voltage Vth. The first capacitor C1 stores the voltage of the data signal Data, and its capacitance affects the speed of writing this voltage. Furthermore, during the light-emitting phase t4, the total capacitance between the gate and the first electrode of the driving transistor T3 is the capacitance of the first capacitor C1 and the second capacitor C2 in series.

[0165] After testing and analysis, to meet the needs of the circuit, the capacitance of the second capacitor C2 can be made not less than that of the first capacitor C1. Furthermore, the second capacitor C2 can be made larger than the first capacitor C1, and the ratio of the first capacitor C1 to the second capacitor C2 can be greater than 1 and less than 1.5.

[0166] It should be noted that although the steps of the driving method of the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0167] The structure of the display panel of the present disclosure is described below based on the pixel circuit of any of the above embodiments:

[0168] As shown in FIG4 , the driving backplane BP may include a substrate SU and a driving circuit provided on one side of the substrate SU. The driving circuit includes a pixel circuit and a peripheral circuit. The pixel circuit may be a structure of any of the above embodiments.

[0169] The driving backplane BP may further include a semiconductor layer SE, which is disposed on one side of the substrate SU. The active portions of each transistor in the pixel circuit are located in the semiconductor layer SE, i.e., the active portions of each transistor are disposed on the same layer. Light-emitting devices LD are disposed on a side of the semiconductor layer SE away from the substrate SU, and a first electrode ANO of each light-emitting device LD can be connected to the first electrode of a driving transistor T3 in a pixel circuit.

[0170] As shown in FIG5 to FIG7 and FIG16 to FIG18, in order to facilitate signal transmission, in some embodiments of the present disclosure, the display panel may further include an emission control line EML, a first reset control line REL1, a second reset control line REL2, a scan line GL, a data control line DCL, a first reset line VRL, and a second reset line VIL, wherein:

[0171] The emission control line EML extends along the row direction X and overlaps the active portion ACT5 of the emission control transistor T5 to transmit the emission control signal EM. There are multiple emission control lines EML, which are spaced apart along the column direction Y. Each pixel circuit in a row is connected to a single emission control line EML.

[0172] The first reset control line REL1 extends along the row direction X and overlaps the active portion ACT7 of the third reset transistor T7 to transmit a reset control signal RE1. There are multiple first reset control lines REL1, which are spaced apart along the column direction Y. Pixel circuits in the same row are connected to a first reset control line REL1.

[0173] The second reset control line REL2 can extend along the row direction X and be connected to the gates of the first reset transistor T1 and the second reset transistor T2 for transmitting a reference control signal RE2. Multiple second reset control lines REL2 are provided and spaced apart along the column direction Y. Pixel circuits in the same row are connected to a second reset control line REL2.

[0174] The scan line GL may extend along the row direction X and be connected to the gate of the write transistor T4 for transmitting a scan signal Gate. There are multiple scan lines GL, which are spaced apart along the column direction Y. Each pixel circuit in the same row is connected to a scan line GL.

[0175] The data control line DCL can extend along the row direction X and be connected to the gate of the data control transistor T6 for transmitting the data control signal DC. There are multiple data control lines DCL, which are spaced apart along the column direction Y. Each pixel circuit in the same row is connected to a data control line DCL.

[0176] A first reset line VRL can extend along the row direction X and be connected to the first electrode of the first reset transistor T1 and the first electrode of the second reset transistor T2 for transmitting a reference signal Vref. Multiple first reset lines VRL are provided and spaced apart along the column direction Y. Pixel circuits in the same row are connected to a first reset line VRL.

[0177] The second reset line VIL can extend along the row direction X and be connected to the first electrode of the third reset transistor T7 for transmitting the reset signal Vinit. There are multiple second reset lines VIL, which are spaced apart along the column direction Y. Pixel circuits in the same row are connected to a second reset line VIL.

[0178] Furthermore, as shown in Figures 5-7 and 16-18, in some embodiments of the present disclosure, the positive projections of the light-emitting control line EML, the scan line GL, the data control line DCL, the first reset line VRL, the second reset control line REL2, the first reset control line REL1 and the second reset line VIL on the substrate SU can be distributed in sequence along the column direction Y.

[0179] As shown in Figures 7, 8, 12, 18, 19, and 23, the orthographic projection of the active portion ACT3 of the drive transistor T3 on the substrate SU is located between the orthographic projections of the data control line DCL and the second reset control line REL2 on the substrate SU. The orthographic projections of the active portion ACT4 of the write transistor T4 and the first capacitor C1 on the substrate SU are at least partially located between the orthographic projections of the emission control line EML and the data control line DCL on the substrate SU. The orthographic projections of the active portions ACT1 and ACT2 of the first reset transistor T1 and the second reset transistor T2 on the substrate SU are located between the orthographic projections of the active portion ACT3 of the drive transistor T3 and the second reset control line REL2 on the substrate SU.

[0180] As shown in Figures 5, 16, 27, and 38, to provide a first power signal VDD to the pixel circuits, in some embodiments of the present disclosure, the display panel further includes a plurality of first power lines VDL, which may be disposed on a side of the pixel circuits away from the substrate SU. The first power lines VDL may extend along the column direction Y, and the first power lines VDL may be spaced apart along the row direction X. A first power line VDL overlaps a column of pixel circuits and is connected to the first electrode of the emission control transistor T5 of the pixel circuit in that column, thereby providing the first power signal VDD to the pixel circuits.

[0181] As shown in Figures 5, 6, 16, 17, 27, 28, 38, and 39, to reduce resistance, multiple first auxiliary power lines VDLs can be provided on the side of the pixel circuits facing away from the substrate SU. The first power lines VDL are located on the side of the first auxiliary power lines VDLS facing away from the substrate SU. Each first auxiliary power line VDLS can extend in the row direction X and be distributed in the column direction Y. A first auxiliary power line VDLS can be provided between two adjacent rows of pixel circuits. A first auxiliary power line VDLS is connected to the first electrode of the emission control transistor T5 in the row of pixel circuits adjacent to it. A first power line VDL and each first auxiliary power line VDLS are located on a different layer and connected through contact holes. The first power line VDL can be connected to the pixel circuits via the first auxiliary power lines VDLS. The first power line VDL and the first auxiliary power lines VDLS can form a network within the space to transmit the first power signal VDD, which helps reduce resistance.

[0182] As shown in Figures 5, 16, 27, and 38, to provide data signals Data to the pixel circuits, the display panel may further include multiple data lines DAL. These data lines DAL may be located on a side of the first auxiliary power line VDLS away from the substrate SU and may be arranged on the same layer as the first power line VDL. Each data line DAL may extend in the column direction Y and be spaced apart in the row direction X. A data line DAL overlaps a column of pixel circuits and is connected to the first electrode of the write transistor T4 in the column of pixel circuits to transmit the data signal Data.

[0183] As shown in Figures 5, 16, 27, and 38, in some embodiments of the present disclosure, the display panel further includes a plurality of second power lines VSL, which may be disposed on a side of the first auxiliary power line VDLS away from the substrate SU. Each second power line VSL extends along the column direction Y and is spaced apart along the row direction X. A second power line VSL may overlap with a column of pixel circuits, but the number of second power lines VSL may be less than the number of pixel circuit columns, i.e., only some columns of pixel circuits may overlap with a second power line VSL. The second power lines VSL are used to transmit a second power signal VSS.

[0184] The peripheral area WA of the display panel may also be provided with a first power bus and a second power bus. A first power line VDL may extend into the peripheral area WA and be connected to the first power bus. A first power signal VDD may be input to the first power line VDL via the first power bus. A second power line VSL may extend into the peripheral area WA and be connected to the second power bus. A second power signal VSS may be input to the second power line VSL via the second power bus. Each light-emitting device LD may share a common second electrode CAT. That is, the second electrode CAT may be a continuous, single-layer structure and may be connected to the second power bus in the peripheral area WA to receive the second power signal VSS. The second power line VSL reduces resistance and thus reduces the voltage drop of the second power signal VSS.

[0185] As shown in FIG. 27 , FIG. 37 , FIG. 38 , and FIG. 48 , in some embodiments of the present disclosure, the display panel further includes a plurality of first auxiliary reset lines VRLs and second auxiliary reset lines VILs, wherein:

[0186] The first auxiliary reset lines VRLs and the second auxiliary reset lines VILs can be arranged on a side of the first auxiliary power line VDLS away from the substrate SU, and the first auxiliary reset lines VRLs and the second auxiliary reset lines VILs can be arranged on the same layer. Each of the first auxiliary reset lines VRLs and the second auxiliary reset lines VILs extends in the column direction Y and is spaced apart in the row direction X.

[0187] The first auxiliary reset line VRLs can be located on a different layer from the first reset line VRL and can be connected via a contact hole. The first auxiliary reset line VRLs and the first reset line VRL can form a network within the space for transmitting the reference signal Vref, which helps reduce resistance. The second auxiliary reset line VILs can be located on a different layer from the second reset line VIL and can be connected via a contact hole. The second auxiliary reset line VILs and the second reset line VIL can form a network within the space for transmitting the reset signal Vinit, which helps reduce resistance.

[0188] A first auxiliary reset line VRLs may overlap with a column of pixel circuits, and a second auxiliary reset line VILs may overlap with a column of pixel circuits; however, the number of first auxiliary reset lines VRLs and second auxiliary reset lines VILs is less than the number of columns of pixel circuits, that is, only some columns of pixel circuits may overlap with the first auxiliary reset lines VRLs and the second auxiliary reset lines VILs.

[0189] In some embodiments of the present disclosure, as shown in Figures 27, 37, 38, and 48, the data line DAL and first power line VDL connected to the same column of pixel circuits PC can be defined as a column line group YG. That is, each column of pixel circuits PC can be connected to a column line group YG. Furthermore, one of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be provided between two adjacent column line groups YG. In other words, the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs are distributed in the space between the column line groups YG. Furthermore, two of the second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs can be provided on either side of the same column line group YG. This allows for full utilization of space and a more uniform distribution of the wiring in the column direction Y.

[0190] Furthermore, in a pixel circuit where a first power line VDL and its overlap occur, the first power line VDL overlaps with the active portion ACT4 of the write transistor T4, the active portion ACT4 of the data control transistor T6, the active portion ACT1 of the first reset transistor T1, and the active portion ACT2 of the second reset transistor T2. The second power line VSL overlaps with the active portion ACT5 of the light-emission control transistor T5, the active portion ACT3 of the drive transistor T3, and the active portion ACT7 of the third reset transistor T7. Because the first power line VDD, the second power line VSS, the reference signal Vref, and the reset signal Vinit are all constant voltage signals, they shield the transistors blocked by the first power line VDL and the second power line VSL, preventing interference from voltage changes on the first electrode ANO of the light-emitting device LD.

[0191] In some embodiments of the present disclosure, the emission control line EML, scan line GL, data control line DCL, second reset control line REL2, first reset line VRL, and first reset control line REL1 connected to the same row of pixel circuits can be defined as a row line group. That is, each row of pixel circuits PC is connected to a row line group. Furthermore, a first auxiliary power line VDLs and a second reset line VIL can be provided between two adjacent row line groups. A row line group is located between a first auxiliary power line VDLs and a second reset line VIL.

[0192] As shown in FIG13 and FIG14 , to reduce resistance, the light-emitting control line EML and the first reset control line REL1 can have a double-layer structure. For example, the light-emitting control line EML can include a first sub-light-emitting control line EML1 and a second sub-light-emitting control line EML2, which are arranged in a direction away from the substrate SU. The first sub-light-emitting control line EML1 and the second sub-light-emitting control line EML2 both extend in the row direction X and are connected. The orthographic projections of the first sub-light-emitting control line EML1 and the second sub-light-emitting control line EML2 on the substrate SU at least partially overlap.

[0193] The first reset control line REL1 may include a first sub-reset control line REL11 and a second sub-reset control line REL12 arranged in a direction away from the substrate SU. The first sub-reset control line REL11 and the second sub-reset control line REL12 both extend in the row direction X and are connected. The orthographic projections of the first sub-reset control line REL11 and the second sub-reset control line REL12 on the substrate SU at least partially overlap.

[0194] To simplify the structure and process, one of the first plate C11 and the second plate C12 of the first capacitor C1 can be placed on the same layer as one of the first plate C21 and the second plate C22 of the second capacitor C2. The co-located films can be formed simultaneously through the same patterning process, which helps simplify the structure and process. Furthermore, one of the first capacitor C1 and the second capacitor C2 can overlap with the active portion ACT3 of the drive transistor T3, allowing the capacitor plate to serve as the gate of the drive transistor T3, which also helps save space.

[0195] In some embodiments of the present disclosure, as shown in Figures 7, 8, 10-14, 18, 19 and 20-24, the first plate C11 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are arranged in the same layer and are distributed along the column direction Y; the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are arranged in the same layer and are an integrated structure. Of course, they can also be structures that are in the same layer but separated from each other; the first plate C21 and the second plate C22 of the second capacitor C2 overlap with the active portion ACT3 of the driving transistor T3.

[0196] By changing the width-to-length ratio of the driving transistor T3, the on-state current (Ion) can be increased or the subthreshold swing (SS) can be reduced. For example:

[0197] The first electrode, active portion ACT3, and second electrode of the driving transistor T3 may be distributed along the column direction Y. In the first embodiment of the present disclosure, the width of the active portion ACT3 of the driving transistor T3 along the row direction X may be increased to increase the width of the channel region, thereby increasing the aspect ratio and improving the on-state current. For example, the width of the channel region of the active portion ACT3 of the driving transistor T3 in the row direction X may be no less than 6 μm and no more than 20 μm, and the width may be 6 μm, 10 μm, 16 μm, or 20 μm, etc. In this case, the aspect ratio of the driving transistor T3 may be 16 / 6, 20 / 6, etc.

[0198] In the second embodiment of the present disclosure, the active portion ACT3 of the driving transistor T3 can be curved to increase the length of the channel region, thereby reducing the aspect ratio and lowering the subthreshold swing. For example, the length of the channel region of the active portion ACT3 of the driving transistor T3 in its extension direction is not less than 20 μm and not more than 30 μm. The length can be 20 μm, 25 μm, or 30 μm, etc. In this case, the aspect ratio of the driving transistor T3 can be 4 / 25, 4 / 30, etc.

[0199] Through the above two implementations, the width-to-length ratio of the driving transistor T3 can be limited to be no greater than 20 / 6 and no less than 4 / 30.

[0200] The channel region of each transistor herein is the region where its active portion overlaps with its gate.

[0201] The width-to-length ratio of the driving transistor T3 can be set by designing the pattern of the active portion ACT3 of the driving transistor T3. The following is an exemplary description using the pattern of the semiconductor layer corresponding to a pixel circuit as an example:

[0202] As shown in Figures 5 to 9, 12, 16 to 20, and 23, in some embodiments of the present disclosure, the semiconductor layer SE may include a first semiconductor portion SE1, a second semiconductor portion SE2, and a third semiconductor portion SE3 spaced apart along the row direction X; the second semiconductor portion SE2 is located between the first semiconductor portion SE1 and the third semiconductor portion SE3.

[0203] The active portions ACT4, ACT6, and ACT1 of the write transistor T4, data control transistor T6, and first reset transistor T1 are all located in the first semiconductor portion SE1 and are sequentially connected along the column direction Y. The active portion ACT2 of the second reset transistor T2 is located in the second semiconductor portion SE2. The active portion ACT5 of the light emission control transistor T5, the active portion ACT3 of the drive transistor T3, and the active portion ACT7 of the third reset transistor T7 are located in the third semiconductor portion SE3 and are sequentially connected along the column direction Y. The second semiconductor portion SE2 and the third semiconductor portion SE3 are connected, thereby connecting the first electrode of the first reset transistor T1 to the first electrode of the second reset transistor T2.

[0204] In the first embodiment described above, the third semiconductor portion SE3 includes a first semiconductor segment SE31 and a second semiconductor segment SE32 distributed along the column direction Y. The active portion ACT3 of the driver transistor T3 is connected between the first semiconductor segment SE31 and the second semiconductor segment SE32. Furthermore, the width of the active portion ACT3 of the driver transistor T3 in the row direction X is greater than the widths of the first semiconductor segment SE31 and the second semiconductor segment SE32 in the row direction X. Thus, by increasing the width of the third semiconductor portion SE3 in the row direction X, the channel width of the driver transistor T3 can be increased, thereby improving its aspect ratio.

[0205] The first semiconductor segment SE31 and the second semiconductor segment SE32 can extend linearly along the column direction Y. The active portion ACT3 of the driver transistor T3 can extend toward both sides of the first and second semiconductor segments SE31 and SE32 in the row direction X to maximize the channel width of the driver transistor T3. Alternatively, the active portion ACT3 can extend toward only one side. Furthermore, the active portions ACT3 on both sides of the first and second semiconductor segments SE31 and SE32 can be symmetrical or asymmetrical. Furthermore, the orthographic projection of the active portion ACT3 of the driver transistor T3 on the substrate SU can be rectangular, but may also have other shapes such as an ellipse.

[0206] In the second embodiment described above, the third semiconductor portion SE3 also includes a first semiconductor segment SE31 and a second semiconductor segment SE32 arranged along the column direction Y, and the active portion ACT3 of the driver transistor T3 is connected between the first semiconductor segment SE31 and the second semiconductor segment SE32. Unlike the first embodiment, the active portion ACT3 of the driver transistor T3 can bend toward and / or away from the first semiconductor portion SE1 along the row direction X. The term "bending" here refers to the driver transistor T3 extending along a curved or zigzag path. This path can be U-shaped, V-shaped, or wavy, and its shape is not particularly limited herein. Thus, by extending the length of a portion of the third semiconductor portion SE3, the channel length of the driver transistor T3 can be increased, thereby reducing the aspect ratio.

[0207] The first semiconductor segment SE31 and the second semiconductor segment SE32 can extend straight along the column direction Y. The active portion ACT3 of the driver transistor T3 can be bent toward one side of the first semiconductor segment SE31 and the second semiconductor segment SE32 in the row direction X, or can be bent toward both sides simultaneously, thereby maximizing the channel length of the driver transistor T3. Furthermore, if the active portion ACT3 is bent toward both sides, the active portions ACT3 on both sides of the first semiconductor segment SE31 and the second semiconductor segment SE32 can be symmetrical or asymmetrical.

[0208] The following is an exemplary description of the film layers and patterns of the driving backplane BP:

[0209] As shown in FIG4 and FIG5 , in some embodiments of the present disclosure, the display panel includes a light shielding layer BSM, a first gate layer GA1, a second gate layer GA2, a first source and drain layer SD1, and a second source and drain layer SD2, wherein:

[0210] As shown in Figure 10, a light shielding layer BSM is provided on one side of the substrate SU. The material of the light shielding layer BSM can be metal or other conductive and light shielding materials. The light shielding layer BSM can include the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2. That is, the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are provided in the same layer, and the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be connected to form an integrated structure.

[0211] As shown in Figures 9 and 11, the first gate layer GA1 can be disposed on a side of the light shielding layer BSM away from the substrate SU. The first gate layer GA1 can include a first plate C11 of a first capacitor C1, a second plate C22 of a second capacitor C2, a first sub-emission control line EML1, and a first sub-reset control line REL11. The semiconductor layer SE is disposed on a side of the first gate layer GA1 away from the substrate SU.

[0212] As shown in FIG. 7 and FIG. 13 , the second gate layer GA2 may be disposed on a side of the semiconductor layer SE away from the substrate SU, and include a second sub-emission control line EML2 and a second sub-reset control line REL12 .

[0213] As shown in Figures 6 and 14, the first source and drain layer SD1 can be arranged on the side of the second gate layer GA2 away from the substrate SU, and includes a first auxiliary power line VDLs, a scan line GL, a data control line DCL, a second reset control line REL2, a first reset line VRL and a second reset line VIL.

[0214] As shown in FIG5 and FIG15, the second source and drain layer SD2 may be provided on a side of the first source and drain layer SD1 away from the substrate SU, and include a data line DAL, a first power line VDL, a second power line VSL, a first auxiliary reset line VRLs, and a second auxiliary reset line VILs.

[0215] Furthermore, as shown in FIG4 , in some embodiments of the present disclosure, the display panel may further include insulating film layers, including a buffer layer BUF, a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer dielectric layer ILD, a passivation layer, a first planar layer PLN1, and a second planar layer PLN2, wherein:

[0216] The buffer layer BUF can cover the light-shielding layer BSM; the first gate layer GA1 is arranged on the surface of the buffer layer BUF away from the substrate SU; the first gate insulating layer GI1 covers the first gate layer GA1; the semiconductor layer SE is arranged on the surface of the first gate insulating layer GI1 away from the substrate SU; the second gate insulating layer GI2 covers the semiconductor layer SE; the second gate layer GA2 is arranged on the surface of the second gate insulating layer GI2 away from the substrate SU; the interlayer dielectric layer ILD covers the second gate layer GA2; the first source and drain layer SD1 is arranged on the surface of the interlayer dielectric layer ILD away from the substrate SU; the passivation layer covers the first source and drain layer SD1, and the first flat layer PLN1 covers the passivation layer. Of course, the passivation layer may not be provided, and the first flat layer PLN1 directly covers the first source and drain layer SD1; the second source and drain layer SD2 is arranged on the surface of the first flat layer PLN1 away from the substrate SU; the second flat layer PLN2 covers the second source and drain layer SD2. The first electrode ANO of the light-emitting device LD is arranged on the surface of the second flat layer PLN2 away from the substrate SU, and can be separated by the pixel definition layer PDL. Specifically, the pixel definition layer PDL and the first electrode ANO are arranged on the surface of the second flat layer PLN2 away from the substrate SU, and the pixel definition layer PDL is provided with a pixel opening exposing the first electrode ANO, and the light-emitting layer EL is at least partially arranged in the pixel opening.

[0217] The following is a further description of the patterns of some film layers:

[0218] At least a portion of the transistors in the pixel circuit may include a gate (bottom gate) located on the side of the active portion close to the substrate SU and a gate (top gate) located on the side of the active portion away from the substrate SU, and the bottom gate and top gate of at least some of the transistors are connected, for example, the bottom gate and top gate of the first reset transistor T1, the second reset transistor T2, the third reset transistor T7, the write transistor T4, the light emitting control transistor T5, and the data control transistor T6 are connected, and the first electrode of the driving transistor T3 is connected to at least one of the top gate and the bottom gate.

[0219] Light-shielding layer BSM

[0220] As shown in Figures 7-10, 18-21, 32, and 43, in some embodiments of the present disclosure, the light-shielding layer BSM of a pixel circuit includes a second plate C12 of a first capacitor C1 and a first plate C21 of a second capacitor C2, and the second plate C12 and the first plate C21 can be connected into an integral structure to achieve the series connection of the first capacitor C1 and the second capacitor C2.

[0221] The second plate C12 of the first capacitor C1 includes a first blocking portion BS2 that extends from the first blocking body BS1 in the row direction X. This increases the area of ​​the second plate C12, thereby facilitating an increase in the capacitance of the first capacitor C1. The first blocking portion BS2 overlaps the first semiconductor portion SE1, and its orthographic projection on the substrate SU is located between the active portion ACT4 of the write transistor T4 and the active portion ACT6 of the data control transistor T6.

[0222] The first plate C21 of the second capacitor C2 can overlap with the active portion ACT3 of the driving transistor T3. The orthographic projection of the active portion ACT3 on the substrate SU is located within the orthographic projection of the first plate C21 on the substrate SU. The second capacitor C2 shields the driving transistor T3, preventing light from reaching the active portion ACT3 of the driving transistor T3. The first plate C21 of the second capacitor C2 has a second shielding body BS3 and a second shielding portion BS4 extending along the column direction Y. The second shielding portion BS4 can overlap with the third semiconductor portion SE3.

[0223] The first plate C21 of the second capacitor C2 may further include a third shielding portion BS5 formed by extending the edge of the second shielding portion BS4 along the row direction X. The orthographic projection of the third shielding portion BS5 on the substrate SU is located between the orthographic projections of the first reset line VRL and the second reset control line REL2 on the substrate SU, and between the orthographic projections of the first semiconductor portion SE1 and the third semiconductor portion SE3 on the substrate SU. The second shielding portion BS4 and the third shielding portion BS5 increase the area of ​​the first plate C21 of the second capacitor C2, thereby increasing the capacitance of the second capacitor C2.

[0224] As shown in Figures 7 to 10, for the first type of implementation described above, the second blocking body BS3 has two blocking sides BSL extending along the row direction X and distributed along the column direction Y, which can overlap with the active portion ACT3 of the driving transistor T3 in the row direction X, thereby blocking the active portion ACT3.

[0225] As shown in Figures 18-21 , for the second embodiment described above, the second blocking body BS3 protrudes toward the first semiconductor portion SE1, and the protruding portion has two blocking side edges BSL distributed along the column direction Y. The spacing between the two blocking side edges BSL decreases as it approaches the first semiconductor portion SE1, such that the extension directions of the two blocking side edges BSL intersect both the row direction X and the column direction Y. The second blocking body BS3 can overlap the active portion ACT3 of the driving transistor T3, thereby shielding the active portion ACT3.

[0226] First gate layer GA1

[0227] As shown in Figures 5-9, 11, 16-20, 22, 33, and 44, in some embodiments of the present disclosure, the first gate layer GA1 can be used to form the gate of at least part of the transistor, and it may also include a first gate portion GA41, a second gate portion GA61, a third gate portion GA31, and a fourth gate portion GA11; the first sub-light-emitting control line EML1, the first plate C11 of the first capacitor C1, the second plate C22 of the second capacitor C2, and the first sub-reset control line REL11 can be distributed in sequence along the column direction Y. The first gate portion GA41, the second gate portion GA61, the third gate portion GA31, and the fourth gate portion GA11 are distributed along the column direction Y between the first sub-light-emitting control line EML1 and the first sub-reset control line REL11; the first gate portion GA41, the second gate portion GA61, and the third gate portion GA31 are located between the first sub-light-emitting control line EML1 and the second plate C22 of the second capacitor C2, and the second gate portion GA61 is located between the first gate portion GA41 and the third gate portion GA31; the fourth gate portion GA11 is located between the third gate portion GA31 and the first sub-reset control line REL11, and is distributed along the row direction X with the second plate C22 of the second capacitor C2; wherein:

[0228] The first gate portion GA41 overlaps with the active portion ACT4 of the write transistor T4 to form the gate of the write transistor T4 (the bottom gate of the write transistor T4 ).

[0229] The second gate portion GA61 overlaps the active portion ACT6 of the data control transistor T6 to form a gate of the data control transistor T6 (a bottom gate of the data control transistor T6 ).

[0230] The third gate portion GA31 is connected to the second plate C22 of the second capacitor C2 and can be an integral structure. The third gate portion GA31 can also be considered as a part of the second plate C22 of the second capacitor C2, that is, the second plate C22 includes the third gate portion GA31. At the same time, the third gate portion GA31 can overlap with the active portion ACT3 of the driving transistor T3 to form the gate of the driving transistor T3 (the bottom gate of the driving transistor T3). The length of the third gate portion GA31 in the row direction X is not less than the length of the active portion ACT3 of the driving transistor T3 in the row direction X, that is, the width of the channel of the driving transistor T3.

[0231] The fourth gate portion GA11 overlaps the active portions ACT1 and ACT2 of both the first and second reset transistors T1 and T2 to form gates of the first and second reset transistors T1 and T2 (bottom gates of the first and second reset transistors T1 and T2 ).

[0232] Furthermore, in order to increase the capacity of the first capacitor C1, the first gate layer GA1 may further include a first capacitor extension portion GL1 and a second capacitor extension portion GL2, wherein:

[0233] The first capacitor extension GL1 can extend along the extension path of the first blocking portion BS2 and be connected to or integrally formed with the first electrode plate C11. The first capacitor extension GL1 overlaps with the first blocking portion BS2, thereby forming a portion of the first capacitor C1. The orthographic projection of the first capacitor extension GL1 on the substrate SU is located within the orthographic projection of the first blocking portion BS2 on the substrate SU, so that the first capacitor extension GL1 does not extend beyond the boundary of the first blocking portion BS2.

[0234] The second capacitor extension GL2 can extend along the extension path of the second shielding portion BS4 and the third shielding portion BS5 and be connected to or integrally formed with the third gate portion GA31. The second capacitor extension GL2 overlaps with the second shielding portion BS4 and the third shielding portion BS5, thereby forming a portion of the second capacitor C2. The orthographic projection of the second capacitor extension GL2 on the substrate SU is located within the orthographic projections of the second shielding portion BS4 and the third shielding portion BS5 on the substrate SU, so that the second capacitor extension GL2 does not extend beyond the boundary of the second shielding portion BS4 and the third shielding portion BS5.

[0235] As shown in Figures 5-9 and 12 , for the first embodiment described above, the profile of the third gate portion GA31 can be the same as that of the second blocking body BS3, that is, the third gate portion GA31 extends along the row direction X. The third gate portion GA31 has two gate side edges GAL distributed along the column direction Y and extending along the row direction X. The third gate portion GA31 can overlap with the active portion ACT3 of the driving transistor T3 in the row direction X and be located within the boundary of the second blocking body BS3.

[0236] As shown in Figures 16-20 and 22 , for the second embodiment described above, the profile of the third gate portion GA31 can be the same as that of the second shielding body BS3. The third gate portion GA31 also protrudes toward the first semiconductor portion SE1, and the protruding portion has two gate side edges GAL distributed along the column direction Y. The spacing between the two gate side edges GAL decreases as it approaches the first semiconductor portion SE1, such that the extension direction of the two gate side edges GAL intersects both the row direction X and the column direction Y. The third gate portion GA31 can overlap the active portion ACT3 of the drive transistor T3 and be located within the boundary of the second shielding body BS3.

[0237] Semiconductor layer SE

[0238] As shown in Figures 5 to 9, 12, 16 to 20, 23, 34, and 45, in some embodiments of the present disclosure, the semiconductor layer SE may include a first semiconductor portion SE1, a second semiconductor portion SE2, and a third semiconductor portion SE3 spaced apart along the row direction X. The specific patterns have been described above and will not be described in detail here.

[0239] The second gate layer GA2

[0240] As shown in Figures 5 to 9, 13, 16 to 20, 24, 35, and 46, in some embodiments of the present disclosure, the second gate layer GA2 may further include a fifth gate portion GA42, a sixth gate portion GA62, a seventh gate portion GA32, and an eighth gate portion GA12; the second sub-light emitting control line EML2, the fifth gate portion GA42, the sixth gate portion GA62, the seventh gate portion GA32, the eighth gate portion GA12, and the second sub-reset control line REL12 may be sequentially distributed along the column direction Y, and the fifth gate portion GA42, the sixth gate portion GA62, the seventh gate portion GA32, and the eighth gate portion GA12 are located between the second sub-light emitting control line EML2 and the second sub-reset control line REL12; wherein:

[0241] The fifth gate portion GA42 overlaps with the active portion ACT4 of the write transistor T4 and is connected to the first gate portion GA41 to form the gate of the write transistor T4 (the top gate of the write transistor T4). At the same time, the orthographic projection of the region where the fifth gate portion GA42 overlaps with the active portion ACT4 of the write transistor T4 on the substrate SU is located within the orthographic projection of the region where the first gate portion GA41 overlaps with the active portion ACT4 of the write transistor T4 on the substrate SU.

[0242] The sixth gate portion GA62 overlaps with the active portion ACT6 of the data control transistor T6 and is connected to the second gate portion GA61 to form the gate of the data control transistor T6 (the top gate of the data control transistor T6). At the same time, the orthographic projection of the region where the sixth gate portion GA62 overlaps with the active portion ACT6 of the data control transistor T6 on the substrate SU is located within the orthographic projection of the region where the second gate portion GA61 overlaps with the active portion ACT6 of the data control transistor T6 on the substrate SU.

[0243] The seventh gate portion GA32 overlaps with the active portion ACT3 of the drive transistor T3 to form the gate of the drive transistor T3 (the top gate of the drive transistor T3). The length of the seventh gate portion GA32 in the row direction X is not less than the length of the active portion ACT3 of the drive transistor T3 in the row direction X, that is, the width of the channel of the drive transistor T3. At the same time, the orthographic projection of the area where the seventh gate portion GA32 overlaps with the active portion ACT3 of the drive transistor T3 on the substrate SU is located within the orthographic projection of the area where the third gate portion GA31 overlaps with the active portion ACT3 of the drive transistor T3 on the substrate SU; the channel region of the drive transistor T3 is the area where the active portion ACT3 overlaps with the seventh gate portion GA32.

[0244] The eighth gate portion GA12 overlaps with the active portion ACT1 of the first reset transistor T1 and the active portion ACT2 of the second reset transistor T2, and is connected to the fourth gate portion GA11 to form the gates of the first reset transistor T1 and the second reset transistor T2 (top gates of the first reset transistor T1 and the second reset transistor T2). Simultaneously, the orthographic projection on the substrate SU of the region where the eighth gate portion GA12 overlaps with the active portion ACT1 of the first reset transistor T1 is located within the orthographic projection on the substrate SU of the region where the fourth gate portion GA11 overlaps with the active portion ACT1 of the first reset transistor T1; and the orthographic projection on the substrate SU of the region where the eighth gate portion GA12 overlaps with the active portion ACT2 of the second reset transistor T2 is located within the orthographic projection on the substrate SU of the region where the fourth gate portion GA11 overlaps with the active portion ACT2 of the second reset transistor T2.

[0245] First source and drain layer SD1

[0246] As shown in Figures 5 to 9, 14, 16 to 20, 25, 36, and 47, in some embodiments of the present disclosure, the first source / drain layer SD1 may include a first connection portion SL1, a second connection portion SL2, a third connection portion SL3, a fourth connection portion SL4, and a fifth connection portion SL5; the first auxiliary power line VDLs, the scan line GL, the data control line DCL, the second reset control line REL2, and the second reset line VIL may be sequentially distributed along the column direction Y. The first reset line VRL at least partially overlaps with the first reset control line REL1. For example, the first reset line VRL is located between the second reset line VIL and the second reset control line REL2, and partially overlaps with the first reset control line REL1.

[0247] The first connection portion SL1 is located between the first auxiliary power line VDLs and the scan line GL; the first connection portion SL1 is connected to the data line DAL and the first electrode of the write transistor T4 through the contact hole, and the data line DAL can transmit the data signal Data to the first electrode of the write transistor T4 through the first connection portion SL1.

[0248] The second connection portion SL2 is located between the scan line GL and the data control line DCL. One end of the second connection portion SL2 is connected to the first plate C11 of the first capacitor C1 through a contact hole, and the other end is connected through a contact hole to the region of the first semiconductor portion SE1 between the active portion ACT4 of the write transistor T4 and the active portion ACT6 of the data control transistor T6. This connects the first plate C11 of the first capacitor C1 to the first electrode of the write transistor T4 and the first electrode of the data control transistor T6, thereby transmitting the data signal Data. The second connection portion SL2 serves as the N5 node of the pixel circuit.

[0249] The third connection portion SL3 is located between the data control line DCL and the second reset control line REL2. One end of the third connection portion SL3 is connected to the seventh gate portion GA32 through a contact hole, and the other end is connected to the region of the first semiconductor portion SE1 between the active portion ACT1 of the first reset transistor T1 and the active portion ACT6 of the data control transistor T6 through a contact hole. Thus, the gate (top gate) of the drive transistor T3, the second electrode of the data control transistor T6, and the second electrode of the first reset transistor T1 are connected through the third connection portion SL3 to transmit the data signal Data and the reference signal Vref. The third connection portion SL3 serves as the N1 node of the pixel circuit.

[0250] The fourth connection part SL4 is located between the third connection part SL3 and the second reset control line REL2; the fourth connection part SL4 is connected to one end of the second semiconductor part SE2 close to the driving transistor T3 and the first electrode C21 of the second capacitor C2 through a contact hole, thereby connecting the second electrode of the second reset transistor T2 to the first electrode C21 of the second capacitor C2 to transmit the reference signal Vref.

[0251] The fifth connection part SL5 is located between the second reset line VIL and the second reset control line REL2; one end of the fifth connection part SL5 is connected to the second electrode plate C22 of the second capacitor C2 through a contact hole, and the other end is connected to the area between the active part ACT3 of the driving transistor T3 and the active part ACT7 of the third reset transistor T7 in the third semiconductor part SE3 through a contact hole, thereby connecting the first electrode of the driving transistor T3, the second electrode plate C22 of the second capacitor C2 and the second electrode of the third reset transistor T7 to transmit the reset signal Vinit.

[0252] The first auxiliary power line VDLs is connected through a contact hole to an end of the third semiconductor portion SE3 located at the active portion ACT5 of the emission control transistor T5, away from the active portion ACT3 of the drive transistor T3. This connects the first auxiliary reset line VRLs to the first electrode of the emission control transistor T5 to transmit the first power signal VDD. Simultaneously, the first auxiliary power line VDLs is connected to the first electrode of the emission control transistor T5 in the same row of pixel circuits.

[0253] The scan line GL is connected to the first gate portion GA41 and the fifth gate portion GA42 through the contact hole, and can transmit the scan signal Gate to the bottom gate and the top gate of the write transistor T4 at the same time.

[0254] The data control line DCL is connected to the second gate portion GA61 and the sixth gate portion GA62 through the contact hole, and can simultaneously transmit the data control signal DC to the bottom gate and the top gate of the data control transistor T6.

[0255] The second reset control line REL2 is connected to the fourth gate portion GA11 and the eighth gate portion GA12 through the contact hole, and can simultaneously transmit the reference control signal RE2 to the bottom gate and the top gate of the first reset transistor T1 and the second reset transistor T2.

[0256] As shown in Figures 5 to 9, 14, 16 to 20, 25, 27 to 31, 36, 38 to 42, and 47, the first reset line VRL is connected to one end of the first semiconductor portion SE1 away from the driving transistor T3, thereby being connected to the first electrodes of the first reset transistor T1 and the second reset transistor T2 at the same time. The reference signal Vref can be transmitted to the first reset transistor T1 and the second reset transistor T2 at the same time through the first reset line VRL.

[0257] The second reset line VIL is connected to an end of the third semiconductor portion SE3 away from the driving transistor T3 through a contact hole, and is thereby connected to a first electrode of the third reset transistor T7 to transmit a reset signal Vinit.

[0258] Second source and drain layer SD2

[0259] As shown in Figures 5-9, 15, 16-20, 26, 27-31, 37, 38-42, and 48, in some embodiments of the present disclosure, the second source and drain layer SD2 may include the aforementioned data line DAL, the first power line VDL, and the second power line VSL, and may also include a first auxiliary reset line VRLs and a second auxiliary reset line VILs.

[0260] The data line DAL and the first power line VDL connected to the same pixel circuit form a column line group YG, overlapping the pixel circuit. For example:

[0261] The data line DAL overlaps the first connection portion SL1, the first gate portion GA41, the fifth gate portion GA42, the sixth gate portion GA62, the fourth gate portion GA11, and the eighth gate portion GA12. The data line DAL may be connected to the first connection portion SL1 through a contact hole to transmit the data signal Data to the first electrode of the write transistor T4 through the first connection portion SL1.

[0262] The first power line VDL overlaps the first semiconductor portion SE1 and the second semiconductor portion SE2, and also overlaps the active portion ACT4 of the write transistor T4, the active portion ACT6 of the data control transistor T6, the active portion ACT1 of the first reset transistor T1, and the active portion ACT2 of the second reset transistor T2. This allows the first power line VDL to shield the channels of the write transistor T4, the data control transistor T6, the first reset transistor T1, and the second reset transistor T2. Furthermore, because the first power signal VDD is a constant voltage signal, this reduces interference from signal variations on the side of the first power line VDL away from the substrate SU on the transistors shielded by the first power line VDL. Furthermore, the first power line VDL can be connected to the first auxiliary power line VDLs via contact holes, thereby forming a network for transmitting the first power signal VDD. This helps reduce impedance and ensures a uniform voltage for the first power signal VDD.

[0263] The second power line VSL, the first auxiliary reset line VRLs, and the second auxiliary reset line VILs overlap with different pixel circuits, respectively. For example, among three adjacent pixel circuits in the row direction X, the three pixel circuits are respectively connected to one column line group YG, one pixel circuit overlaps with one second power line VSL, one pixel circuit overlaps with one first auxiliary reset line VRLs, and one pixel circuit overlaps with one second auxiliary reset line VILs. For the second power line VSL, the first auxiliary reset line VRLs, the second auxiliary reset line VILs, and the pixel circuits overlapping with each other:

[0264] The second power line VSL overlaps with the third semiconductor portion SE3 and also overlaps with the active portion ACT5 of the emission control transistor T5, the active portion ACT3 of the drive transistor T3, and the active portion ACT7 of the third reset transistor T7. Because the second power signal VSS is a constant voltage signal, signal variations on the side of the second power line VSL away from the substrate SU can be reduced from interfering with transistors shielded by the second power line VSL. Furthermore, within the display area AA, the second power line VSL is not connected to the second electrode CAT of the light-emitting device LD, nor is it directly connected to the transistors of the pixel circuit. Instead, it is connected to the second power bus in the peripheral area WA, which helps reduce impedance and ensures a uniform voltage across the second power signal VSS.

[0265] The first auxiliary reset line VRLs overlaps the third semiconductor portion SE3 and also overlaps the active portion ACT5 of the emission control transistor T5, the active portion ACT3 of the drive transistor T3, and the active portion ACT7 of the third reset transistor T7. Because the reference signal Vref is a constant voltage signal, signal variations on the side of the first auxiliary reset line VRLs away from the substrate SU can be reduced from interfering with transistors shielded by the first auxiliary reset line VRLs. Furthermore, the first auxiliary reset line VRLs is connected to the first reset line VRL via a contact hole, forming a network for transmitting the reference signal Vref. This helps reduce impedance and ensures a uniform voltage across the reference signal Vref.

[0266] The second auxiliary reset line VILs overlaps with the third semiconductor portion SE3 and also overlaps with the active portion ACT5 of the emission control transistor T5, the active portion ACT3 of the drive transistor T3, and the active portion ACT7 of the third reset transistor T7. Because the reset signal Vinit is a constant voltage signal, signal variations on the side of the second auxiliary reset line VILs away from the substrate SU can be reduced from interfering with transistors shielded by the second auxiliary reset line VILs. Furthermore, the second auxiliary reset line VILs is connected to the second reset line VIL via a contact hole, forming a network for transmitting the reset signal Vinit. This helps reduce impedance and ensures a uniform voltage across the reset signal Vinit.

[0267] In addition, as shown in Figures 5 and 16, in some embodiments of the present disclosure, for any pixel circuit, the second source-drain layer SD2 may further include a sixth connection portion SL6, which is located between the first power line VDL and the adjacent second power line VSL, second auxiliary reset line VILs, or first auxiliary reset line VRLs. Simultaneously, the sixth connection portion SL6 may be connected to the fifth connection portion SL5 via a contact hole, and may also be connected to the first electrode ANO of the light-emitting device LD via the contact hole, thereby simultaneously connecting the second electrode of the third reset transistor T7 and the first electrode of the drive transistor T3 to the first electrode ANO of the light-emitting device LD.

[0268] The present disclosure further provides a display device, which may include a display panel. The display panel may be any of the above-described embodiments. The specific structure and beneficial effects of the display panel may be referenced above with respect to the embodiments of the display panel and will not be described in detail here. The display device of the present disclosure may be a mobile phone, tablet computer, television, or other electronic device with a display function, such as a smartwatch, smart glasses, or an in-vehicle display, which will not be enumerated here.

[0269] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, comprising a plurality of pixel circuits arranged in an array along a row direction and a column direction, wherein the pixel circuit comprises a plurality of transistors, a first capacitor and a second capacitor, and each of the transistors comprises a driving transistor, a writing transistor, a light emitting control transistor, a first reset transistor, a second reset transistor and a third reset transistor; The first electrode of the light-emitting control transistor is used to receive a first power supply signal, and the second electrode of the light-emitting control transistor is connected to the second electrode of the driving transistor; the first electrode of the writing transistor is used to receive a data signal, and the second electrode of the writing transistor is connected to the gate of the driving transistor and the first electrode plate of the first capacitor, the second electrode plate of the first capacitor is connected to the first electrode plate of the second capacitor, and the second electrode plate of the second capacitor is connected to the first electrode of the driving transistor; The first electrode of the first reset transistor and the first electrode of the second reset transistor are used to receive a reference signal, and the second electrode of the first reset transistor is connected to the gate of the driving transistor; the second electrode of the second reset transistor is connected to the second electrode plate of the first capacitor and the first electrode plate of the second capacitor; the first electrode of the third reset transistor is used to receive a reset signal, and the second electrode of the third reset transistor is connected to the first electrode of the driving transistor and the second electrode plate of the second capacitor; The display panel comprises: substrate; A semiconductor layer, disposed on one side of the substrate and including an active portion of each of the transistors; A plurality of light emitting devices are arranged on a side of the semiconductor layer away from the substrate, and one of the light emitting devices is connected to a first electrode of a driving transistor of the pixel circuit; One of the first plate and the second plate of the first capacitor is arranged in the same layer as one of the first plate and the second plate of the second capacitor; and one of the first capacitor and the second capacitor overlaps with the active portion of the driving transistor.

2. The display panel according to claim 1, wherein: The first plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer and distributed along the column direction; the second plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer and are an integrated structure; the first plate and the second plate of the second capacitor overlap with the active part of the driving transistor.

3. The display panel according to claim 2, wherein: The pixel circuit further includes a data control transistor, a first electrode of the data control transistor is connected to a second electrode of the write transistor and a first electrode plate of the first capacitor, and a second electrode of the data control transistor is connected to a gate electrode of the drive transistor.

4. The display panel according to claim 3, wherein: The semiconductor layer comprises a first semiconductor portion, a second semiconductor portion and a third semiconductor portion which are spaced apart along the row direction; the second semiconductor portion is located between the first semiconductor portion and the third semiconductor portion, and the first semiconductor portion is connected to the second semiconductor portion; The active parts of the write transistor, the data control transistor and the first reset transistor are all located in the first semiconductor part and are sequentially connected along the column direction; the active part of the second reset transistor is located in the second semiconductor part; Active portions of the light emission control transistor, the drive transistor, and the third reset transistor are located in the third semiconductor portion and are sequentially connected along the column direction.

5. The display panel according to claim 4, wherein: The third semiconductor portion includes a first semiconductor segment and a second semiconductor segment distributed along the column direction; the active portion of the driving transistor is connected between the first semiconductor segment and the second semiconductor segment; The width of the active portion of the driving transistor in the row direction is greater than the width of the first semiconductor segment and the second semiconductor segment in the row direction.

6. The display panel according to claim 5, wherein: The width of the active portion of the driving transistor in the row direction is not less than 6 μm and not more than 20 μm.

7. The display panel according to claim 4, wherein: The third semiconductor portion includes a first semiconductor segment and a second semiconductor segment distributed along the column direction; the active portion of the driving transistor is connected between the first semiconductor segment and the second semiconductor segment; The active portion of the driving transistor is bent toward and / or away from the first semiconductor portion along the row direction.

8. The display panel according to claim 7, wherein: The length of the active portion of the driving transistor in the extending direction thereof is not less than 20 μm and not more than 30 μm.

9. The display panel according to claim 1, wherein: The width-to-length ratio of the driving transistor is not greater than 20 / 6 and not less than 4 / 30.

10. The display panel according to claim 4, wherein: The first plate and the second plate of the first capacitor overlap the third semiconductor portion and the first semiconductor portion.

11. The display panel according to claim 1, wherein: The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

12. The display panel according to claim 4, wherein: The display panel further includes: a light emitting control line extending along the row direction and overlapping with the active portion of the light emitting control transistor, and used for transmitting a light emitting control signal; a first reset control line extending along the row direction and overlapping with the active portion of the third reset transistor, for transmitting a reset control signal; a second reset control line connected to the gates of the first reset transistor and the second reset transistor, and used for transmitting a reference control signal; A scanning line extending along the row direction and connected to the gate of the write transistor for transmitting a scanning signal; A data control line extending along the row direction and connected to the gate of the data control transistor for transmitting a data control signal; a first reset line extending along the row direction and connected to a first electrode of the first reset transistor and a first electrode of the second reset transistor, and used for transmitting the reference signal; The second reset line extends along the row direction and is connected to the first electrode of the third reset transistor for transmitting the reset signal.

13. The display panel according to claim 12, wherein: The orthographic projections of the light emitting control line, the scan line, the data control line, the second reset control line, the first reset control line and the second reset line on the substrate are sequentially spaced along the column direction; the first reset line overlaps the first reset control line; The orthographic projection of the active portion of the driving transistor on the substrate is located between the orthographic projections of the data control line and the second reset control line on the substrate; The orthographic projections of the active portion of the write transistor and the first capacitor on the substrate are at least partially located between the orthographic projections of the light emitting control line and the data control line on the substrate; Orthographic projections of active portions of the first reset transistor and the second reset transistor on the substrate are located between orthographic projections of the data control line and the first reset control line on the substrate.

14. The display panel according to claim 13, wherein: The display panel further includes: A plurality of first auxiliary power lines extending along the row direction and distributed along the column direction; a first auxiliary power line is provided between two adjacent rows of pixel circuits; the first auxiliary power line is connected to a first electrode of a light emitting control transistor of the pixel circuit on one side thereof; A plurality of first power lines are arranged on a side of the first auxiliary power line away from the substrate, each of the first power lines extends along the column direction and is spaced apart along the row direction; one first power line is connected to each of the first auxiliary power lines and overlaps with a column of the pixel circuits; A plurality of data lines are arranged on a side of the first auxiliary power line away from the substrate, each of the data lines extends along the column direction and is spaced apart along the row direction; one of the data lines overlaps with a column of the pixel circuits and is connected to the first electrode of the write transistor for transmitting the data signal.

15. The display panel according to claim 14, characterized in that: The display panel further includes: A plurality of second power lines, a first auxiliary reset line, and a second auxiliary reset line extending along the column direction and distributed along the row direction, and arranged on a side of the first auxiliary power line away from the substrate; the second power line is used to transmit a second power signal, the first auxiliary reset line is connected to the first reset line, and the second auxiliary reset line is connected to the second reset line; The first power line and the data line connected to the pixel circuits in the same column are defined as a line group, and the second power line, the first auxiliary reset line and one of the second auxiliary reset line are arranged between two adjacent line groups; The light emitting device has a first electrode and a second electrode, the first electrode is connected to the first electrode of the driving transistor, and the second electrode is connected to the second power line.

16. The display panel according to claim 15, characterized in that: The light emitting control line comprises a first sub-light emitting control line and a second sub-light emitting control line arranged in a direction away from the substrate, wherein the first sub-light emitting control line and the second sub-light emitting control line are both extended and connected along the row direction; The first reset control line includes a first sub-reset control line and a second sub-reset control line arranged in a direction away from the substrate, and the first sub-reset control line and the second sub-reset control line are both extended and connected in the row direction.

17. The display panel according to claim 16, characterized in that: The display panel further includes: A light shielding layer, provided on one side of the substrate, and comprising a second electrode plate of the first capacitor and a first electrode plate of the second capacitor; a first gate layer, which is disposed on a side of the light shielding layer away from the substrate and includes a first plate of the first capacitor, a second plate of the second capacitor, the first sub-light emitting control line and the first sub-reset control line; and the semiconductor layer is disposed on a side of the first gate layer away from the substrate; A second gate layer is provided on a side of the semiconductor layer away from the substrate and includes the second sub-light emitting control line and the second sub-reset control line; a first source-drain layer, disposed on a side of the second gate layer away from the substrate, and comprising the first auxiliary power line, the scan line, the data control line, the second reset control line, the first reset line and the second reset line; The second source-drain layer is disposed on a side of the first source-drain layer away from the substrate, and includes the data line, the first power line, the second power line, the first auxiliary reset line and the second auxiliary reset line.

18. The display panel according to claim 17, characterized in that: The first gate layer further includes: a first gate portion overlapping the active portion of the write transistor to form a gate of the write transistor; a second gate portion overlapping the active portion of the data control transistor to form a gate of the data control transistor; and a first plate of the second capacitor including a third gate portion; A fourth gate portion overlaps the active portions of the first reset transistor and the second reset transistor to form gates of the first reset transistor and the second reset transistor.

19. The display panel according to claim 18, characterized in that: The second gate layer comprises: a fifth gate portion overlapping the active portion of the write transistor and connected to the first gate portion to form a gate of the write transistor; a sixth gate portion overlapping the active portion of the data control transistor and connected to the second gate portion to form a gate of the data control transistor; A seventh gate portion overlaps with the active portion of the driving transistor and overlaps with the third gate The gate of the driving transistor is connected to the transistor; An eighth gate portion overlaps with active portions of the first reset transistor and the second reset transistor and is connected to the fourth gate portion to form gates of the first reset transistor and the second reset transistor.

20. The display panel according to claim 19, characterized in that: The first source-drain layer comprises: a first connecting portion, located between the first auxiliary power line and the scan line, and connected to the data line and the first electrode of the write transistor; a second connecting portion, located between the scan line and the data control line, and connected to the first plate of the first capacitor and a region of the first semiconductor portion located between the active portion of the write transistor and the active portion of the data control transistor; a third connection portion, located between the data control line and the second reset control line, and connected to the seventh gate portion and a region of the first semiconductor portion located between an active portion of the first reset transistor and an active portion of the data control transistor; a fourth connection portion, located between the third connection portion and the second reset control line, and connected to the first electrode plate of the second capacitor and one end of the second semiconductor portion close to the active portion of the driving transistor; and one end of the second semiconductor portion far from the active portion of the driving transistor is connected to the first semiconductor portion; The fifth connection portion is located between the first reset control line and the second reset control line and is connected to the second plate of the second capacitor and a region of the third semiconductor portion located between the active portion of the driving transistor and the active portion of the third reset transistor.

21. The display panel according to any one of claims 1 to 20, characterized in that: The material of the semiconductor layer includes metal oxide.

22. A display device comprising the display panel according to any one of claims 1 to 21.

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