Inkjet head driving circuit

Abstract

The invention provides an ink jet head driving circuit capable of suppressing generation of unnecessary high-frequency vibration of an actuator of an ink jet head. The inkjet head drive circuit according to an embodiment includes: a waveform pattern generation unit that generates a waveform pattern based on input data; and a drive waveform generation unit that generates a drive waveform for driving the actuator on the basis of the waveform pattern. The drive waveform generation unit includes: a power source that supplies a drive voltage to be applied to the actuator; a plurality of switching elements connecting the power source and the actuator; and a drive waveform output unit that outputs a drive waveform for driving the actuator by switching on / off of the plurality of switching elements on the basis of the waveform pattern. The waveform pattern changes the number of switching elements that are turned on among the plurality of switching elements in at least one of a plurality of sections in one cycle of a drive waveform that causes the actuator to eject one drop of ink.

Description

Technical Field

[0001] Embodiments of the present invention relate to an inkjet head driving circuit. Background Art

[0002] Typically, an inkjet head includes a pressure chamber for storing ink, an actuator for expanding and contracting the pressure chamber, and an inkjet head driving circuit for driving the actuator. The inkjet head driving circuit expands and contracts the pressure chamber through the actuator, thereby ejecting ink from a nozzle connected to the pressure chamber. Summary of the invention

[0003] The actuator generally uses a piezoelectric actuator. It is preferred that the drive waveform of the actuator rises and falls quickly in terms of the speed of the actuator's response. However, when the drive waveform of the actuator rises and falls too quickly, the actuator will generate unnecessary high-frequency vibrations. The generation of such unnecessary high-frequency vibrations will cause the printing quality of the inkjet head to deteriorate.

[0004] An object of the present invention is to provide an inkjet head driving circuit that suppresses generation of unnecessary high-frequency vibrations of an actuator of an inkjet head.

[0005] The inkjet head driving circuit involved in the embodiment drives the inkjet head, and the inkjet head has: a pressure chamber that contains ink; a nozzle that is connected to the pressure chamber; and an actuator that expands and contracts the pressure chamber to eject ink from the nozzle. The inkjet head driving circuit has: a waveform pattern generating unit that generates a waveform pattern based on input data; and a driving waveform generating unit that generates a driving waveform for driving the actuator based on the waveform pattern. The driving waveform generating unit has: a power supply that supplies a driving voltage applied to the actuator; a plurality of switching elements that connect the power supply and the actuator; and a driving waveform output unit that switches the on / off of the plurality of switching elements based on the waveform pattern, thereby outputting a driving waveform for driving the actuator. The waveform pattern changes the number of switching elements that are set to be on among the plurality of switching elements in at least one interval of a plurality of intervals in one cycle of the driving waveform that causes the actuator to eject one drop of ink. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing a configuration example of an inkjet printer including an inkjet head driving circuit according to an embodiment.

[0007] Figure 2 This is a block diagram showing a configuration example of an inkjet head driving circuit according to an embodiment.

[0008] Figure 3 This is a block diagram showing a configuration example of a gate driver included in the inkjet head driving circuit according to the embodiment.

[0009] Figure 4 About Figure 3 The diagram shows a list of gate levels, waveform output levels, and on-resistances of each of a plurality of switching elements included in the gate driver.

[0010] Figure 5 About Figure 3 The diagram shows an overview of waveform output levels, switch sizes, on switches, and parallel resistances for each of the three pairs of switching elements included in the gate driver shown.

[0011] Figure 6 This is a block diagram showing a configuration example of a waveform pattern generating section of an inkjet head driving circuit according to a conventional example.

[0012] Figure 7 This is a diagram showing a list of time setting times of a timer and waveform output levels in one cycle of a waveform pattern corresponding to one cycle of a driving waveform in an operation example of an inkjet head driving circuit according to a conventional example.

[0013] Figure 8 The figure shows the operation example of the inkjet head driving circuit according to the prior art. Figure 7 The waveform pattern input shown, Figure 3 FIG. 1 is a diagram showing the driving waveform of the gate driver output.

[0014] Fig. 9 The figure shows an operation example of the inkjet head driving circuit according to the prior art. In the setting of the switch size 1, the Figure 7 The waveform pattern input shown, Figure 3 FIG. 1 is a diagram showing the driving waveform of the gate driver output.

[0015] Fig.10 This is a block diagram showing a configuration example of a waveform pattern generating unit according to a first configuration example of the ink jet head driving circuit according to the embodiment.

[0016] Fig.11 This is a block diagram showing a configuration example of a waveform pattern generating unit according to a second configuration example of the inkjet head driving circuit according to the embodiment.

[0017] Fig.12 This is a diagram showing an overview of the timer setting time, waveform output level, and switch size in one cycle of the waveform pattern corresponding to one cycle of the driving waveform in the first operation example of the ink jet head driving circuit according to the embodiment.

[0018] Fig.13 In the first operation example of the inkjet head driving circuit according to the embodiment, Fig.12 The waveform pattern input shown, Figure 3FIG. 1 is a diagram showing the driving waveform of the gate driver output.

[0019] Fig.14 This is a diagram showing an overview of the timer setting time, waveform output level, and switch size in one cycle of the waveform pattern corresponding to one cycle of the driving waveform in the second operation example of the ink jet head driving circuit according to the embodiment.

[0020] Fig.15 In the second operation example of the inkjet head driving circuit according to the embodiment, Fig.14 The waveform pattern input shown, Figure 3 FIG. 1 is a diagram showing the driving waveform of the gate driver output.

[0021] Description of Reference Numerals

[0022] 100… inkjet head, 101… inkjet head driving circuit, 102… actuator group, 110… I / O unit, 111… comparator, 112… serial-parallel conversion unit, 120… logic unit, 121… start byte recognition unit, 122… setting data register, 123… printing data register, 124… waveform pattern generation unit, 130… analog unit, 131… level converter, 132… pre-buffer, 133… gate driver, 140… waveform pattern generation unit, 141… waveform timer, 142… decoder state machine, 143… waveform level selector, 144… waveform level selector, 146… selection unit, 151~156…AND circuit, 160…waveform pattern generating unit, 166…selecting unit, 167…timer, 168…decoder state machine, 170…waveform pattern generating unit, 171…waveform timer, 172…decoder state machine, 173…waveform level selector, 174…waveform level selector, 200…inkjet printer, 201…processor, 202…ROM, 203…RAM, 204…operation panel, 205…communication interface, 206…conveying motor, 207…motor driving circuit, 208…pump, 209…pump driving circuit, 210…bus, QA~QF…switching element. DETAILED DESCRIPTION

[0023] (Inkjet Printer)

[0024] First, refer to Figure 1 An inkjet printer 200 including an inkjet head 100 including an inkjet head driving circuit 101 according to the embodiment will be described. Figure 1 2 is a block diagram showing a configuration example of an inkjet printer 200. In the following description, the inkjet printer 200 is abbreviated as printer 200, the inkjet head 100 is abbreviated as head 100, and the inkjet head driving circuit 101 is abbreviated as head driving circuit 101.

[0025] The printer 200 has a head 100. The head 100 has a head driving circuit 101 and an actuator group 102. The actuator group 102 has a plurality of actuators. Each actuator is a driving element for expanding or contracting a pressure chamber that contains ink and for ejecting ink droplets from a nozzle connected to the pressure chamber. For example, each actuator is a piezoelectric driving element made of PZT (lead zirconate titanate). The head driving circuit 101 is a circuit that generates a driving signal for the actuator group 102. Each actuator of the actuator group 102 operates according to the driving signal supplied from the head driving circuit 101, so that the pressure chamber expands or contracts and ink droplets are ejected from the nozzle.

[0026] The printer 200 includes, in addition to the head 100, a processor 201, a ROM (Read Only Memory) 202, a RAM (Random Access Memory) 203, an operation panel 204, a communication interface 205, a conveying motor 206, a motor driving circuit 207, a pump 208, and a pump driving circuit 209. It should be noted that in the drawings, the interface is abbreviated as "IF".

[0027] In addition, the printer 200 has a bus 210 such as an address bus and a data bus. The processor 201, ROM 202, RAM 203, operation panel 204, communication interface 205, motor drive circuit 207, pump drive circuit 209, and head drive circuit 101 are connected to the bus 210 directly or via an input / output circuit, and can mutually transmit and receive data.

[0028] The processor 201 corresponds to the core part of the computer. The processor 201 realizes various parts according to the operating system or application program to realize various functions of the printer 200. The processor 201 is, for example, a CPU (Central Processing Unit).

[0029] The ROM 202 corresponds to the main storage unit dedicated to reading of the above-mentioned computer. The ROM 202 stores the above-mentioned operating system and application programs. The ROM 202 may also store data necessary for the processor 201 to execute processing for controlling each unit.

[0030] RAM 203 corresponds to the rewritable main storage part of the above-mentioned computer. RAM 203 stores data required for the processor 201 to execute the process. In addition, RAM 203 is also used as a work area for the processor 201 to rewrite information as appropriate. The work area includes an image memory where print data is expanded.

[0031] The operation panel 204 has an operation unit and a display unit. The operation unit is provided with function keys such as a power key, a paper feed key, and an error cancel key. The display unit can display various states of the printer 200.

[0032] The communication interface 205 receives print data from a client terminal connected via a network such as a LAN (Local Area Network) or the like. For example, when an error occurs in the printer 200 , the communication interface 205 transmits a signal notifying an error to the client terminal.

[0033] The motor drive circuit 207 controls the driving of the conveying motor 206. The conveying motor 206 functions as a driving source of a conveying mechanism for conveying recording media such as printing paper. When the conveying motor 206 is started, the conveying mechanism starts conveying the recording medium. The conveying mechanism conveys the recording medium to the printing position of the head 100. The conveying mechanism discharges the recording medium that has been printed to the outside of the printer 200 from a discharge port not shown in the figure.

[0034] The pump driving circuit 209 controls the driving of the pump 208. When the pump 208 is driven, ink in an ink cartridge (not shown) is supplied to the head 100.

[0035] The head driving circuit 101 drives the actuator group 102 of the head 100 based on the printing data. The actuator group 102 expands and contracts the pressure chamber containing the ink, and ejects the ink droplets from the nozzles connected to the pressure chamber. Thus, the head 100 ejects the ink to the recording medium transported by the transport mechanism, and prints the image on the recording medium.

[0036] (Head drive circuit)

[0037] Next, refer to Figure 2 The head driving circuit 101 according to the embodiment will be described. Figure 2 1 is a block diagram showing a configuration example of the head driving circuit 101 according to the embodiment.

[0038] The head driving circuit 101 includes an I / O unit 110 , a logic unit 120 , and an analog unit 130 .

[0039] The I / O unit 110 includes a comparator 111 and a serial-parallel converter 112. In the drawings, the "serial-parallel converter" is abbreviated as "converter".

[0040] The comparator 111 receives a clock signal CLK and a data signal DI of low voltage differential signaling (LVDS). The data signal DI includes printing data, setting data, etc. The comparator 111 outputs the data of the clock signal CLK and the data signal DI to the serial-parallel converter 112 .

[0041] The serial-to-parallel converter 112 converts the serial format data input from the comparator 111 into parallel format data. The data of the data signal DI is acquired at the timing of the rise of the clock signal CLK. Specifically, the value (0 or 1) of the setting data and the printing data included in the data signal DI is acquired at the timing when the clock signal CLK changes from 0 to 1. The serial-to-parallel converter 112 outputs the data of the parallel format data signal DI to the logic unit 120. In addition, the serial-to-parallel converter 112 outputs the data of the clock signal CLK to the logic unit 120 and the analog unit.

[0042] The logic unit 120 includes a start byte recognition unit 121 , a setting data register 122 , a printing data register 123 , and a waveform pattern generation unit 124 .

[0043] The start byte recognition unit 121 recognizes the start byte of the data of the parallel format data signal DI input from the serial-parallel conversion unit 112 and separates it into setting data and printing data. The start byte recognition unit 121 outputs the setting data to the setting data register 122 and outputs the printing data to the printing data register 123.

[0044] The setting data register 122 stores the setting data input from the start byte recognition unit 121 .

[0045] The print data register 123 stores the print data input from the start byte recognition unit 121 .

[0046] The waveform pattern generation unit 124 obtains the setting data from the setting data register 122 and the printing data from the printing data register 123 , and generates a waveform pattern based on the setting data and the printing data. The waveform pattern generation unit 124 outputs the generated waveform pattern to the simulation unit 130 .

[0047] That is, the analog section 130 is a driving waveform generating section that generates a driving waveform based on a waveform pattern. The analog section 130 includes a level shifter 131 , a pre-buffer 132 , and a gate driver 133 .

[0048] The level shifter 131 converts the waveform pattern input from the waveform pattern generating section 124 into a high voltage. The level shifter 131 outputs the waveform pattern converted into a high voltage to the pre-buffer 132 .

[0049] The pre-buffer 132 appropriately amplifies and shapes the waveform pattern input from the level shifter 131. The pre-buffer 132 outputs the appropriately amplified and shaped waveform pattern to the gate driver 133.

[0050] The gate driver 133 controls the on / off of a plurality of switching elements of the gate driver 133 based on the waveform pattern input from the pre-buffer 132, thereby outputting a driving waveform for driving the actuator group 102 of the head 100. That is, the gate driver 133 is a driving waveform output unit that outputs a driving waveform based on the waveform pattern. For example, the switching element is a MOSFET, and the gate driver 133 controls the on / off of the MOSFET by applying a control signal (gate voltage) to the gate of the MOSFET.

[0051] (Gate Driver)

[0052] Next, refer to Figure 3 The gate driver 133 included in the head driving circuit 101 according to the embodiment will be described. Figure 3 1 is a block diagram showing a configuration example of the gate driver 133 included in the head driving circuit 101 according to the embodiment. Figure 3 The gate driver 133 shown is a gate driver for one actuator PZT in the actuator group 102 .

[0053] The gate driver 133 includes a power supply PS and a plurality of switching elements QA, QB, QC, QD, QE, and QF.

[0054] The power supply PS includes a first power supply PSA and a second power supply PSB. The first power supply PSA provides a first voltage VA to a reference potential VSS. The second power supply PSB provides a second voltage VB to the reference potential VSS. The first voltage VA and the second voltage VB are different voltages. For example, the reference potential VSS is a negative potential, and the first voltage VA is higher than the second voltage VB.

[0055] The plurality of switch elements QA to QF include six switch elements QA to QF. The six switch elements QA to QF include a first pair of switch elements QA and QB, a second pair of switch elements QC and QD, and a third pair of switch elements QE and QF. The first pair of switch elements QA and QB are connected in parallel between a pair of electrodes of the actuator PZT. The second pair of switch elements QC and QD are connected in parallel between the actuator PZT and the first power supply PSA. The third pair of switch elements QE and QF are connected in parallel between the actuator PZT and the second power supply PSB.

[0056] Specifically, one electrode of the actuator PZT connects one power terminal of the first power supply PSA to one power terminal of the second power supply PSB and is maintained at a reference potential VSS. The second pair of switch elements QC and QD connects the other electrode of the actuator PZT to the other power terminal of the first power supply PSA in parallel. The third pair of switch elements QE and QF connects the other electrode of the actuator PZT to the other power terminal of the second power supply PSB in parallel.

[0057] The on-resistance of one switching element QA of the first pair of switching elements QA and QB is different from the on-resistance of the other switching element QB. The on-resistance of one switching element QC of the second pair of switching elements QC and QD is different from the on-resistance of the other switching element QD. The on-resistance of one switching element QE of the third pair of switching elements QE and QF is different from the on-resistance of the other switching element QF.

[0058] For example, the on-resistance of one switch element QA in the first pair of switch elements QA and QB, the on-resistance of one switch element QC in the second pair of switch elements QC and QD, and the on-resistance of one switch element QE in the third pair of switch elements QE and QF are equal to each other.

[0059] In addition, the on-resistance of the other switching element QB in the first pair of switching elements QA, QB, the on-resistance of the other switching element QD in the second pair of switching elements QC, QD, and the on-resistance of the other switching element QF in the third pair of switching elements QE, QF are equal to each other.

[0060] For example, each of the switching elements QA to QF is a MOSFET. For each of the six switching elements QA to QF, a list of gate level, waveform output level, and on-resistance is provided in Figure 4 The gate level is the level of the voltage applied to the gate to turn on each switching element, the waveform output level is the level of the voltage applied to each switching element, and the on-resistance is the resistance when each switching element is turned on.

[0061] For the switch element QA, the gate level is NAg, the waveform output level is VSS, and the on-resistance is 1000Ω. For the switch element QB, the gate level is NBg, the waveform output level is VSS, and the on-resistance is 200Ω. For the switch element QC, the gate level is PCg, the waveform output level is VA, and the on-resistance is 1000Ω. For the switch element QD, the gate level is PDg, the waveform output level is VA, and the on-resistance is 200Ω. For the switch element QE, the gate level is PEg, the waveform output level is VB, and the on-resistance is 1000Ω. For the switch element QF, the gate level is PFg, the waveform output level is VB, and the on-resistance is 200Ω.

[0062] For each of the first pair of switching elements QA, QB, the second pair of switching elements QC, QD, and the third pair of switching elements QE, QF, a list of waveform output levels, switch sizes, on switches, and parallel resistances is provided in Figure 5 The on switch shows the switch turned on for each pair of switch elements, and the parallel resistor shows the resistance of each pair of switch elements at that time.

[0063] For example, for the first pair of switch elements QA and QB, the parallel resistance when both switch elements QA and QB are turned on is 167Ω, the parallel resistance when switch element QA is turned off and switch element QB is turned on is 200Ω, and the parallel resistance when switch element QA is turned on and switch element QB is turned off is 1000Ω. Figure 5 As shown, the same is true for each pair of switching elements in the second pair of switching elements QC, QD and the third pair of switching elements QE, QF.

[0064] The switch size is an index indicating the speed of the rise and fall of the drive waveform driving the actuator PZT. The rise and fall of the switch size 3 are faster than the switch size 2. On the other hand, the rise and fall of the switch size 1 are slower than the switch size 2.

[0065] The switch size is related to the parallel resistance of each pair of switch elements. Specifically, the switch size of each pair of switch elements is larger when the parallel resistance is low than when the parallel resistance is high. That is, the rise and fall of each pair of switch elements is faster when the parallel resistance is low than when the parallel resistance is high.

[0066] (Waveform Pattern Generator in Head Driving Circuit According to Conventional Example)

[0067] Next, refer to Figure 6 The waveform pattern generating section 140 of the head driving circuit 101 according to the conventional example will be described. Figure 6 1 is a block diagram showing a configuration example of the waveform pattern generating section 140 of the head driving circuit 101 according to a conventional example.

[0068] The waveform pattern generating section 140 includes six AND circuits 151 to 156 for controlling the on / off of six switching elements QA to QF in the gate driver 133 , respectively.

[0069] The AND circuit 151 outputs the gate signal Nag input to the gate of the switch element QA in order to control the on / off of the switch element QA of the first pair of switch elements QA and QB of the gate driver 133. In addition, the AND circuit 152 outputs the gate signal NBg input to the gate of the switch element QB in order to control the on / off of the switch element QB of the first pair of switch elements QA and QB of the gate driver 133. It should be noted that Figure 6 For convenience, the gate signal of the switching element QB of the switching element QA and QB is marked with Figure 4 Gate levels NAg and NBg are shown.

[0070] Likewise, AND circuits 153 and 154 output gate signals PCg and PDg, respectively, for the second pair of switching elements QC and QD of gate driver 133. AND circuits 155 and 156 output gate signals PEg and PFg, respectively, for the third pair of switching elements QE and QF of gate driver 133.

[0071] The waveform pattern generating section 140 further includes a waveform timer 141 , a decoder state machine 142 , a waveform level selector 143 , a waveform level selector 144 , and a SW selecting section 146 .

[0072] The waveform timer 141 is a timer circuit that generates a pulse signal for forming ink droplets in a multi-drop method. Fire1, Fire2, ..., Fire14 correspond to ink droplets (grayscales), respectively. In addition, Timer [7: 0] indicates that the pulse signal is 8-bit data.

[0073] The decoder state machine 142 outputs data specifying the waveform output level to the waveform level selector 143 and the waveform level selector 144 based on the pulse signal generated by the waveform timer 141. FW[2:0] corresponds to Figure 4 and Figure 5 The waveform output levels VSS, VA, and VB shown represent 3-bit data.

[0074] The waveform level selector 143 supplies a control signal VA for causing the AND circuits 153 and 154 to output a waveform output level VA based on the print data.

[0075] The waveform level selector 144 supplies the control signal VB for causing the AND circuits 155 and 156 to output the waveform output level VB based on the print data.

[0076] Furthermore, the waveform pattern generating section 140 supplies the control signal VSS for causing the AND circuits 151 and 152 to output the waveform output level VSS based on the printing data to the AND circuits 151 and 152 via a waveform level selector (not shown).

[0077] The SW selection unit 146 selects a switch element to be turned on among the six switch elements QA to QF in the gate driver 133 based on the setting data. The SW selection unit 146 supplies a control signal Z to the AND circuits 151 to 156 corresponding to the switch element to be turned on, and the control signal Z causes the switch element to output a gate signal of a gate level.

[0078] Through the control described above, the logic unit 120 controls the on / off of the six switching elements QA to QF in the gate driver 133 in the analog unit 130 based on the printing data and the setting data, and outputs a drive waveform for driving one actuator PZT in the actuator group 102 of the head 100 .

[0079] (Operation Example of Head Driving Circuit According to Conventional Example)

[0080] exist Figure 6 In the waveform pattern generator 140 according to the conventional example, the SW selector 146 sets the switch size to a fixed value based on the setting data when setting the head 100 (when configuring). Therefore, based on the waveform pattern generated by the waveform pattern generator 140 according to the conventional example, the rising and falling speeds of the drive waveform output by the gate driver 133 are fixed.

[0081] Next, refer to Figure 7 to Figure 9 The driving waveform output by the head driving circuit 101 according to the conventional example will be described. That is, the driving waveform output by the gate driver 133 will be described based on the waveform pattern generated by the waveform pattern generating unit 140. Here, for convenience, an example of causing one actuator PZT to eject one drop of ink (an example of grayscale level 1) will be described.

[0082] Figure 7 This is a diagram showing a list of time setting times and waveform output levels of a timer in one cycle of a waveform pattern corresponding to one cycle of a driving waveform for causing one actuator PZT to eject one drop of ink.

[0083] One cycle of the waveform pattern has four intervals SA, SB, SC and SD. The length of each interval SA, SB, SC, SD is 2.00μs. The waveform output level in interval SA is VSS, the waveform output level in interval SB is VB, the waveform output level in interval SC is VA, and the waveform output level in interval SD is VSS.

[0084] For example, VSS is a negative potential, VB is a zero potential, and VA is a positive potential. In addition, for the pressure chamber containing ink, section SA corresponds to an expansion section, section SB corresponds to a release section, section SC corresponds to a contraction section, and section SD corresponds to a release section.

[0085] Figure 8 The figure shows that when the SW selection unit 146 sets the switch size to switch size 3, the Figure 7 The waveform pattern shown is input, and the gate driver 133 outputs the drive waveform of the actuator PZT. Fig. 9 The figure shows that when the SW selection unit 146 sets the switch size to switch size 1, the Figure 7 The waveform pattern shown is a diagram of the drive waveform of the actuator PZT output by the gate driver 133. Figure 8 and Fig. 9 In addition to showing the drive waveforms, the waveform output levels are also shown.

[0086] By comparison Figure 8 and Fig. 9 It can be seen that at any switching time of the waveform output level change interval, Figure 8 The rise and fall of the driving waveform are both Fig. 9 The driving waveform of the Fig. 9 Compared with the driving waveform, Figure 8 The driving waveform drives the actuator PZT with a faster response. This is preferred in terms of improving the printing quality. However, when the rise and fall of the driving waveform are too fast, the actuator PZT may generate unnecessary high-frequency vibrations. The generation of unnecessary high-frequency vibrations may become a cause of reduced printing quality.

[0087] (Waveform Pattern Generator According to First Configuration Example in Head Driving Circuit According to Embodiment)

[0088] Next, refer to Fig.10 The waveform pattern generating section 160 of the first configuration example in the head driving circuit 101 according to the embodiment will be described. Fig.10 1 is a block diagram showing a configuration example of a waveform pattern generating unit 160 according to a first configuration example in the head driving circuit 101 according to the embodiment. Fig.10 In the Figure 6 Components with the same reference numerals as those shown are identical components, and detailed descriptions thereof are omitted.

[0089] Similar to the waveform pattern generating section 140 , the waveform pattern generating section 160 according to the first configuration example includes a waveform timer 141 , a decoder state machine 142 , a waveform level selector 143 , a waveform level selector 144 , and six AND circuits 151 to 156 .

[0090] The details of the waveform timer 141, the decoder state machine 142, the waveform level selector 143, the waveform level selector 144, and the six AND circuits 151 to 156 are as described above.

[0091] The waveform pattern generating unit 160 according to the first configuration example includes a SW selecting unit 166 instead of the SW selecting unit 146 of the waveform pattern generating unit 140. The SW selecting unit 166 selects the switching element to be turned on among the six switching elements QA to QF in the gate driver 133 based on the setting data. The SW selecting unit 166 supplies the control signal Z to the AND circuits 151 to 156 corresponding to the switching element to be turned on, and the control signal Z causes the switching element to be turned on to output a gate signal of a gate level. In this respect, the SW selecting unit 166 is similar to the SW selecting unit 146.

[0092] As described above, the SW selection unit 146 sets the switch size to a fixed value based on the setting data when setting (configuring) the head 100. That is, the SW selection unit 146 cannot change the switch size. Therefore, the head driving circuit 101 having the waveform pattern generation unit 140 of the conventional example outputs the drive waveform from the gate driver 133 at a fixed rising and falling speed.

[0093] In contrast, the head driving circuit 101 including the waveform pattern generating unit 160 according to the first configuration example can change the rising and falling speeds of the driving waveform output from the gate driver 133. That is, the head driving circuit 101 including the waveform pattern generating unit 160 according to the first configuration example can change the switching size during one cycle of the driving waveform for causing the actuator PZT to eject one drop of ink.

[0094] In other words, the head driving circuit 101 including the waveform pattern generating unit 160 according to the first configuration example can change the parallel resistance of the switch element pair in the gate driver 133 during one cycle of the driving waveform, that is, during one cycle of the waveform pattern. Therefore, the head driving circuit 101 including the waveform pattern generating unit 160 according to the first configuration example can change the number of switch elements turned on among the switch elements QA to QF in the gate driver 133 during one cycle of the waveform pattern. More specifically, the head driving circuit 101 including the waveform pattern generating unit 160 can change the switch element pair turned on among the plurality of switch element pairs in the gate driver 133 during one cycle of the waveform pattern.

[0095] Therefore, the SW selection unit 166 of the waveform pattern generation unit 160 according to the first configuration example includes a timer 167 and a decoder state machine 168 .

[0096] The setting time of the timer 167 is the same as the setting time of the waveform timer 141. Therefore, Timer[7:0] indicating the setting time of the timer 167 is the same as Timer[7:0] indicating the setting time of the waveform timer 141, and the pulse signal is 8-bit data.

[0097] The decoder state machine 168 outputs a control signal Z to the six AND circuits 151 to 156 for changing the number of switch elements turned on among the six switch elements QA to QF in the gate driver 133 during one cycle of the waveform pattern, based on the set time of the timer 167. In other words, the control signal Z is selection data for selecting a switch element turned on among the switch elements QA to QF in the gate driver 133 during one cycle of the waveform pattern.

[0098] That is, in the waveform pattern generating unit 160 according to the first configuration example, the SW selecting unit 166 generates selection data for selecting a switching element to be turned on among the switching elements QA to QF in the gate driver 133 during one cycle of the waveform pattern. That is, the SW selecting unit 166 is a selection data generating unit that generates selection data for selecting a switching element to be turned on among the switching elements QA to QF in the gate driver 133 during one cycle of the waveform pattern.

[0099] (Waveform Pattern Generator According to Second Configuration Example in Head Driving Circuit According to Embodiment)

[0100] Next, refer to Fig.11 The waveform pattern generating section 170 of the second configuration example in the head driving circuit 101 according to the embodiment will be described. Fig.11 1 is a block diagram showing a configuration example of the waveform pattern generating section 170 according to the second configuration example in the head driving circuit 101 according to the embodiment.

[0101] The waveform pattern generating unit 170 according to the second configuration example includes a waveform timer 171 , a decoder state machine 172 , a waveform level selector 173 , and a waveform level selector 174 .

[0102] The function and the like of the waveform timer 171 are the same as those of the waveform timer 141 of the waveform pattern generating unit 140 .

[0103] The decoder state machine 172 outputs data specifying the waveform output level to the waveform level selectors 173 and 174 based on the pulse signal generated by the waveform timer 171. Furthermore, the decoder state machine 172 outputs data specifying the switch element to be turned on among the six switch elements QA to QF in the gate driver 133 to the waveform level selectors 173 and 174 based on the setting data.

[0104] Therefore, the decoder state machine 172 outputs 5-bit data FW[4:0] to the waveform level selector 173 and the waveform level selector 174. As described above, the data for specifying the waveform output level is 3-bit data. In addition, each pair of switching elements in the gate driver 133 is turned on / off together. Therefore, the data for specifying the switching element to be turned on is 2-bit data.

[0105] The waveform level selector 173 sets the waveform output level of the second pair of switch elements QC, QD in the gate driver 133 to VA based on the data input from the decoder state machine 172 and the printing data, and controls the on / off of the second pair of switch elements QC, QD.

[0106] The waveform level selector 174 sets the waveform output level of the third pair of switch elements QE, QF in the gate driver 133 to VB based on the data input from the decoder state machine 172 and the printing data, and controls the on / off of the third pair of switch elements QE, QF.

[0107] In addition, the waveform pattern generating unit 170 sets the waveform output level of the first pair of switching elements QA and QB in the gate driver 133 to VSS based on the data and printing data input from the decoder state machine 172 by a waveform level selector (not shown), and controls the on / off of the first pair of switching elements QA and QB.

[0108] With such a configuration, the waveform pattern generating unit 170 according to the second configuration example can operate in the same manner as the waveform pattern generating unit 160 according to the first configuration example.

[0109] That is, the head driving circuit 101 having the waveform pattern generating unit 170 involved in the second configuration example can change the switch size during one cycle of the driving waveform that causes the actuator PZT to eject one drop of ink. In other words, the head driving circuit 101 having the waveform pattern generating unit 170 involved in the second configuration example can change the parallel resistance of the switch element pair in the gate driver 133 during one cycle of the driving waveform. Therefore, the head driving circuit 101 having the waveform pattern generating unit 170 involved in the second configuration example can change the number of switch elements that are turned on among the switch elements QA to QF in the gate driver 133 during one cycle of the driving waveform. In more detail, the head driving circuit 101 having the waveform pattern generating unit 170 can change the switch element pair that is turned on among the multiple switch element pairs in the gate driver 133 during one cycle of the driving waveform.

[0110] (First Operation Example of Head Driving Circuit According to Embodiment)

[0111] Next, refer to Fig.12 and Fig.13The first operation example of the head driving circuit 101 according to the embodiment will be described. That is, the driving waveform output by the gate driver 133 will be described based on the waveform pattern generated by the waveform pattern generating unit 160 according to the first configuration example or the waveform pattern generating unit 170 according to the second configuration example. Here, for convenience, an example of causing one actuator PZT to eject one drop of ink (an example of grayscale level 1) will be described.

[0112] Fig.12 This is a diagram showing an overview of the timer setting time, waveform output level, and switch size in one cycle of the waveform pattern corresponding to one cycle of the drive waveform for causing one actuator PZT to eject one drop of ink in the first operation example.

[0113] One cycle of the waveform pattern in the first operation example has four intervals SA, SB, SC, and SD. The length of each interval SA, SB, SC, and SD is 2.00 μs. The waveform output level in the interval SA is VSS, the waveform output level in the interval SB is VB, the waveform output level in the interval SC is VA, and the waveform output level in the interval SD is VSS.

[0114] For example, VSS is a negative potential, VB is a zero potential, and VA is a positive potential. In addition, for the pressure chamber containing ink, the interval SA corresponds to the expansion interval, the interval SB corresponds to the release interval, the interval SC corresponds to the contraction interval, and the interval SD corresponds to the release interval. The pressure chamber ejects ink when switching from the expansion interval of the interval SA to the release interval of the interval 3B.

[0115] As described above, the waveform pattern generator 160 of the first configuration example or the waveform pattern generator 170 of the second configuration example can change the switch size. The switch size in section SA is 1, the switch size in section SB is 3, the switch size in section SC is 1, and the switch size in section SD is 1.

[0116] Fig.13 is shown relative to Fig.12 The waveform pattern shown is a diagram of the drive waveform of the actuator PZT output by the gate driver 133. Fig.13 In addition to the drive waveforms, the waveform output levels and switch sizes are also shown.

[0117] The actuator PZT shows a fast response for a switch size of 3 and a slow response for a switch size of 1. Therefore, Fig.13 The driving waveform shown rises quickly only in the section SB of the switching size 3 , and rises and falls slowly in the other sections SA, SC, and SD of the switching size 1 .

[0118] Therefore, in the sections SA, SC, and SD, the generation of unnecessary high-frequency vibration in the actuator PZT can be suppressed. On the other hand, in the section SB, since the rise of the driving waveform is fast, the degradation of the printing quality caused by the accent of the driving waveform can be suppressed.

[0119] Thus, in the first operation example, the head driving circuit 101 according to the embodiment changes the number of switch elements turned on among the switch elements QA to QF in the gate driver 133 between a plurality of sections of the waveform pattern corresponding to one cycle of the driving waveform for causing the actuator PZT to eject one drop of ink. More specifically, the head driving circuit 101 according to the embodiment can change the pair of switch elements turned on among a plurality of switch pairs in the gate driver 133 during one cycle of the driving waveform.

[0120] Thus, the head driving circuit 101 according to the first operation example can suppress the generation of unnecessary high-frequency vibration in the actuator PZT by changing the parallel resistance of the switching element pair of the gate driver 133 , and can suppress the degradation of printing quality.

[0121] (Second Operation Example of Head Driving Circuit According to Embodiment)

[0122] Next, refer to Fig.14 and Fig.15 A second operation example of the head driving circuit 101 according to the embodiment will be described. That is, a driving waveform output by the gate driver 133 will be described based on the waveform pattern generated by the waveform pattern generating unit 160 according to the first configuration example or the waveform pattern generating unit 170 according to the second configuration example. Here, for convenience, an example of causing one actuator PZT to eject one drop of ink (an example of grayscale level 1) will be described.

[0123] Fig.14 This is a diagram showing a list of timer setting times, waveform output levels, and switch sizes in one cycle of a waveform pattern corresponding to one cycle of a drive waveform for causing one actuator PZT to eject one drop of ink in the second operation example.

[0124] One cycle of the waveform pattern in the second operation example includes 7 intervals: SA, SB, SC, SD, SE, SF, and SG. The time length of the intervals SA, SD, and SF is 0.20 μs, the time length of the intervals SB, SE, and SG is 1.80 μs, and the time length of the interval SC is 2.00 μs. The waveform output level in the intervals SA and SB is VSS, the waveform output level in the interval SC is VB, the waveform output level in the intervals SD and SE is VA, and the waveform output level in the intervals SF and SG is VB. The switch size in the intervals SA, SD, and SF is 1, and the switch size in the intervals SB, SC, SE, and SG is 3.

[0125] For example, VSS is a negative potential, VB is a zero potential, and VA is a positive potential. In addition, for the pressure chamber that contains ink, the intervals SA and SB correspond to the expansion interval, the interval SC corresponds to the release interval, the intervals SD and SE correspond to the contraction interval, and the intervals SF and SG correspond to the release interval. The pressure chamber ejects ink when switching from the expansion interval of the interval SB to the release interval of the interval SC.

[0126] Fig.15 is shown relative to Fig.14 The waveform pattern shown is a diagram of the drive waveform of the actuator PZT output by the gate driver 133. Fig.15 In addition to the drive waveforms, the waveform output levels and switch sizes are also shown.

[0127] In one cycle of the drive waveform, in the first intervals SA and SB where the waveform output level is VSS, the switch size is 1 in the initial 0.20 μs interval SA, so the drive waveform falls relatively slowly. In contrast, in the 1.80 μs interval SB following the interval SA, the switch size is 3, so the drive waveform falls relatively quickly.

[0128] In the 2.00 μs section SC following the section SB where the waveform output level is VB, the switch size is 3, and therefore the rising edge of the drive waveform changes rapidly.

[0129] In the sections SD and SE where the waveform output level is VA following the section SC, in the initial section SE of 0.20 μs, the rise of the drive waveform changes relatively slowly because the switch size is 1. In contrast, in the section SE of 1.80 μs following the section SD, the rise of the drive waveform changes relatively quickly because the switch size is 3.

[0130] In the intervals SF and SG where the waveform output level is VB following the interval SE, in the initial 0.20 μs interval SF, the drop of the drive waveform changes relatively slowly because the switch size is 1. In contrast, in the 1.80 μs interval SG following the interval SF, the drop of the drive waveform changes relatively quickly because the switch size is 3.

[0131] Thus, in the second operation example, the head driving circuit 101 according to the embodiment changes the switch size in at least one of the plurality of sections based on the waveform output level in one cycle of the waveform pattern corresponding to one cycle of the driving waveform for causing one actuator PZT to eject one drop of ink. Specifically, the head driving circuit 101 according to the second operation example changes the switch size in each of the three sections SA, SB, sections SD, SE, and sections SF, SG based on the waveform output level.

[0132] More specifically, the head driving circuit 101 according to the second operation example changes the switching size, that is, the number of switching elements turned on among the switching elements QA to QF in the gate driver 133, in each of the three sections SA, SB, sections SD, SE, and sections SF, SG during the initial period and the subsequent periods. More specifically, the head driving circuit 101 according to the second operation example changes the number of switching element pairs turned on among the plurality of switching element pairs in the gate driver 133 during one cycle of the drive waveform.

[0133] More specifically, the head driving circuit 101 according to the second operation example increases the switching size throughout the entire section SC that contributes to ink ejection, and decreases the switching size during the initial period in other sections and increases the switching size during the subsequent period.

[0134] Thus, the head driving circuit 101 according to the second operation example can suppress the generation of unnecessary high-frequency vibration in the actuator PZT and suppress the degradation of printing quality.

[0135] (Effect)

[0136] As described above, the head driving circuit 101 according to the embodiment changes the number of switch elements QA to QF in the gate driver 133 that are set to be turned on between a plurality of intervals of the waveform pattern corresponding to one cycle of the driving waveform that causes the actuator PZT to eject one drop of ink. For example, the head driving circuit 101 according to the embodiment changes the number of switch elements that are set to be turned on in at least one interval of a plurality of intervals based on the waveform output level. Thus, the rising and falling speeds can be appropriately adjusted at appropriate positions between one cycle of the driving waveform. As a result, by reducing the rising and falling speeds at appropriate positions during one cycle of the driving waveform, the generation of unnecessary high-frequency vibrations in each actuator PZT of the actuator group 102 of the head 100 can be suppressed, and by increasing the rising and falling speeds at appropriate positions during one cycle of the driving waveform, the degradation of printing quality can be suppressed.

[0137] (Variation Example)

[0138] In the description of the embodiment, the gate driver 133 has six switching elements, that is, three pairs of switching elements, and the waveform output level input to the gate driver 133 is an example of three potentials. However, this is only an example, and the present invention is not limited to this. That is, the gate driver 133 may also have more than three pairs of switching elements, and the waveform output level input to the gate driver 133 is a plurality of potentials more than three. For example, the gate driver 133 may also have five pairs of switching elements, and the waveform output level input to the gate driver 133 is five potentials.

[0139] (other)

[0140] The program involved in this embodiment can be transferred in a state of being stored in an electronic device, or it can be transferred in a state of not being stored in an electronic device. In the latter case, the program can be transferred via a network, or it can be transferred in a state of being stored in a storage medium. A storage medium is a non-temporary tangible medium. A storage medium is a computer-readable medium. The storage medium can be any form of medium, such as a CD-ROM, a memory card, etc., that can store a program and can be read by a computer.

[0141] Although several embodiments of the present invention have been described, these embodiments are only presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the purpose of the invention. These embodiments and their variations are included in the scope and purpose of the invention, and are also included in the invention described in the claims and their equivalents.

Claims

1. An inkjet head driving circuit is an inkjet head driving circuit for driving an inkjet head, wherein the inkjet head has: a pressure chamber for containing ink; A nozzle connected to the pressure chamber; and an actuator that expands and contracts the pressure chamber to eject ink from the nozzle, wherein the inkjet head driving circuit is characterized in that: A waveform pattern generating unit that generates a waveform pattern based on input data; as well as a drive waveform generating unit that generates a drive waveform for driving the actuator based on the waveform pattern, The driving waveform generating unit comprises: a power supply for supplying a driving voltage applied to the actuator; a plurality of switch elements connecting the power source and the actuator; as well as a drive waveform output unit that switches the plurality of switch elements on / off based on the waveform pattern to output the drive waveform for driving the actuator, The waveform pattern changes the number of switching elements turned on among the plurality of switching elements in at least one interval among a plurality of intervals in one cycle of the drive waveform for causing the actuator to eject one drop of ink.

2. The inkjet head driving circuit according to claim 1, wherein: The power supply includes a first power supply for supplying a first voltage to a reference potential and a second power supply for supplying a second voltage to the reference potential. The plurality of switch elements include: a first pair of switch elements, connecting the actuators in parallel; a second pair of switch elements connecting the actuator and the first power source in parallel; as well as The third pair of switch elements connects the actuator and the second power supply in parallel. The on-resistance of one switching element of the first pair of switching elements is different from the on-resistance of the other switching element. The on-resistance of one switching element of the second pair of switching elements is different from the on-resistance of the other switching element. An on-resistance of one switching element and an on-resistance of the other switching element of the third pair of switching elements are different from each other.

3. The inkjet head driving circuit according to claim 2, wherein: the on-resistance of the one switching element in the first pair of switching elements, the on-resistance of the one switching element in the second pair of switching elements, and the on-resistance of the one switching element in the third pair of switching elements are equal to each other, The on-resistance of the other switching element in the first pair of switching elements, the on-resistance of the other switching element in the second pair of switching elements, and the on-resistance of the other switching element in the third pair of switching elements are equal to each other.

4. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generating section includes a selection data generating section configured to generate selection data for selecting the switching element to be turned on during one cycle of the waveform pattern.

5. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generated by the waveform pattern generating unit includes selection data for selecting the switching element to be turned on.

6. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generating unit includes a waveform timer.

7. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generating unit includes a decoder state machine.

8. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generating section includes a waveform level selector.

9. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generating section has six AND circuits.

10. The inkjet head driving circuit according to claim 1, wherein: The waveform pattern generating section has two waveform level selectors.

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