Memory management method and device, electronic equipment and storage medium

Abstract

The invention provides a memory management method and device, electronic equipment and a storage medium, and relates to the technical field of memory management, the method improves the reliability of memory management through compiling and instrumentation of multi-modular redundancy memory management, can reduce modification of source codes, and is compatible with an existing memory management mechanism. The method can comprise the following processes: identifying that a guide exists in a compiling object; the guide is used for modifying the memory variable to represent that the modified memory variable is a target variable which needs to apply for the multimode redundant memory; performing compiling instrumentation on the compiling object to obtain a target code; the executable code corresponding to the target code is at least used for applying for N memories corresponding to the target variable during running, and N is an integer greater than or equal to 2.

Description

Technical Field

[0001] The present application relates to the field of memory management technology, and in particular to a memory management method, device, electronic device and storage medium. Background Art

[0002] Strict business scenarios such as industrial control and aerospace are affected by harsh factors such as electromagnetic radiation and cosmic rays, which may cause various types of failures. Among them, the logic of memory failure is relatively complex, and there is currently a lack of relatively mature fault-tolerant solutions.

[0003] One solution to memory failure is to improve reliability by upgrading hardware. For example, space-grade multi-mode dynamic random access memory (DRAM) is used to replace traditional memory. High-reliability hardware such as space-grade DRAM can significantly reduce the failure rate, but most of them are expensive. According to statistics, the cost of space-grade dedicated chips is about 1,000 times higher than that of ordinary commercial off-the-shelf (COTS) devices. The high cost limits the practical application of this memory failure solution. Therefore, a lower-cost fault-tolerant solution is needed to improve the reliability of memory management. Summary of the invention

[0004] The present application provides a memory management method, device, electronic device and storage medium. During the compilation process, multi-module redundant memory management is performed on variables modified by guides through compilation stubs, which can reduce costs, reduce failure rates and improve memory management reliability.

[0005] In the first aspect, the embodiment of the present application provides a memory management method, which includes: identifying the presence of a lead in a compiled object; the lead is used to modify a memory variable to characterize the modified memory variable as a target variable that needs to apply for multi-module redundant memory; compiling the compiled object to obtain the target code; the executable code corresponding to the target code is used to apply for at least N copies of memory corresponding to the target variable during runtime, where N≥2 and is an integer. Compared with high-reliability hardware such as aerospace-grade hardware, this method can significantly reduce costs, and is compatible with current memory manager standards, without the need for intrusive shotgun modification of the source code, and is a practical memory management fault-tolerant solution.

[0006] In a feasible implementation, compilation stubs are performed on the compilation object, including: modifying the memory application interface with the target variable as the object in the compilation object to call the first API; the first API is a multi-module redundant memory application function; the multi-module redundant memory application function is used to apply for at least N copies of memory corresponding to the target variable. The first API is a function for implementing multi-module redundant memory management (memory application), which can be called independently during the compilation process, and there is no need to modify the existing memory application interface in the source code, but only to add a modifier when defining the variable, thereby reducing the modification of the source code and helping to achieve one track of the source code; on the other hand, this method of calling the corresponding function through compilation stubs can be compatible with the current general memory management mechanism. For example, it can be achieved that the malloc function, free function and other memory management functions are still used in the source code. The executable code (binary code) obtained through compilation stubs can implement multi-module redundant memory management at runtime, solving the problem of incompatibility between multi-module redundant management and traditional memory management (i.e., non-multi-module redundant memory management).

[0007] In a feasible implementation, compiling and stubbing the compiled object includes: modifying the read operation with the target variable as the object in the compiled object to call the second API; the second API is a multi-module redundant memory read function; the multi-module redundant memory read function is at least used to read the values ​​stored in N copies of memory. Similar to the first API, the second API is a function for executing the read operation in the multi-module redundant memory management, which can be called independently during the compilation process, and there is no need to modify the existing memory read interface in the source code, which reduces the modification of the source code and helps to achieve one track of the source code; and it can be compatible with the current general memory management mechanism.

[0008] In a feasible implementation, compile stubs are performed on the compiled object, including: modifying the write operation with the target variable as the object in the compiled object to call the third API; the third API is a multi-module redundant memory write function; the multi-module redundant memory write function is at least used to write the value of the target variable into N copies of memory. Similar to the first API, the third API is a function for executing write operations in multi-module redundant memory management, which can be called independently during the compilation process, and there is no need to modify the existing memory write interface in the source code, reducing the modification of the source code, which helps to achieve one track of the source code; and it can be compatible with the current general memory management mechanism.

[0009] In a feasible implementation, compiling and stubbing the compiled object includes: modifying the memory release interface with the target variable as the object in the compiled object to call the fourth API; the fourth API is a multi-module redundant memory release function; the multi-module redundant memory release function is used to release at least N copies of memory. Similar to the first API, the fourth API is a function for executing the release operation in the multi-module redundant memory management, which can be called independently during the compilation process, and there is no need to modify the existing memory release interface in the source code, which reduces the modification of the source code and helps to achieve one track of the source code; and it can be compatible with the current general memory management mechanism.

[0010] In a feasible implementation, the executable code corresponding to the target code is also used to apply for a multi-module redundant memory management structure when running; the multi-module redundant memory management structure is used to manage N copies of memory; the multi-module redundant memory release function is used to release N copies of memory and the multi-module redundant memory management structure.

[0011] In a feasible implementation, identifying that there is a preamble in the compiled object includes: identifying that there is a preamble in the code line corresponding to the target variable in the compiled object. The location of adding the preamble is flexible and is not limited to adding it before the variable, which is easy to implement.

[0012] In a feasible implementation, N copies of memory include 1 main memory block and N-1 backup memory blocks; the target code includes calling a first API; the first API is used to perform the following operations: apply for a multi-module redundant memory management structure; the multi-module redundant management structure includes an object header; the header is used to store at least the base addresses of N-1 backup memory blocks; apply for N copies of memory corresponding to the target variable, and return the base addresses corresponding to the N copies of memory; define the pointer used to access the target variable as a wide pointer; return the wide pointer; the high bit of the wide pointer is used to store the first base address, and the low bit is used to store the first pointer; wherein the first base address is the base address of the main memory block; the first pointer points to the memory address in the main memory block used to store the value of the target variable. This method provides a multi-module memory addressing scheme in a multi-module redundant memory management scenario.

[0013] In a feasible implementation manner, the target code includes calling a second API; the second API is used to perform the following operations:

[0014] Based on the first base address and the first pointer, determine the second base address and the second pointer to the Nth pointer corresponding to the N-1 backup memory blocks; wherein the second base address is the base address of the header; the second pointer to the Nth pointer respectively point to the memory addresses in the N-1 backup memory blocks for storing the values ​​of the target variables; read the values ​​in the memory addresses pointed to by the first pointer and the second pointer to the Nth pointer respectively.

[0015] In a feasible implementation, based on the first base address and the first pointer, determining the second base address and the second pointer to the Nth pointer corresponding to the N-1 backup memory blocks includes: determining the second base address based on the first base address and the first offset; the first offset is the offset of the second base address relative to the first base address, and the first offset is a constant; according to the second base address, reading the base addresses corresponding to the N-1 backup memory blocks respectively; determining the second offset of the memory address pointed to by the first pointer relative to the first base address; determining the second pointer to the Nth pointer according to the base addresses and the second offsets corresponding to the N-1 backup memory blocks respectively.

[0016] In a feasible implementation, the header is also used to store the N values ​​returned by the first pointer to the Nth pointer; the executable code corresponding to the second API is also used to perform the following operations when running: comparing the N values, determining the correct value and returning it as the value of the target variable; determining the faulty memory block; and writing the correct value into the faulty memory block. The reliability of memory management is improved through multi-mode memory arbitration.

[0017] In a feasible implementation, the target code includes calling a first API; the first API is used to perform the following operations: apply for N copies of memory corresponding to the target variable; wherein the base address of the tth copy of memory is fixedly offset relative to the base address of the t-1th copy of memory; 2≤t≤N.

[0018] In a feasible implementation, N copies of memory include 1 main memory and N-1 backup memory blocks; the target code includes calling a second API; the executable code corresponding to the second API is used to perform the following operations when running: based on the first pointer and the offset of the fixed offset, respectively determine the second pointer to the Nth pointer; wherein the first pointer points to the memory address in the main memory block where the value of the target variable is stored; read the values ​​in the memory addresses pointed to by the first pointer and the second pointer to the Nth pointer respectively through the first pointer, and return them.

[0019] In a feasible implementation, the target code includes calling a first API; the executable code corresponding to the first API is used to perform the following operations when running: applying for a third multi-module redundant memory management structure; the third multi-module redundant management structure includes a first virtual memory area and a second virtual memory area; the first virtual memory area is used to store target variables; the second virtual memory area is used to store memory variables that do not require applying for multi-module redundant memory; within the address space occupied by the first virtual memory area, applying for N copies of memory, in which the base address of the tth memory block is fixedly offset relative to the base address of the t-1th memory block; 2≤t≤N.

[0020] In a feasible implementation, after the code corresponding to the memory application interface is compiled and plugged, and the first code is obtained, the method also includes: identifying a read operation and / or a write operation with the target variable as the object; modifying the code corresponding to the read operation and / or the write operation to a fifth target code through a compiler; the executable code corresponding to the fifth target code is used to perform the following operations at runtime: starting a patrol thread; triggering the patrol thread, and performing the following operations through the patrol thread: writing the value of the target variable into N copies of memory respectively; or reading the value in the N copies of memory corresponding to the target variable; obtaining the correct value based on the arbitration strategy and returning it as the value of the target variable; determining the memory block storing the error; and writing the correct value into the memory block storing the error. This implementation can be applied to large-scale or high-concurrency read / write operation application scenarios, can cope with frequent read / write operations, and reduce the possibility of system crashes.

[0021] In a feasible implementation, when the target variable is a static variable or a global variable, a compilation stub is performed on the compilation object to obtain the target code, including: defining the target variable as the object in the compilation object, linking to the multi-mode data segment of the binary program, and obtaining the executable code; the executable code is used to apply for N copies of memory corresponding to the target variable when it is loaded or loaded by the operating system.

[0022] In the second aspect, an embodiment of the present application also provides a memory management device, which includes: a preamble recognition module, used to recognize the presence of a preamble in a compiled object; the preamble is used to modify a target variable, and the target variable is a memory variable that needs to apply for multi-module redundant memory; a compilation stub module, used to perform compilation stubs on the compiled object to obtain a target code; when the executable code corresponding to the target code is run, it is used to apply for at least N copies of memory corresponding to the target variable, where N ≥ 2 and is an integer.

[0023] In a feasible implementation, the compilation stub module is specifically used to modify the memory application interface with the target variable as the object in the compilation object to call the first API; the first API is a multi-mode redundant memory application function; the multi-mode redundant memory application function is used to apply for at least N copies of memory corresponding to the target variable.

[0024] In a feasible implementation, the compilation stub module is specifically used to modify the read interface with the target variable as the object in the compilation object to call the second API; the second API is a multi-mode redundant memory read function; the multi-mode redundant memory read function is at least used to read the values ​​stored in N copies of the memory.

[0025] In a feasible implementation, the compilation stub module is specifically used to modify the write interface with the target variable as the object in the compilation object to call the third API; the third API is a multi-module redundant memory write function; the multi-module redundant memory write function is at least used to write the value of the target variable into N copies of the memory respectively.

[0026] In a feasible implementation, the compilation stub module is specifically used to modify the memory release interface with the target variable as the object in the compilation object to call the fourth API; the fourth API is a multi-module redundant memory release function; the multi-module redundant memory release function is used to release at least N copies of memory.

[0027] In a feasible implementation, N copies of memory include 1 main memory block and N-1 backup memory blocks; the target code includes calling a first API; the first API is used to perform the following operations: apply for a multi-module redundant memory management structure; the multi-module redundant management structure includes an object header; the header is used to store at least the base addresses of N-1 backup memory blocks; apply for N copies of memory corresponding to the target variable, and return the base addresses corresponding to the N copies of memory respectively; define a pointer used to access the target variable as a wide pointer; return the wide pointer; the high bit of the wide pointer is used to store the first base address, and the low bit is used to store the first pointer; wherein the first base address is the base address of the main memory block; the first pointer points to the memory address in the main memory block used to store the value of the target variable.

[0028] In a feasible implementation, the target code includes calling a second API; the second API is used to perform the following operations: based on the first base address and the first pointer, determine the second pointer to the Nth pointer corresponding to the second base address and N-1 backup memory blocks; wherein the second base address is the base address of the header; the second pointer to the Nth pointer respectively point to the memory addresses in the N-1 backup memory blocks for storing the values ​​of the target variables; read the values ​​in the memory addresses pointed to by the first pointer and the second pointer to the Nth pointer respectively.

[0029] In a feasible implementation, the target code includes calling a first API; the first API is used to perform the following operations: apply for N copies of memory corresponding to the target variable; wherein the base address of the tth copy of memory is fixedly offset relative to the base address of the t-1th copy of memory; 2≤t≤N.

[0030] In a feasible implementation, compilation stubs are performed on the compilation object, including: modifying the read interface and / or write interface in the compilation object with the target variable as the object into code for performing the following operations: pulling up a patrol thread; triggering the patrol thread, the patrol thread is used to: write the value of the target variable into N copies of memory respectively; or, read the value in N copies of memory corresponding to the target variable; compare the values ​​in N copies of memory, obtain the correct value based on the arbitration strategy, and return it as the value of the target variable.

[0031] In a feasible implementation, when the target variable is a static variable or a global variable, a compilation stub is performed on the compilation object to obtain the target code, including: defining the target variable as the object in the compilation object, linking to the multi-mode data segment of the binary program, and obtaining the executable code; the executable code is used to apply for N copies of memory corresponding to the target variable when it is loaded or loaded by the operating system.

[0032] In a third aspect, an embodiment of the present application also provides a computer program product, which includes a program; the program includes a preamble, which is used to modify a target variable, and the target variable is a memory variable that needs to apply for multi-mode redundant memory; the target code corresponding to the program is at least used to apply for N copies of memory corresponding to the target variable; wherein the target code includes the code obtained by compiling and plugging the program; N≥2 and is an integer.

[0033] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes a program. When the program is executed by an electronic device, the electronic device implements the method as described in any one of the above-mentioned first aspects.

[0034] In the fifth aspect, an embodiment of the present application also provides an electronic device for sending data through a data transmission interface, the electronic device comprising: one or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, enable the electronic device to perform a method as described in any one of the above-mentioned first aspects.

[0035] In a sixth aspect, an embodiment of the present application further provides a storage medium, comprising computer instructions, which, when executed on an electronic device, enables the electronic device to execute a method as described in any one of the above-mentioned first aspects.

[0036] In the seventh aspect, an embodiment of the present application also provides a chip system, including: a communication interface for inputting and / or outputting data; a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any one of the above-mentioned first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is an example diagram of the full fault scenario mode;

[0038] Figure 2 It is a schematic diagram of an application scenario of the memory management method provided in an embodiment of the present application;

[0039] Figure 3 It is a schematic diagram of the architecture of the method of the related technology 2;

[0040] Figure 4 It is a schematic diagram of the architecture of an embodiment of the memory management method provided by the present application;

[0041] Figure 5 is a schematic diagram of the system architecture corresponding to the related technology 2;

[0042] Figure 6 is a schematic diagram comparing an embodiment of the memory management method provided by the present application with related technologies and prior arts;

[0043] Figure 7 It is a schematic diagram of the system architecture of dynamic memory management in the memory management method provided by this application;

[0044] Figure 8 is a schematic diagram of a compiler architecture in one embodiment of a memory management method provided by the present application;

[0045] Fig. 9 It is a schematic diagram of the system architecture of static memory management in the memory management method provided by this application;

[0046] Fig.10 It is a comparative schematic diagram of a specified introduction and no introduction under static memory management in one embodiment of the memory management method provided by the present application;

[0047] Fig.11 It is a schematic diagram of compilation and instrumentation in a specific embodiment of the memory management method provided by the present application;

[0048] Fig.12 is a schematic diagram of compilation and instrumentation in another specific embodiment of the memory management method provided by the present application;

[0049] Fig.13 It is a schematic diagram of compilation and instrumentation in another specific embodiment of the memory management method provided by the present application;

[0050] Fig.14 is a schematic diagram of starting a patrol thread in another specific embodiment of the memory management method provided by the present application;

[0051] Fig.15 Schematic diagram of the hardware structure of the electronic device. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0053] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0054] like Figure 1 As shown in the figure, in demanding business application scenarios such as industrial control and aerospace, the hardware may experience faults such as jump, lock, burn, hang, link interruption, etc. due to the influence of adverse factors such as electromagnetic radiation (such as cosmic rays), process problems, device aging, high and low temperature, load, electromigration, stress migration, negative bias temperature instability, hot carrier injection and humidity. If the hardware fault is not handled in time, the software fault behaviors such as UnACE (Architecturally Correct Execution), DUE (Detected Unrecoverable Error), SDC (Silent Data Corruption), CEE (Corrupt Execution Errors), SCEE (Silent Corrupt Execution Error), interruption loss, resource leakage, etc. will affect the application business behavior, and then cause business layer faults, such as business function errors, business interruptions, business timeouts, business DFX failures, etc.

[0055] From a macro perspective, common fault types can be divided into memory faults, external memory faults, link faults, CPU faults, etc. Among them, for CPU faults, hardware-based Lock-step is generally used as the mainstream CPU fault tolerance technology. CPUs that support the LockStep architecture are composed of two processors to monitor each other. External memory faults have a relatively simple logic due to their long life cycle; link faults rely on hardware or protocol fault tolerance capabilities; and memory faults have complex logic and currently there is a relative lack of fault tolerance solutions.

[0056] Stack memory failure and heap memory failure are memory failures. Compared with stack memory, which has a short life cycle and concentrated code and data segments, heap memory is one of the main factors affecting memory reliability due to its different life cycles, scattered locations, and business memory accounting for up to 95%. Therefore, one of the core challenges of reliability issues in the industrial control and aerospace fields is to ensure the reliability of heap memory.

[0057] In order to understand the improvements made to the solution proposed in the embodiment of the present application, two related technologies are listed below for illustration.

[0058] In the first related technology, the response to memory failures such as heap memory failures is to upgrade and transform the hardware, and reduce the failure rate by configuring high-reliability dedicated hardware such as aerospace-grade multi-mode DRAM. For example, the high-reliability multi-mode redundant DRAM Teledyne e2v launched in 2020 adds 4 DRAM particles to the traditional DRAM, that is, through 5 bare die DRAM particles, to increase the system-level error detection capability, realize multi-mode redundant memory from the hardware, and improve reliability. However, this solution has the following disadvantages:

[0059] Specialized chips and other devices are expensive: For example, in aerospace scenarios, it is recorded that the failure rate of CTOS devices is about 100,000 times higher than that of space-grade devices. That is, the failure rate of space-grade specialized devices can be reduced to about one hundred thousandth of that of ordinary CTOS devices. However, the cost of specialized high-reliability devices such as space-grade devices is about 1,000 times higher than that of COTS.

[0060] Slow technological evolution: Space-grade devices are small in quantity, have high reliability requirements, and are conservative in technology and processes. Their evolution is much slower than that of CTOS devices.

[0061] Small storage space: Redundant storage space, additional system-level error detection circuits, and conservative process technology make the storage space of aerospace-grade DRAM several times smaller than that of COTS devices.

[0062] In the related technology 2, the solution to deal with memory failure is to improve reliability by implementing multi-module redundant memory management through software. In order to implement multi-module redundant memory management, this solution adds a multi-module redundant arbitration layer based on the traditional memory allocator, and through the newly added API, reads and writes multiple independent memory blocks at the same time to achieve multi-module redundant memory access.

[0063] During the research, the inventor found that the solution needs to add new memory management interfaces in the source code. For example, to implement multi-module redundant memory application, release, read and write, it is necessary to add corresponding memory application interfaces, memory release interfaces, memory read interfaces and memory write interfaces in the source code. These newly added interfaces are equivalent to adding a set of interfaces independent of the current general memory manager, and are not compatible with the currently commonly used memory managers, such as ptmalloc.

[0064] For example, in the ptmalloc memory manager, the malloc function and free function can be used to implement memory application and memory release respectively. However, in this solution, the malloc function and free function cannot be used to implement the application and release of multi-module redundant memory variables, and pointers cannot be used directly for reading, writing and other operations like malloc.

[0065] Therefore, due to the lack of compatibility, it is impossible to achieve compatibility of the same set of code with both unreliable and highly reliable scenarios. To pre-implement multi-module redundant memory management, it is necessary to perform intrusive shotgun reinforcement modifications on the historical version of the source code. For large-scale software codes, the code quality and maintenance costs are unacceptable.

[0066] It can be seen that in the relevant technology, the cost of high-reliability hardware is high; the solution of adding a dedicated multi-mode redundant memory interface to the software is incompatible with the method used in unreliable scenarios (malloc, free, pointer access), and requires shotgun modification.

[0067] In the fields of industrial control and aerospace, there is a widespread demand for business-transparent multi-module redundant memory management and execution efficiency. As a new infrastructure information network and a global seamless network integrating the sky and the earth, the satellite communication network has an important impact on the development of many fields such as future communications (such as 6G) and needs to have high reliability. Due to the demands of cost, computing power, and rapid iteration, the satellite communication field is turning to the use of COTS devices, and the failure rate of COTS in strong radiation environments increases by nearly 10%. 5 The reliability pain points brought about by this transformation require aerospace software to increase the implementation of multi-mode redundancy to ensure its error detection and fault tolerance capabilities.

[0068] As the business and scale of the satellite field expand, the code size has grown from the traditional hundreds of thousands to tens of millions. How to avoid code-invasive shotgun reinforcement has become particularly important. Therefore, solving problems such as code quality and maintenance costs caused by shotgun modifications introduced by multi-mode redundancy has become a key demand.

[0069] In view of this, an embodiment of the present application proposes a new memory management solution to meet the above challenges.

[0070] like Figure 2As shown, the solution provided by the embodiment of the present application can be applied to application scenarios with high reliability requirements such as industrial control, aerospace, satellite communications, railways, nuclear power plants, and medical treatment, and can also be applied to various application scenarios in daily life production that have high requirements for memory reliability. For example, it can be applied to application scenarios where entities such as banks and government agencies store important data information.

[0071] The embodiment of the present application proposes a new multi-module redundant memory management solution, which does not require adding a new API in the source code. Instead, during the compilation process, for variables modified by adding a preamble, at least one of the memory application interface, memory release interface, memory read interface, and memory write interface with the variable as the execution object is compiled into a call to a plug-in function (multi-module redundant memory management interface), thereby realizing multi-module redundant memory management without modifying the memory management interface in the source code, and being compatible with memory managers such as ptmalloc. That is, it is possible to implement various memory application, release, and read-write interfaces without modifying them in the source code, and still use various functions of the ptmalloc manager, but after compilation, when the executable code is running, for variables with added preambles, multi-module redundant memory management is executed.

[0072] In order to facilitate the understanding of the solution proposed in the embodiment of the present application, the relevant terms are briefly explained:

[0073] Directive: a compilation guidance statement, which is commonly used in heterogeneous programming (such as cuda) to guide the compiler to generate auxiliary instructions other than source program instructions, so as to make full use of the characteristics of heterogeneous hardware and give full play to the optimal system performance. The embodiment of the present application introduces directives into multi-mode redundant memory management for the first time, so that multi-mode memory reinforcement can be achieved without modifying the business code, so that multi-mode memory reinforcement and traditional memory allocation can coexist, and the version onetrack of the business code of multi-mode memory reinforcement and traditional memory allocation can be achieved.

[0074] One Track: A software development model that uses a code repository trunk. The entire product software uses the same code repository trunk during the multi-version development process, and continuously delivers to meet user needs through iteration. One Track of software code versions can reduce the number of parallel development versions of different products, reduce branching and synchronization waste, achieve the effect of continuous evolution of a set of codes and simultaneous benefits for multiple software versions, greatly shorten development time, reduce code maintenance costs, and ensure code quality costs. The solution of adding a new calling interface in the source code in related technologies cannot achieve One Track because it is not compatible with previous software code versions.

[0075] like Figure 2As shown, the method proposed in the embodiment of the present application can be upgraded on the basis of the original code warehouse trunk to realize multi-mode redundant memory management and improve reliability. For example, it can be implemented by adding a functional plug-in during the compilation process. XMR Pass is a functional plug-in for upgrading multi-mode redundant management. The functional plug-in can be added to the Pass pipeline sequence during the compilation process to realize compilation plug-in without making major modifications to the source code.

[0076] Multi-modular Redundancy (MMR): A fault-tolerant technology that uses multiple independent modules to perform the same task and identifies and corrects the faulty modules through consistency comparison to ensure that the system can still operate normally when a fault occurs. When one of the modules fails, the remaining modules can continue to work, and then the faulty module is identified and corrected through consistency comparison to achieve system reliability and stability.

[0077] The principle of multi-mode redundancy technology is based on the principle of probability statistics. Assuming that the failure probability of each module is independent, the probability of multiple modules failing at the same time is very small and can often be ignored. Therefore, multi-mode redundancy can effectively improve the reliability and stability of the system. Multi-mode redundancy technology is widely used in fields with high reliability requirements such as aerospace, railways, and nuclear power plants to ensure the safe operation of the system in extreme environments.

[0078] Triple modular redundancy (TMR): The multi-module redundancy technology is constructed using three independent modules, which is called triple modular redundancy technology.

[0079] Multi-module redundant memory management (MMR MM): A highly reliable memory allocator that can use multiple independent memory pools to allocate memory. Each memory pool is independent and can be in different physical locations or different virtual address spaces. When a user applies for a memory block, the allocator obtains a memory block of the same capacity from multiple independent memory pools and returns it to the user for use. When one of the memory blocks fails, the faulty memory block can be identified by comparing the contents of different memory blocks for consistency, and the error of the faulty memory block can be corrected to achieve highly reliable memory management. Multi-module redundant memory allocators are often used in high-reliability and high-availability systems, such as aerospace, railways, medical and other fields. It can effectively avoid single point failures and improve the fault tolerance and reliability of the system.

[0080] Triple Modular Redundant Memory Management (TMR MM): Multi-modular redundant memory management that allocates memory from three independent memory pools is called triple modular redundant memory management.

[0081] Application Programming Interface (API), in the embodiment of the present application, API is a predefined function for calling.

[0082] In order to more intuitively compare the improvements made by the solutions proposed in the embodiments of the present application, for example, Figure 3 and Figure 4 As shown, Figure 3 It is a schematic diagram of the relevant technical solution. Figure 4 This is a schematic diagram of a new solution proposed in the embodiment of the present application. Figure 3 As shown, in the related art, multiple dedicated APIs for multi-mode redundancy management are newly added, and the source code needs to be significantly modified, and a calling interface for the dedicated API is added to the source code, or corresponding API codes are added. Figure 3 As shown in the figure, the calling interfaces for the special API are newly added in the source code, namely ***malloc(), ***free(), ***read(), and ***write(). After compilation, the executable code executes the corresponding operations of each API when it runs. "***malloc()" and so on indicate that the calling interfaces for the newly added special API are two different interfaces from the calling interfaces in the current general memory manager, and are therefore incompatible, or in other words, incompatible with the memory management interface used in the code repository trunk.

[0083] In the solution provided in the embodiment of the present application, Figure 4 As shown, in the source code, there is no need to modify the original interface, but the malloc() function, free() function, read() function and write() function can continue to be called. It is only necessary to add a lead to modify the variable when defining the variable. In the compilation stage, for various interfaces corresponding to the variables modified by the lead, such as the memory application interface of calling the malloc() function, the write interface of calling the write() function, the read interface of calling the read() function and the release interface of calling the free() function, in the compilation stage, they are compiled into a special interface for multi-mode redundant memory management through the compiler, for example, they are compiled into calling the first API, calling the second API, calling the third API and calling the fourth API respectively to obtain the compiled target code.

[0084] The first to fourth APIs are plug-in functions, which can be pre-added to the library function for calling. When the executable code corresponding to the target code is running, the first API is at least used to apply for N copies of memory, the second API is at least used to write the value of the variable into N copies of memory, the third API is at least used to read the value in N copies of memory, and the fourth API is at least used to release N copies of memory. The second API and the third API can also compare the values ​​of multiple memory blocks for consistency, perform arbitration, and correct errors.

[0085] Among them, it should be noted that Figure 4 In the figure, the first API to the fourth API are marked with dotted boxes, indicating that in some embodiments, the first API to the fourth API can be called during the compilation stage; in other embodiments, the codes of the first API to the fourth API can be directly added to the target code, that is, the various interfaces such as memory application in the source code are compiled into the codes of the corresponding API, and the API is directly executed at runtime without calling the corresponding API again.

[0086] In addition, the solution proposed in the embodiment of the present application can be based on the following Figure 5 It can be executed by the common memory allocator shown in , that is, it can be compatible with at least one memory manager among ptmalloc, jemalloc, and tcmalloc without adding a dedicated memory allocator.

[0087] The solution in the related art needs to be Figure 5 That is, it is not compatible with the current general memory allocator, and a dedicated triple-module redundant fault-tolerant memory allocator needs to be added. For example, a multi-module redundant arbitration layer is added to realize the application / release / read / write and consistency arbitration and error correction of multi-module memory, and then multi-module redundant memory access is realized through the newly added multi-module read and write API.

[0088] like Figure 6 As shown, the solution proposed in the embodiment of the present application (the solution labeled ③) can be executed based on ordinary memory allocation managers ① such as ptmalloc, without adding a special manager. It is only necessary to add a modifying preamble before the memory variable. Compared with the shotgun modification in the related technology ②, the modification of the source code is significantly reduced. For example, it is only necessary to add a preamble "_tmr" before the pointer variable "*p", which can be specifically implemented through macro definition; the code of the non-high-reliability scenario is almost completely consistent with the code of the high-reliability reinforcement scenario (except for a small number of preambles), ensuring the onetrack of software versions in different scenarios.

[0089] The above comparison is for illustrative purposes only and is not intended to limit the method provided in the embodiments of the present application.

[0090] Specifically, the memory management method provided in the embodiment of the present application can be used to perform dynamic memory allocation or static memory allocation, and can be run at the operating levels of both kernel mode and user mode operating systems. In this way, the method provided in the embodiment of the present application can be specifically applied to two categories and four scenarios: user mode multi-mode redundant dynamic memory management (such as ptmalloc), kernel mode multi-mode redundant dynamic memory management (such as kalloc), user mode multi-mode redundant static memory management, and kernel mode multi-mode redundant static memory management.

[0091] The following describes the method proposed in the embodiment of the present application from the two perspectives of dynamic memory management and static memory management.

[0092] In the dynamic memory management (user state or kernel state) scenario, the memory management method proposed in the embodiment of the present application can be implemented during the compilation process, and specifically may include the following process:

[0093] S1, recognize that there is a preamble in the compilation object.

[0094] The introduction is used to modify the memory variable, that is, the modified object of the introduction is the memory variable, and the modified memory variable is the target variable that needs to apply for multi-module redundant memory. The introduction can play an identification role, so that during the compilation process, the compiler can distinguish between the variables and variables that need to be managed by multi-module redundant memory and those that do not need to be managed by multi-module redundant memory by identifying the introduction.

[0095] In some embodiments, a preamble can be added to the source code to be compiled as a modified preamble of a memory variable without adding a new API or a new calling interface to the source code. For example, the source code needs to call a memory application API (i.e., a memory application interface) compatible with POSIX. When applying for multi-mode redundant memory, a multi-mode redundant preamble (such as __xmr) is added before receiving the definition of the memory variable. Then, the memory application interface modified with the preamble is: __xmr char*p=malloc(size). Optionally, the preamble can be added to the source code in a unified manner in the form of a macro definition without the need to manually modify them one by one.

[0096] The lead may specifically be a character or a combination of characters that can play an identification role, for example, one or more combinations of numbers, letters and special symbols may be used. For example, the lead may specifically be "XMR", "xmr", "_XMR", "XMR_", "MMR", "TMR", "MMR_", "5MR", "MR5_", "M3R&", etc. Any character that can play a modifying and identifying role may be used as a specific expression form of the lead, and the embodiments of the present application will not be enumerated. The following description will mostly take "MMR" or "TMR" as an example.

[0097] The compiled object, i.e. the code to be compiled, may be source code or intermediate code. The compilation of high-level language source code can be divided into front-end processing, mid-end processing and back-end processing. The method provided in the embodiment of the present application can be implemented before the source code is compiled into binary code, for example, in the mid-end processing, so the compiled object is the intermediate code after the front-end processing.

[0098] For example, when the source code is in C / C++, the compilation process is: preprocessing → compiling → assembling → linking, and then generating executable code (i.e. binary code), then the compilation object can be the intermediate code after preprocessing. If the source code is Java, the corresponding compilation process is: source code with .java extension, Java source code file is compiled into Java bytecode file (.class file) by Java compiler (such as javac), then the compilation object is source code with .java extension.

[0099] The lead in the compiled object may be added to the code, such as the source code, before the compiled object is compiled. In some embodiments, the lead is added to the source code, and the modified lead may be added to the variables that need to be managed by multi-module redundant memory uniformly by macro definition.

[0100] It should be noted that in the embodiment of the present application, multi-mode redundant memory management includes one or more of a variety of operations such as multi-mode redundant memory application, multi-mode redundant memory release, multi-mode redundant memory reading, multi-mode redundant memory writing, multi-mode redundant memory arbitration and correction.

[0101] For ease of description, the memory variables that require multi-mode redundant memory management are defined as target variables, and the memory variables that do not require multi-mode redundant memory management are defined as ordinary memory variables.

[0102] In some embodiments, the introduction can be added to the code line corresponding to the target variable. The code line corresponding to the target variable can be the code line where the code defining the target variable is located. The code line is defined as the target code line, and the code line corresponding to the target variable can be the target code line or other code lines within the preset range of the target code line.

[0103] For example, in a dynamic memory management scenario, the target variable is *p, then the target code line corresponding to the target variable is: __xmr char*p=malloc(size). Among them, __xmr is a preamble, char*p is the code that defines the target variable, and the code line where the code that defines the target variable *p is located is: __xmr char*p=malloc(size), which is the target code line. malloc(size) is a memory neural interface that calls the malloc function. In this embodiment, the preamble is added before the target variable. In other embodiments, the preamble can be added to other locations, such as after the target variable, and the resulting code line (target code line) is: char*p__xmr=malloc(size); or the preamble can be added after the memory application interface, and the resulting code line (target code line) is: char*p=malloc(size)__xmr; or, it can also be added between the target variable type definition character char and the target variable *p, and the resulting code line (target code line) is: char__xmr*p=malloc(size).

[0104] In other embodiments, the preamble may also be added to a code line adjacent to or close to the target code line, for example, in the above example, __xmr char*p=malloc(size)

[0105] The code can be changed to the following:

[0106] __xmr

[0107] char*p=malloc(size)

[0108] This code example is a preamble as a separate code line, which appears in a line adjacent to or close to the target code line. That is, the preamble can appear in the previous or next line of char*p=malloc(size), or in the preset number of lines before or after it. It can play the role of identifying the target variable during compilation. In actual applications, the farther the distance between the preamble and the target variable is, the greater the compilation difficulty. "__xmr" is only an example and can be replaced by other characters.

[0109] In the static memory management scenario, it is also added to the code line corresponding to the code that defines the target variable. However, in the static memory management scenario, the application of multi-mode redundant memory does not require calling the memory application function, such as the malloc function, so there is no memory application interface. In this case, the introduction can be added before or after char*p, or between char and *p, or to adjacent or similar code lines.

[0110] Accordingly, when identifying whether there is a preamble in the compiled object, the identification method corresponds to the method of adding the preamble. For example, if the addition method is to add the preamble before the target variable, then during identification, it is necessary to analyze whether there is a preamble before the memory variable that appears in the code. If the method of adding the preamble is to add it after the memory application interface, then during identification, it is possible to query whether there is a preamble after the memory application interface.

[0111] In the embodiments of the present application, it is supported to add modification preambles to various types of memory variables. For example, the modified memory variables can be auto (local variables), extern (global variables) or static variables, etc. Static variables include global variables and local variables with the keyword static as storage type description. According to the data type stored, the memory variable can be one or more of numeric type, character type, date type, date and time type, logical type and currency type. For example, char*p is a character type variable. Compatible with the current memory manager (such as ptmalloc), the solution provided by the embodiments of the present application supports accessing memory variables in the form of pointers.

[0112] It should be noted that the embodiments of the present application mostly use the malloc function as the memory request API for illustrative description. In fact, the solution provided in the embodiments of the present application can also be applied to the calloc function or the realloc function.

[0113] S2, compile and insert the compiled object to obtain the target code.

[0114] When the executable code corresponding to the target code is run, it is used to apply for at least N memory portions (eg, N memory blocks) corresponding to the target variable, where N ≥ 2 and is an integer.

[0115] In some embodiments, compiling and instrumenting the compiled object at least modifies the memory application interface with the target variable as the object in the compiled object to call the first API. The executable code corresponding to the first API is used to apply for N memory corresponding to the target variable at least during runtime. The first API is a function for executing multi-module redundant memory application, which can be pre-defined and added to the library function.

[0116] Exemplarily, before the compiler compiles the code into an executable binary program, the memory application interface with the added multi-module redundant preamble will be changed to call the multi-module redundant memory application interface to apply for multiple copies of memory of the same capacity from multiple memory pools, for example, applying for N copies of memory, and applying for a multi-module redundant memory management structure to uniformly manage multiple memory blocks, at least returning the addresses of multiple memory blocks, and in some embodiments, the address of the multi-module redundant memory management structure can also be returned.

[0117] In some embodiments, compiling and instrumenting the compiled object further includes modifying the read operation of the compiled object with the target variable as the object to call a second API. The second API is a function for performing a multi-module redundant memory read operation, and the executable code corresponding to the second API is used to read the values ​​stored in the N memories respectively when running.

[0118] In the same embodiment or other embodiments, performing compilation stub on the compiled object may also include: modifying the write operation with the target variable as the object in the compiled object to call a third API. The third API is a function for performing a multi-module redundant memory write operation. The executable code corresponding to the third API is used at least to write the value of the target variable into N copies of memory respectively when running.

[0119] For example, the memory read interface example in the source code is a=*p, because *p specifies the multi-module redundant preamble when applying for memory, that is, *p is a memory variable. Therefore, before the compiler compiles the code a=*p into an executable binary program, it will convert the pointer read access form (such as *p) into a call to the multi-module redundant memory read interface (third API), such as __xmr_read. The multi-module redundant memory read interface (__xmr_read) reads the values ​​in N copies of memory in sequence, reads their contents in sequence, and checks the consistency of multiple copies of memory. For inconsistent memory, correct its errors. In some embodiments, the addresses of multiple memory blocks can be stored in a multi-module redundant memory management structure, and the multi-module redundant memory read interface (__xmr_read) reads the specified multiple copies of memory according to the multi-module redundant memory management structure, and returns the value of the correct memory in the multiple copies of memory.

[0120] For another example, the memory write interface example in the source code is *p=10. Because *p specifies the multi-module redundant directive when applying for memory, the compiler will convert the pointer write access form (such as *p) into a call to the multi-module redundant memory write interface (second API), such as __xmr_write, before compiling the code into an executable binary program. The multi-module redundant memory write interface (such as __xmr_write) updates the value of each memory in turn, and checks the consistency of multiple memories. For inconsistent memories, correct their errors and return the value of the correct memory in the multiple memories. In some embodiments, optionally, the addresses of multiple memory blocks can be stored in a multi-module redundant memory management structure, and the multi-module redundant memory write interface (__xmr_write) writes the value of *p in turn to the specified multiple memories according to the multi-module redundant memory management structure, and returns the value of the correct memory in the multiple memories.

[0121] Similarly, for the compilation of the release interface, the memory release interface with the target variable as the object in the compilation object is modified to call the fourth API. The fourth API is a function for executing the multi-module redundant memory release. The executable code corresponding to the fourth API is used to release at least N copies of memory when running.

[0122] For example, for the memory release interface example in the source code, free(p), the compiler determines whether the memory variable to be released is a normal memory variable or a target variable that requires multi-module redundant memory management based on the input parameter p in the free interface. For the target variable, multiple copies of memory requested by malloc are released in sequence, and then the multi-module redundant memory management structure is released. For normal memory variables, the memory space occupied by them can be directly released.

[0123] Specifically, the memory application interface with the target variable as the object in the compilation object is modified to call the first API, and the code corresponding to the memory application interface in the source code is modified and compiled into the code that calls the first API.

[0124] For example, Figure 7 As shown, Figure 7 A feasible system architecture for dynamic memory allocation is shown, which includes a compiler and a user-mode / kernel-mode multi-mode redundant dynamic memory manager. The user-mode / kernel-mode multi-mode redundant dynamic memory manager includes multiple memory pools and a multi-mode redundant memory management structure.

[0125] During the compilation process, the compiler recognizes "__xmr char*p=malloc(size)" in the source code and the presence of the introduction "__xmr", so it is necessary to compile the code corresponding to the memory application interface "__xmr char*p=malloc(size)" into the code that calls the first API through the compiler XMR plug-in: "_xmr malloc(i32%size)", where "_xmrmalloc" is the function name of the first API.

[0126] Figure 7 In the source code shown, a=*p is a read operation with the target variable *p as the object. During compilation, the compiler XMR plug-in compiles it into code for calling the third API: "call void@tmr_read(i8*%p,i32 1)", where "tmr_read" is the function name of the third API.

[0127] *p=10 is a write operation with the target variable *p as the object. During compilation, the compiler XMR plug-in compiles it into code for calling the second API: "call void@tmr_write(i8*%p,i8 10)", where "tmr_write" is the function name of the second API.

[0128] After compilation and stubbing, the target code obtained can at least execute the operations of applying for N memory, writing N memory, reading N memory, and releasing N memory at runtime. N = 3 means three-mode memory redundancy management, and N = 5 means five-mode memory redundancy management. N can be specified in the compiler XMR plug-in.

[0129] Exemplarily, in some embodiments, the executable code corresponding to the target code obtained after compiling and inserting can also apply for a multi-module redundant memory management structure for managing N copies of memory when running. Exemplarily, when the executable code corresponding to the first API is running, it first applies for a multi-module redundant memory management structure and then applies for N copies of memory; when releasing, when the executable code corresponding to the fourth API is running, it first releases N copies of memory and then releases the multi-module redundant memory management structure.

[0130] For example, Figure 7 The three-mode memory management structure and the five-mode memory management structure shown. To apply for a multi-mode redundant memory management structure, it is necessary to reserve corresponding memory space to store the necessary information required for read / write operations on N copies of memory, so as to manage the N copies of memory. In different embodiments, the memory space reserved for the management structure may include the memory space occupied by N memory blocks, or may not include the memory space occupied by N copies of memory.

[0131] In contrast, ordinary memory variables (i.e. Figure 7 In this way, if there is no multi-mode redundancy preamble as shown in , there is no need to compile and insert stubs, but directly apply for 1 memory block. In this way, if there is a preamble, the stubs are compiled, and if there is no preamble, the stubs are not compiled, so that the same set of code can be compatible with both high-reliability memory management requirements and non-high-reliability memory management requirements.

[0132] It should be noted that the solution provided in the embodiment of the present application can be run in user mode or in kernel mode.

[0133] The source code in the embodiments of the present application may include business APP code and / or non-business code.

[0134] Furthermore, if Figure 8 As shown, illustratively, taking the source code in CC++ language as an example, the compilation stub is further explained.

[0135] Figure 8The changes of the business APP code (source code) and the compiler IR code before and after the compilation and stubbing are shown. In the business APP code stage, the introduction "_tmr" (triple module redundancy) is added. In the compilation stage, the compiler IR code is modified to call the multi-module redundant memory application function (first API) "_xmr malloc()", call the multi-module redundant memory read function (third API) "call void@_xmr read()", call the multi-module redundant memory write function (second API) "_xmrwrite()", etc. It should be supplemented that when the free() function appears in the source code, that is, when the memory release interface appears, it is compiled to call the multi-module redundant memory release function (fourth API) "_xmr free()".

[0136] like Figure 8 As shown, the compilation process can be divided into Frontend, Midend and Backend processing, and the compilation plug-in can be implemented in the mid-end processing stage. Exemplarily, the compiler XMR plug-in, specifically XMRPass, is added to the Pass Pipeline. For example, in some embodiments, it can be added at the end of the Pass Pipeline. Among them, pass represents a functional plug-in that may play an optimization role in the compilation process, and Pass Pipeline is a plug-in sequence. For example, LLVM (Low Level Virtual Machine) is a framework system for building compilers. For specific compilation optimizations, LLVM needs to use a set of fixed Passes, and a set of Passes with a fixed combination is PassPipeline. In an embodiment of the present application, the Pipeline after compilation plug-in is composed of Inline Pass, DCE Pass...XMR Pass. It should be noted that in other embodiments, XMR Pass can also be added to other positions in the pipeline, not limited to being added to the end of the pipeline.

[0137] Optionally, a compilation switch for controlling whether to start XMR Pass can be set. If the switch is turned on, compilation instrumentation is performed, and if the switch is turned off, compilation instrumentation is not performed.

[0138] It should be noted that, in order to realize the recognition of the lead-in during the compilation process, it is also necessary to add the lead-in attributes in the source code analysis and recognition stage. In a compilation process, the source code analysis and recognition stage, i.e., the front-end processing process, may include three stages: lexical analysis, grammatical analysis, and semantic analysis, to obtain the intermediate code, wherein the source code is subjected to lexical analysis to obtain lexical terms, the lexical terms are subjected to grammatical analysis to obtain a grammatical tree, and the grammatical tree is subjected to semantic analysis to obtain the intermediate code. In some embodiments of the present application, it is necessary to add attribute recognition for the lead-in in at least one of the lexical analysis layer, the grammatical analysis layer, and the semantic analysis layer. For example, if the lead-in in the source code is "tmr_", it is necessary to add semantic recognition for the character "tmr_" in the source code analysis and recognition stage.

[0139] In some embodiments, the introduction only needs to be added when the target variable memory is applied for. After the application, the reading, writing and releasing of the target variable do not need to add the introduction. This requires adding attribute information about the target variable during the compilation process, for example, in at least one of the lexical analysis layer, the syntax analysis layer and the semantic analysis layer, so that the compiler can identify the variable as a target variable that needs to be managed by multi-module redundant memory.

[0140] After compiling and inserting, the target code is obtained. In some embodiments, the target code can be Figure 8 The IR code (intermediate representation) obtained after the "Midend" processing shown in the figure is obtained. The target code is then processed by the backend to obtain the machine code (executable code).

[0141] The compilation process of C / C++ may also be divided into multiple stages: preprocessing, compilation, assembly and linking. In other embodiments, the target code may be the code after compilation and before assembly.

[0142] For Java language source code, the target code obtained after compilation and instrumentation is the code with the extension .class, that is, the Java bytecode file.

[0143] It should be noted that the product form corresponding to the method provided in the embodiment of the present application can be an application program, a program upgrade package, a functional plug-in, etc., for example Figure 8 The functional plug-in TMR Pass shown is used to upgrade the software version and improve reliability.

[0144] In addition to implementing dynamic memory management, the method provided in the embodiment of the present application can also implement static memory management.

[0145] When the modified memory variables are static variables and global variables, static memory management is applicable. Static variables include static local variables and static global variables. Different from dynamic memory management, static memory is centralized in a unified program segment by the compiler. When the binary program is loaded, the OS applies for memory at one time; when the program exits or the OS is shut down, the memory is released at one time.

[0146] like Fig. 9 As shown, static memory management can be based on Fig. 9 The system architecture shown is executed, and the system architecture includes a program loader or an OS loader, a memory manager, and a compiler. The APP memory space is the memory space allocated by the memory manager for the APP.

[0147] Specifically, the static memory management method provided in the embodiment of the present application may include the following process:

[0148] S10, identifying that there is a lead in the compilation object.

[0149] In static memory management, the introduction is used to modify static variables or global variables to indicate that the modified memory variable is the target variable that needs to apply for multi-module redundant memory;

[0150] S20, compile and insert stubs on the compiled object to obtain the target code.

[0151] When the executable code corresponding to the target code is run, it is used to apply for at least N memory corresponding to the target variable, where N ≥ 2 and is an integer.

[0152] In some embodiments, different from dynamic memory management, the compilation instrumentation for the memory application interface and the memory release interface is as follows:

[0153] Memory request:

[0154] The compiler links the variable definitions specified in the compilation directive to the multi-mode data segment of the binary program (executable code), for example, see Fig.10 , where, when there is a specified multi-mode redundant directive (such as _tmr) in the compilation object, the variable c definition with the directive is linked to the multi-mode memory segments ".data_tmr1, .data_tmr2, .data_tmr3" (i.e., the multi-mode data segment) of the binary program; the variable a definition without a specified compilation directive is linked to the original data segment of the binary program (such as .data).

[0155] Specifically, taking the three-mode as an example, the compiler recognizes variable symbols with compilation directives such as "tmr" and stores them in the symbol table during the lexical analysis and syntax analysis stages; three multi-mode redundant data segments (such as .data_tmr1, .data_tmr2, and .data_tmr3) are added to store the variable data of each mode respectively.

[0156] Fig.10 In the example, char a represents a character variable a, char c represents a character variable c, ELF Header represents an ELF file header, Program header represents a program header, .text represents text, data represents a data segment, and section header represents a segment header. Kernel data represents kernel data, stack represents a stack, heap represents a heap, Shared LibrariesMemory Mapping represents the memory mapping area of ​​a shared library; Load Segments.data represents loading segment data, and do_execve(), Search_binary_handler, load_elf_binary, and start_thread are all functions.

[0157] The program loader or the OS loader parses the multi-module redundant data segments in the binary program when the program is loaded or the OS is loaded, and uniformly applies for memory space of multiple copies of the multi-module redundant data segments.

[0158] Memory release:

[0159] When the program exits or the OS shuts down, the program loader releases multiple multi-mode redundant data segments uniformly.

[0160] For a memory read interface with a memory variable (target variable) modified by a preamble as the object, for example, *p is the target variable and a=*p is the read interface, the compilation and instrumentation operations for the read interface are as follows:

[0161] Because *p specifies the multi-mode redundant directive when applying for memory, the compiler will convert the pointer read access form (such as *p) into a call to the multi-mode redundant memory read interface (such as __xmr_read) before compiling the code into an executable binary program.

[0162] The multi-mode redundant memory read interface (such as __xmr_read) reads the contents of multiple copies of memory specified by the multi-mode memory management structure in sequence, checks the consistency of the multiple copies of memory, corrects the errors of inconsistent memories, and returns the value of the correct memory among the multiple copies of memory.

[0163] The compilation and instrumentation operations for the write interface (example *p=10) are as follows:

[0164] Because *p specifies the multi-mode redundant directive when applying for memory, the compiler will convert the pointer write access form (such as *p) into a call to the multi-mode redundant memory write interface (such as __xmr_write) before compiling the code into an executable binary program.

[0165] The multi-mode redundant memory write interface (such as __xmr_write) updates the value of each memory in turn according to the multiple memories specified by the multi-mode memory management structure, checks the consistency of the multiple memories, corrects the errors of the inconsistent memories, and returns the value of the correct memory among the multiple memories.

[0166] According to the above embodiments, it can be obtained that, in static memory management, compiling and instrumenting the compiled object to obtain the target code may include at least one of the following:

[0167] Memory application: The definition of the target variable in the compiled object is linked to the multi-mode data segment of the binary program to obtain the executable code; the executable code is used to apply for N copies of memory corresponding to the target variable when it is loaded or loaded by the operating system.

[0168] Memory read: modify the read interface with the target variable as the object in the compiled object to call the second API; the second API is a function for performing multi-module redundant memory read operations; the executable code corresponding to the second API is used to read at least the values ​​stored in N copies of memory during runtime.

[0169] Memory write: modify the write operation with the target variable as the object in the compiled object to call the third API; the third API is a function for performing multi-module redundant memory write operations; the executable code corresponding to the third API is used to at least write the value of the target variable into N copies of memory during runtime.

[0170] Several specific embodiments are listed below.

[0171] like Fig.11 As shown, in a specific embodiment, TMRheader is added based on the ptmalloc memory management structure, and FatPointer (fat pointer, also called wide pointer) is used to implement TMR memory tracking. The specific implementation steps are as follows:

[0172] S11, identifying the lead in the compilation object. In this embodiment, the compilation object is a C / C++ language source code, the target variable is *p, and the code line corresponding to the target variable (target code line) is: __xmr char*p=malloc(size), where "__xmr" is the lead, "char*p" is the definition of the target variable, and "malloc()" is the memory application interface.

[0173] The memory application interface "malloc()" is a POSIX-compatible memory application API. POSIX, or Portable Operating System Interface, is a general term for a series of interrelated standards that define APIs for running software on various UNIX operating systems. Its formal name is IEEE Std 1003, and its international standard name is ISO / IEC 9945. The method provided in the embodiment of the present application compiles POSIX-compatible memory application, release, read, write and other memory management interfaces, that is, it is compatible with the current ISO / IEC 9945 standard, that is, it implements multi-mode redundant memory management without changing the memory management interface under the current standard. The related technology is not compatible with POSIX because it uses a new memory management interface in the source code.

[0174] It should be noted that the embodiments of the present application are mostly described using the ptmalloc memory manager as an example. In fact, the method provided in the embodiments of the present application can also be compatible with memory managers such as jemalloc and tcmalloc.

[0175] In this embodiment, the introduction is added before the target variable, so when identifying, the introduction can be identified first, and then the memory variable after the introduction can be determined as the target variable. Therefore, the modified memory variable needs to add a new attribute, which is used to indicate that the memory variable needs to be managed with multi-module redundant memory. Specifically, the attribute information about the target variable can be added in the source code analysis and identification stage during compilation, such as in at least one of the lexical analysis layer, the syntax analysis layer, and the semantic analysis layer, so that during the compilation process, other operations with the target variable as the object, such as releasing, reading and / or writing interfaces, can be identified as objects that need to be compiled and plugged in without adding introductions, that is, the original ordinary function call is modified to call the second API, the third API, or the fourth API.

[0176] S12, compile and insert the compiled object to obtain the target code.

[0177] In this embodiment, the compilation object is compiled and plugged, which may be a memory management interface with the target variable as the object, and a compilation and plugging operation is performed, and the memory management interface includes at least one of a memory application interface, a memory read interface, a memory write interface, and a memory release interface; the compilation and plugging may be specifically performed in the following manner:

[0178] Before the compiler compiles the compiled object (source code or intermediate code) into an executable binary program, the following process is added to the memory allocation interface with the multi-module redundant preamble (for example, __xmr char*p=malloc(size)):

[0179] Preprocessing: reserve memory space for the TMR management structure and apply for the TMR management structure. The TMR management structure is a new management structure based on the original ptmalloc management structure. For example, Fig.11 As shown in the figure, TMR Header is a newly added TMR management structure, which is used to manage multiple memories occupied by target variables.

[0180] Reserving memory space for the TMR management structure may be implemented based on a variety of existing memory reservation methods, such as reservation based on an mmeblock management mechanism, and may be reserved from system available physical memory or user reserved memory.

[0181] The TMR management structure includes at least a TMR Header. Optionally, the TMR management structure may also include an mchunkHeader and an address space for applying for three copies of memory.

[0182] Application: After applying for the TMR Header, apply for three independent memory blocks from the free queue. This embodiment uses triple-module redundant memory management as an example to explain, that is, for each target variable, three memory blocks need to be applied for its use. Fig.11 As shown, three memory blocks are applied, namely, primary mchunk1, backup mchunk2, and backup mchunk3.

[0183] Allocation: After obtaining three independent memory blocks, the first addresses of the memory blocks are uniformly returned to the TMR management structure. Specifically, in this embodiment, the base addresses of the backup mchunk2 and backup mchunk3 are returned to the TMR Header, where pTmr3 is a memory unit for storing the base address of the backup mchunk3, and pTmr2 is a memory unit for storing the base address of the backup mchunk2.

[0184] Returns a wide pointer: Use the high bit of fatpointer to store the base address of main mchunk1 (such as Fig.11 The first pointer is stored in the low bit. A wide pointer is a pointer that occupies two bytes of a normal pointer, and a first pointer is a normal pointer that occupies half the bytes of a wide pointer. Exemplarily, the wide pointer in this embodiment occupies 64 bits (8 bytes), and the first pointer occupies 32 bits. The wide pointer fatpointer can be (pBase, p1), where p1 is the first pointer.

[0185] The first pointer points to the memory address in the main mchunk1 memory block for storing the value of the target variable. The base address is the starting address of the memory block, and the memory address pointed to by the first pointer is the address where the value of the target variable is actually stored.

[0186] In other embodiments, the high bit of the wide pointer can also be used to store the base address of the TMR header, that is, when applying for the management structure, the base address of the TMR header is returned as the high bit of the fatpointer, and the first pointer is used as the low bit of the fatpointer.

[0187] The memory address pointed to by the first pointer may be the address in the main memory block mchunk1 returned after the write operation is performed on the three memory blocks. The memory addresses in the backup mchunk2 and backup mchunk3 used to store the values ​​of the target variables do not need to be returned.

[0188] In this way, after the above operations, N copies of memory can be applied for. When the TMR memory is accessed through pointer read / write, pBase is found through the compiler instrumentation function, and then the TMR header address is found. Then, three independent memory blocks are obtained in turn, and read / write operations are performed on them. The data consistency of the three copies of memory is compared, the correct data is obtained through arbitration, and the wrong data is corrected.

[0189] Specifically, exemplarily, the compilation and instrumentation operations for the memory read interface are as follows:

[0190] For the memory read interface in the compiled object, such as a=*p, since *p specifies the multi-mode redundant directive when applying for memory, the compiler will convert the pointer read access form, such as *p, into the following process before compiling the code into an executable binary program:

[0191] Get the base address (pBase) of "main mchunk1" through the high bit of fatpointer, and get the first pointer (p1) of "main mchunk1" through the low bit.

[0192] Next, according to the base address pBase of the main memory block mchunk1, the base address of the TMR Header is obtained, and then the base addresses of "standby mchunk2" and "standby mchunk3" are obtained.

[0193] When applying for a memory management structure, reserve the memory space that the TMR Header needs to occupy, and specify the offset (first offset) of the base address of the main memory block mchunk1 relative to the base address of the TMR Header. The first offset is a known constant, for example, the first offset is a fixed value of m bytes. Therefore, when performing a read operation, according to the high bit of the wide pointer, the base address of the main memory block mchunk1 is obtained as pBase, then pBase plus or minus the first offset, for example, plus or minus m bytes, can get the TMR Header base address.

[0194] Then, based on pBase and p1, the pointers p1, p2, and p3 of the corresponding types of memory located at the corresponding positions in "primary mchunk1", "standby mchunk2", and "standby mchunk3" are calculated. There are two specific calculation methods, as follows:

[0195] Method 1, p1 is the second offset:

[0196] As a feasible implementation, the memory address pointed to by the first pointer p1 may be an offset address relative to pBase, that is, p1 represents an offset (second offset) relative to the main memory block mchunk1. Since the base addresses of the backup memory block mchunk2 and the backup memory block mchunk3 are stored in the TMR Header, after obtaining the base address of the TMR Header, the base address (pTmr2) of the backup memory block mchunk2 and the base address (pTmr3) of the backup memory block mchunk3 can be obtained. The base address of the backup memory block mchunk2 plus the second offset is the memory address corresponding to the second pointer, that is, the address for storing the value of the target variable. The base address of the backup memory block mchunk3 plus the second offset is the memory address corresponding to the third pointer, that is, the address for storing the value of the target variable.

[0197] Method 2: The second offset is the offset of p1 relative to pBase:

[0198] As another feasible implementation, the memory address pointed to by the first pointer p1 may be an absolute address. Then the second offset is the offset of p1 relative to the base address pBase of the main memory block mchunk1. First, the second offset of p1 relative to pBase is calculated. Since the base addresses of the backup memory block mchunk2 and the backup memory block mchunk3 are stored in the TMR Header, after obtaining the base address of the TMR Header, the base address (pTmr2) of the backup memory block mchunk2 and the base address (pTmr3) of the backup memory block mchunk3 can be obtained. The base address of the backup memory block mchunk2 plus the second offset is the memory address corresponding to the second pointer, that is, the address used to store the value of the target variable. The base address of the backup memory block mchunk3 plus the second offset is the memory address corresponding to the third pointer, that is, the address used to store the value of the target variable.

[0199] Thus, through the above method 1 or 2, the second pointer p2 and the third pointer p3 can be obtained. The data in the addresses p1, p2, and p3 are read, and the consistency of the data in the three memories is compared, the correct data is obtained by arbitration, and the wrong data is corrected.

[0200] For example, Fig.12In the example, the TMR Header is also used to store the values ​​of three memory blocks. For example, the three memory units uTmr3sum, uTmr2sum, and uTmr1sum are used to store the values ​​of backup mchunk3, backup mchunk2, and primary mchunk1, respectively, for quick comparison. After the comparison, the correct values ​​can be written into the three memory blocks respectively.

[0201] Specifically, exemplarily, the compilation and instrumentation operation for the memory write interface may be as follows:

[0202] For the memory write interface in the source code, for example, *p=10, since *p specifies the multi-mode redundant directive when applying for memory, the compiler will convert the pointer write access form, for example, *p=10, into the following process before compiling the code into an executable binary program:

[0203] Get the base address (pBase) of "main mchunk1" through the high bit of fatpointer, and get the first pointer (p1) of "main mchunk1" through the low bit.

[0204] In the address pointed to by the first pointer P1, write the value of the target variable, for example, write "10", and then obtain the base address of the TMR Header according to the base address pBase of the main memory block mchunk1, and then obtain the base addresses of "standby mchunk2" and "standby mchunk3".

[0205] For the specific method of obtaining the base addresses of "standby mchunk2" and "standby mchunk3" based on pBase, please refer to the compilation and instrumentation operation of the read interface, which will not be repeated here.

[0206] Then, the base addresses of "spare mchunk2" and "spare mchunk3" and p1 are used to obtain pointers p2 and p3 of the corresponding types of memory at the corresponding positions in "spare mchunk2" and "spare mchunk3". The specific method is the same as the above method 1 or method 2, which will not be repeated here.

[0207] Write the value of the target variable into the addresses pointed to by p2 and p3 respectively.

[0208] After writing, the data in the addresses p1, p2, and p3 can be read, and the data consistency of the three copies of memory can be compared to arbitrate the correct data and correct the incorrect data.

[0209] Exemplarily, the compilation and instrumentation operation for the memory release interface may be as follows:

[0210] For the memory release interface free(p) in the compiled object, since the input parameter p specifies the multi-mode redundant preamble when applying for memory, the compiler will convert the memory release interface into the following execution process before compiling the code into an executable binary program:

[0211] Release 3 memory blocks; release TMR Header.

[0212] In summary, Fig.11 A specific embodiment shown in the figure first performs preprocessing, applies for memory space (size) to reserve the TMR management structure, and then applies for 3 memory blocks from the four-layer idle queue. The queue parallelism of the idle queue is twice the number of cores. After obtaining the 3 memory blocks, they are uniformly managed through the TMR Header. Then, the high bit of the fatpointer is used to store the base address pBase of the main memory block or the base address of the TMR Header, and the low bit is the traditional pointer (first pointer); when the first pointer accesses, the compiled plug-in function can find pBase to perform multi-mode comparison. When performing read and write operations, memory access can be compatible with traditional heap memory access. First, during compilation, the pointer access operation is replaced with a read / write plug-in function (i.e., the second API, the third API). The read / write stub function can implement the following operations at runtime: obtain pBase through the high bit of fatpointer, obtain the pointer (p) of the corresponding type of memory in the main memory block mchunk1 through the low bit, obtain the base address of the backup memory block mchunk2 and the backup memory block mchunk3 through pBase, and calculate the pointers p1, p2, and p3 of the corresponding type of memory located in the corresponding positions of the main memory block mchunk1, the backup memory block mchunk2, and the backup memory block mchunk3 based on pBase and p. Perform triple-module redundancy comparison and return the execution result.

[0213] According to the description of the above specific embodiment, other embodiments can be summarized. In these embodiments, N copies of memory may include 1 main memory block and N-1 backup memory blocks. The target code obtained by compiling and plugging includes calling the first API. When the executable code corresponding to the first API is running, it can apply for the first multi-module redundant memory management structure, and then apply for N copies of memory corresponding to the target variable based on the first multi-module redundant management structure, and return the base addresses corresponding to the N copies of memory respectively; the first multi-module redundant management structure includes at least an object header header. The header is used to store at least the base addresses of N-1 backup memory blocks. In other embodiments, the first multi-module redundant management structure may include an object header header and a first address space; applying for N copies of memory corresponding to the target variable is applied in the first address space. Exemplarily, when applying for the first multi-module redundant management structure, the offset between the starting address of the first address space and the starting address of the header can be specified, and the starting address of the main memory block is the starting address of the first address space.

[0214] Then, define the pointer used to access the target variable as a wide pointer; return the wide pointer; the high bit of the wide pointer is used to store the first base address, and the low bit is used to store the first pointer; wherein the first base address is the base address of the main memory block mchunk1; the first pointer points to the memory address in the main memory block mchunk1 for storing the value of the target variable.

[0215] In the same embodiment or other embodiments, the target code obtained by compiling and inserting also includes calling a second API. When the executable code corresponding to the second API is running, based on the first base address pBase and the first pointer p1, the second pointer to the Nth pointer corresponding to the second base address and N-1 spare memory blocks are determined; wherein the second base address is the base address of the header; the second pointer to the Nth pointer point to the memory addresses in the N-1 spare memory blocks for storing the values ​​of the target variables, respectively. The values ​​of the target variables in each memory block can be accessed through the first pointer and the second pointer to the Nth pointer.

[0216] Among them, based on the first base address and the first pointer, the second base address and the second pointer to the Nth pointer corresponding to the N-1 spare memory blocks are determined. The second base address can be determined based on the first base address and the first offset; the first offset is the offset of the second base address relative to the first base address, and the first offset is a constant; then, according to the second base address, the base addresses corresponding to the N-1 spare memory blocks are read respectively; the second offset of the memory address pointed to by the first pointer relative to the first base address is determined; according to the base addresses and the second offsets corresponding to the N-1 spare memory blocks respectively, the second pointer to the Nth pointer are determined.

[0217] It should be noted that the base address of each spare memory block is stored starting from the starting address (i.e., the base address) of the header. In some embodiments, the header is also used to store the N values ​​returned by the first pointer to the Nth pointer; the second API can also compare the N values ​​returned in the N copies of memory, determine the correct value through arbitration, and return it; and correct the faulty memory block, for example, write the correct value into the faulty memory block.

[0218] The specific embodiment listed above and other embodiments that can be derived therefrom, based on the ptmalloc memory management structure, add a TMR header, use FatPointer to implement TMR memory tracking, and implement business-insensitive TMR heap memory reading and writing through multi-module redundant computing plug-ins, and support the mixed use of multiple-granularity conventional heap memory and TMR heap memory.

[0219] Another embodiment is listed below. Fig.12 As shown, in this other embodiment, a fixed offset is used to implement TMR memory tracking, and multi-module redundant read and write function plug-ins are used to implement business-insensitive TMR heap memory reading and writing. By replacing fatpointer with a fixed offset, the pointer size is avoided from being doubled, and the compiler work is relatively simple. Specifically, the following process may be included:

[0220] S21, identifying the introduction in the compilation object.

[0221] For identification of introductions, see Fig.11 The corresponding embodiments will not be described in detail here.

[0222] S22, perform compilation stubs on the compilation object to obtain the target code.

[0223] Exemplarily, for each operation of the multi-module redundant memory application, release, read, and write functions based on the introduction, the specific implementation steps are as follows.

[0224] In the source code, when calling the POSIX-compatible memory request API, the corresponding memory variable definition, for example, adds a multi-mode redundant directive __xmr before char*p, indicating that multi-mode redundant memory needs to be requested with *p.

[0225] Before the compiler compiles the code into an executable binary program, the following process is added to the memory allocation interface with the multi-module redundant directive, such as __xmr char*p=malloc(size).

[0226] Preprocessing: reserve memory space for the TMR management structure and apply for the TMR management structure. Fig.12 As shown, the TMR management structure applied for in this embodiment includes three memory spaces with relatively fixed offsets and the same structure, which are respectively mapped to the underlying memory pool.

[0227] Application: Apply for 3 independent memory blocks from 3 independent memory pools at the bottom layer.

[0228] Allocation: Allocate 3 independent memory blocks.

[0229] Since the offsets between the main memory block mchunk1, the backup memory block mchunk2, and the backup memory block mchunk3 are known fixed offset values, it is only necessary to record the address of the main memory block mchunk1, and then add the known fixed offset value to the address to obtain the remaining two independent memory block addresses in turn, and perform read / write operations on them, compare the data consistency of the three copies of memory, arbitrate to obtain the correct data, and correct the erroneous data.

[0230] For the memory release interface, such as free(p), it is replaced by calling the fourth API to first release the three pieces of memory and then release the management structure.

[0231] For the memory read interface, for example, for a=*p, because *p specifies the multi-mode redundant directive when applying for memory, the compiler will convert the pointer read access form (such as *p) into the following process before compiling the code into an executable binary program:

[0232] Since the offsets between the main memory block mchunk1, the backup memory block mchunk2, and the backup memory block mchunk3 are known fixed offset values, the address (p1) of the main memory block mchunk1 is obtained, and the address of the main memory block mchunk1 plus the known fixed offset value can be used to obtain the remaining two independent memory block addresses (p2, p3) in sequence.

[0233] Read the data of p1, p2, and p3 memory in sequence, compare the data consistency of the three memories, arbitrate to get the correct data, and correct the wrong data. Return the value of the correct memory among the multiple memories.

[0234] The compilation method of the memory write interface (example *p=10) is similar to that of the memory read interface, which will not be repeated here.

[0235] According to the description of another embodiment above, other embodiments can be summarized. In these embodiments, by compiling and stubbing, the target code obtained includes calling the first API; the first API applies for N copies of memory corresponding to the target variable; wherein the base address of the tth memory block is fixedly offset relative to the base address of the t-1th memory block; 2≤t≤N. That is, in the N copies of memory applied for, the offset between the base addresses of two adjacent memory blocks is a fixed value. In other embodiments, the first API may first apply for a second multi-module redundant memory management structure; the second multi-module redundant management structure includes a second address space; and N copies of memory may be applied for in the second address space.

[0236] In the same embodiment or other embodiments, N copies of memory include 1 main memory and N-1 backup memory blocks. The target code includes calling a second API; when the executable code corresponding to the second API is running, based on the first pointer and the offset of the fixed offset, the second pointer to the Nth pointer are determined respectively. The first pointer points to the memory address in the main memory block where the value of the target variable is stored. The memory address pointed to by the first pointer can be an offset address or an absolute address. The value of the target variable in each memory block can be read through the first pointer and the second pointer to the Nth pointer.

[0237] Fig.12 The corresponding embodiment and other embodiments derived therefrom replace wide pointers with fixed offsets to avoid doubling of pointer size, and the compiler work is relatively simple. However, since it is impossible to distinguish between TMR memory variables (target variables) and traditional memory variables (ordinary memory variables) at the binary code stage, all read and write operations require stubbing.

[0238] Another embodiment is listed below. Fig.13 As shown, in another embodiment, fixed partitioning + virtual address separation + compiler plugging is used to achieve business-insensitive TMR memory management. This embodiment still replaces fatpointer with a fixed offset to avoid doubling the pointer size, and the compiler work is relatively simple. By separating the virtual address, the TMR memory area and the traditional memory area are distinguished, and it can be achieved that only the TMR memory read and write operations require plugging.

[0239] like Fig.13 As shown, when applying for a management structure, you can apply for a TMR virtual memory partition (ie, a TMR virtual memory partition) and a traditional virtual memory partition, that is, apply for two independent memory spaces to achieve storage separation of target variables and ordinary memory variables.

[0240] The specific process may include the following:

[0241] S31, identifying the introduction in the compilation object.

[0242] For identification of introductions, see Fig.11 The corresponding embodiments will not be described in detail here.

[0243] S32, perform compilation stubs on the compilation object to obtain the target code.

[0244] Exemplarily, for each operation of the multi-module redundant memory application, release, read, and write functions based on the introduction, the specific implementation steps are as follows.

[0245] Before the compiler compiles the code into an executable binary program, the following process is added to the memory allocation interface with the multi-module redundant directive, such as __xmr char*p=malloc(size).

[0246] Preprocessing: Apply for TMR virtual memory partition (first virtual memory area) and traditional virtual memory partition (second virtual memory area). In the TMR virtual memory partition, it can be divided into multiple sub-areas, such as primary 1 partition, backup 2 partition and backup 3 partition. In each sub-area, the corresponding management structure can be applied. For example, the management structure corresponding to the primary 1 partition includes header (pre_s, size, fd, dk), value (uTmr1sum) and memory block (primary mchunk1). Virtual memory partition is equivalent to specifying the memory address space range occupied by the target variable during the compilation process. When applying for a memory block, it is only applied within the memory space range. Ordinary memory variables can only be applied within another address space range, and the virtual addresses and physical addresses of the two address spaces do not overlap.

[0247] Application: Apply for three independent memory blocks from the three independent memory pools at the bottom of the TMR virtual memory partition mapping.

[0248] Allocation: Allocate 3 independent memory blocks.

[0249] Since the offsets between the main memory block mchunk1, the backup memory block mchunk2, and the backup memory block mchunk3 are known fixed offset values, it is only necessary to record the address of the main memory block mchunk1, and then add the known fixed offset value to the address to obtain the remaining two independent memory block addresses in turn, and perform read / write operations on them, compare the data consistency of the three copies of memory, arbitrate to obtain the correct data, and correct the erroneous data.

[0250] With the above Fig.12 The difference between the corresponding embodiments is that this embodiment performs virtual memory partitioning to separate the TMR virtual memory from the ordinary virtual memory. The compilation of the read, write and release interfaces can refer to the aforementioned embodiments and will not be repeated here.

[0251] According to the description of the above another embodiment, other embodiments can be summarized. In these embodiments, by compiling and inserting, the target code includes calling the first API. The first API applies for the first virtual memory area and the second virtual memory area; the first virtual memory area is used to store the value of the target variable; the second virtual memory area is used to store the value of the memory variable other than the target variable; in the address space occupied by the first virtual memory area, N copies of memory are applied, and among the N copies of memory, the base address of the tth copy of memory is fixedly offset relative to the base address of the t-1th copy of memory; 2≤t≤N. In one embodiment, the first API can first apply for a third multi-module redundant management structure, and the third multi-module redundant management structure includes the first virtual memory area and the second virtual memory area.

[0252] In another embodiment, a fixed offset is used to implement TMR memory tracking, and the traditional memory area and the TMR memory area are distinguished by virtual address separation, so that only TMR memory read and write operations are plugged in; multi-module redundant read and write function plugging is used to implement business-insensitive TMR heap memory reading and writing. On the one hand, by replacing fatpointer with a fixed offset, the pointer size is avoided from being doubled, and the compiler work is relatively simple; on the other hand, by virtual address separation, the TMR memory area and the traditional memory area are distinguished, and only TMR memory read and write operations need to be plugged in.

[0253] Another embodiment is listed below. Fig.14 As shown, this embodiment can improve performance based on any one of the above embodiments or a combination of multiple embodiments, and change the read operation and / or write operation with the target variable modified by the introduction as the object to OS inspection, which can greatly improve the system performance for scenarios with a large number of reads / writes.

[0254] The following description may be expanded on the basis of the above embodiments. For each operation of the multi-module redundant memory application, release, read, and write functions based on the introduction, the specific implementation steps are as follows.

[0255] S41, identifying the introduction in the compilation object.

[0256] The identification of the introduction may be carried out in the manner described in any of the above embodiments, which will not be described in detail here.

[0257] S42, compile and insert stubs on the compiled object to obtain the target code.

[0258] For the compilation of the memory application interface, the method described in any of the above embodiments may be adopted. For example, in the source code, when it is necessary to call the POSIX-compatible memory application API to apply for multi-mode redundant memory, a multi-mode redundant preamble (such as __xmr) may be added before the variable definition for receiving the memory. An example of the memory application interface after adding the preamble is: __xmr char*p=malloc(size). Then, before the compiler compiles the code into an executable binary program, for the memory application interface with the multi-mode redundant preamble added, the following process is added: reserve memory space for the TMR management structure and apply for the TMR management structure; apply for 3 independent memory blocks from the underlying memory pool; allocate 3 independent memory blocks.

[0259] In this embodiment, the following process may be used for compiling the read interface:

[0260] Because *p specifies the multi-mode redundant directive when applying for memory, the compiler will convert the pointer read access form (such as *p) into the following process before compiling the code into an executable binary program:

[0261] The TMR read inspection thread is started during the OS startup phase.

[0262] The TMR read inspection thread triggers the TMR memory inspection when the given conditions are met. The given conditions can be periodic triggering or triggering based on a preset frequency, such as triggering an inspection once every hour, or triggering an inspection once every 10 minutes, etc. In other embodiments, a switch can be set for the triggering of the inspection, and controlled through user interaction.

[0263] The TMR read inspection thread reads each multi-module redundant memory in turn, compares the data consistency of each memory, arbitrates to obtain the correct data, and corrects the erroneous data.

[0264] Returns the correct value of the memory in multiple copies.

[0265] For the compilation of the write interface, you can refer to the compilation and instrumentation process of the read interface above. For example, you can use the following process:

[0266] The TMR write inspection thread is started during the OS startup phase.

[0267] The TMR write inspection thread triggers TMR memory inspection when the given conditions are met.

[0268] The TMR write inspection thread writes the value of the target variable to each multi-module redundant memory in turn, compares the data consistency of each memory, arbitrates to obtain the correct data, and corrects the erroneous data.

[0269] In this embodiment, the compilation and instrumentation of the memory release interface can refer to any of the above embodiments, which will not be described again here.

[0270] According to the description of the above embodiment, other embodiments can be summarized. In these embodiments, compilation plugging is performed on the compilation object, including modifying the read interface and / or write interface of the compilation object with the target variable as the object to the code for performing the following operations: pulling up the inspection thread; triggering the inspection thread, wherein the inspection thread is used to: write the value of the target variable into N copies of memory respectively; or, read the value in N copies of memory corresponding to the target variable; compare the values ​​in N copies of memory, obtain the correct value based on the arbitration strategy, and return it as the value of the target variable. The arbitration strategy can be to take the value with the highest proportion as the correct value, for example, among 5 memory blocks, 4 memory blocks have the same value, all 11100101; the value of another memory block is 11100100, and 11100101 accounts for 80%, then 11100101 is arbitrated as the correct value. And write 11100101 into another memory block for correction.

[0271] In summary, the memory management method provided in the embodiment of the present application proposes to add a multi-mode redundant preamble (such as __tmr) to the memory block to be applied for, indicating that the memory block is a multi-mode memory block. The memory manager will apply for multiple copies of memory according to the preamble and manage them uniformly. In addition, the memory block read operation and / or write operation of the multi-mode redundant preamble is also proposed, and all or part of the compilation plug-in is performed according to the constraints of performance, reliability and specific scenarios. The plug-in function compares the consistency of the multi-mode memory block and gives the arbitration result.

[0272] In this way, based on this method, shotgun reinforcement and modification of software codes of large-scale systems can be avoided, reliability reinforcement errors are invisible to the business, and the code quality, maintenance cost, and coordinated rapid iterative evolution of business codes in reliable and unreliable scenarios of large-scale software are guaranteed.

[0273] In addition, after testing, the memory management method provided in the embodiment of the present application has achieved positive technical effects in terms of reliability, robustness, and real-time performance, as follows:

[0274] Reliability: The system can be used normally under heavy load, high concurrency, and long-term operation.

[0275] Robustness: In abnormal situations such as single-particle upset, it can achieve fault tolerance and ensure the normal operation of the system.

[0276] Real-time: Supports flexible and efficient memory allocation algorithms and strategies to speed up memory allocation and reading and writing.

[0277] The embodiment of the present application also provides a computer program product, which includes a program; the program includes a preamble, which is used to modify a target variable, and the target variable is a memory variable that needs to apply for multi-module redundant memory. The target code corresponding to the program is at least used to apply for N copies of memory corresponding to the target variable; wherein the target code includes the code obtained by compiling and plugging the program; N≥2, and is an integer.

[0278] It should be noted that in some embodiments, the process of compiling different languages ​​is different, and the target code can be an intermediate code or an executable code (binary code). For example, after the source code based on the Java language is compiled and plugged, the target code can be a code in the .class format or a code in the .dex format; after the source code based on the C / C++ language is compiled and plugged, the target code can be a code in the .i format or the .s format or the .exe format or the .out format. In the target code, there will be at least a code line corresponding to the memory application interface, where the memory application interface is a memory application interface with a memory variable modified by a guide as the object.

[0279] The present application also provides a computer program product, which includes a program, and when the program is executed by an electronic device, the electronic device implements the method described in any of the above embodiments. For example, the program product may be an application, or an upgrade package or functional plug-in for upgrading the application.

[0280] An embodiment of the present application also provides an electronic device, which includes: one or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, enable the electronic device to execute a method as described in any of the above embodiments.

[0281] Specifically, the electronic device may be a server or server cluster that provides operator sequence optimization services. Fig.15 ,The hardware structure of an electronic device may include: a processor, a memory and a chipset.

[0282] Processor, the core that handles all computing tasks and requests, including at least the CPU.

[0283] Storage: includes memory and hard disk. The larger the capacity, the more requests and files can be processed simultaneously.

[0284] Chipset: includes northbridge chip and southbridge chip, which connect various I / O devices. Northbridge chip connects CPU, memory and PCI bus, while southbridge chip connects hard disk, network and other I / O devices.

[0285] I / O bus: connects various I / O devices, such as network cards, USB, etc. The larger the I / O bus bandwidth of the server, the more requests it can handle. I / O devices: including network cards, USB, etc. The network card is the main device that connects the server to the external network. Its speed and performance directly affect the response speed and transmission speed of the server.

[0286] Power supply: Provides stable power to the server to ensure normal operation of the server.

[0287] Chassis: The outer shell of the server hardware that protects the hardware from dust, vibration, and temperature.

[0288] Exemplarily, the processor may include one or more processing units, for example, the processor includes a neural-network processing unit (NPU), and may also include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a digital signal processor (DSP), a baseband processor, etc. Among them, different processing units may be independent devices or integrated into one or more processors. The controller may generate an operation control signal according to the instruction opcode and the timing signal to complete the control of fetching and executing instructions.

[0289] The memory can be used to store computer executable program codes, which include instructions. The internal memory may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, at least one application required for a function, etc. The data storage area may store data (such as input data, output data) created during the use of the electronic device, etc. In addition, the internal memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory and / or instructions stored in a memory provided in the processor.

[0290] Alternatively, the electronic device may also be a terminal device with certain computing capabilities, such as a mobile phone, a personal computer (PC) (such as a laptop), a tablet computer (Tablet Personal Computer, Tablet PC), a wearable electronic device, etc. The terminal device may include a processor, an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, etc.

[0291] It is to be understood that the structure illustrated in the embodiment of the present invention is only an example and does not constitute a limitation on the electronic device. The electronic device in the embodiment of the present application may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0292] An embodiment of the present application further provides a storage medium, including computer instructions, which, when executed on an electronic device, enables the electronic device to execute a method as described in any of the above embodiments.

[0293] An embodiment of the present application also provides a chip system, including a communication interface for inputting and / or outputting data; and a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any of the above embodiments.

[0294] It should be noted that the solution provided in the embodiments of the present application includes any one or more of the memory management method, device, electronic device and storage medium, or may also be other forms of software products, hardware products or virtual service products obtained based on the technical concept of the method described in the specification of this application.

[0295] In the description of the device in the embodiment of the present application, various modules for implementing the method flow functions are constructed in the device. The division of modules is merely a division of logical functions. When implementing the embodiment of the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0296] Specifically, each functional module can be fully or partially integrated into one physical entity during actual implementation, or can be physically separated. And these modules can all be implemented in the form of software calling through processing elements; or all can be implemented in the form of hardware; or some modules can be implemented in the form of software calling through processing elements, and some modules can be implemented in the form of hardware. For example, the detection module can be a separately established processing element, or it can be integrated in a chip of an electronic device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. In the implementation process, each step of the above method or each module above can be completed by an integrated logic circuit of hardware in a processor element or instructions in the form of software.

[0297] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital signal processors (DSP), or one or more field programmable gate arrays (FPGA), etc. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0298] Specifically, in one embodiment of the present application, the above-mentioned one or more computer programs are stored in the above-mentioned memory, and the above-mentioned one or more computer programs include instructions. When the above-mentioned instructions are executed by the above-mentioned device, the above-mentioned device executes the method steps described in the embodiment of the present application.

[0299] Specifically, in one embodiment of the present application, the processor of the electronic device may be a SOC device on a chip, which may include a central processing unit (CPU) and may further include other types of processors, such as a graphics processing unit (GPU). Specifically, in one embodiment of the present application, the processor of the electronic device may be a PWM control chip.

[0300] Specifically, in an embodiment of the present application, the processor involved may include, for example, a CPU, a DSP, a microcontroller or a digital signal processor, and may also include a GPU, an embedded neural network processor (Neural-network Process Units, NPU) and an image signal processor (Image Signal Processing, ISP). The processor may also include necessary hardware accelerators or logic processing hardware circuits, such as ASICs, or one or more integrated circuits for controlling the execution of the program of the technical solution of the present application. In addition, the processor may have the function of operating one or more software programs, and the software programs may be stored in a storage medium.

[0301] Specifically, in one embodiment of the present application, the memory of the electronic device may be a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage devices, or may be any computer-readable medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer.

[0302] Specifically, in an embodiment of the present application, the processor and the memory can be combined into a processing device, more commonly, they are independent components, and the processor is used to execute the program code stored in the memory to implement the method described in the embodiment of the present application. In specific implementation, the memory can also be integrated into the processor, or independent of the processor.

[0303] Furthermore, the devices, apparatuses, and modules described in the embodiments of the present application may be implemented by computer chips or entities, or by products having certain functions.

[0304] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0305] In the several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0306] The embodiments described in this application are described with reference to the flowcharts and / or block diagrams of the methods, devices (apparatus), and computer program products according to the embodiments of the application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0307] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0308] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0309] It should also be noted that in the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0310] In the embodiments of the present application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, method, commodity or device including the element.

[0311] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0312] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0313] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments of the present application can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0314] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0315] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory management method, characterized in that: The method comprises: Recognize that there is a preamble in the compilation object; the preamble is used to modify a target variable, and the target variable is a memory variable for which a multi-mode redundant memory needs to be applied; Compile and insert the compiled object to obtain the target code; when the executable code corresponding to the target code is run, it is used to apply for at least N memory corresponding to the target variable, where N is greater than or equal to 2 and is an integer.

2. The method according to claim 1, characterized in that Performing compilation instrumentation on the compilation object includes: The memory application interface with the target variable as the object in the compiled object is modified to call the first API; the first API is a multi-mode redundant memory application function; the multi-mode redundant memory application function is used to apply for at least N copies of memory corresponding to the target variable.

3. The method according to claim 1 or 2, characterized in that Performing compilation instrumentation on the compilation object includes: The read interface with the target variable as the object in the compiled object is modified to call the second API; the second API is a multi-mode redundant memory read function; the multi-mode redundant memory read function is at least used to read the values ​​stored in the N copies of memory respectively.

4. The method according to any one of claims 1 to 3, characterized in that Performing compilation instrumentation on the compilation object includes: The write interface in the compiled object with the target variable as the object is modified to call a third API; the third API is a multi-module redundant memory write function; the multi-module redundant memory write function is at least used to write the value of the target variable into the N copies of memory respectively.

5. The method according to any one of claims 1 to 4, characterized in that Performing compilation instrumentation on the compilation object includes: The memory release interface with the target variable as the object in the compiled object is modified to call the fourth API; the fourth API is a multi-module redundant memory release function; the multi-module redundant memory release function is used to release at least the N copies of memory.

6. The method according to claim 5, characterized in that The executable code corresponding to the target code is also used to apply for a multi-module redundant memory management structure when running; the multi-module redundant memory management structure is used to manage the N copies of memory; The multi-module redundant memory release function is used to release the N copies of memory and the multi-module redundant memory management structure.

7. The method according to any one of claims 1 to 6, characterized in that Identify the presence of preambles in the compiled object, including: It is identified that in the compiled object, the preamble exists in the code line corresponding to the target variable.

8. The method according to any one of claims 1 to 7, characterized in that The N memory blocks include 1 main memory block and N-1 backup memory blocks; The target code includes calling a first API; the first API is used to perform the following operations: Applying for a multi-module redundant memory management structure; the multi-module redundant management structure includes an object header; the header is used to store at least the base addresses of the N-1 spare memory blocks; Apply for N memory copies corresponding to the target variable, and return the base addresses corresponding to the N memory copies respectively; Define a pointer used to access the target variable as a wide pointer; Return a wide pointer; the high bit of the wide pointer is used to store the first base address, and the low bit is used to store the first pointer; wherein the first base address is the base address of the main memory block; the first pointer points to the memory address in the main memory block used to store the value of the target variable.

9. The method according to claim 8, characterized in that The target code includes calling a second API; the second API is used to perform the following operations: Based on the first base address and the first pointer, determine the second base address and the second pointer to the Nth pointer corresponding to the N-1 backup memory blocks; wherein the second base address is the base address of the header; the second pointer to the Nth pointer respectively point to the memory addresses in the N-1 backup memory blocks for storing the value of the target variable; Read the values ​​in the memory addresses pointed to by the first pointer, the second pointer to the Nth pointer respectively.

10. The method according to any one of claims 1 to 7, characterized in that The target code includes calling a first API; the first API is used to perform the following operations: Apply for N copies of memory corresponding to the target variable; wherein the base address of the t-th copy of memory is fixedly offset relative to the base address of the t-1-th copy of memory; 2≤t≤N.

11. The method according to any one of claims 1 to 10, characterized in that Performing compilation instrumentation on the compilation object includes: The read interface and / or write interface of the compiled object with the target variable as the object is modified into a code for performing the following operations: Pull up the inspection thread; Trigger the inspection thread, which is used to: Writing the values ​​of the target variables into the N copies of memory respectively; or reading the values ​​of the N copies of memory corresponding to the target variables; Compare the values ​​in the N memories, obtain the correct value based on the arbitration strategy, and return it as the value of the target variable.

12. The method according to any one of claims 1 to 11, characterized in that When the target variable is a static variable or a global variable, performing compilation stubs on the compiled object to obtain the target code includes: The definition of the target variable in the compiled object is linked to the multi-mode data segment of the binary program to obtain executable code; the executable code is used to apply for N copies of memory corresponding to the target variable when it is loaded or loaded by the operating system.

13. A memory management device, characterized in that: The device comprises: A preamble recognition module is used to recognize that a preamble exists in a compilation object; the preamble is used to modify a target variable, and the target variable is a memory variable that needs to apply for a multi-module redundant memory; The compiling and plugging module is used to compile and plug the compiled object to obtain the target code; when the executable code corresponding to the target code is run, it is used to apply for N memory corresponding to the target variable at least, where N≥2 and is an integer.

14. The device according to claim 13, characterized in that The compilation stub module is specifically used to modify the memory application interface in the compilation object with the target variable as the object to call the first API; the first API is a multi-mode redundant memory application function; the multi-mode redundant memory application function is at least used to apply for N copies of memory corresponding to the target variable.

15. The device according to claim 13 or 14, characterized in that The compilation stub module is specifically used to modify the read interface of the compiled object with the target variable as the object to call the second API; the second API is a multi-module redundant memory read function; The multi-module redundant memory read function is at least used to read the values ​​respectively stored in the N copies of memory.

16. The device according to any one of claims 13 to 15, characterized in that The compilation stub module is specifically used to modify the write interface in the compilation object with the target variable as the object to call a third API; the third API is a multi-module redundant memory write function; the multi-module redundant memory write function is at least used to write the value of the target variable into the N copies of memory respectively.

17. The device according to any one of claims 13 to 16, characterized in that The compilation stub module is specifically used to modify the memory release interface in the compilation object with the target variable as the object to call the fourth API; the fourth API is a multi-module redundant memory release function; the multi-module redundant memory release function is at least used to release the N copies of memory.

18. The device according to any one of claims 13 to 17, characterized in that The N memory blocks include 1 main memory block and N-1 backup memory blocks; The target code includes calling a first API; the first API is used to perform the following operations: Applying for a multi-module redundant memory management structure; the multi-module redundant management structure includes an object header; the header is used to store at least the base addresses of the N-1 spare memory blocks; Apply for N memory copies corresponding to the target variable, and return the base addresses corresponding to the N memory copies respectively; Define a pointer used to access the target variable as a wide pointer; Return a wide pointer; the high bit of the wide pointer is used to store the first base address, and the low bit is used to store the first pointer; wherein the first base address is the base address of the main memory block; the first pointer points to the memory address in the main memory block used to store the value of the target variable.

19. The device according to claim 18, characterized in that The target code includes calling a second API; the second API is used to perform the following operations: Based on the first base address and the first pointer, determine the second base address and the second pointer to the Nth pointer corresponding to the N-1 backup memory blocks; wherein the second base address is the base address of the header; the second pointer to the Nth pointer respectively point to the memory addresses in the N-1 backup memory blocks for storing the value of the target variable; Read the values ​​in the memory addresses pointed to by the first pointer, the second pointer to the Nth pointer respectively.

20. The device according to any one of claims 13 to 17, characterized in that The target code includes calling a first API; the first API is used to perform the following operations: Apply for N copies of memory corresponding to the target variable; wherein the base address of the t-th copy of memory is fixedly offset relative to the base address of the t-1-th copy of memory; 2≤t≤N.

21. The device according to any one of claims 13 to 20, characterized in that Performing compilation instrumentation on the compilation object includes: The read interface and / or write interface of the compiled object with the target variable as the object is modified into a code for performing the following operations: Pull up the inspection thread; Trigger the inspection thread, which is used to: Writing the values ​​of the target variables into the N copies of memory respectively; or reading the values ​​of the N copies of memory corresponding to the target variables; Compare the values ​​in the N memories, obtain the correct value based on the arbitration strategy, and return it as the value of the target variable.

22. The device according to any one of claims 13 to 21, characterized in that When the target variable is a static variable or a global variable, performing compilation stubs on the compiled object to obtain the target code includes: The definition of the target variable in the compiled object is linked to the multi-mode data segment of the binary program to obtain executable code; the executable code is used to apply for N copies of memory corresponding to the target variable when it is loaded or loaded by the operating system.

23. An electronic device, characterized in that: The electronic device comprises: One or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the electronic device, cause the electronic device to perform a method as described in any one of claims 1 to 12.

24. A storage medium, characterized in that The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method as claimed in any one of claims 1 to 12.

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