Field programmable gate array (FPGA) calling method, device and equipment based on window sliding method and storage medium
By adopting multi-threaded and multi-service core parallel operation in the CPU and FPGA architecture, and dynamically adjusting the data transmission sequence and window size in combination with the window sliding method, the problem of not being able to fully utilize the high-speed processing characteristics of the CPU and FPGA architecture in the existing technology is solved, and the service processing capabilities with high concurrency and low latency are achieved.
Patent Information
- Application Number
- CN202411699487.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-03-14
AI Technical Summary
When the existing CPU and FPGA architectures are concurrently computed, they cannot fully utilize the high-speed processing characteristics, especially when the processing delay difference between different services is large, the interval between CPU sending data cannot be effectively adjusted.
The FPGA calling method based on the window sliding method is adopted, and the order of the data sent to the FPGA service is dynamically adjusted through the CPU multi-threading mechanism and the FPGA multi-service core parallel operation, and the size of the sliding window and sub-window is dynamically adjusted according to the processing status of different services in the FPGA.
It improves the processing capability of the equipment in high concurrency and multi-service processing, ensures the use needs of high reliability, high concurrency and low latency, and fully utilizes the high-speed parallel computing characteristics of FPGAs.
Smart Images
Figure CN119621320A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and more specifically, to an FPGA calling method, device, equipment and storage medium based on a window sliding method. Background Art
[0002] For devices with multiple different business functions and concurrent requirements, they usually need to be directly or indirectly connected to multiple devices with different functions through the communication bearer network in the system, and need to communicate with multiple other devices at the same time during the business process. According to the characteristics of the system, the device itself needs to have multiple different business functions at the same time, that is, technically, the CPU and FPGA need to coordinate and schedule each other to achieve the high-speed parallel processing capability of the device.
[0003] At present, for devices with CPU and FPGA architectures, the following methods are generally used when performing concurrent business operations: using a blocking method, after the CPU sends a packet of data to the FPGA, it waits for the FPGA to respond, and only sends the next packet of data after the CPU receives the FPGA response. Although this method can effectively ensure that each packet of data can be stably and reliably operated, it cannot give full play to the high-speed processing characteristics of the architecture. Using a non-blocking method, according to the FPGA business processing performance, the FPGA processing delay of different services is calculated separately, and the maximum processing delay of the FPGA is used as the threshold value to control the interval of CPU sending data to be greater than the threshold value. This method can improve the data processing capability, but when the processing delays between different services differ greatly, the CPU must send data according to the maximum delay interval, which cannot give full play to the FPGA's high-speed computing capability. Summary of the invention
[0004] In view of at least one defect or improvement need in the prior art, the present invention provides an FPGA calling method, apparatus, device and storage medium based on a window sliding method, which can solve at least one of the problems existing in the above-mentioned background technology.
[0005] To achieve the above object, according to a first aspect of the present invention, a FPGA calling method based on a window sliding method is provided, the method comprising:
[0006] The CPU monitors the TCP / UDP data of the port and creates multiple new threads based on the intercommunication objects. Each thread independently records the interaction information with different devices.
[0007] When multiple threads receive service data at the same time, the CPU dynamically adjusts the order of sending service data to the FPGA based on the current operation status of the FPGA and the performance of processing different services;
[0008] According to the computing power of FPGA, the window sliding method is used to continuously send the business data to be processed to FPGA. According to the operation status of different businesses currently running in FPGA, the size of each business sub-window is dynamically adjusted according to the processing status of each different business under the window.
[0009] Furthermore, the above-mentioned FPGA calling method based on the window sliding method also includes:
[0010] Furthermore, in the above FPGA calling method based on the window sliding method, if a thread does not receive data from the opposite device within the first time interval, the thread is closed to release CPU resources.
[0011] Furthermore, the above-mentioned FPGA calling method based on the window sliding method, wherein the window sliding method is used, specifically includes:
[0012] The window sliding method is used for data call. The CPU sends data to the FPGA according to the window size, and the window is continuously sliding as the FPGA responds to the data.
[0013] Furthermore, the above FPGA calling method based on the window sliding method further includes:
[0014] When the CPU sends data to the FPGA, the window size is set to N. When the device is in multi-service concurrent processing, the CPU controls the number of services being processed inside the FPGA. When the CPU receives the response data from the FPGA, it sends the next packet of service data to be processed in the service processing queue to the FPGA.
[0015] Furthermore, the above FPGA calling method based on the window sliding method further includes:
[0016] When communicating with multiple external devices with different business functions, the CPU will allocate a corresponding sub-window to each independent business, and use the window sliding method to call the FPGA function on the sub-window. For each different business, the number of business cores deployed in the FPGA is different. When one of the business processing is completed, the CPU will adjust the sub-windows of other businesses.
[0017] Furthermore, in the above FPGA calling method based on the window sliding method, the CPU adjusts the sub-windows of other services, specifically including:
[0018] The CPU and FPGA dynamically adjust the size of the window between them based on the performance and latency of all services currently being processed;
[0019] The window size of the sub-window is dynamically adjusted based on the performance and latency of processing different services.
[0020] According to a second aspect of the present invention, there is also provided an FPGA calling device based on a window sliding method, comprising:
[0021] The thread creation module is used by the CPU to monitor the TCP / UDP data of the port and create multiple new threads according to the intercommunication objects. Each thread independently records the interaction information with different devices.
[0022] The first adjustment module is used for dynamically adjusting the order of sending the service data to the FPGA according to the current operation status of the FPGA and the performance of processing different services when multiple threads receive service data at the same time;
[0023] The second adjustment module is used to continuously send the business data to be processed to the FPGA using the window sliding method according to the computing power of the FPGA, and dynamically adjust the size of each business sub-window according to the processing status of each different business under the window according to the operation status of different businesses currently being carried out in the FPGA.
[0024] According to the third aspect of the present invention, there is also provided an FPGA calling device based on the window sliding method, which comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of any one of the above-mentioned methods.
[0025] According to a fourth aspect of the present invention, a storage medium is also provided, which stores a computer program that can be executed by an FPGA calling device based on the window sliding method. When the computer program runs on the FPGA calling device based on the window sliding method, the FPGA calling device based on the window sliding method executes the steps of any one of the above-mentioned methods.
[0026] According to a fifth aspect of the present invention, there is also provided a computer program product, comprising a computer program, characterized in that when the computer program is executed by a processor, the steps of the FPGA calling method based on the window sliding method as described in any one of the above items are implemented.
[0027] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:
[0028] (1) The FPGA calling method based on the window sliding method provided by the present invention is based on the CPU+FPGA architecture. By using a variety of technical means such as the CPU multi-threading mechanism, the service queue management mechanism, the FPGA multi-service core parallel operation mechanism, and the FPGA scheduling mechanism based on the multiple window sliding method, the high concurrency processing capability of the device when simultaneously processing a large number of different services is improved, ensuring that the device meets the use requirements of high reliability, high concurrency, and low latency.
[0029] (2) The FPGA calling method based on the window sliding method provided by the present invention is adopted. Based on the CPU+FPGA architecture, the intercommunication status of each different device is independently maintained on the CPU side through multi-threading technology, and the service data sent by the opposite device can be received in time, and stored in the CPU cache in time, waiting for subsequent service processing; the service processing queue of the CPU to send data to the FPGA is optimized, and the order of sending different service data is automatically adjusted according to the optimal processing capacity of the device according to the different service processing conditions inside the FPGA; according to the different service processing conditions inside the FPGA, the size of the sliding window and the subordinate sub-window is automatically adjusted on the CPU side according to the service quantity and the processing performance of a single service core, so as to give full play to the high parallel computing characteristics of the FPGA and enhance the efficiency of the CPU scheduling the FPGA; according to the concurrency requirements of the device in the system and the processing capacity of a single service core in the FPGA, multiple service cores are deployed in the FPGA for each service function, so as to improve the parallel processing capacity of the device, and realize the reliable processing of multiple services and high concurrency of the device in the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0031] Figure 1 A flowchart of an FPGA calling method based on a window sliding method provided in an embodiment of the present application;
[0032] Figure 2 A schematic diagram of system deployment provided for an embodiment of the present application;
[0033] Figure 3 A schematic diagram of multithreading and data transmission control provided in an embodiment of the present application;
[0034] Figure 4 A schematic diagram of the hardware logic structure design of the CPU+FPGA provided in the embodiment of the present application;
[0035] Figure 5 A schematic diagram of a current service window and multiple service sub-windows provided in an embodiment of the present application;
[0036] Figure 6 A schematic diagram of the adjusted current service window and multiple service sub-windows provided in an embodiment of the present application. DETAILED DESCRIPTION
[0037] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0038] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.
[0039] Figure 1 A flowchart of an FPGA calling method based on a window sliding method provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, an FPGA calling method based on a window sliding method provided in an embodiment of the present application includes:
[0040] 101. The CPU monitors the TCP / UDP data of the port and creates multiple new threads according to the intercommunication objects. Each thread independently records the interaction information with different devices.
[0041] Specifically, in one embodiment, the FPGA calling method based on the window sliding method provided in the embodiment of the present application can be run on a device to realize the functions of multi-service and high-concurrency service processing. The device can be directly connected to other devices through a switch, such as Figure 2 As shown, when multiple other devices are connected, the concurrent use requirements of the devices can be met through software and hardware design, and interconnection with different business functions of different devices can be achieved at the same time.
[0042] When the device communicates with other external devices through IP networks, the CPU will always monitor the TCP / UDP data and data transmission and reception of the corresponding port. When receiving a data packet composed of the specified protocol, the CPU will create a new thread according to the intercommunication object, such as Figure 3 As shown, the multi-threading mechanism is adopted so that each thread independently records the interaction information with different devices.
[0043] 102. When multiple threads receive business data at the same time, the CPU dynamically adjusts the order of sending the business data to the FPGA according to the current operation status of the FPGA and the performance of processing different businesses.
[0044] Specifically, the CPU side adopts a control mechanism for the business data that needs to be processed. When multiple threads receive business data at the same time, the CPU will judge the FPGA's current ability to process business function 1, business function 2, etc. according to the FPGA's current operating status and the performance of processing different businesses, and dynamically adjust the order of sending business data to the FPGA to give full play to the device's computing power.
[0045] 103. According to the computing power of FPGA, the window sliding method is used to continuously send the business data to be processed to FPGA. According to the operation status of different businesses currently being carried out in FPGA, the size of each business sub-window is dynamically adjusted according to the processing status of each different business under the window.
[0046] Specifically, when the CPU side calls the FPGA to process multiple services, it uses a non-blocking method. According to the computing power of the FPGA, the window sliding method is used to continuously send a large amount of service data to be processed to the FPGA, and the high-speed computing characteristics of the FPGA are used to improve the multi-service parallel processing capabilities of the device. The sliding window method is a commonly used double-pointer algorithm that is widely used in substring or subarray problems in data structures such as strings and arrays, such as string matching, longest substring, minimum covering substring, etc., where the window refers to the area formed between two pointers. The sliding window algorithm can optimize the time complexity of brute force enumeration, making the algorithm more efficient.
[0047] like Figure 4 As shown in the figure, after receiving and parsing the data sent by the CPU to the FPGA, it will be processed in parallel by multiple business cores, and the processed data will be encapsulated and sent back to the CPU. At the same time, according to the current operation of different services of the FPGA, the size of each business window is dynamically adjusted according to the processing status of each different business under the large window.
[0048] The FPGA calling method based on the window sliding method provided in the embodiment of the present application is based on the CPU+FPGA architecture. By using a variety of technical means such as the CPU multi-threading mechanism, the business queue management mechanism, the FPGA multi-business core parallel computing mechanism, and the FPGA scheduling mechanism based on the multiple window sliding method, the high concurrency processing capability of the device when simultaneously processing a large number of different businesses is improved, ensuring that the device meets the use requirements of high reliability, high concurrency, and low latency.
[0049] Optionally, in the FPGA calling method based on the window sliding method provided in the embodiment of the present application, if a thread does not receive data from the opposite device within the first time interval, the thread is closed to release CPU resources.
[0050] The first time interval can be set according to actual needs, and its function is to release CPU memory resources when a certain thread has not received data from the opposite device for a long time, thereby increasing the utilization efficiency of the device and avoiding waste of memory resources.
[0051] Optionally, the FPGA calling method based on the window sliding method provided in the embodiment of the present application, wherein the window sliding method is used, specifically includes:
[0052] The window sliding method is used for data call. The CPU sends data to the FPGA according to the window size, and the window is continuously sliding as the FPGA responds to the data.
[0053] Specifically, when the CPU calls the FPGA, it uses the window sliding method to call data. The CPU sends data to the FPGA according to the window size. As the FPGA responds to data, the window continues to slide, allowing the device to fully utilize the processing power of the FPGA when performing multi-business processing.
[0054] Optionally, the FPGA calling method based on the window sliding method provided in the embodiment of the present application further includes:
[0055] When the CPU sends data to the FPGA, the window size is set to N. When the device is in multi-service concurrent processing, the CPU controls the number of services being processed inside the FPGA. When the CPU receives the response data from the FPGA, it sends the next packet of service data to be processed in the service processing queue to the FPGA.
[0056] Optionally, the FPGA calling method based on the window sliding method provided in the embodiment of the present application further includes:
[0057] When communicating with multiple external devices with different business functions, the CPU will allocate a corresponding sub-window to each independent business, and use the window sliding method to call the FPGA function on the sub-window. For each different business, the number of business cores deployed in the FPGA is different. When one of the business processing is completed, the CPU will adjust the sub-windows of other businesses.
[0058] Optionally, in the FPGA calling method based on the window sliding method provided in the embodiment of the present application, the CPU adjusts the sub-window of other services, specifically including:
[0059] The CPU and FPGA dynamically adjust the size of the window between them based on the performance and latency of all services currently being processed;
[0060] The window size of the sub-window is dynamically adjusted based on the performance and latency of processing different services.
[0061] Specifically, in one embodiment, when the CPU sends data to the FPGA, the window size N is set to 10. When the device communicates with multiple external devices with different service functions, the CPU uses the window sliding method to call the FPGA function for each independent service, and sets the current window to N. The sub-windows of the four different services are N1, N2, N3, and N4, respectively. Figure 5 shown.
[0062] For each different service, the number of service cores deployed in the FPGA is different, and the processing performance of a single service core for different services is different, so that under the large window, the number of sub-windows maintained by each different service is different. When service 2 is processed, the CPU side data processing queue also has no such task, so the CPU can dynamically adjust window N to N', and adjust the sub-windows of services 1, 3, and 4 to N1', N2', and N3' respectively.
[0063] The CPU and FPGA dynamically adjust the size of the window N' between the CPU and FPGA according to the performance and latency of all the services currently being processed. At the same time, in view of the performance and latency of processing different services, under a large window N', according to the different services in the CPU queue to be processed and the deployment of the service cores in the FPGA, the sizes of the sub-windows N1', N2' and N3' are dynamically adjusted, such as Figure 6 As shown, the high-speed computing performance of FPGA is fully utilized to improve the processing ability of communicating with multiple other devices for different services at the same time.
[0064] In view of the high concurrency and multi-service intercommunication requirements of the device, if a single service core is used for service processing, when facing concurrent services, the responsiveness of the entire device will be limited by the processing performance of a single service core, affecting the device's ability to handle multiple services simultaneously. This application enhances the FPGA's ability to process multiple different services in parallel by integrating multiple service cores in the FPGA, effectively solving the problem that the processing power and latency of a single service core do not meet system requirements, and improving the device's concurrency capability.
[0065] The FPGA calling method based on the window sliding method provided in the embodiment of the present application is based on the CPU+FPGA architecture. The intercommunication status of each different device is independently maintained on the CPU side through multi-threading technology, and the service data sent by the opposite device can be received in time, and stored in the CPU cache in time, waiting for subsequent service processing; the service processing queue for sending data from the CPU to the FPGA is optimized, and the order of sending different service data is automatically adjusted according to the optimal processing capability of the device according to the different service processing conditions inside the FPGA; according to the different service processing conditions inside the FPGA, the size of the sliding window and the subordinate sub-window is automatically adjusted on the CPU side according to the service quantity and the processing performance of a single service core, so as to give full play to the high parallel computing characteristics of the FPGA and enhance the efficiency of the CPU scheduling the FPGA; according to the concurrency requirements of the device in the system and the processing capability of a single service core in the FPGA, multiple service cores are deployed in the FPGA for each service function to improve the parallel processing capability of the device, so as to realize the reliable processing of multiple services and high concurrency of the device in the system.
[0066] In one embodiment, based on the FPGA calling method based on the window sliding method provided by the present application, corresponding hardware design and software design are performed on multi-service, high-concurrency devices to achieve functions such as high-speed computing for specific different services. The design is as follows:
[0067] 1. Hardware Design
[0068] The hardware structure of the device adopts a CPU+FPGA design architecture, in which the CPU is mainly used to realize online communication with other devices in the system through the IP network, and can actively initiate services to other devices or respond to service requests initiated by other devices; the FPGA is mainly used to realize functions such as high-speed computing for specific different services.
[0069] 2. Software Design
[0070] a. Multi-thread design on the CPU side: Multi-threads are created by inheriting the Thread method. Each thread independently maintains the interaction information with different devices. Multiple threads process multiple business information at the same time, and the CPU manages the threads throughout their life cycle.
[0071] b. CPU-side business data control design: The CPU creates a data sending queue to record the business information being processed and pending business information on the FPGA. According to the number of business cores in the FPGA and the business processing performance, it controls the sending order of different business data packets in the queue, giving full play to the computing power of the equipment while ensuring system performance.
[0072] c. Call design of the multiple window sliding method: The CPU dynamically adjusts the size of the total window between the CPU and the FPGA according to the business type in the data queue and the processing capability of the FPGA. Then, according to the ability of the FPGA to simultaneously process the same business, the number of windows for each business is dynamically adjusted to give full play to the high-speed parallel computing characteristics of the FPGA.
[0073] d.FPGA multi-service core design: Deploy multiple different service cores inside the FPGA to support the multi-service functions of the device; at the same time, deploy multiple sets of the same service cores according to the service type to improve the parallel computing capability of the device.
[0074] The present application also provides an FPGA calling device based on a window sliding method, comprising:
[0075] The thread creation module is used by the CPU to monitor the TCP / UDP data of the port and create multiple new threads according to the intercommunication objects. Each thread independently records the interaction information with different devices.
[0076] The first adjustment module is used for dynamically adjusting the order of sending the service data to the FPGA according to the current operation status of the FPGA and the performance of processing different services when multiple threads receive service data at the same time;
[0077] The second adjustment module is used to continuously send the business data to be processed to the FPGA using the window sliding method according to the computing power of the FPGA, and dynamically adjust the size of each business sub-window according to the processing status of each different business under the window according to the operation status of different businesses currently being carried out in the FPGA.
[0078] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, the steps of the above method are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.
[0079] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.
[0080] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0081] In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.
[0082] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0083] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0084] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM), random access memory (RAM), mobile hard disk, disk or optical disk and other media that can store program code.
[0085] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which can include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.
[0086] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.
[0087] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0088] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A FPGA calling method based on a window sliding method, characterized in that: include: The CPU monitors the TCP / UDP data of the port and creates multiple new threads based on the intercommunication objects. Each thread independently records the interaction information with different devices. When multiple threads receive business data at the same time, the CPU dynamically adjusts the order of sending business data to the FPGA based on the current operation status of the FPGA and the performance of processing different businesses; According to the computing power of FPGA, the window sliding method is used to continuously send the business data to be processed to FPGA. According to the operation status of different businesses currently running in FPGA, the size of each business sub-window is dynamically adjusted according to the processing status of each different business under the window.
2. The FPGA calling method based on the window sliding method as claimed in claim 1, characterized in that: If a thread does not receive data from the peer device within the first time interval, the thread is closed to release CPU resources.
3. The FPGA calling method based on the window sliding method as claimed in claim 1, characterized in that: The window sliding method is used, specifically including: The window sliding method is used for data call. The CPU sends data to the FPGA according to the window size, and the window is continuously sliding as the FPGA responds to the data.
4. The FPGA calling method based on the window sliding method as claimed in claim 3, characterized in that: Also includes: When the CPU sends data to the FPGA, the window size is set to N. When the device is in multi-service concurrent processing, the CPU controls the number of services being processed inside the FPGA. When the CPU receives the response data from the FPGA, it sends the next packet of service data to be processed in the service processing queue to the FPGA.
5. The FPGA calling method based on the window sliding method as claimed in claim 4, characterized in that: Also includes: When communicating with multiple external devices with different business functions, the CPU will allocate a corresponding sub-window to each independent business, and use the window sliding method to call the FPGA function on the sub-window. For each different business, the number of business cores deployed in the FPGA is different. When one of the business processing is completed, the CPU will adjust the sub-windows of other businesses.
6. The FPGA calling method based on the window sliding method as claimed in claim 5, characterized in that: The CPU adjusts the sub-windows of other services, specifically including: The CPU and FPGA dynamically adjust the size of the window between them based on the performance and latency of all services currently being processed; The window size of the sub-window is dynamically adjusted based on the performance and latency of processing different services.
7. An FPGA calling device based on a window sliding method, characterized in that: include: The thread creation module is used by the CPU to monitor the TCP / UDP data of the port and create multiple new threads according to the intercommunication objects. Each thread independently records the interaction information with different devices. The first adjustment module is used for dynamically adjusting the order of sending the service data to the FPGA according to the current operation status of the FPGA and the performance of processing different services when multiple threads receive service data at the same time; The second adjustment module is used to continuously send the business data to be processed to the FPGA using the window sliding method according to the computing power of the FPGA, and dynamically adjust the size of each business sub-window according to the processing status of each different business under the window according to the operation status of different businesses currently being carried out in the FPGA.
8. An FPGA calling device based on a window sliding method, characterized in that: The method comprises at least one processing unit and at least one storage unit, wherein the storage unit stores a computer program, and when the computer program is executed by the processing unit, the processing unit executes the steps of the method according to any one of claims 1 to 6.
9. A storage medium, characterized in that: It stores a computer program that can be executed by an FPGA calling device based on the window sliding method. When the computer program runs on the FPGA calling device based on the window sliding method, the FPGA calling device based on the window sliding method executes the steps of the method described in any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the FPGA calling method based on the window sliding method as claimed in any one of claims 1 to 6 are implemented.