Hardware-assisted page table management systems, methods, media, program products, and terminals

Abstract

The application provides a hardware-assisted page table management system, method, medium, program product and terminal, and efficient address conversion is realized through cooperative work of a memory management unit and a memory unit. Key steps including a translation lookaside buffer hit detection, a guest page table lookup, a page walk cache lookup and the like are included. After receiving an access instruction, the memory management unit performs detection through a translation lookaside buffer hit detection module; if a hit does not occur, a corresponding host physical address is obtained by a guest page table lookup module. The system performs a lookup in a page walk cache module, accesses a second cache of the memory unit if necessary, and stores a lookup result into a cache line in a preset format. The application realizes transparent conversion of a customer page table address in a cache in a hardware-assisted manner, and provides a complete shadow page table item life cycle management scheme.

Description

Technical Field

[0001] This application relates to the field of computing processor architecture, and in particular to a hardware-assisted page table management system, method, medium, program product, and terminal. Background Technology

[0002] In modern virtualization environments, virtual machines (VMs) provide users with a secure sandbox environment by multiplexing multiple hardware resources. Virtualization technology, as the cornerstone of cloud computing, separates hardware from software and allows multiple operating systems and applications to run simultaneously on a single machine. This isolation significantly optimizes resource utilization, reduces costs, enhances system security, and enables large-scale services. However, virtualization comes with significant address translation overhead, primarily due to sequential accesses to multi-level radix page tables. In modern x86-64 architectures, a four-level page table divides a 48-bit virtual address into four segments, translating them into physical addresses via sequential memory access. While this method reduces page table storage space, in non-virtualized environments, a single TLB (Translation Lookaside Buffer) miss may require up to four sequential memory accesses. In virtualized environments, page tables are organized in a multi-level tree structure. The guest operating system's virtual address (gVA) needs to be translated into a guest physical address (gPA) through the guest's page table (gPT). This address is then used as the host operating system's virtual address (hVA), and further translated into a host physical address (hPA) through a nested page table (nPT) to access the final data.

[0003] To address these issues, the industry has widely adopted hardware-assisted virtualization technologies, such as Intel's Extended Page Table (EPT) and AMD's Nested Page Table (NPT), which utilize hardware functions to cache address translation and reduce the complexity of nested page lookups. Furthermore, shadow page tables are maintained by the Virtual Machine Monitor (VMM) or hypervisor, providing a direct mapping from virtual addresses to physical addresses for each virtual machine. While shadow page tables reduce page table lookup requirements, virtual machine exits are necessary whenever the guest operating system updates the page table, resulting in significant performance overhead. Victima is an emerging technology that improves translation efficiency by utilizing underutilized L2 cache resources. It uses L2 cache lines to store evicted TLB entries, providing additional low-latency, high-capacity fallback components to support the last-level TLB and reduce page table walker (PTW) overhead.

[0004] While existing technologies have addressed address translation issues in virtualized environments to some extent, each has its limitations. TLB and shadow page table technologies, although reducing address translation time, are inefficient under high loads or large memory workloads. Shadow page tables, in particular, place a significant burden on performance due to frequent virtual machine exits. While Victima utilizes L2 caching to enhance TLB caching capabilities, high cache utilization and potential performance saturation limit its practical application advantages. Furthermore, although hardware-assisted address translation alleviates software pressure, the high latency of TLB misses and page table traversals remains a challenge under increasing memory demands. These limitations indicate that further innovative solutions are needed to optimize address translation in virtualized environments to further improve efficiency and performance. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a hardware-assisted page table management system, method, medium, program product and terminal to solve the problem that the efficiency of address translation is still limited under high load and large memory workload in the existing page table management technology, thereby affecting system performance and responsiveness.

[0006] To achieve the above and other related objectives, a first aspect of this application provides a hardware-assisted page table management system, the system comprising an MMU unit and a memory unit, the system comprising: the MMU unit comprising: a TLB hit detection module, a guest page table lookup module, and a page traversal cache module; the memory unit comprising: a level 1 cache and a level 2 cache; the interaction method of the system includes the following steps: the MMU unit receives an access instruction; the TLB hit detection module performs a hit detection operation based on the access instruction; if a TLB hit occurs, the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction; the MMU unit... The page table lookup operation is performed in the page traversal cache module based on the host physical address. If the lookup fails, the MMU unit sends the host physical address to the memory unit to initiate an address translation request. The memory unit performs a page table lookup operation in the secondary cache based on the host physical address. If the lookup is successful, the found client page table entry is stored in a cache line of a preset format, and the cache line of the preset format is stored in the secondary cache and the page traversal cache module. The page traversal cache module sends the shadow page table entry to the guest page table lookup module so that the guest page table lookup module can perform the corresponding access operation based on the shadow page table entry.

[0007] In some embodiments of the first aspect of this application, the cache line with the preset format includes: a label, a status bit, multiple client page table entries, and a first shadow flag bit; each client page table entry includes: a second shadow flag bit and a page number; wherein, the first shadow flag bit includes a first flag and a second flag, wherein the first flag is used to indicate that the current cache line contains a client page table entry that has been replaced with a shadow page table entry; the second flag is used to indicate that the current cache line does not contain a client page table entry that has been replaced with a shadow page table entry; the second shadow flag bit includes a third flag and a fourth flag, wherein the third flag is used to indicate that the current client page table entry has been replaced with a shadow page table entry; the fourth flag is used to indicate that the current client page table entry has not been replaced with a shadow page table entry.

[0008] In some embodiments of the first aspect of this application, the process of storing the found client page table entry into a cache line of a preset format includes: the secondary cache determining the second shadow flag bit in the current client page table entry; if the second shadow flag bit is a fourth flag, then converting the current client page table entry into the corresponding shadow page table entry through the nested page table addresser in the memory unit, and setting the second shadow flag bit to a third flag; storing the replaced client page table entry into the current cache line, and setting the first shadow flag bit of the current cache line to a first flag.

[0009] In some embodiments of the first aspect of this application, the interaction of the system includes one or more of the following steps: if the first-level cache misses while the second-level cache hits, and the second shadow flag of the requested client page table entry is a fourth flag, then the requested client page table entry is sent to the first-level data cache of the memory unit; if the first-level cache misses while the second-level cache hits, and the second shadow flag of the requested client page table entry is a third flag, then other cache layers or DRAM memory are requested to provide a cache line that does not contain a shadow page table entry, and the cache line that does not contain a shadow page table entry is sent to the first-level data cache of the memory unit; if the first-level cache misses while the second-level cache misses, the MMU unit and the memory unit perform a client page table entry consistency maintenance operation.

[0010] In some embodiments of the first aspect of this application, the guest page table lookup module includes: a guest page table traverser and a first register; the first register includes a valid bit and a host physical address bit, wherein the initial state bit of the valid bit is invalid.

[0011] In some embodiments of the first aspect of this application, the process by which the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction includes: the first register and the second register being communicatively connected; the first register obtaining the guest physical address from the second register based on the access instruction; the second register searching for the corresponding host physical address in the host page table traverser based on the guest physical address, and sending the host physical address back to the first register; the MMU unit storing the host physical address in the first register, and setting the valid bit in the first register to a valid state.

[0012] To achieve the above and other related objectives, a second aspect of this application provides a hardware-assisted page table management method, applied to a computer processor. The method includes: receiving an access instruction; performing a hit detection operation based on the access instruction; if a TLB miss occurs, obtaining the host physical address corresponding to the access instruction, storing the host physical address, and performing a valid bit setting operation based on the access instruction; performing a page table lookup operation based on the host physical address; if the lookup fails, performing a page table lookup operation in the secondary cache based on the host physical address; if the lookup succeeds, storing the found client page table entry into a cache line of a preset format, and storing the cache line of the preset format into the secondary cache; and performing a corresponding access operation based on the shadow page table entry.

[0013] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the hardware-assisted page table management method.

[0014] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product including computer program code, which, when executed on a computer, enables the computer to implement the hardware-assisted page table management method.

[0015] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the hardware-assisted page table management method.

[0016] As described above, the hardware-assisted page table management system, method, medium, program product, and terminal of this application have the following beneficial effects: 1) Transparent translation of client page table addresses in the cache is achieved through hardware assistance, effectively reducing address translation overhead; 2) An innovative lifecycle management scheme for shadow page table entries is designed to ensure the stability and reliability of system operation; 3) A unique client operating system page table maintenance processing scheme is adopted, achieving software-level transparency and reducing system complexity. Experimental results show that compared with the prior art, this invention significantly improves performance, by 17% compared to nested paging and 8.5% compared to Victima, enabling the performance of the virtualization environment to reach 89% of the native performance, and greatly improving the overall performance of the virtualization system. Attached Figure Description

[0017] Figure 1 A schematic diagram of an embodiment of the hardware-assisted page table management system of this application is shown.

[0018] Figure 2 The diagram shows a flowchart illustrating the interaction process in one embodiment of the hardware-assisted page table management system of this application.

[0019] Figure 3 The diagram shows the structure of the SgCR3 register and gCR3 register in one embodiment of the hardware-assisted page table management system of this application.

[0020] Figure 4 The diagram shows a schematic representation of the cache line structure in one embodiment of the hardware-assisted page table management system of this application.

[0021] Figure 5 The diagram shows a flowchart of address translation in one embodiment of the hardware-assisted page table management system of this application.

[0022] Figure 6 The diagram shows a flowchart illustrating different hit scenarios in one embodiment of the hardware-assisted page table management system of this application.

[0023] Figure 7 The diagram illustrates the effect of multiple load conditions in one embodiment of the hardware-assisted page table management system of this application.

[0024] Figure 8 The diagram shows a flowchart of an embodiment of the hardware-assisted page table management method of this application.

[0025] Figure 9 The diagram shows a structural schematic of an embodiment of the hardware-assisted page table management terminal of this application. Detailed Implementation

[0026] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0027] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0028] <1> Page table management refers to the process of creating, updating, and maintaining page tables. Page tables are used by the operating system to manage the mapping between virtual memory and physical memory.

[0029] <2> MMU Unit: The Memory Management Unit (MMU) is a computer hardware component responsible for translating virtual addresses into physical addresses and implementing memory protection and address space management.

[0030] <3> Memory Cells: Memory cells are the fundamental components of computer memory, responsible for persistent data storage. Their internal structure includes multiple levels of cache, such as L1, L2, and L3 caches, and supports the mapping between guest page table entries (GPT entries) and host page table entries (NPT entries) in virtualization. The XBAR (Extended Cross-Band) provides parallel communication capabilities to improve data transfer efficiency between the processor and memory. Dynamic Random Access Memory (DRAM), as the core of main memory, needs to be refreshed periodically to maintain data validity.

[0031] <4> Guest Page Table Walker: The Guest Page Table Walker is used to access and look up page tables inside a virtual machine, and is commonly used in virtualization environments.

[0032] <5> Host Page Table Walker: The host page table walker is a component that accesses the internal page tables of the host operating system and manages the mapping of the host virtual address space.

[0033] <6> Page Walk Cache Module: The Page Walk Cache Module is a caching mechanism used to store recently used page table entries, thereby speeding up the page table traversal process.

[0034] <7> SgCR3 Register: The SgCR3 register stores the base address of the guest page table, which is used to point to the page table in the guest's physical address space.

[0035] <8> gCR3 Register: The gCR3 register records the base address of the page table associated with the current virtual machine context and is used for address translation.

[0036] <9> Page table lookup operation: The page table lookup operation is the process of obtaining the physical address corresponding to the virtual address by looking up the page table.

[0037] <10> Cache line: A cache line is the basic unit of data storage in the CPU cache. It usually consists of multiple bytes and determines the smallest granularity of data retrieval from main memory.

[0038] <11> DRAM: Dynamic Random Access Memory (DRAM) is a type of semiconductor memory widely used in computers and electronic devices. It stores data dynamically and requires constant refreshing to maintain information.

[0039] <12> Guest Physical Address: The guest physical address refers to the physical memory address that the virtual machine can directly access, which is translated through the host machine's memory management.

[0040] <13> Host Physical Address: The host physical address is the actual physical memory address of the host machine. The physical address of the guest virtual machine is mapped through this address.

[0041] <14> Shadow Guest Page Table Entry: A shadow guest page table entry is a page table entry maintained on the host machine. It is used to quickly translate the guest virtual address to the host physical address and avoid accessing the guest page table.

[0042] <15> TLB: Translation Lookaside Buffer (TLB) is a caching mechanism used to store the mapping of recently accessed virtual addresses to physical addresses, thus accelerating address translation.

[0043] <16> Guest Page Table: The Guest Page Table (gPT) is a page table maintained internally by the virtual machine to manage the mapping of virtual addresses in the guest operating system to their physical addresses.

[0044] <17> Nested Translation Lookaside Buffer: The nested translation lookaside buffer is used to improve address translation efficiency in nested virtualization environments and to store virtual machine address mappings.

[0045] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 This invention illustrates a schematic diagram of a hardware-assisted page table management system according to an embodiment of the present invention. The system includes an MMU unit and a memory unit. The MMU unit includes a TLB hit detection module, a guest page table lookup module, and a page traversal cache module. The memory unit includes a level 1 cache and a level 2 cache. The present invention significantly reduces the need for nested address translation by replacing the guest physical address (gPA) of the guest page table in the cache with the host physical address (hPA), while maintaining the software transparency of the guest operating system. The replaced guest page table entry containing the hPA is referred to as a shadow guest page table entry.

[0046] The interaction of the hardware-assisted page table management system in this embodiment is as follows: Figure 2 As shown, the main steps include the following:

[0047] Step S21: The MMU unit receives an access instruction; the TLB hit detection module performs a hit detection operation based on the access instruction. If the TLB is not hit, the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction.

[0048] In one embodiment of the present invention, after obtaining the host physical address corresponding to the access instruction, the following steps are also performed: storing the host physical address in the guest page table lookup module, and performing a valid bit setting operation on the guest page table lookup module.

[0049] In one embodiment of this invention, the process by which the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction includes: the guest page table lookup module requests the host page table lookup module to convert the guest physical address gPA into the host physical address hPA based on the access instruction. The host page table addresser includes a host page table traverser and a second register.

[0050] In one embodiment of the present invention, the guest page table lookup module includes: a guest page table traverser and a first register; the first register includes a valid bit and a host physical address bit, wherein the initial state bit of the valid bit is invalid.

[0051] In one embodiment of the present invention, the first register is the SgCR3 register and the second register is the gCR3 register. Figure 3 The diagram illustrates the structure of the SgCR3 and gCR3 registers in this embodiment. In the gCR3 register, bits 65-52 are reserved, and bits 51-13 represent the gPA of the first-level customer page table. In the SgCR3 register, bits 65-53 are reserved, bits 53-52 are valid, and bits 51-13 represent the hPA of the first-level customer page table. The reserved bits are unused register bits, reserved for future expansion or compatibility. The SgCR3 register sets a 1 in the reserved bits to a valid bit to indicate whether the hPA currently stored in SgCR3 is valid.

[0052] In this embodiment, the SgCR3 register is used to directly provide the first-level hPA of the client page table to the Guest Page Table Walker (GPTW), thereby reducing additional translation or lookup steps and thus reducing latency. The Guest Page Table Walker is responsible for finding and resolving the structure of the client page table in the virtual environment. A traditional GPTW is used to map gvA to gPA, a process that includes lookup, hierarchical structure, and address translation. The GPTW accesses the client page table level by level, starting with the first-level page table and continuing until the target page table entry is found. Client page tables typically employ a multi-level structure, such as two- or three-level page tables, and obtain the physical address by reading the content of each level. In this embodiment, when the guest operating system initiates a memory access request, the GPTW directly accesses the memory using the Host Physical Address (hPA) stored in the SgCR3 register.

[0053] In this embodiment, the operating system and virtualization monitoring program are not allowed to directly modify the SgCR3 register to ensure system stability and security. The initial state bit of the valid bit is set to invalid to indicate that a valid hPA mapping has not yet been established in the SgCR3 register. The SgCR3 register and the gCR3 register maintain consistency through an automatic access and synchronization mechanism. Specifically, when SgCR3 is invalid, the gPA is automatically retrieved from the gCR3 register, and the MMU unit is requested to convert the gPA to hPA. The generated hPA is then stored in SgCR3 and the valid bit is set to establish the gPA-hPA mapping.

[0054] Furthermore, when the gCR3 register is modified, the valid bits of SgCR3 are cleared, enabling address translation to be re-performed on the next access, thus ensuring that any updates are reflected and avoiding potential data inconsistencies. Maintaining consistency between the SgCR3 and gCR3 registers is crucial for system stability and data integrity. If they are out of sync, memory access errors may occur, impacting overall system performance. In addition, through dynamic mapping and intelligent invalidation mechanisms, the SgCR3 design effectively adapts to different memory requirements, improving access efficiency and reducing expected latency.

[0055] In one embodiment of the present invention, the process by which the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction includes: the first register and the second register being communicatively connected; the first register obtaining the guest physical address from the second register based on the access instruction; the second register searching for the corresponding host physical address in the host page table traverser based on the guest physical address, and sending the host physical address back to the first register; the MMU unit storing the host physical address in the first register, and setting the valid bit in the first register to a valid state.

[0056] Step S22: The MMU unit performs a page table lookup operation in the page traversal cache module based on the host physical address; if the lookup fails, the MMU unit sends the host physical address to the memory unit to initiate an address translation request.

[0057] In one embodiment of the present invention, the MMU is used for address translation and memory management, and simultaneously translates virtual addresses into physical addresses so that the processor can access memory. In this embodiment, the host physical address is input into the MMU, and the MMU searches for the corresponding page table entry in the page traversal cache module. The page traversal cache is a caching mechanism used to store recently used page table information, designed to accelerate page table lookup operations. The page table is used to map virtual addresses to physical addresses. By performing a page table lookup operation, the MMU can quickly identify the physical page corresponding to the host physical address. However, if the MMU fails to find a matching page table entry in the cache, further address translation operations need to be performed in the main memory unit. Subsequently, the MMU sends the host physical address to the memory unit to initiate an address translation request, requesting the memory management system or other hardware units (such as main memory) to perform deeper address translation to determine the actual physical address.

[0058] Step S23: The memory unit performs a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, the found client page table entry is stored in a cache line of a preset format, and the cache line of the preset format is stored in the secondary cache and the page traversal cache module.

[0059] In one embodiment of the present invention, the cache line with the preset format includes: a label, a status bit, multiple client page table entries, and a first shadow flag bit; each client page table entry includes: a second shadow flag bit and a page number; wherein, the first shadow flag bit includes a first flag and a second flag, wherein the first flag is used to indicate that the current cache line contains a client page table entry that has been replaced with a shadow page table entry; the second flag is used to indicate that the current cache line does not contain a client page table entry that has been replaced with a shadow page table entry; the second shadow flag bit includes a third flag and a fourth flag, wherein the third flag is used to indicate that the current client page table entry has been replaced with a shadow page table entry; the fourth flag is used to indicate that the current client page table entry has not been replaced with a shadow page table entry.

[0060] Figure 4 This illustration shows a schematic diagram of a cache line structure according to an embodiment of the present invention, comprising a 64-byte cache line containing eight 8-byte client page table entries. The present invention creatively selects one bit from the unused bits of each client page table entry as a shadow flag bit to indicate whether the client page table entry is a shadow client page table entry or an original client page table entry. For example, initially, the shadow flag bit is set to 0, indicating that the client page table entry is in its original state. When the cache converts an original client page table entry into a shadow client page table entry, the shadow flag is set to 1. At this time, the current cache line cannot be directly read by the guest operating system and cannot be written back to memory, thereby ensuring the memory security and effectiveness of the virtual machine.

[0061] It's worth noting that this innovation effectively reduces storage requirements by utilizing unused bits of client page table entries as shadow flags, eliminating additional storage overhead and thus improving memory utilization efficiency. Secondly, using shadow flags allows for quick identification of the status of client page table entries, optimizing the address translation process. This efficient status indication reduces lookup time and improves overall system performance. Furthermore, when original client page table entries are converted to shadow client page table entries, a strategy that prevents direct reading or writing back to memory is employed, enhancing virtual machine security. This design prevents the guest operating system from directly accessing sensitive data, ensuring memory protection.

[0062] In one embodiment of the invention, efficient periodic management is provided for the shadow client page table entries. While converting the original client page table entries into shadow client page table entries can accelerate page table traversal, the original client page table entries still need to be retained for management by the client operating system. Furthermore, to prevent modification or replacement of the unique copy in the caching system, a protection mechanism is implemented when creating the shadow client page table entries, thereby ensuring that the original client page table entries are securely stored and remain valid during page table entry conversion.

[0063] Specifically, when the shadow flag of a data block in the L2 cache is updated from 0 to 1, it indicates that the data block will only contain original client page table entries, and one of these entries is about to be converted into a shadow client page table entry. During this process, the L2 cache first writes the data block back to the L3 cache to ensure that all original client page table entries are safely stored in the L3 cache, thus preventing the loss of the original virtual address (gPA) in the guest page table (gPT). When the L2 cache moves a data block containing a shadow client page table entry to the L3 cache due to replacement, the system first checks if the corresponding shadow data block exists in the L3 cache. If it exists, the L3 cache writes this data block to main memory, which is responsible for storing these original client page table entries. When the L3 cache needs to evict a data block containing a shadow client page table entry, this data block is discarded. If this shadow client page table entry needs to be accessed again in the future, the system will re-convert it from the corresponding original client page table entry. These mechanisms collectively ensure efficient page table management and data integrity. Simply put, they can effectively manage virtual memory, ensuring that critical data is not lost and can be accessed and updated quickly.

[0064] In one embodiment of the present invention, the process of storing the found client page table entry into a cache line of a preset format includes: the secondary cache determining the second shadow flag bit in the current client page table entry; if the second shadow flag bit is a fourth flag, then converting the current client page table entry into the corresponding shadow page table entry through the nested page table addresser in the memory unit, and setting the second shadow flag bit to a third flag; storing the replaced client page table entry into the current cache line, and setting the first shadow flag bit of the current cache line to a first flag.

[0065] Figure 5 This diagram illustrates the address translation process in one embodiment of the present invention. As shown in steps 1 and 2, when both L1TLB and L2TLB are not hit, GPTW is activated to perform the page table traversal operation in step 3. The page table traversal operation includes: performing step 4, retrieving the hPA of the Global Level 4 Page Table (gL4) from the SgCR3 register. As described in the previous embodiment, the initial state of the valid bits in the SgCR3 register is invalid. On the first access, as shown in step 5, the SgCR3 register retrieves the gPA of gL4 from the gCR3 register, and performs step 6 to request the host page table addresser to convert it to hPA, stores the converted hPA in the SgCR3 register, and marks the valid bits in the SgCR3 register as valid.

[0066] Further, as shown in step 7, the GPTW queries the shadow client page table entry in the Page Walk Cache (PWC). If the shadow client page table entry is not found in the PWC, the L2 cache is accessed. In step 8, if the client page table entry is found in the L2 cache or retrieved from a lower-level cache, the L2 cache checks if the shadow flag of the requested client page table entry is set to 1. If not, the L2 cache sends a request to the Host Page Table Walker (HPTW) (step 9) to convert the client page table entry into a shadow client page table entry and sets the shadow flag to 1. Finally, the shadow client page table entry is cached in both the L2 cache and the PWC and ultimately returned to the GPTW so that the client page table walker can directly access the next-level guest page table using the physical address (hPA) in the shadow client page table entry, thereby avoiding requests to the Nested Translation Lookaside Buffer (NTLB) or the execution of a nested page translation (PTW). Nested Translation Backup Buffer (NTLB) is a memory management mechanism designed to support virtualization technology by optimizing memory access through improved address translation efficiency in virtual environments. NTLB is primarily used for memory access between the hypervisor and virtual machines (VMs), allowing for multi-level mapping between virtual machine addresses and host physical addresses.

[0067] Step S24: The page traversal cache module sends the shadow page table entry to the guest page table lookup module, so that the guest page table lookup module can perform the corresponding access operation based on the shadow page table entry.

[0068] In one embodiment of the present invention, the interaction mode of the system includes one or more of the following steps: if the first-level cache misses while the second-level cache hits, and the second shadow flag of the requested client page table entry is a fourth flag, then the requested client page table entry is sent to the first-level data cache of the memory unit; if the first-level cache misses while the second-level cache hits, and the second shadow flag of the requested client page table entry is a third flag, then other cache structures or DRAM memory are requested to provide a cache line without shadow page table entries, and the cache line without shadow page table entries is sent to the first-level data cache of the memory unit; if the first-level cache misses while the second-level cache misses, the MMU unit and the memory unit perform client page table entry consistency maintenance operations.

[0069] Figure 6This embodiment demonstrates that when the client operating system reads the client page table, if the requested client page table entry is not found in the L1 data cache, the request is further sent to the L2 cache, and different operations are performed based on the L2 cache hit status and the setting of the shadow flag bit.

[0070] Specifically, this embodiment includes three scenarios. For scenario one, if the L2 cache hits the requested client page table entry, and the shadow flag in the cache block is not set (i.e., the third flag mentioned above), it indicates that the requested client page table entry was found in the current L2 cache, and no client page table entry in the cache data block (cache line) has been converted to a shadow client page table entry. In this case, since the shadow flag is not set, the client page table entry remains the original valid entry and can be directly used for physical address translation. The L2 cache directly forwards the currently hit cache data block to the L1 data cache to satisfy the client operating system's access request.

[0071] In scenario two, if the L2 cache hits the requested client page table entry and the shadow flag in the cache block is set, it indicates that the block containing the requested client page table entry contains one or more shadow client page table entries. To prevent the guest operating system from reading shadow client page table entries, the L2 cache cannot directly return the block to the L1 data cache. Directly returning such a block could lead to the guest operating system receiving invalid or inconsistent data, causing security and stability issues. Therefore, the L2 cache needs to request a block from other caches or from DRAM via the bus where the shadow flag is not set. This ensures that the returned data is valid and does not contain shadow client page table entries. Once a valid block is successfully received, the L2 cache sends the data directly to the L1 data cache without updating the L2 cache to avoid overwriting any existing shadow client page table entries.

[0072] For scenario three, if the requested client page table entry is not found in the L2 cache, the L2 cache will follow the standard cache miss handling procedure and request the target block. When the client operating system writes to the client page table, the system initiates a consistency request to ensure that the L1 Data Cache holds an exclusive or modified copy of the target client page table entry block. This operation will invalidate all copies of related blocks in the L2 and L3 caches. Furthermore, the related client page table entry must also be invalidated in the Page Written Cache (PWC) module. To maintain PWC consistency, a PWC cleanup operation is performed during Translation Backing Buffer (TLB) flushing to ensure that after the client page table is modified, old shadow client page table entries are promptly invalidated in the PWC, L2, and L3 caches, thereby eliminating the risk of data inconsistency.

[0073] To evaluate the performance and energy efficiency of this invention, experiments were conducted under multiple load conditions and compared with existing methods. The experimental results indicate that the method corresponding to this invention should be named Ninja. Figure 7 The x-axis represents various common computational tasks and algorithms, while the y-axis represents speedup, with higher values ​​indicating more significant performance improvements. The x-axis also represents various algorithms, including: Betweenness Centrality (BC), used to evaluate the importance of a node's connection in a network; Breadth-First Search (BFS), a graph search algorithm that traverses adjacent nodes layer by layer from the starting node; Connected Components (CC), representing the largest reachable subgraph in a graph that is not connected to other parts; Deep Learning Recommendation Model (DLRM), a deep learning algorithm for personalized recommendations; Graph Coloring (GC), an algorithm for coloring nodes in a graph to ensure that adjacent nodes have different colors; k-mercounting in GenomicsBench, a benchmark workload for evaluating computational system performance; PageRank (PR), an algorithm that determines the importance of a webpage based on its link structure; Random Access (RND), the process of randomly selecting paths to traverse a graph; and Shortest Path. Path (SP) is used to calculate the shortest path from the source node to other nodes; Triangle Counting (TC) is used to analyze the structural characteristics of a graph by counting the number of triangles in the graph; Monte Carlo cross-section search performance analysis tool (XSBench, XS) The Monte Carlo method is a numerical method based on random sampling, widely used in computational simulation and optimization problems in various fields. Macro-section search refers to the process of finding the optimal solution in a large-scale search space; Geometric Mean (GMEAN) is a statistical method used to measure the overall performance of different test results.

[0074] Figure 7This paper demonstrates the performance of Victima, the present invention, and Native (performance in a non-virtualized environment, for reference) in terms of execution time acceleration. The present invention significantly outperforms existing solutions in terms of performance. On average, the present invention achieves a 17% performance improvement compared to nested paging and an 8.5% improvement compared to Victima. Furthermore, with the optimizations of the present invention, the average performance in a virtualized environment is improved from 76% to 89% of the native performance level.

[0075] In the embodiments of this application, terms such as "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first shadow flag and the second shadow flag are only used to distinguish different shadow flags and do not limit their order. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or execution order, and that terms such as "first" and "second" do not necessarily imply that they are different.

[0076] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0077] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0078] Figure 8 This is a flowchart illustrating the hardware-assisted page table management method provided in an embodiment of this application. Figure 8 As shown, the method is applied to a computer processor, and the method includes the following steps:

[0079] Step S81: Receive access instruction; perform a hit detection operation based on the access instruction; if the TLB is not hit, obtain the host physical address corresponding to the access instruction based on the access instruction, store the host physical address, and perform a valid bit setting operation.

[0080] Step S82: Perform a page table lookup operation based on the host physical address; if the lookup fails, perform a page table lookup operation in the second-level cache based on the host physical address; if the lookup succeeds, store the found client page table entry in a cache line of a preset format, and store the cache line of the preset format in the second-level cache.

[0081] Step S83: Based on the shadow page table entry, perform the corresponding access operation.

[0082] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0083] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0084] Figure 9 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 9 As shown, the electronic terminal includes at least one processor 901, a memory 902, at least one network interface 903, and a user interface 905. The various components in the device are coupled together via a bus system 904. It is understood that the bus system 904 is used to implement communication between these components. In addition to a data bus, the bus system 904 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 9 The general will label all buses as bus systems.

[0085] The user interface 905 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0086] It is understood that memory 902 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0087] In this embodiment of the invention, the memory 902 is used to store various types of data to support the operation of the electronic terminal 900. Examples of this data include: any executable program for operation on the electronic terminal 900, such as the operating system 9021 and application programs 9022; the operating system 9021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 9022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The hardware-assisted page table management method provided in this embodiment of the invention can be included in the application program 9022.

[0088] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by processor 901. Processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 901 or by instructions in software form. The processor 901 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 901 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 901 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0089] In an exemplary embodiment, the electronic terminal 900 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0090] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the hardware-assisted page table management method of any of the embodiments shown above.

[0091] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the hardware-assisted page table management method of any of the embodiments shown above.

[0092] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0093] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0094] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0098] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state drives (SSDs)).

[0099] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0101] In summary, this application provides a hardware-assisted page table management system, method, medium, program product, and terminal, offering a page table cache management method in a virtualization system. This method achieves efficient address translation through the collaborative work of the MMU unit and memory units. Key steps include TLB hit detection, guest page table lookup, and page traversal cache lookup. After receiving an access instruction, the MMU unit performs a check via the TLB hit detection module; if a hit is missed, the guest page table lookup module retrieves the corresponding host physical address. The system performs a lookup in the page traversal cache module, accessing the secondary cache of the memory unit when necessary, and storing the lookup result in a cache line with a preset format. This invention achieves transparent translation of guest page table addresses in the cache through hardware assistance and provides a complete shadow page table entry lifecycle management scheme. Therefore, this application effectively overcomes various shortcomings of the prior art and has high industrial applicability.

[0102] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A hardware-assisted page table management system, characterized in that, The system includes an MMU unit and a memory unit. The system includes: The MMU unit includes: a TLB hit detection module, a guest page table lookup module, and a page traversal cache module; The memory unit includes: a level 1 cache and a level 2 cache; The interaction method of the system includes the following steps: The MMU unit receives an access instruction; the TLB hit detection module performs a hit detection operation based on the access instruction; if the TLB is not hit, the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction; the host physical address is stored in the first register in the guest page table lookup module so as to obtain the host physical address through the first register; The MMU unit performs a page table lookup operation in the page traversal cache module based on the host physical address to obtain a shadow page table entry; if the lookup fails, the MMU unit sends the host physical address to the memory unit to initiate an address translation request; the shadow page table entry is obtained by replacing the guest physical address in the guest page table entry with the host physical address, thereby converting the guest page table entry. The memory unit performs a page table lookup operation in the secondary cache based on the host physical address; if the lookup is successful, the found client page table entry is stored in a cache line of a preset format, and the cache line of the preset format is stored in the secondary cache and the page traversal cache module. The page traversal cache module sends the shadow page table entry to the guest page table lookup module, so that the guest page table lookup module can perform the corresponding access operation based on the shadow page table entry.

2. The hardware-assisted page table management system according to claim 1, characterized in that, The cache line in the preset format includes: a tag, a status bit, multiple customer page table entries, and a first shadow flag bit; each customer page table entry includes: a second shadow flag bit and a page number; The first shadow flag includes a first flag and a second flag, wherein the first flag is used to indicate that the current cache line contains a customer page table entry that has been replaced with a shadow page table entry; and the second flag is used to indicate that the current cache line does not contain a customer page table entry that has been replaced with a shadow page table entry. The second shadow flag includes a third flag and a fourth flag, wherein the third flag is used to indicate that the current customer page table entry has been replaced with a shadow page table entry; and the fourth flag is used to indicate that the current customer page table entry has not been replaced with a shadow page table entry.

3. The hardware-assisted page table management system according to claim 2, characterized in that, The process of storing the retrieved customer page entries into a cache line with a preset format includes: The secondary cache determines the second shadow flag bit in the current client page table entry; if the second shadow flag bit is the fourth flag, the current client page table entry is converted into the corresponding shadow page table entry through the nested page table addresser in the memory unit, and the second shadow flag bit is set to the third flag; the converted client page table entry is stored in the current cache line, and the first shadow flag bit of the current cache line is set to the first flag.

4. The hardware-assisted page table management system according to claim 2, characterized in that, The system's interaction methods include one or more of the following steps: If the first-level cache misses but the second-level cache hits, and the second shadow flag of the requested client page table entry is the fourth flag, then the requested client page table entry is sent to the first-level data cache of the memory unit. If the first-level cache misses while the second-level cache hits, and the second shadow flag of the requested client page table entry is the third flag, then other cache structures or DRAM memory are requested to provide a cache line that does not contain a shadow page table entry, and the cache line that does not contain a shadow page table entry is sent to the first-level data cache of the memory unit. If both the L1 and L2 caches are missed, the MMU unit and memory unit will perform client page table entry consistency maintenance operations.

5. The hardware-assisted page table management system according to claim 1, characterized in that, The guest page table lookup module includes a guest page table traverser and a first register; the first register includes a valid bit and a host physical address bit, wherein the initial state of the valid bit is invalid.

6. The hardware-assisted page table management system according to claim 5, characterized in that, The system further includes a host page table lookup module, which includes a host page table traverser and a second register; when the first register is invalid, the process by which the guest page table lookup module obtains the host physical address corresponding to the access instruction based on the access instruction further includes: The first register is communicatively connected to the second register; the first register obtains the guest physical address from the second register based on the access instruction; The second register searches for the corresponding host physical address in the host page table traverser based on the guest physical address, and sends the host physical address back to the first register; The MMU unit stores the host physical address in the first register and sets the valid bit in the first register to the valid state.

7. A hardware-assisted page table management method, characterized in that, The method is applied to a computer processor, and the method includes: Receive an access instruction; perform a TLB hit detection operation based on the access instruction; if the TLB is not hit, obtain the host physical address corresponding to the access instruction based on the access instruction; the host physical address is stored in the first register of the MMU unit so as to obtain the host physical address through the first register; A page table lookup operation is performed based on the host physical address to obtain a shadow page table entry; if the lookup fails, a page table lookup operation is performed in the L2 cache of the memory unit based on the host physical address; if the lookup succeeds, the found client page table entry is stored in a cache line of a preset format, and the cache line of the preset format is stored in the L2 cache; the shadow page table entry is obtained by replacing the guest physical address in the client page table entry with the host physical address, thereby converting the client page table entry; Based on the shadow page table entry, the corresponding access operation is performed.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the hardware-assisted page table management method of claim 7.

9. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, enables the computer to implement the hardware-assisted page table management method as described in claim 7.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the hardware-assisted page table management method of claim 7.

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