DDR access method and device, equipment and storage medium

Abstract

The invention relates to a DDR (Double Data Rate) access method, device and equipment and a storage medium, which are applied to the field of chip verification, and comprise an IP (Intellectual Property) core for acquiring JTAG (Joint Test Action Group) access, an IP core for XDMA (Extensible Direct Memory Access) access, an IP core of a DDR memory and a bus IP core, connecting the IP core accessed by the JTAG, the IP core accessed by the XDMA, the IP core of the DDR memory and the IP core of the bus to generate a block design; the block design is subjected to instantiation processing in the RISC-V processor, and an overall design is generated; and transplanting the overall design to an FPGA (Field Programmable Gate Array). The method has the technical effect that the DDR access efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a DDR access method, device, equipment and storage medium. Background Art

[0002] With the continuous development of the development and application scale of open source SoC (System on Chip) based on RISC-V core, simulation verification investment occupies more and more R&D costs and development time. FPGA (Field Programmable Gate Array) prototype verification has become a mainstream and mature verification method, playing a key role in accelerating design verification and shifting chip development left. Limited by the single capacity of mainstream FPGAs in the market, prototype verification systems based on multiple FPGAs have become the mainstream demand in the field of cutting-edge design verification. In the scenario of prototyping open source SoC based on RISC-V core, the commonly used method is that the RISC-V processor core needs to send / receive data through the AXI (Advanced Extensible Interface) bus, and then after being processed by the AXI port of the DDR (Double Data Rate) controller, the data is controlled by the DDR controller, and then transmitted to the DDR memory or read from the DDR memory through the DDR PHY interface.

[0003] However, after the design is transplanted to multiple FPGAs and split into multiple FPGAs, the system operating rate will be reduced to several MHz or even lower. Directly accessing the DDR memory through the AXI bus and loading data and instructions into the main memory DDR to boot the system will consume a lot of verification time, thereby reducing the efficiency of chip verification. Summary of the invention

[0004] In order to help solve the problem that directly accessing DDR memory through the AXI bus and loading data and instructions into the main memory DDR to boot the system will consume a lot of verification time, thereby reducing the efficiency of chip verification, the present application provides a DDR access method, device, equipment and storage medium.

[0005] In a first aspect, the present application provides a DDR access method, which adopts the following technical solution: the method is applied to a DDR access system, the DDR access system includes a RISC-V processor, and the method includes: Get JTAG access IP core, XDMA access IP core, DDR memory IP core and bus IP core; Connecting the JTAG access IP core, the XDMA access IP core, the DDR memory IP core, and the bus IP core to generate a block design; Instantiate the block design in the RISC-V processor and generate an overall design; The overall design is ported to FPGA.

[0006] In a specific implementation scheme, the RISC-V processor includes a processor master interface, the block design includes a block design slave interface, and the instantiation of the block design in the RISC-V processor includes: The processor master interface is connected to the block design slave interface to implement the instantiation of the block design in the RISC-V processor.

[0007] In a specific implementation scheme, the transplanting of the overall design to the FPGA includes: Performing comprehensive processing on the overall design and generating a netlist file; The netlist file is imported into FPGA.

[0008] In a specific implementation scheme, the number of FPGAs is several, and importing the netlist file into the FPGA includes: The netlist file is divided according to the capacity of the FPGA, and a plurality of subnetlist files are generated; Performing layout and routing processing on the plurality of subnet table files to generate a plurality of bit files; The plurality of bit files are imported into the plurality of FPGAs, wherein one bit file is imported into one FPGA.

[0009] In a specific implementation scheme, after the overall design is transplanted to the FPGA, the method further includes: The execution information sent by the host computer is obtained, and the JTAG access path accesses the DDR or the XDMA access path accesses the DDR according to the execution information.

[0010] In a specific possible implementation scheme, the acquiring execution information sent by the host computer and implementing the JTAG access path to access the DDR or the XDMA access path to access the DDR according to the execution information includes: Get the JTAG operation instruction sent by the host computer and start the JTAG access path; A JTAG access instruction sent by a host computer is obtained, and access to the DDR through the JTAG access path is implemented according to the JTAG access instruction.

[0011] In a specific possible implementation scheme, the acquiring execution information sent by the host computer and implementing the JTAG access path to access the DDR or the XDMA access path to access the DDR according to the execution information includes: Obtain an XDMA driver file sent by a host computer, and load the driver file in the overall design, wherein the XDMA driver file includes a read data execution file and a write data execution file; The data read execution file and the data write execution file are used to access the DDR through the XDMA access path.

[0012] In a second aspect, the present application provides a DDR access device, which adopts the following technical solution: the device is applied to a DDR access system, the DDR access system includes a RISC-V processor, and the device includes: A data acquisition module is used to acquire the IP core accessed by JTAG, the IP core accessed by XDMA, the DDR memory IP core, and the bus IP core; A block design generation module, used for connecting the IP core accessed by JTAG, the IP core accessed by XDMA, the DDR memory IP core and the bus IP core to generate a block design; Design an instantiation module, used to instantiate the block design in the RISC-V processor and generate an overall design; The design transplantation module is used to transplant the overall design to FPGA.

[0013] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute any of the above-mentioned DDR access methods.

[0014] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute any of the above-mentioned DDR access methods.

[0015] In summary, this application has the following beneficial technical effects: By adding IP cores for JTAG and XDMA access, additional ways of accessing DDR memory are added, thereby adding two paths for quickly reading and writing DDR data. In addition, the use of multiple FPGA processing can not only effectively solve the problem of insufficient resources in the RISC-V processor verification process, but also quickly and accurately load data and instructions into the main memory, while solving the two major bottleneck problems in the RISC-V processor verification process mentioned above. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1is a flow chart of the method in the embodiment of the present application; Figure 2 It is a schematic diagram of the overall design of the embodiment of the present application; Figure 3 is a schematic diagram of a device in an embodiment of the present application; Figure 4 It is a schematic diagram used to embody a computer device in an embodiment of the present application.

[0017] Reference numerals: 301, data acquisition module; 302, block design generation module; 303, design instantiation module; 304, design migration module. DETAILED DESCRIPTION

[0018] The following combination Figure 1-Figure 4 This application is described in further detail.

[0019] The embodiment of the present application discloses a DDR access method, which can support access and control of FPGA internal resources through a JTAG interface or an XDMA interface, and can perform data interaction with a main memory DDR.

[0020] As the development and application scale of open source SoC based on RISC-V core continues to grow, simulation verification investment occupies more and more R&D costs and development time. FPGA prototype verification has become a mainstream and mature verification method, playing a key role in accelerating design verification and shifting chip development left. Limited by the single-chip capacity of mainstream FPGAs in the market, prototype verification systems based on multiple FPGAs have become the mainstream demand in the field of cutting-edge design verification. In the scenario of prototyping open source SoC based on RISC-V core, the commonly used method is that the RISC-V processor core needs to send / receive data through the AXI bus, and then after being processed by the AXI port of the DDR controller, the data is controlled by the DDR controller, and then transmitted to the DDR memory or read from the DDR memory through the DDR PHY interface.

[0021] However, due to the transplantation to multiple FPGAs, after the design is divided into multiple FPGAs, the system operating rate will be down-clocked to several megahertz or even lower. Directly accessing the DDR memory through the AXI bus, loading data and instructions into the main memory DDR to boot the system will consume a lot of verification time, thereby reducing the efficiency of chip verification. In addition, the software may not be fully developed during the verification phase, and the software configuration cannot be used for debugging. Therefore, a method is needed that can be used in multi-chip FPGA prototype verification without relying on software configuration and can quickly start the system from the main memory DDR. In order to help improve DDR access efficiency. The present application provides a DDR access method.

[0022] Reference Figure 1, the method comprises the following steps: S10, obtaining the IP core accessed by JTAG, the IP core accessed by XDMA, the DDR memory IP core, and the bus IP core.

[0023] Specifically, obtain the IP core for JTAG access, the IP core for XDMA access, the DDR memory IP core, and the bus IP core. The IP core (Intellectual Property Core) can be understood as a module with specific functions that can be used directly. In the existing method of accessing DDR, the DDR memory can only be directly accessed through the RISC-V processor. However, the direct access method will result in a decrease in speed after the design is divided into multiple FPGAs. Therefore, by adding JTAG access and XDMA access methods, a multi-path access method is provided to increase the access rate. The DDR memory core bus IP core is used to set the DDR memory core bus. For the newly added JTAG access method and XDMA access method, the JTAG access IP core and the XDMA access IP core are added to the system to implement the access methods of the two newly added path paths.

[0024] In the embodiment of the present application, the IP core used for JTAG access is JTAG to AXI, which is a powerful IP core provided by Xilinx. It converts the JTAG interface into an AXI interface, realizes the interaction between the JTAG interface and the internal resources of the FPGA, and connects the interface of the IP core to the main memory DDR through the AXI4 bus to realize read and write access to the DDR memory. The IP core used in the XDMA access path is PCIE XDMA0, which is a high-performance, configurable SG mode DMA for PCIE2.0 and PCIE3.0 provided by Xilinx, providing a user-selectable AXI4-full interface or AXI4-Lite interface. In the embodiment of the present application, the AXI4-full interface is used to connect to the main memory DDR through the AXI4 bus to realize read and write access to the DDR.

[0025] S20, connecting the IP core for JTAG access, the IP core for XDMA access, the DDR memory IP core, and the bus IP core to generate a block design.

[0026] Specifically, the IP cores are connected to generate a block design to implement two read and write access methods to the main memory DDR: JTAG to AXI and XDMA.

[0027] S30, instantiate the block design in the RISC-V processor and generate an overall design.

[0028] Specifically, the block design is instantiated into the RISC-V processor to access and control the internal resources of the FPGA and to implement data interaction with the main memory DDR. The design of instantiating the block design into the RISC-V processor is an overall design.

[0029] The RISC-V processor includes a processor master interface, and the block design includes a block design slave interface. The specific instantiation method is to connect the processor master interface with the block design slave interface to realize the instantiation of the block design in the RISC-V processor.

[0030] S40, migrate the entire design to FPGA.

[0031] Specifically, the ultimate goal of transplanting the overall design into FPGA and improving the DDR access efficiency is to improve the efficiency of chip prototype verification, which requires the use of FPGA to implement chip prototype verification operations. In the open source SoC chip based on the RISC-V core, RISC-V is the core part of the chip, and the verification of the RISC-V processor is an important part of chip verification. The RISC-V processor with instantiation of JTAG access and XDMA access is transplanted into the FPGA to access and control the internal resources of the FPGA and interact with the main memory DDR for data.

[0032] When the overall design is ported to FPGA, the originally generated overall design cannot run in the FPGA environment. Therefore, the originally generated overall design needs to be processed before porting. Specifically, the overall design is first synthesized and a netlist file is generated. After that, the netlist file is imported into the FPGA. The process of importing the netlist file into the FPGA is the process of porting the overall design to the FPGA.

[0033] In addition, considering that the logic capacity of a single mainstream FPGA in the market is difficult to support a fast and efficient complete verification work, multiple FPGAs are usually used to achieve fast and efficient verification work. When the overall design is transplanted into multiple FPGAs, the overall design also needs to be split. Specifically, after the overall design is synthesized and the netlist file is generated, the netlist file is split according to the capacity of the FPGA and several subnetlist files are generated; the several subnetlist files are placed and routed to generate several bit files; the several bit files are imported into several FPGAs, where one FPGA imports one bit file.

[0034] Reference Figure 2, which is a schematic diagram of the overall design framework in the embodiment of the present application. In the current existing solutions, the DDR memory can only be accessed through the RISC-V processor itself. In the embodiment of the present application, two IP cores, JTAG toAXI and PCIE XDMA0, are added, so that the internal resources of the FPGA can be accessed and controlled through the JTAG interface or PCIE interface, and data can be exchanged with the main memory DDR. After completing the overall design and instantiation processing, the existing integrated compilation software hsPtCompiler is used for segmentation processing, and it is divided into four FPGAs for on-board testing.

[0035] In the present application, by adding IP cores for JTAG and XDMA access, additional ways of accessing DDR memory are added, thereby adding two paths for quickly reading and writing DDR data; in addition, the use of multiple FPGA processing can not only effectively solve the problem of insufficient resources in the RISC-V processor verification process, but also quickly and accurately load data and instructions into the main memory, while solving the two major bottleneck problems in the above-mentioned RISC-V processor verification process.

[0036] In one embodiment, considering that it is difficult for the path design in the hardware design to actively perform read and write operations, it is necessary to perform corresponding operations according to the execution information of the host computer. Therefore, after the overall design is transplanted to the FPGA, the following steps can also be performed: Obtain the execution information sent by the host computer, and implement the JTAG access path to access the DDR or the XDMA access path to access the DDR according to the execution information.

[0037] Specifically, for JTAG access path to access DDR, obtain the JTAG run instruction sent by the host computer, and start the JTAG access path; obtain the JTAG access instruction sent by the host computer, the JTAG path reads and writes data mainly through the Xilinx JTAGto AXI IP core, and when reading and writing data, generates AXI transfer transactions and drives the AXI interface. The data bit width can be configured to 32 bits or 64 bits. In the embodiment of the present application, the JTAG path mainly uses TCL commands to communicate with the JTAG to AXI core, and uses the create_hw_axi_txn command and the run_hw_axi command to create and run AXI read and write transfer transactions respectively; therefore, before using the JTAG path to load data, it is necessary to first generate the corresponding TCL script file on the host computer, and the generated TCL script contains the run instructions of the JTAG path. Afterwards, access to DDR is achieved through the JTAG access path according to the JTAG access instruction; specifically, after the bit file is imported into the FPGA, that is, after the bit file is burned into the FPGA, the FPGA and the host are connected via a USB cable, the project is started on the software side, and the device is connected; after the connection is successful, the TCL script file can be executed to complete the reading and writing of the main memory DDR through the JTAG path.

[0038] For XDMA access channel to access DDR, obtain the XDMA driver file sent by the host computer, and load the driver file in the overall design. The XDMA driver file includes a read data execution file and a write data execution file; XDMA channel reads and writes data mainly through the Xilinx XDMA IP core, and the use of this IP core requires compiling and loading the XDMA driver. First download and compile the XDMA driver, generate the driver module file locally, then compile and test the relevant test program, and the test program compilation is completed if the test passes. After the driver and application are compiled, load the driver. Before the driver is loaded, if it is detected that the system has already loaded the driver, the loaded driver will be unloaded and then loaded. The driver file contains the read data and write data execution files. After the driver is loaded, the read data execution file and the write data execution file are used to access DDR through the XDMA access channel; specifically, the host computer of the DMA channel provided in the driver writes data to the executable file dma_to_device of the board, and the board writes data to the executable file dma_from_device of the host computer to complete the XDMA channel to read and write the main memory DDR.

[0039] In the present application, the execution instructions or driver files output by the host computer are used to implement access to the DDR memory through the XDMA and JTAG paths, thereby achieving fast data read and write operations, improving the access efficiency of the DDR, and further improving the efficiency of chip verification.

[0040] Figure 1 FIG. 1 is a flow chart of a DDR access method in one embodiment. It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows; unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders; and Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0041] Based on the above method, an embodiment of the present application also discloses a DDR access device.

[0042] Reference Figure 3 , the device includes the following modules: The data acquisition module 301 is used to acquire the IP core accessed by JTAG, the IP core accessed by XDMA, the DDR memory IP core and the bus IP core; The block design generation module 302 is used to connect the IP core accessed by JTAG, the IP core accessed by XDMA, the DDR memory IP core and the bus IP core to generate a block design; A design instantiation module 303 is used to instantiate the block design in the RISC-V processor and generate an overall design; The design migration module 304 is used to migrate the entire design to the FPGA.

[0043] In one embodiment, the design instantiation module 303 is specifically used to connect the processor master interface with the block design slave interface to implement the instantiation of the block design in the RISC-V processor.

[0044] In one embodiment, the design migration module 304 is specifically used to perform synthesis processing on the overall design and generate a netlist file; and import the netlist file into the FPGA.

[0045] In one embodiment, the design transplantation module 304 is specifically used to divide the netlist file according to the capacity of the FPGA and generate a number of subnetlist files; perform layout and routing processing on the several subnetlist files to generate a number of bit files; and import the several bit files into a number of FPGAs, wherein one FPGA imports one bit file.

[0046] In one embodiment, the design transplantation module 304 is further used to obtain execution information sent by the host computer, and implement the JTAG access path to access the DDR or the XDMA access path to access the DDR according to the execution information.

[0047] In one embodiment, the design transplantation module 304 is also used to obtain the JTAG operation instruction sent by the host computer and start the JTAG access path; obtain the JTAG access instruction sent by the host computer, and access the DDR through the JTAG access path according to the JTAG access instruction.

[0048] In one embodiment, the design transplantation module 304 is also used to obtain the XDMA driver file sent by the host computer and load the driver file in the overall design. The XDMA driver file includes a read data execution file and a write data execution file; the read data execution file and the write data execution file are used to access the DDR through the XDMA access path.

[0049] The DDR access device provided in the embodiment of the present application can be applied to the DDR access method provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0050] It should be noted that: the DDR access device provided in the embodiment of the present application only uses the division of the above-mentioned functional modules / functional units as an example when performing DDR access. In actual applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the DDR access device is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the DDR access method provided in the above method embodiment and the implementation method of the DDR access device provided in this embodiment belong to the same concept. The specific implementation process of the DDR access device provided in this embodiment is detailed in the above method embodiment, which will not be repeated here.

[0051] The embodiment of the present application also discloses a computer device.

[0052] Specifically, if Figure 4As shown, the computer device can be a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. The processor and the memory may be connected via a bus or other means. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above chips.

[0053] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0054] The embodiment of the present application also discloses a computer-readable storage medium.

[0055] Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application is a program that can be completed by instructing the relevant hardware through a computer program, which can be stored in a computer-readable storage medium. When the program is executed, it may include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0056] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A DDR access method, characterized in that: The method is applied to a DDR access system, the DDR access system includes a RISC-V processor, and the method includes: Get JTAG access IP core, XDMA access IP core, DDR memory IP core and bus IP core; Connecting the JTAG access IP core, the XDMA access IP core, the DDR memory IP core, and the bus IP core to generate a block design; Instantiate the block design in the RISC-V processor and generate an overall design; The overall design is ported to FPGA.

2. The method according to claim 1, characterized in that: The RISC-V processor includes a processor master interface, the block design includes a block design slave interface, and instantiating the block design in the RISC-V processor includes: The processor master interface is connected to the block design slave interface to implement the instantiation of the block design in the RISC-V processor.

3. The method according to claim 1, characterized in that: The step of transplanting the overall design to FPGA includes: Performing comprehensive processing on the overall design and generating a netlist file; The netlist file is imported into FPGA.

4. The method according to claim 3, characterized in that: The number of FPGAs is several, and the step of importing the netlist file into the FPGA comprises: The netlist file is divided according to the capacity of the FPGA, and a plurality of subnetlist files are generated; Performing layout and routing processing on the plurality of subnet table files to generate a plurality of bit files; The plurality of bit files are imported into the plurality of FPGAs, wherein one bit file is imported into one FPGA.

5. The method according to claim 1, characterized in that: After the overall design is transplanted to the FPGA, the method further includes: The execution information sent by the host computer is obtained, and the JTAG access path accesses the DDR or the XDMA access path accesses the DDR according to the execution information.

6. The method according to claim 5, characterized in that: The acquiring of the execution information sent by the host computer and implementing the JTAG access path to access the DDR or the XDMA access path to access the DDR according to the execution information comprises: Get the JTAG operation instruction sent by the host computer and start the JTAG access path; A JTAG access instruction sent by a host computer is obtained, and access to the DDR through the JTAG access path is implemented according to the JTAG access instruction.

7. The method according to claim 5, characterized in that: The acquiring of the execution information sent by the host computer and implementing the JTAG access path to access the DDR or the XDMA access path to access the DDR according to the execution information comprises: Obtain an XDMA driver file sent by a host computer, and load the driver file in the overall design, wherein the XDMA driver file includes a read data execution file and a write data execution file; The read data execution file and the write data execution file are used to access the DDR through the XDMA access path.

8. A DDR access device, characterized in that: The device is applied to a DDR access system, the DDR access system includes a RISC-V processor, and the device includes: A data acquisition module (301) is used to acquire an IP core for JTAG access, an IP core for XDMA access, a DDR memory IP core, and a bus IP core; A block design generation module (302) is used to connect the JTAG access IP core, the XDMA access IP core, the DDR memory IP core and the bus IP core to generate a block design; A design instantiation module (303) is used to instantiate the block design in the RISC-V processor and generate an overall design; The design transplantation module (304) is used to transplant the overall design to the FPGA.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.

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