A secure bus architecture for multi-core chiplet chip systems

Abstract

The application belongs to the security field in a multi-core system chip, and discloses a security bus architecture for a multi-core Chiplet chip system, which comprises five parts of an active interposer, a function chip, a storage chip, a Core chip and a security chiplet, the Core chip contains CPU cores of the chip system, the storage chip contains a memory for storing data and codes, the function chip contains most peripherals and function IPs, the active interposer is used for connecting all the chiplets and realizing access control of the chiplets, and the security chiplet is used for controlling and managing the security configuration of the whole chip system. When the chiplet provided by a supplier cannot be trusted, the security bus architecture can realize isolation and access limitation of the non-security chiplet. The bus architecture is realized in the security active interposer, and a security chiplet is used for configuring the access permission of each chiplet in the chip system, so that the data access of the remaining chiplets can be controlled, and the system security is enhanced.

Description

Technical Field

[0001] This invention belongs to the field of security in multi-core system chips, and particularly relates to a security bus architecture for multi-core chiplet chip systems. Background Technology

[0002] As chip performance and functionality continue to improve, chip design and manufacturing face increasing challenges, particularly in areas such as power consumption, thermal management, manufacturing costs, and design complexity. Chiplet is a design concept that integrates multiple small chips into a chip system. Its advantage lies in its ability to combine chips with different functions or manufacturing processes, providing flexibility and scalability, and it is expected to improve manufacturing yield and reduce design and manufacturing costs.

[0003] However, the flexibility and scalability of chiplet systems also bring new security challenges. If the purchased chiplets contain security vulnerabilities, the entire chip system may malfunction. Currently, researchers have proposed a chip bus architecture for 2.5D integration. Specifically, it implements a secure bus and a secure CPU within an active interposer layer. The secure CPU is responsible for configuring the security policy of the entire chip system, and the secure bus controls memory access. However, this secure bus architecture has two significant problems. First, considering cost, this architecture requires implementing the secure bus, secure CPU, and register set for configuring security policies within the active interposer layer, consuming substantial resources and potentially significantly reducing the manufacturing yield of the active interposer layer, thus increasing the cost of the chip system. This secure bus architecture also has security vulnerabilities. Since the security of the chiplet containing the memory cannot be guaranteed, these factors indirectly affect the credibility of the security policies configured by the secure CPU. Although the secure CPU in the interposer layer has no security issues during the bus access phase, the code and data obtained from accessing memory may not be trustworthy, and attackers may exploit this to attack the entire chip system. Furthermore, the bus clock reset signal also has security vulnerabilities, requiring a dedicated security chiplet to address these issues. Summary of the Invention

[0004] This invention proposes a secure bus architecture for multi-core chiplet chip systems, addressing the following technical problem: when vendor-supplied chiplets cannot be trusted, this secure bus architecture can isolate and restrict access to insecure chiplets. Implementing the bus architecture in a secure active intermediary layer, and having a single secure chiplet configure the access permissions of each chiplet in the chip system, ensures that data access to other chiplets is controlled, enhancing system security while maintaining flexibility.

[0005] To address the aforementioned technical problems, the present invention provides a specific technical solution for a secure bus architecture for multi-core Chiplet chip systems as follows:

[0006] A secure bus architecture for multi-core chiplet chip systems comprises five parts: an active intermediary layer, functional chips, memory chips, a core chip, and a security chiplet. The core chip contains the CPU core of the chip system; the memory chip contains memory for storing data and code; the functional chips contain most peripherals and functional IPs; the active intermediary layer is used to connect all the chiplets and implement access control for each chiplet; and the security chiplet is used to manage the security configuration of the overall chip system.

[0007] Furthermore, the components in the active intermediary layer include: a data transmission bus, a bus access controller, and a special signal controller. The data transmission bus is the means of data communication for the entire chip system. Each host interface of the data transmission bus is equipped with a bus access controller, which records the security control policies for different address segments and restricts data transmission according to the security control policies. The special signal controller records the security attributes of different chips and compares the security attributes of the special signal input and output chips. Only when the security attributes of the two match can communication be allowed.

[0008] Furthermore, the data transmission bus adopts the AHB bus.

[0009] Furthermore, the bus access controller includes two modules: a transmission controller and a control policy register group. The control policy register group stores all control policies for the bus interface. Each control policy includes an address range and the read / write permissions for that address range. The control policy register group can only be modified by the CPU in the security chip. The transmission controller is responsible for restricting bus access operations based on the control information provided by the control policy register group.

[0010] Furthermore, whenever the bus host interface initiates a transmission, the transmission controller compares the transmission address and operation type with the policy in the control policy register group. If the comparison result indicates a legitimate access, the access request is transmitted to the data bus in the active intermediary layer. If the comparison result indicates an illegitimate access, the access request is blocked, the transmission cannot reach the data bus in the active intermediary layer, and an alarm signal is output to inform the CPU in the security chip.

[0011] Furthermore, the special signal controller includes two modules: a connectivity controller and a security attribute configurator. The security attribute configurator stores the security attributes of each chip and can only be configured through a secure CPU. The connectivity controller compares the security attributes of the input and output chips of the special signal by searching for relevant configurations in the security attribute configurator, and controls the connectivity of the special signal. If the security attributes of the input and output chips are consistent, the connectivity controller directly connects the input signal to the output port. If the security attributes do not match, the output port will be clamped to 0, blocking the signal connection.

[0012] Furthermore, the security chip controls the secure startup of the entire chip system and the configuration of security policies. Therefore, the security chip integrates a security CPU and a configuration bus. The configuration bus provides a series of configuration interfaces, which are connected to the bus access controller and special signal controller in the active intermediary layer. The security CPU accesses and modifies the register groups in these controllers.

[0013] Furthermore, the bus in the active intermediary layer requires a clock and a reset signal, and the clock control unit and reset control unit are implemented in the security chip.

[0014] The secure bus architecture for multi-core Chiplet chip systems proposed in this invention has the following advantages:

[0015] 1. Implement the bus and controller only in the active interposer layer to reduce the impact on interposer layer yield; 2. Include a controller for bus access and generate warning signals for illegal access; 3. Include a controller for special signals and generate warning signals for illegal access; 4. Simplify the control strategy for special signals, only needing to judge based on the security attributes of the two end chips, thereby reducing register overhead; 5. Place the clock and reset control unit in the security chip to prevent targeted malicious attacks; 6. Provide the security CPU with an independent configuration bus to prevent the security policy configuration from occupying bus resources; 7. Provide the security CPU with an independent memory to prevent the chip where the memory is located from being maliciously attacked; 8. Implement the bus access controller at the interface of the bus host to prevent malicious hosts from occupying the bus. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the effect of applying a security solution to a Childet chip system.

[0017] Figure 2 This is an internal structure diagram of the bus access controller.

[0018] Figure 3This is a diagram of the internal structure of a special signal controller.

[0019] Figure 4 This is a diagram of the internal structure of a security chip. Detailed Implementation

[0020] To better understand the purpose, structure, and function of this invention, a secure bus architecture for multi-core Chiplet chip systems will be described in further detail below with reference to the accompanying drawings.

[0021] Appendix Figure 1 This is a schematic diagram illustrating the effect of applying a security solution to a Childet chip system.

[0022] This invention discloses a secure bus architecture for multi-core chip systems, comprising five parts: an active interposer layer, functional chips, memory chips, a core chip, and a security chiplet. The core chip contains the CPU core of the chip system and can be manufactured using advanced process technology to meet performance requirements; the memory chip contains memory for storing data and code; the functional chips contain most peripherals and functional IPs; the active interposer layer connects all the chiplets and implements access control for each chiplet; and the security chiplet manages the overall security configuration of the chip system.

[0023] The components in the active interposer layer include: 1. a data transmission bus; 2. a bus access controller; and 3. a special signal controller. The data transmission bus can use an AHB bus as the means of data communication for the entire chip system. Each host interface on the data transmission bus needs to be equipped with a bus access controller, which records the security control policies for different address ranges and restricts data transmission according to these policies. The special signal controller records the security attributes of different chips and compares the security attributes of the special signal input and output chips; only when the security attributes match is communication allowed.

[0024] Appendix Figure 2 This is an internal structure diagram of the bus access controller.

[0025] The bus access controller comprises two modules: a transmission controller and a control policy register set. The control policy register set stores all control policies for the bus interface. Each control policy includes an address range and its read / write permissions. To ensure the control policies cannot be arbitrarily changed, the control policy register set is designed to be modifiable only by the CPU within the security chip. The transmission controller is responsible for restricting bus access operations based on the control information provided by the control policy register set.

[0026] Whenever the host interface of the bus initiates a transmission, the transmission controller compares the transmission address and operation type with the policy in the control policy register group. If the comparison result indicates a legitimate access, the access request is transmitted to the data bus in the active intermediary layer. If the comparison result indicates an illegitimate access, the access request is blocked, the transmission cannot reach the data bus in the active intermediary layer, and an alarm signal is output to notify the CPU in the security chip.

[0027] Appendix Figure 3 This is a diagram of the internal structure of a special signal controller.

[0028] Similar to the bus access controller, the special signal controller comprises two modules: a connectivity controller and a security attribute configurator. The security attribute configurator stores the security attributes of each chip and can only be configured via the secure CPU. The connectivity controller checks the relevant configuration in the security attribute configurator, compares the security attributes of the input and output chips of the special signal, and controls the connectivity of the special signal. If the security attributes of the input and output chips match, the connectivity controller directly connects the input signal to the output port; if the security attributes do not match, the output port is clamped to 0, blocking the signal connection.

[0029] Appendix Figure 4 This is a diagram of the internal structure of a security chip.

[0030] The security chip needs to control the secure boot and security policy configuration of the entire chip system. Therefore, it requires the integration of a security CPU and a configuration bus. The security CPU has minimal performance requirements, so a CPU with low area and power consumption can be used. The configuration bus provides a series of configuration interfaces, connecting to the bus access controller and special signal controller in the active interposer layer, facilitating access and modification of the register sets in these controllers by the security CPU. Furthermore, the bus in the active interposer layer requires clock and reset signals; to ensure data access security, a clock control unit and a reset control unit need to be implemented within the security chip.

[0031] In the chiplet system security solution proposed in this invention, the bus needs to be implemented on an active intermediary layer, and the configuration of security policies within the bus requires an additional security chiplet. All chipslets are integrated on the active intermediary layer, and all signal transmissions pass through it. Therefore, the security of the active intermediary layer is crucial, requiring the chip supplier to design it and a trusted foundry to manufacture it. Similarly, since the overall security policy is controlled by the security chiplet, the manufacturing of the security chiplet and its connection to the intermediary layer also require close attention. The security solution proposed in this invention implements the following functions on the active intermediary layer: 1. Bus and bus access controller; 2. Special signal controller. Each chiplet can be mounted on the bus of the active intermediary layer through one or more bus interfaces. Each chiplet's bus interface is subject to access restrictions by the bus access controller, while other signals transmitted in the active intermediary layer are monitored by a special signal controller. The bus access controller contains configurable access policies corresponding to each bus host interface. The access policy defines the address range accessible by the bus host interface and the read / write permissions for data within that range. This is stored in a series of registers. All access policy registers can only be modified by the CPU within the security chip; malicious modifications will trigger an interrupt. Besides bus signals, some special signals are transmitted through the active intermediary layer, such as interrupt indication signals and event reception and output signals. For these signals, a special signal controller is designed in the active intermediary layer to manage them based on the security attributes of the signal sender and receiver. The security attributes of each sender and receiver are defined by the registers in the special signal controller and can also only be modified by the secure CPU core within the security chip; malicious modifications will trigger an interrupt. In addition to the CPU used to configure the security policy, the security chip also needs to include memory accessible only by this CPU, secure boot components such as a boot ROM, and bus clock and reset control components.

[0032] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A secure bus architecture for multi-core Chiplet chip systems, characterized in that, The system comprises five parts: an active interposer layer, functional chips, memory chips, a core chip, and a security chip. The core chip contains the CPU core of the chip system; the memory chip contains memory for storing data and code; the functional chips contain most peripherals and functional IPs; the active interposer layer connects all the chips and implements access control for each chip; the security chip manages the overall security configuration of the chip system. Components in the active interposer layer include: a data transmission bus, a bus access controller, and a special signal controller. The data transmission bus is the means of data communication for the entire chip system. Each host interface of the data transmission bus is equipped with a bus access controller, which records security control policies for different address ranges and restricts data transmission according to these policies. The special signal controller records the security attributes of different chips and compares the security attributes of the input and output chips for special signals; only when the security attributes match is communication allowed. The bus access controller includes two modules: a transmission controller and a control policy register group. The control policy register group stores all control policies for the bus interface. Each control policy includes an address range and its read / write permissions. The control policy register group can only be modified by the CPU in the security chip. The transmission controller is responsible for restricting bus access operations based on the control information provided by the control policy register group. Whenever the bus host interface initiates a transmission, the transmission controller compares the transmission address and operation type with the policy in the control policy register group. If the comparison result indicates a legitimate access, the access request is transmitted to the data bus in the active intermediary layer. If the comparison result indicates an illegitimate access, the access request is blocked, the transmission cannot reach the data bus in the active intermediary layer, and an alarm signal is output to notify the CPU in the security chip. The special signal controller comprises two modules: a connectivity controller and a security attribute configurator. The security attribute configurator stores the security attributes of each chip and can only be configured via a secure CPU. The connectivity controller compares the security attributes of the input and output chips of the special signal by searching for relevant configurations in the security attribute configurator, and controls the connectivity of the special signal. If the security attributes of the input and output chips are consistent, the connectivity controller directly connects the input signal to the output port. If the security attributes do not match, the output port is clamped to 0, blocking the signal connection.The security chip controls the secure boot and security policy configuration of the entire chip system. Therefore, the security chip integrates a security CPU and a configuration bus. The configuration bus provides a series of configuration interfaces connecting to the bus access controller and special signal controller in the active intermediary layer. The security CPU accesses and modifies the register sets in these controllers.

2. The secure bus architecture for multi-core Chiplet chip systems according to claim 1, characterized in that, The data transmission bus uses the AHB bus.

3. The secure bus architecture for multi-core Chiplet chip systems according to claim 1, characterized in that, The bus in the active interposer layer requires a clock and a reset signal, and the clock control unit and reset control unit are implemented in the security chip.

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