Implementation method of reading and writing arbitrary byte length of RapidIO memory

Abstract

The application provides an implementation method of reading and writing any byte length of RapidIO memory, comprising the following steps: the communication node and the FPGA node are interconnected with the RapidIO exchange chip through the RapidIO bus; the FPGA node realizes the reading and writing of any byte length of RapidIO memory by unpacking and padding the length field of the memory write sending or the memory read sending input by the user logic. In the application, the FPGA node unpacks and pads the length field of the memory write sending or the memory read sending input by the user logic, on the one hand, for the memory write sending, the actual application data length is sent out after the data is completely sent, thereby solving the problem of the memory write of any byte length. On the other hand, for the memory read sending, the data received by the memory read response is discarded according to the length of the data to be read input by the user logic, thereby solving the problem of the memory read of any byte length.

Description

Technical Field

[0001] The present invention relates to the field of integrated electronic information systems, and in particular to a method for realizing RapidIO memory reading and writing arbitrary byte lengths. Background Art

[0002] FPGA chips are programmable, highly flexible, have short development cycles, and have strong parallel processing capabilities, and are increasingly being used in integrated electronic information system hardware platforms.

[0003] As a bus interconnection standard in the embedded field, RapidIO bus is increasingly used for high-speed interconnection between chips and modules due to its high bandwidth, low latency, and high reliability. It is connected to the RapidIO switching network through RapidIO switching chips.

[0004] In FPGA nodes, RapidIO data transmission and reception is implemented by calling the RapidIO IP Core. For applications requiring large amounts of data and high bandwidth, memory reads and writes are implemented. Calling the RapidIO IP Core is generally based on the HELLOFormat protocol. The length range (in bytes) for memory reads and writes using the HELLOFormat protocol is 8, 16, 32, 64, 96 (memory reads only), 128, 192 (memory reads only), 224 (memory reads only), and 256 for a single RapidIO data packet. As can be seen, the length range of a single RapidIO memory read and write data packet is limited and is always aligned to 8 bytes. In practice, requiring 8-byte alignment across all nodes is difficult to achieve. Summary of the Invention

[0005] The present invention aims to provide a method for realizing the reading and writing of arbitrary byte lengths in RapidIO memory, thereby solving the problem that the RapidIO memory reading and writing mode in FPGA nodes cannot transmit arbitrary byte lengths without substantially increasing the system software cost.

[0006] The present invention provides a method for implementing RapidIO memory reading and writing arbitrary byte lengths, comprising:

[0007] Both the communication nodes and FPGA nodes are interconnected with the RapidIO switch chip via the RapidIO bus;

[0008] The FPGA node unpacks and pads the length field of the memory write or memory read input by the user logic to implement RapidIO memory read and write of arbitrary byte length.

[0009] In some embodiments, the FPGA node internally comprises a RapidIO IP core, a memory write sending Send_nwrite control module, a memory read sending Send_nread control module, a data sending Send_data control module, a memory read response receiving Recv_resp_nread control module, a memory write receiving Recv_nwrite control module, a memory read receiving Recv_nread control module, and a memory read response sending Send_resp_nread control module.

[0010] In some embodiments, the memory write sending Send_nwrite control module receives, on one hand, a memory write sending start signal, memory write sending data, memory write sending length, and memory write sending start address from a user input; and on the other hand, unpacks the input data according to the memory write sending length, splits the data into N integer data packets + 1 tail packet data packet, and performs a padding operation on the tail packet data packet; writes the data packet data after unpacking and padding into a data FIFO; and when the integer data packet and the tail packet data packet are written, writes the length of the split data packet into the low 32 bits of a length FIFO and writes the start address of the split data into the high 32 bits of the length FIFO.

[0011] In some embodiments, the memory read sending Send_nread control module receives, on one hand, a memory read sending start signal, memory read sending length, and memory read sending start address from a user input; and on the other hand, unpacks the input memory read sending length, splits the length into N integer data packets + 1 tail packet data packet, and performs a padding operation on the tail packet data packet; and writes each memory read sending length after unpacking and padding into the low 32 bits of a FIFO, and writes each memory read sending start address into the high 32 bits of the FIFO.

[0012] In some embodiments, the data sending Send_data control module receives, on one hand, a memory write data packet sending FIFO empty signal, memory write data packet sending data, memory write data packet sending, memory write data packet sending start address, and a memory write data packet sending tail packet indication signal from the memory write sending Send_nwrite control module; and on the other hand, receives a memory read data packet sending FIFO empty signal, memory read data packet sending, and memory read data packet sending start address from the memory read sending Send_nread control module; starts an internal sending process when either the memory write data packet sending FIFO empty signal or the memory read data packet sending FIFO empty signal is 0; generates a memory write sending RapidIO data packet or a memory read sending RapidIO data packet, and sends the data packet to a RapidIO switching network through the RapidIO IP core.

[0013] In some embodiments, the memory read receiving Recv_nread control module receives data from the RapidIO IP core input, extracts the memory read receiving length and memory read receiving address by parsing the RapidIO data packet, and then generates a memory read receiving start signal.

[0014] In some embodiments, the memory read response sending Send_resp_nread control module receives the memory read receiving start signal from the output of the memory read receiving Recv_nread control module, and sends the memory read response data from the user logic to the RapidIO switch network through the RapidIO IP core according to the memory read receiving length and memory read receiving address.

[0015] In some embodiments, the memory write sending Send_nwrite control module enters an initial state after power-on reset is completed, and then determines whether the user logic starts memory write. If the user logic starts memory write, it is determined whether the to-be-sent data length is greater than X bytes.

[0016] If the to-be-sent data length is greater than X bytes, X bytes of data are written into the data FIFO, then X is written into the low 32 bits and the to-be-sent data start address is written into the high 32 bits in the length FIFO, the to-be-sent data length and the to-be-sent data start address are updated, and then it is determined whether the to-be-sent data length is greater than X bytes, and the above process is repeated.

[0017] If the to-be-sent data length is not greater than X bytes, the to-be-sent data length is zero-padded according to 8-byte alignment, then the zero-padded data is written into the data FIFO, the zero-padded data length is written into the low 32 bits and the to-be-sent data start address is written into the high 32 bits in the length FIFO, and finally the initial state is returned.

[0018] In some embodiments, the memory read sending Send_nread control module enters an initial state after power-on reset is completed, and then determines whether the user logic starts memory read. If the user logic starts memory read, it is determined whether the to-be-read data length is greater than X bytes.

[0019] If the to-be-read data length is greater than X bytes, X is written into the low 32 bits and the to-be-read data start address is written into the high 32 bits in the FIFO, the to-be-read data length and the to-be-read data start address are updated, and then it is determined whether the to-be-read data length is greater than X bytes, and the above process is repeated.

[0020] If the length of the data to be read is not greater than X bytes, the length of the data to be read X bytes is aligned and zero-filled, then the aligned and zero-filled data length X is written into the FIFO in the low 32 bits, the start address of the data to be read is written into the FIFO in the high 32 bits, and then the initial state is returned.

[0021] In some embodiments, the data sending Send_data control module enters the initial state after power-on reset is completed, and then determines whether the memory read data packet sending FIFO empty signal is 0:

[0022] If the memory read data packet sending FIFO empty signal is 0, a memory read RapidIO data packet is generated, and then it is determined whether a memory read response is received. If the memory read response is received, the initial state is returned. Otherwise, it is determined whether the memory read response is timed out. If the memory read response is timed out, the initial state is returned.

[0023] If the memory read data packet sending FIFO empty signal is not 0, it is determined whether the memory write data packet sending FIFO empty signal is 0. If the memory write data packet sending FIFO empty signal is not 0, the initial state is returned. If the memory write data packet sending FIFO empty signal is 0, it is determined whether the memory write data packet sending tail packet indication identification signal is 0. If the memory write data packet sending tail packet indication identification signal is 0, a memory write length X byte RapidIO data packet is generated, and then the initial state is returned.

[0024] If the memory write data packet sending tail packet indication identification signal is not 0, it is determined whether the memory write data packet sending length is equal to X. If the memory write data packet sending length is equal to X, a memory write length X byte tail packet RapidIO data packet is generated, and then the memory write received data length is sent to the receiver in the memory write manner. A doorbell is sent to the receiver, and then it is determined whether a doorbell response is received. If the doorbell response is received, the initial state is returned. If the doorbell response is not received, it is determined whether the doorbell response is timed out. If the doorbell response is timed out, the initial state is returned.

[0025] If the memory write data packet sending length is not equal to X, the memory write data packet sending length is determined every time by half length until the shortest length is reached. A corresponding length of RapidIO data packet is generated every time, and then the length of the data to be sent is updated. The memory write received data length is sent to the receiver in the memory write manner, and a doorbell is sent to the receiver. Then it is determined whether a doorbell response is received. If the doorbell response is received, the initial state is returned. If the doorbell response is not received, it is determined whether the doorbell response is timed out. If the doorbell response is timed out, the initial state is returned.

[0026] In some embodiments, the memory read response receiving Recv_resp_nread control module enters an initial state after power-on reset is completed, then determines whether the received RapidIO data packet is a memory read response, if the received RapidIO data packet is a memory read response, writes the received memory read response RapidIO data packet into a Recv_resp_nread data FIFO, then determines whether the current memory read response RapidIO data packet is all written into the FIFO, if the current memory read response RapidIO data packet is all written into the FIFO, determines whether the data length written into the FIFO is greater than or equal to a memory read receiving sending length:

[0027] If the data length written into the FIFO is greater than or equal to the memory read receiving sending length, according to reading the FIFO, a data byte valid identification state is given, then determines whether the FIFO is read empty, if the FIFO is read empty, a receiving response data length count state is cleared, then returns to the initial state;

[0028] If the data length written into the FIFO is less than the memory read receiving sending length, returns to determine whether the received RapidIO data packet is a memory read response, and repeats the above process.

[0029] In some embodiments, the memory write receiving Recv_nwrite control module enters an initial state after power-on reset is completed, then determines whether the received RapidIO data packet is a memory write:

[0030] If the received RapidIO data packet is a memory write, determines whether the received RapidIO data packet is a length data packet, if the received RapidIO data packet is a length data packet, records an actual sending data length of a sending end, then reads the FIFO according to the actual sending data length, gives a data byte valid identification, then returns to the initial state;

[0031] If the received RapidIO data packet is not a memory write, writes the received data into the FIFO, then returns to determine whether the received RapidIO data packet is a memory write, and repeats the above process.

[0032] In some embodiments, the memory read receiving Recv_nread control module enters an initial state after power-on reset is completed, then determines whether the received RapidIO data packet is a memory read, if the received RapidIO data packet is a memory read, records a to-be-read address and a to-be-read length, then returns to the initial state.

[0033] In some embodiments, the memory read response sending Send_resp_nread control module enters an initial state after power-on reset is completed, then judges whether Recv_resp_start is valid, if Recv_resp_start is valid, generates a memory read response packet according to the address to be read and the length to be read, and then returns to the initial state.

[0034] In conclusion, due to the adoption of the above technical solutions, the present application has the following advantages:

[0035] In the present application, the FPGA node performs unpacking and padding operation on the length field of the memory write sending or memory read sending of the user logic input, on the one hand, for the memory write sending, after the data is completely sent, the actual application data length is sent out, solving the problem of memory write arbitrary byte length. On the other hand, for the memory read sending, according to the user logic input data length to be read, the data received by the memory read response is discarded, solving the problem of memory read arbitrary byte length. Moreover, the present application is simple in software implementation, and can realize the decoupling of the driver and the application. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a schematic diagram of the implementation method of the RapidIO memory read and write arbitrary byte length of the present application.

[0037] Figure 2 is Figure 1 the implementation principle diagram.

[0038] Figure 3 is Figure 2 the memory write sending Send_nwrite control module processing flow chart.

[0039] Figure 4 is Figure 2 the memory read sending Send_nread control module processing flow chart.

[0040] Figure 5 is Figure 2 the data sending Send_data control module processing flow chart.

[0041] Figure 6 is Figure 2 the memory read response receiving Recv_resp_nread control module processing flow chart.

[0042] Figure 7 is Figure 2 the memory write receiving Recv_nwrite control module processing flow chart.

[0043] Figure 8 is Figure 2Memory read receiving Recv_nread control module processing flow chart.

[0044] Figure 9 is Figure 2 Memory read response sending Send_resp_nread control module processing flow chart. DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0046] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0047] The present embodiment provides an implementation method of RapidIO memory read and write of any byte length, comprising:

[0048] The communication node and the FPGA node are interconnected with the RapidIO switch chip through the RapidIO bus;

[0049] The FPGA node realizes the RapidIO memory read and write of any byte length by unpacking and padding the length field of the memory write sending or memory read sending of the user logic input.

[0050] Referring to Figure 1 , a RapidIO switching network is configured, comprising a communication node, a RapidIO switch chip and an FPGA node; the communication node is interconnected with the RapidIO switch chip through the RapidIO bus; the FPGA node is interconnected with the RapidIO switch chip through the RapidIO bus;

[0051] In some embodiments, the communication node type can be any one of three different types of nodes, FPGA node, DSP node and PPC node;

[0052] In some embodiments, the FPGA node chip adopts Xilinx FPGA devices of K7, V7, Z7 and above models or corresponding domestic FPGA devices;

[0053] In some embodiments, the RapidIO switch chip uses an imported RapidIO switch device or a corresponding domestically produced RapidIO switch device.

[0054] See Figure 2 The FPGA node internally includes a RapidIO IP core, a memory write send Send_nwrite control module, a memory read send Send_nread control module, a data send Send_data control module, a memory read response receive Recv_resp_nread control module, a memory write receive Recv_nwrite control module, a memory read receive Recv_nread control module, and a memory read response send Send_resp_nread control module.

[0055] The overall operating principle is as follows: After system power-on initialization, the Send_nwrite and Send_nread control modules monitor user logic for memory write or read operations. They unpack and zero-pad the length field of the user logic input. The Send_data control module receives the FIFO empty flag signal from the Send_nwrite and Send_nread control modules, initiates the memory write or read operation, and sends the RapidIO data packet to the RapidIO switching network via the RapidIO IP core. The memory read response receiving Recv_resp_nread control module receives RapidIO data packets input from the RapidIO switching network, extracts the RapidIO data packets transmitted back by the memory read response, and writes them into the Recv_resp_nread data FIFO; based on the memory read send length User_send_nread_len, it reads the Recv_resp_nread data FIFO and outputs the memory read response receive data User_recv_resp_nread_data and the memory read response receive data byte valid signal User_recv_resp_nread_data_byte_valid to the user logic.

[0056] In the application, on one hand, the FPGA node unpacks and pads the data length of the memory write sent by the user logic input, and sends it out through the memory write mode, and after all the user application data is sent, the actual length of the application data is sent out through the memory write mode; the receiving end unpacks the memory write RapidIO data packet input from the RapidIO IP core, discards the received memory write redundant byte data according to the actual length of the application data, thereby solving the problem of memory write arbitrary byte length. On the other hand, the FPGA node unpacks and pads the data length of the memory read sent by the user logic input, and then sends the unpacked and padded data packet through the memory read mode, and the FPGA node unpacks the memory read response RapidIO data packet input through the RapidIO IP core, discards the received redundant byte memory read response received data according to the actual read data length recorded locally, thereby solving the problem of memory read arbitrary byte length.

[0057] Figure 2 In the application, the memory write sending Send_nwrite control module receives the memory write sending start signal User_send_nwrite_start, the memory write sending data User_send_nwrite_data, the memory write sending length User_send_nwrite_len and the memory write sending start address User_send_nwrite_addr input from the user on one hand; on the other hand, the input data is unpacked according to the memory write sending length User_send_nwrite_len, and is split into N 256-byte length integer data packets + 1 non-256-byte length tail packet data packet, and the tail packet data packet is padded according to the 8-byte alignment mode; the unpacked and padded data packet data is written into the Send_nwrite data FIFO; and when each 256-byte length integer data packet and the tail packet data packet is written, the length of the split data packet is written into the Send_nwrite length FIFO, and the start address of the split data is written into the high 32 bits.

[0058] Figure 2In the middle, the memory read sending Send_nread control module, on the one hand, receives the memory read sending start signal User_send_nread_start, the memory read sending length User_send_nread_len, the memory read sending start address User_send_nread_addr from the user input; on the other hand, the input memory read sending length User_send_nwrite_len is unpacked; Split into N 256 byte length integer data packets + 1 non-256 byte length tail packet data packet, the tail packet data packet is padded according to 256 bytes; and write each memory read sending length (256 bytes) after unpacking and padding to the low 32 bits of Send_nread FIFO, and write each memory read sending start address to Send_nread FIFO high 32 bits.

[0059] Figure 2 In the middle, the data sending Send_data control module, on the one hand, receives the memory write packet sending FIFO empty signal Send_nwrite_packet_empty, the memory write packet sending data Send_nwrite_packet_data, the memory write packet sending Send_nwrite_packet_len, the memory write packet sending start address Send_nwrite_packet_addr, and the memory write packet sending tail packet indication signal Send_nwrite_last_flag from the memory write sending Send_nwrite control module output; on the other hand, receives the memory read packet sending FIFO empty signal Send_nread_packet_empty, the memory read packet sending Send_nread_packet_len, and the memory read packet sending start address Send_nread_packet_addr from the memory read sending Send_nread module module output. When either the memory write packet sending FIFO empty signal Send_nwrite_packet_empty or the memory read packet sending FIFO empty signal Send_nread_packet_empty is 0, start the internal sending process; generate the memory write sending RapidIO packet or the memory read sending RapidIO packet, and send it to the RapidIO switching network through the RapidIO IP core.

[0060] Figure 2In the memory read response receiving module, the data RIO_IP_in input from the RapidIO IP core is received, the memory read response data is extracted by analyzing the RapidIO data packet, and the memory read response data is written into the Recv_resp_nread data FIFO. According to the memory read sending length User_send_nread_len, the memory read response receiving data User_recv_resp_nread_data and the memory read response receiving data byte valid signal User_recv_resp_nread_data_byte_valid are output to the user logic by reading the Recv_resp_nread data FIFO.

[0061] Figure 2 In the memory write receiving module, the data RIO_IP_in input from the RapidIO IP core is received, the memory write receiving data is extracted by analyzing the RapidIO data packet, and the memory write receiving data is written into the Recv_nwrite data FIFO. The extracted memory write receiving data length User_recv_nwrite_len and the memory write receiving data start address User_recv_nwrite_addr are output to the user logic. According to the memory write receiving data length User_recv_nwrite_len, the memory write receiving data User_recv_nwrite_data and the memory write receiving data byte valid signal User_recv_nwrite_data_byte_valid are output to the user logic by reading the Recv_nwrite data FIFO.

[0062] Figure 2 In the memory read receiving module, the data RIO_IP_in input from the RapidIO IP core is received, the memory read receiving length Recv_nread_len and the memory read receiving address Recv_nread_addr are extracted by analyzing the RapidIO data packet, and the memory read receiving start signal Recv_nread_start is generated.

[0063] Figure 2In the middle, the memory read response Send_resp_nread control module, receiving from the memory read receiving Recv_nread control module output memory read receiving start signal Recv_nread_start, and according to the memory read receiving length Recv_nread_len, memory read receiving address Recv_nread_addr, from the user logic memory read response data User_send_resp_nread_data through RapidIO IP core to RapidIO switch network.

[0064] Referring to Figure 3 , the memory write sending Send_nwrite control module enters the initial state after power-on reset, and then determines whether the user logic starts the memory write. If the user logic starts the memory write, it is determined whether the length of the data to be sent is greater than 256 bytes:

[0065] If the length of the data to be sent is greater than 256 bytes, 256 bytes of data are written to the Send_nwrite data FIFO, then 256 is written to the low 32 bits and the start address of the data to be sent is written to the high 32 bits in the Send_nwrite length FIFO, and then the length of the data to be sent and the start address of the data to be sent are updated. Then, it is determined whether the length of the data to be sent is greater than 256 bytes, and the above process is repeated.

[0066] If the length of the data to be sent is not greater than 256 bytes, the length of the data to be sent is aligned to 8 bytes and zero-filled, then the zero-filled data is written to the Send_nwrite data FIFO, and then the length of the zero-filled data is written to the low 32 bits and the start address of the data to be sent is written to the high 32 bits in the Send_nwrite length FIFO. Finally, return to the initial state.

[0067] Referring to Figure 4 , the memory read sending Send_nread control module enters the initial state after power-on reset, and then determines whether the user logic starts the memory read. If the user logic starts the memory read, it is determined whether the length of the data to be read is greater than 256 bytes:

[0068] If the length of the data to be read is greater than 256 bytes, 256 is written to the low 32 bits and the start address of the data to be read is written to the high 32 bits in the Send_nread FIFO, and then the length of the data to be read and the start address of the data to be read are updated. Then, it is determined whether the length of the data to be read is greater than 256 bytes, and the above process is repeated.

[0069] If the length of the data to be read is not greater than 256 bytes, the length of the data to be read is zero-padded to 256 bytes, then the zero-padded data length of 256 is written into the Send_nread FIFO, the low 32 bits are written into the zero-padded data length of 256, and the high 32 bits are written into the start address of the data to be read, and then the initial state is returned.

[0070] Referring to Figure 5 , the data sending Send_data control module enters the initial state after the power-on reset is completed, and then determines whether the memory read data packet sending FIFO empty signal Send_nread_packet_empty is 0:

[0071] If the memory read data packet sending FIFO empty signal Send_nread_packet_empty is 0, a memory read RapidIO data packet is generated, and then it is determined whether a memory read response is received. If the memory read response is received, the initial state is returned. Otherwise, it is determined whether the memory read response is timed out. If it is timed out, the initial state is returned.

[0072] If the memory read data packet sending FIFO empty signal Send_nread_packet_empty is not 0, it is determined whether the memory write data packet sending FIFO empty signal Send_nwrite_packet_empty is 0. If the memory write data packet sending FIFO empty signal Send_nwrite_packet_empty is not 0, the initial state is returned. If the memory write data packet sending FIFO empty signal Send_nwrite_packet_empty is 0, it is determined whether the memory write data packet sending tail packet indication identification signal Send_nwrite_last_flag is 0. If the memory write data packet sending tail packet indication identification signal Send_nwrite_last_flag is 0, a memory write length of 256 bytes RapidIO data packet is generated, and then the initial state is returned.

[0073] If the memory write data packet sending tail packet indication identification signal Send_nwrite_last_flag is not 0, it is determined whether the memory write data packet sending length Send_nwrite_packet_len is equal to 256. If the memory write data packet sending length Send_nwrite_packet_len is equal to 256, a memory write length of 256 bytes tail packet RapidIO data packet is generated, and then the memory write received data length User_send_nwrite_len is sent to the receiving party in the memory write manner, a doorbell is sent to the receiving party, and then it is determined whether a doorbell response is received. If the doorbell response is received, the initial state is returned. If the doorbell response is not received, it is determined whether the doorbell response is timed out. If it is timed out, the initial state is returned.

[0074] If the memory write packet sending length Send_nwrite_packet_len is not equal to 256, it is determined whether the memory write packet sending length Send_nwrite_packet_len is equal to 128. If the memory write packet sending length Send_nwrite_packet_len is equal to 128, a RapidIO data packet with a memory write length of 128 bytes is generated, and then the data length to be sent is updated. Then it is determined whether the data length to be sent is greater than or equal to 64. If the data length to be sent is greater than or equal to 64, a RapidIO data packet with a memory write length of 64 bytes is generated, and then the data length to be sent is updated. If the data length to be sent is less than 64, it is determined whether the data length to be sent is greater than or equal to 32. If the data length to be sent is greater than or equal to 32, a RapidIO data packet with a memory write length of 32 bytes is generated, and then the data length to be sent is updated. If the data length to be sent is less than 32, it is determined whether the data length to be sent is greater than or equal to 16. If the data length to be sent is greater than or equal to 16, a RapidIO data packet with a memory write length of 16 bytes is generated, and then the data length to be sent is updated. If the data length to be sent is less than 16, it is determined whether the data length to be sent is greater than or equal to 8. If the data length to be sent is greater than or equal to 8, a RapidIO data packet with a memory write length of 8 bytes is generated, and then the memory write receiving data length User_send_nwrite_len is sent to the receiving party in the memory write mode. A doorbell is sent to the receiving party, and then it is determined whether a doorbell response is received. If the doorbell response is received, the initial state is returned. If the doorbell response is not received, it is determined whether the doorbell response is timed out. If the doorbell response is timed out, the initial state is returned.

[0075] Figure 5 If the data length to be sent is less than 8, the User_send_nwrite_len is sent to the receiving party in the memory write mode. A doorbell is sent to the receiving party, and then it is determined whether a doorbell response is received. If the doorbell response is received, the initial state is returned. If the doorbell response is not received, it is determined whether the doorbell response is timed out. If the doorbell response is timed out, the initial state is returned.

[0076] Referring to Figure 6, the memory read response receiving module receives the received RapidIO data packet, and judges whether the received RapidIO data packet is a memory read response. If the received RapidIO data packet is a memory read response, the received memory read response RapidIO data packet is written into the Recv_resp_nread data FIFO. Then, it is judged whether the current memory read response RapidIO data packet is all written into the Recv_resp_nread data FIFO. If the current memory read response RapidIO data packet is all written into the Recv_resp_nread data FIFO, it is judged whether the data length written into the Recv_resp_nread data FIFO is greater than or equal to the memory read receiving sending length User_send_nread_len:

[0077] If the data length written into the Recv_resp_nread data FIFO is greater than or equal to the memory read receiving sending length User_send_nread_len, the Recv_resp_nread data FIFO is read according to the memory read receiving sending length User_send_nread_len, and a data byte valid identification state is given. Then, it is judged whether the Recv_resp_nread data FIFO is read empty. If the Recv_resp_nread data FIFO is read empty, the received response data length count state is cleared. Then, the initial state is returned.

[0078] If the data length written into the Recv_resp_nread data FIFO is less than User_send_nread_len, it is returned to judge whether the received RapidIO data packet is a memory read response, and the above process is repeated.

[0079] Referring to Figure 7 , the memory write receiving module receives the received RapidIO data packet, and judges whether the received RapidIO data packet is a memory write:

[0080] If the received RapidIO data packet is a memory write, it is judged whether the received RapidIO data packet is a length data packet. If the received RapidIO data packet is a length data packet, the actual sending data length User_recv_nwrite_len of the sending end is recorded. Then, the Recv_nwrite data FIFO is read according to the actual sending data length User_recv_nwrite_len, and a data byte valid identification User_recv_nwrite_byte_valid is given. Then, the initial state is returned.

[0081] If the received RapidIO data packet is not a memory write, the received data is written into the Recv_nwrite data FIFO, and then the process of determining whether the received RapidIO data packet is a memory write is repeated.

[0082] Referring to Figure 8 , the memory read receiving Recv_nread control module enters an initial state after power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read. If the received RapidIO data packet is a memory read, the address to be read Recv_nread_addr and the length to be read Recv_nread_len are recorded, and then the initial state is returned.

[0083] Referring to Figure 9 , the memory read response sending Send_resp_nread control module enters an initial state after power-on reset is completed, and then determines whether the Recv_resp_start is valid. If the Recv_resp_start is valid, a memory read response packet is generated according to the address to be read Recv_nread_addr and the length to be read Recv_nread_len, and then the initial state is returned.

[0084] The preferred embodiments of the present application have been described above with the preferred embodiments, but the present application is not limited to the above examples. It will be appreciated by those skilled in the art that the present application can be variously changed and modified. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the present application.

Claims

1. A method for implementing RapidIO memory reading and writing arbitrary byte lengths, characterized in that: include: Both the communication nodes and FPGA nodes are interconnected with the RapidIO switch chip via the RapidIO bus; The FPGA node unpacks and pads the length field of the memory write or memory read input by the user logic to implement RapidIO memory read and write of arbitrary byte length. The FPGA node internally includes a RapidIO IP core, a memory write and send Send_nwrite control module, a memory read and send Send_nread control module, a data send Send_data control module, a memory read response receive Recv_resp_nread control module, a memory write receive Recv_nwrite control module, a memory read receive Recv_nread control module and a memory read response send Send_resp_nread control module; The memory write send Send_nwrite control module receives a memory write send start signal, memory write send data, memory write send length, and memory write send start address input from the user on the one hand; on the other hand, it unpacks the input data according to the memory write send length, splits it into N integer data packets + 1 tail packet data packet, and performs a padding operation on the tail packet data packet; the unpacked and padded data packet data is written into the data FIFO; When the integer data packet and the tail data packet are written, the length of the split data packet is written to the lower 32 bits of the length FIFO, and the starting address of the split data is written to the upper 32 bits; The memory write send Send_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory write. If the user logic starts the memory write, it determines whether the length of the data to be sent is greater than X bytes: If the length of the data to be sent is greater than X bytes, X bytes of data are written to the data FIFO. Then, in the length FIFO, the lower 32 bits are written to X, and the upper 32 bits are written to the starting address of the data to be sent. Then, the length of the data to be sent and the starting address of the data to be sent are updated. Then, it is determined whether the length of the data to be sent is greater than X bytes, and the above process is repeated. If the length of the data to be sent is not greater than X bytes, the data length to be sent will be padded with zeros according to 8 bytes, and then the aligned and padded data will be written to the data FIFO. Then, the aligned and padded data length will be written to the length FIFO in the lower 32 bits, and the starting address of the data to be sent will be written in the upper 32 bits. Finally, the system returns to the initial state.

2. The method for implementing RapidIO memory reading and writing arbitrary byte lengths according to claim 1, characterized in that: The memory read and send Send_nread control module, on the one hand, receives a memory read and send start signal, a memory read and send length, and a memory read and send start address input from the user; on the other hand, it unpacks the input memory read and send length, splits it into N integer data packets + 1 tail packet data packet, and pads the tail packet data packet; and writes each memory read and send length after unpacking and padding into the lower 32 bits of the FIFO, and writes each memory read and send start address into the upper 32 bits of the FIFO.

3. The method for implementing RapidIO memory reading and writing of arbitrary byte length according to claim 1, characterized in that: The data sending Send_data control module receives, on the one hand, a memory write data packet sending FIFO empty signal, a memory write data packet sending data, a memory write data packet sending, a memory write data packet sending starting address, and a memory write data packet sending tail packet indication signal output by the memory write sending Send_nwrite control module; on the other hand, receives a memory read data packet sending FIFO empty signal, a memory read data packet sending, and a memory read data packet sending starting address output by the memory read sending Send_nread module; When either the memory write data packet send FIFO empty signal or the memory read data packet send FIFO empty signal is 0, the internal sending process is started; Generates memory write RapidIO data packets or memory read RapidIO data packets and sends them to the RapidIO switching network through the RapidIO IP core.

4. The method for implementing RapidIO memory reading and writing of arbitrary byte length according to claim 1, characterized in that: The memory read receive Recv_nread control module receives data input from the RapidIO IP core, extracts the memory read receive length and the memory read receive address by parsing the RapidIO data packet, and then generates a memory read receive start signal.

5. The method for implementing RapidIO memory reading and writing of arbitrary byte length according to claim 1, characterized in that: The memory read response sending Send_resp_nread control module receives the memory read reception start signal output by the memory read reception Recv_nread control module, and sends the memory read response data from the user logic to the RapidIO switching network through the RapidIO IP core according to the memory read reception length and the memory read reception address.

6. The method for implementing RapidIO memory reading and writing of arbitrary byte length according to claim 2, characterized in that: The memory read send_nread control module enters the initial state after the power-on reset is completed, and then determines whether the user logic starts the memory read. If the user logic starts the memory read, it determines whether the length of the data to be read is greater than X bytes: If the length of the data to be read is greater than X bytes, the lower 32 bits are written to the FIFO as length X, and the upper 32 bits are written to the starting address of the data to be read. The length of the data to be read and the starting address of the data to be read are then updated. The above process is then repeated to determine whether the length of the data to be read is greater than X bytes. If the length of the data to be read is not greater than X bytes, the data to be read will be aligned and padded with zeros for the length X bytes, and then the lower 32 bits of the aligned and padded data length X will be written to the FIFO, and the upper 32 bits will be written to the starting address of the data to be read, and then the initial state will be returned.

7. The method for implementing RapidIO memory reading and writing arbitrary byte lengths according to claim 3, characterized in that: The data sending control module Send_data enters the initial state after the power-on reset is completed, and then determines whether the memory read data packet sending FIFO empty signal is 0: If the FIFO empty signal sent by the memory read data packet is 0, a memory read RapidIO data packet is generated, and then it is determined whether a memory read response is received. If a memory read response is received, the initial state is returned; Otherwise, determine whether the memory read response has timed out. If so, return to the initial state. If the memory read data packet transmit FIFO empty signal is not 0, then determine whether the memory write data packet transmit FIFO empty signal is 0. If the memory write data packet transmit FIFO empty signal is not 0, then return to the initial state; If the memory write data packet transmit FIFO empty signal is 0, determine whether the memory write data packet transmit tail packet indication identification signal is 0. If the memory write data packet transmit tail packet indication identification signal is 0, generate a memory write RapidIO data packet with a length of X bytes, and then return to the initial state; If the memory write data packet transmission tail packet indication flag signal is not 0, determine whether the memory write data packet transmission length is equal to X. If the memory write data packet transmission length is equal to X, generate a memory write tail packet RapidIO data packet with a memory write length of X bytes, then send the memory write receive data length to the receiver in memory write mode, send a doorbell to the receiver, and then determine whether a doorbell response is received. If a doorbell response is received, return to the initial state. If no doorbell response is received, determine whether the doorbell response has timed out. If so, return to the initial state. If the memory write packet transmission length is not equal to X, the memory write packet transmission length is determined by half of the length each time until the shortest length is reached. Each time, a RapidIO packet of the corresponding length is generated, and the length of the data to be sent is updated. The memory write reception data length is then sent to the receiver in memory write mode, and a doorbell is sent to the receiver. Then, a determination is made as to whether a doorbell response is received. If so, the process returns to the initial state. If no doorbell response is received, a determination is made as to whether the doorbell response has timed out. If so, the process returns to the initial state.

8. The method for implementing RapidIO memory reading and writing of arbitrary byte length according to claim 1, characterized in that: The memory read response receiving Recv_resp_nread control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read response. If the received RapidIO data packet is a memory read response, the received RapidIO data packet of the memory read response is written into the Recv_resp_nread data FIFO. Then, it is determined whether all the RapidIO data packets of the current memory read response are written into the FIFO. If all the RapidIO data packets of the current memory read response are written into the FIFO, it is determined whether the length of the data written into the FIFO is greater than or equal to the memory read receive and send length: If the length of the data written to the FIFO is greater than or equal to the memory read receive and send length, the data byte valid identification status is given according to the read FIFO, and then it is determined whether the FIFO is read empty. If the FIFO is read empty, the receive response data length count status is cleared and then the initial state is returned; If the length of the data written to the FIFO is less than the memory read receive and send length, the process returns to determine whether the received RapidIO data packet is a memory read response and repeats the above process.

9. The method for implementing RapidIO memory reading and writing of arbitrary byte length according to claim 1, characterized in that: The memory write receiving Recv_nwrite control module enters the initial state after the power-on reset is completed, and then determines whether the received RapidIO data packet is a memory write: If the received RapidIO data packet is a memory write, it is determined whether the received RapidIO data packet is a length data packet. If the received RapidIO data packet is a length data packet, the actual length of the data sent by the sender is recorded, and then the FIFO is read according to the actual length of the data sent, and a valid data byte flag is given, and then the initial state is returned. If the received RapidIO data packet is not a memory write, the received data is written into the FIFO, and then the process returns to determine whether the received RapidIO data packet is a memory write, and the above process is repeated.

10. The method for realizing RapidIO memory reading and writing of arbitrary byte length according to claim 1, characterized in that: The memory read receiving Recv_nread control module enters the initial state after power-on reset is completed, and then determines whether the received RapidIO data packet is a memory read. If the received RapidIO data packet is a memory read, it records the address to be read and the length to be read, and then returns to the initial state.

11. The method for realizing RapidIO memory reading and writing of arbitrary byte length according to claim 10, characterized in that: The memory read response sending Send_resp_nread control module enters the initial state after the power-on reset is completed, and then determines whether Recv_resp_start is valid. If Recv_resp_start is valid, it generates a memory read response packet according to the address to be read and the length to be read, and then returns to the initial state.

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