A chip data acquisition method

Abstract

The present invention relates to the field of wireless communication IC chip technology and discloses a chip data acquisition method, comprising: collecting physical layer data from different nodes in the physical layer and performing preprocessing; wherein the physical layer data includes physical layer data and physical layer maintenance and detection signals; while collecting the physical layer data, recording system-on-chip (SOC) operating information to acquire the current SOC maintenance and detection signals via a data bus; combining the SOC maintenance and detection signals and the physical layer data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control, and trigger length control; and writing the processed acquisition signal to a memory unit via a data bus for recording or outputting it directly from a peripheral interface. The chip data acquisition method provided by the present invention collects chip physical layer data and maintenance and detection signals, solving the technical problem of more efficient, accurate, and comprehensive chip data acquisition.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication IC chips, and in particular to a chip data acquisition method. Background Art

[0002] Chip data acquisition is a common status monitoring method for wireless communication IC chips. It collects and records physical layer data through maintenance signal collection, determines the chip's operating status, and provides support for troubleshooting and data analysis. For chip data acquisition, the existing technology first uses a physical layer data frame acquisition device to synchronously collect multi-node data, including multiple WTB physical layer interfaces, data processing units, and control units; then obtains the data collected by the interfaces, including a communication controller, generates a control signal to the communication controller, and controls the multiple WTB physical layer interfaces to synchronously collect data; finally, controls the multiple WTB physical layer interfaces to start working at the same clock beat to synchronously collect physical layer data between all WTB nodes.

[0003] However, existing chip data acquisition methods have the following problems: 1. The data acquisition control mode is simple and inflexible. 2. The collected data is redundant, resulting in wasted storage space. 3. The real-time performance of the collected data is poor. 4. The collected data type is limited. Summary of the Invention

[0004] The present invention provides a chip data acquisition method for acquiring chip physical layer data and maintenance measurement signals, thereby solving the technical problem of how to acquire chip data more efficiently, accurately and comprehensively.

[0005] The present invention provides a chip data acquisition method, comprising:

[0006] Collecting physical layer data collected from different nodes in the physical layer and preprocessing it; wherein the physical layer collected data includes physical layer data and physical layer maintenance and measurement signals;

[0007] While collecting data at the physical layer, record SOC working information to collect current SOC maintenance signal through the data bus;

[0008] Combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control and trigger length control;

[0009] The collected signal after data processing is written into the Memory unit for record through the data bus or output directly from the peripheral interface.

[0010] Furthermore, the step of collecting physical layer data from different nodes in the physical layer and performing preprocessing includes:

[0011] Collect physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the collection node selection instruction and the collection enable selection instruction; wherein the physical layer data includes I-channel data, Q-channel data and physical layer real-time AGC gain signal;

[0012] The physical layer data and the physical layer maintenance signal are converted into a clock domain so as to be synchronized to the data bus clock domain.

[0013] Furthermore, in the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the data selection process includes:

[0014] Receive bus control instructions, and combine the collected signals into three data frames according to the control instructions, and add a timestamp frame header to form a data frame; wherein the three data frames include: only containing physical layer collected data, only containing SOC maintenance and measurement signals, and containing both physical layer collected data and SOC maintenance and measurement signals.

[0015] Furthermore, in the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the extraction includes:

[0016] According to the configured decimation parameters, the corresponding multiple decimation operation is performed on the data after the data frame is formed. Specifically, the sampled data is decimated 1 / N according to the configured decimation multiple. That is, when the decimation multiple is configured as N, the first one of every N collected data is extracted as the decimated data, and the remaining data is discarded; when the decimation multiple is configured as 0, no decimation operation is performed;

[0017] The extracted data frame is written into the memory unit through the data bus for recording or directly output from the peripheral interface.

[0018] Furthermore, in the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the trigger control includes:

[0019] Set edge trigger and condition trigger modes for physical layer data collection and SOC maintenance signal, and configure trigger conditions according to needs. Start counting when it is judged that the trigger conditions are met. Among them, the edge trigger is triggered when the level of a bit data in the judgment signal changes; the condition trigger is triggered when the data changes to the set data value.

[0020] Furthermore, in the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, triggering length control includes:

[0021] After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is the same as the trigger length, the sending of recorded data to the Memory unit or peripheral interface is stopped.

[0022] Furthermore, edge and conditional triggering of physical layer data acquisition is performed, including:

[0023] Collect physical layer I-channel data, Q-channel data and physical layer real-time AGC gain signal according to configuration parameters, and collect physical layer maintenance signal at the same time;

[0024] While collecting data, it is determined whether the configured trigger conditions are met. When the trigger conditions are met, the counter starts counting and records the trigger length to end the collection. Among them, when monitoring the AGC gain is the trigger condition, the conditional trigger determines that the AGC gain is equal to the configured trigger condition, and the trigger is satisfied. The counter starts recording the trigger data length, and the collection ends when the counter is equal to the configured count length. The edge trigger determines the edge change of the AGC lock mark as the trigger condition, and selects the rising edge or falling edge of the signal to determine. When the trigger condition is met, it starts counting and records the trigger length to end the collection.

[0025] Furthermore, the abnormal trigger collection for SOC includes:

[0026] The maintenance and measurement signals of each part of the SOC are collected through the data bus, and the abnormal SOC maintenance and measurement signal status that needs to be monitored is configured as the trigger condition. When the trigger condition is met, the physical layer data and maintenance and measurement signals are recorded, and the analysis data is exported through the data interface to identify the cause of the SOC abnormality.

[0027] The present invention also provides a chip data acquisition system, based on the chip data acquisition method described above, comprising a physical layer acquisition module, a SOC acquisition module, a data processing module, a data bus, a memory unit, and a peripheral interface, wherein the data processing module is connected to the physical layer acquisition module, the SOC acquisition module, and the data bus, respectively, and the data bus is further connected to the memory unit and the peripheral interface;

[0028] The physical layer acquisition module collects physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the acquisition node selection instruction and acquisition enable selection instruction given by the acquisition control module, synchronizes them to the data bus clock domain through clock domain conversion, and sends them to the data processing module;

[0029] The SOC acquisition module collects the current SOC maintenance signal through the data bus while collecting the physical layer signal and sends it to the data processing module;

[0030] The data processing module performs data processing on the physical layer data, the physical layer maintenance signal and the SOC maintenance signal, including data selection processing, extraction, trigger control and trigger length control;

[0031] The memory unit receives the recorded data sent by the data processing module through the data bus, reads the corresponding data according to the input address when exporting, and then sends it to the data interface through the data bus;

[0032] The peripheral interface sends the recorded data derived from the memory unit or the data bus to the outside of the chip.

[0033] The beneficial effects of the present invention are:

[0034] 1. The present invention introduces chip maintenance signal recording, which not only records physical layer data but also includes multi-dimensional information such as physical layer working status, link status, SOC status, etc., thereby improving the real-time and integrity of recorded data and providing more comprehensive data support for problem analysis and performance optimization.

[0035] 2. Flexibly select physical layer data and maintenance signal for recording to reduce data redundancy and improve storage space utilization.

[0036] 3. It has a configurable data extraction mechanism that can save memory storage space and record more data while ensuring the usefulness of the data.

[0037] 4. The introduction of a trigger mechanism can quickly locate the data position of the corresponding conditions. At the same time, under the control of the trigger length, it can quickly find the data of the corresponding length before and after the trigger point, and analyze the data more efficiently.

[0038] 5. The entire data acquisition system works independently. When data acquisition is not needed, the entire system can be bypassed to reduce chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of the process of chip data acquisition method of the present invention.

[0040] Figure 2 This is a flowchart for triggering physical layer data collection in the present invention.

[0041] Figure 3 This is a trigger flow chart for SOC abnormality triggering collection in the present invention.

[0042] Figure 4 It is a structural diagram of the chip data acquisition system of the present invention.

[0043] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0045] The present invention is applied to the fields of vehicle-mounted Bluetooth chips, tire pressure monitoring, digital tags, chip monitoring, digital keys, etc. In wireless communication IC chips, it collects channel physical layer baseband data and maintenance signals for scenarios such as data analysis, monitoring, IC chip troubleshooting, upgrade optimization, etc.; the collected data can be recorded after being extracted at different multiples to save storage space; various trigger conditions for recording data can be set, such as specific value triggering and edge triggering; when the trigger conditions are met, the collected data of the corresponding length before or after the trigger point can be recorded according to the configured trigger length.

[0046] like Figure 1 As shown, the present invention provides a chip data acquisition method, comprising:

[0047] S1. Collect physical layer data collected from different nodes in the physical layer and perform preprocessing; wherein the physical layer collected data includes physical layer data and physical layer maintenance signals.

[0048] Specifically include:

[0049] 1) Physical layer data acquisition: Collects physical layer data, including I and Q channel data and physical layer real-time AGC gain signals; according to the acquisition node selection instructions and acquisition enable selection instructions given by the acquisition control module, collects data from different nodes in the physical layer, synchronizes it to the data bus clock domain through clock domain conversion, and sends it to the data processing module.

[0050] 2) Physical layer maintenance signal acquisition: Collect the physical layer maintenance signal and work synchronously with the physical layer data acquisition module to ensure the real-time performance of the maintenance signal and the collected data; the maintenance signal also needs to be converted into the clock domain before being sent to the data processing module.

[0051] S2. Record SOC working information while collecting data at the physical layer to collect current SOC maintenance signals through the data bus.

[0052] SOC maintenance signal acquisition: Collect the current SOC maintenance signal through the data bus, and record the SOC working information while collecting the physical layer signal to monitor the SOC working status.

[0053] S3. Combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control and trigger length control.

[0054] Data processing specifically includes:

[0055] 1) Data selection processing: According to the control instructions, the input acquisition signal is combined into three types of data frames: containing only physical layer acquisition data, only containing maintenance measurement signals, and containing both physical layer data and maintenance measurement signals; and a timestamp frame header is added to form a data frame.

[0056] 2) Extraction: According to the configured extraction parameters, the data that constitutes the data frame is extracted by a corresponding multiple. If the extraction multiple is configured to 0, no extraction operation is performed; the extracted data frame is written into the memory unit through the data bus for record or directly output from the peripheral interface.

[0057] The decimation operation is as follows: 1 / N decimation is performed on the sampled data according to the configured decimation factor. That is, when the decimation factor is configured to N, the first of every N collected data is extracted as the decimated data, and the remaining data is discarded. When the decimation factor is configured to 0, no decimation is performed. That is, when the decimation factor is configured to 4, the first of every four collected data is extracted as the decimated data, and the remaining three data are discarded. When the decimation factor is configured to 8, the first of every eight data is extracted and the remaining seven are discarded, and so on.

[0058] 3) Trigger control: There are two modes for data and measurement signals: edge trigger and condition trigger. The trigger condition can be configured according to needs. Counting starts when the trigger condition is met.

[0059] a. Edge triggering triggers when a certain bit of signal level changes, i.e., a rising or falling edge. For example, when collecting data before and after physical layer link synchronization, you can configure the rising edge of the physical layer synchronization indicator signal (a single bit, pulled high during synchronization) as the trigger condition.

[0060] b. Conditional triggering is triggered when the data changes to a certain value. For example, if the AGC gain changes from 0, if the trigger condition is set to AGC=3, the trigger will be generated when the AGC gain value changes to 3. For example, when you need to observe data when the AGC gain is adjusted to a certain intensity, configure the corresponding AGC gain value as the trigger condition, and collect data when the AGC is adjusted to the corresponding value.

[0061] 4) Trigger length control: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is equal to the trigger length, the sending of recorded data to the memory unit or peripheral interface is stopped, and the data acquisition process ends.

[0062] Specifically, if Figure 2 As shown, edge and conditional trigger acquisition is performed on physical layer data, including:

[0063] T1. Using the trigger function can quickly and accurately locate and collect data. After the system is started, the physical layer I, Q data and AGC gain value are collected according to the configuration parameters, and the physical layer maintenance signal is collected at the same time.

[0064] T2. Collect data and determine whether the configured trigger conditions are met at the same time. When the trigger conditions are met, the counter starts counting and records the trigger length to end the acquisition. Taking monitoring AGC gain as the trigger condition as an example, the conditional trigger determines that the AGC gain is equal to the configured trigger condition, and the trigger is satisfied. The counter starts recording the trigger data length, and the acquisition ends when the counter is equal to the configured count length. The edge trigger determines the edge change of the AGC lock mark as the trigger condition. You can choose to judge the rising edge or falling edge of the signal (the rising edge trigger of the AGC lock signal indicates that the AGC adjustment has reached a stable state and the physical layer link connection is stable; the falling edge AGC loses lock, and the physical layer link signal may swing greatly at this time, and the AGC gain value needs to be readjusted). After the trigger condition is met, counting starts, and recording ends when the trigger length is reached.

[0065] like Figure 3 As shown, the abnormal trigger collection for SOC includes:

[0066] The data bus collects maintenance and measurement signals from various SOC components. To monitor chip status when the SOC is in an abnormal state, the abnormal SOC maintenance and measurement signal status to be monitored is configured as a trigger condition (for example, monitoring the CPU operating status indicator, triggering data collection when the CPU is operating abnormally, collecting maintenance and measurement signals to analyze the status information of various components within the chip, and troubleshooting the cause of the CPU abnormal state). When the trigger condition is met, the physical layer data and maintenance and measurement signals are recorded, and the analysis data is exported through the data interface to troubleshoot the cause of the SOC abnormality. Since both the SOC maintenance and measurement signals and real-time physical layer data are recorded simultaneously, the analysis of SOC abnormalities is more accurate and comprehensive.

[0067] S4. The collected signal after data processing is written into the memory unit through the data bus for recording or outputted directly from the peripheral interface.

[0068] like Figure 4 As shown, the present invention also provides a chip data acquisition system, which is based on the chip data acquisition method described above and includes a physical layer acquisition module, an SOC acquisition module, a data processing module, a data bus, a memory unit and a peripheral interface. The data processing module is respectively connected to the physical layer acquisition module, the SOC acquisition module and the data bus, and the data bus is also connected to the memory unit and the peripheral interface. The data processing module also includes a system control unit.

[0069] (1) Physical layer acquisition module:

[0070] 1) Physical layer data acquisition: Collects physical layer data, including I and Q channel data and physical layer real-time AGC gain signals; according to the acquisition node selection instructions and acquisition enable selection instructions given by the acquisition control module, collects data from different nodes in the physical layer, synchronizes it to the data bus clock domain through clock domain conversion, and sends it to the data processing module.

[0071] 2) Physical layer maintenance signal acquisition: Collects physical layer maintenance signals and works synchronously with the physical layer data acquisition module to ensure the real-time performance of maintenance signals and collected data. Maintenance signals also need to be converted into clock domains before being sent to the data processing module.

[0072] (2) SOC acquisition module: collects the current SOC maintenance signal through the data bus, and records the SOC working information while collecting the physical layer signal to monitor the SOC working status.

[0073] (3) Data processing module: performs data processing on physical layer data, physical layer maintenance signal and SOC maintenance signal, including data selection processing, extraction, trigger control and trigger length control.

[0074] 1) Data selection processing: According to the control instructions, the input acquisition signal is combined into three types of data frames: containing only physical layer acquisition data, only containing maintenance measurement signals, and containing both physical layer data and maintenance measurement signals; and a timestamp frame header is added to form a data frame;

[0075] 2) Decimation: According to the configured decimation parameters, the corresponding multiple decimation operation is performed on the framed data. If the decimation multiple is configured to 0, no decimation operation is performed. The decimated data frame is written into the memory unit through the data bus for record or directly output from the peripheral interface.

[0076] 3) Trigger control: There are two modes for data and measurement signals: edge trigger and condition trigger. The trigger condition can be configured according to the needs. Counting starts when the trigger condition is met.

[0077] 4) Trigger length control: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is equal to the trigger length, the sending of recorded data to the memory unit or peripheral interface is stopped, and the data acquisition process ends.

[0078] (4) System control: Receive control instructions from the bus, transmit control instructions corresponding to each module, and monitor the working status of the acquisition system.

[0079] (5) Memory unit: Receives the recorded data sent by the acquisition system through the data bus during recording, reads the corresponding data according to the input address during export, and then sends it to the data interface through the data bus.

[0080] (6) Peripheral interface: Sends the recorded data exported from the memory unit or data bus to the outside of the chip.

[0081] The present invention introduces chip maintenance signal recording, which not only records physical layer data but also includes multi-dimensional information such as the physical layer operating status, link status, and SOC status. This improves the real-time and integrity of the recorded data and provides more comprehensive data support for problem analysis and performance optimization. It can flexibly select physical layer data and maintenance signals for recording, reducing data redundancy and improving storage space utilization. At the same time, the present invention has a configurable data extraction mechanism that can save memory storage space and record more data while ensuring useful data information. The present invention also introduces a trigger mechanism that can quickly locate the data position corresponding to the conditions. At the same time, under the control of the trigger length, it can quickly find data of corresponding lengths before and after the trigger point, allowing for more efficient data analysis. The entire data acquisition system works independently and can be bypassed when data acquisition is not required, reducing chip power consumption.

[0082] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, apparatus, article, or method comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, apparatus, article, or method. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, apparatus, article, or method comprising the element.

[0083] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip data acquisition method, characterized in that: include: Collecting physical layer data collected from different nodes in the physical layer and preprocessing it; wherein the physical layer collected data includes physical layer data and physical layer maintenance and measurement signals; specifically including: Collect physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the collection node selection instruction and the collection enable selection instruction; wherein the physical layer data includes I-channel data, Q-channel data and physical layer real-time AGC gain signal; Performing clock domain conversion on the physical layer data and the physical layer maintenance signal to synchronize them to the data bus clock domain; While collecting data at the physical layer, record SOC working information to collect current SOC maintenance signal through the data bus; Combining the SOC maintenance signal and the physical layer acquisition data into an acquisition signal, and performing data processing on the acquisition signal; wherein the data processing includes data selection processing, extraction, trigger control and trigger length control; The collected signal after data processing is written into the Memory unit for record through the data bus or output directly from the peripheral interface.

2. The chip data acquisition method according to claim 1, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the data selection process includes: Receive bus control instructions, and combine the collected signals into three data frames according to the control instructions, and add a timestamp frame header to form a data frame; wherein the three data frames include: only containing physical layer collected data, only containing SOC maintenance and measurement signals, and containing both physical layer collected data and SOC maintenance and measurement signals.

3. The chip data acquisition method according to claim 2, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the extraction includes: According to the configured decimation parameters, the corresponding multiple decimation operation is performed on the data after the data frame is formed. Specifically, the sampled data is decimated 1 / N according to the configured decimation multiple. That is, when the decimation multiple is configured as N, the first one of every N collected data is extracted as the decimated data, and the remaining data is discarded; when the decimation multiple is configured as 0, no decimation operation is performed; The extracted data frame is written into the memory unit through the data bus for recording or directly output from the peripheral interface.

4. The chip data acquisition method according to claim 3, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, the trigger control includes: Set edge trigger and condition trigger modes for physical layer data collection and SOC maintenance signal, and configure trigger conditions according to needs. Start counting when it is judged that the trigger conditions are met. Among them, the edge trigger is triggered when the level of a bit data in the judgment signal changes; the condition trigger is triggered when the data changes to the set data value.

5. The chip data acquisition method according to claim 4, characterized in that: In the step of combining the SOC maintenance signal and the physical layer collected data into a collection signal and performing data processing on the collection signal, triggering length control includes: After the trigger condition is met, the trigger count is increased by 1 each time a data frame is recorded. When the count is the same as the trigger length, the sending of recorded data to the Memory unit or peripheral interface is stopped.

6. The chip data acquisition method according to claim 5, characterized in that: Perform edge and conditional triggering on physical layer acquisition data, including: Collect physical layer I-channel data, Q-channel data and physical layer real-time AGC gain signal according to configuration parameters, and collect physical layer maintenance signal at the same time; While collecting data, it is determined whether the configured trigger conditions are met. When the trigger conditions are met, the counter starts counting and records the trigger length to end the collection. Among them, when monitoring the AGC gain is the trigger condition, the conditional trigger determines that the AGC gain is equal to the configured trigger condition, and the trigger is satisfied. The counter starts recording the trigger data length, and the collection ends when the counter is equal to the configured count length. The edge trigger determines the edge change of the AGC lock mark as the trigger condition, and selects the rising edge or falling edge of the signal to determine. When the trigger condition is met, it starts counting and records the trigger length to end the collection.

7. The chip data acquisition method according to claim 5, characterized in that: Abnormal trigger collection for SOC, including: The maintenance and measurement signals of each part of the SOC are collected through the data bus, and the abnormal SOC maintenance and measurement signal status that needs to be monitored is configured as the trigger condition. When the trigger condition is met, the physical layer data and maintenance and measurement signals are recorded, and the analysis data is exported through the data interface to identify the cause of the SOC abnormality.

8. A chip data acquisition system, characterized in that: The chip data acquisition method according to any one of claims 1 to 7 comprises a physical layer acquisition module, a SOC acquisition module, a data processing module, a data bus, a memory unit, and a peripheral interface, wherein the data processing module is connected to the physical layer acquisition module, the SOC acquisition module, and the data bus, respectively, and the data bus is further connected to the memory unit and the peripheral interface; The physical layer acquisition module collects physical layer data and physical layer maintenance signals of different nodes in the physical layer according to the acquisition node selection instruction and acquisition enable selection instruction given by the acquisition control module, synchronizes them to the data bus clock domain through clock domain conversion, and sends them to the data processing module; The SOC acquisition module collects the current SOC maintenance signal through the data bus while collecting the physical layer signal and sends it to the data processing module; The data processing module performs data processing on the physical layer data, the physical layer maintenance signal and the SOC maintenance signal, including data selection processing, extraction, trigger control and trigger length control; The memory unit receives the recorded data sent by the data processing module through the data bus, reads the corresponding data according to the input address when exporting, and then sends it to the data interface through the data bus; The peripheral interface sends the recorded data derived from the memory unit or the data bus to the outside of the chip.

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