Chip digital layout generation method, device and equipment and readable storage medium

Abstract

The invention provides a chip digital layout generation method, device and equipment and a readable storage medium. The method comprises the steps of extracting contour features of a layer structure and an interlayer connection structure of a chip from a physical layout of the chip; generating a circuit netlist of the chip based on the contour features; wherein the content of the circuit netlist comprises the position information and the size information of the electronic components in the chip and the connection relation between the associated electronic components; on the basis of the circuit netlist, automatic placement of PDK devices of all electronic components can be achieved, and the digital layout of the chip is generated by further combining the metal layer pattern layer and the through hole layer pattern layer extracted from the physical layout. Through the implementation of the scheme of the invention, contour feature extraction, layer operation and device placement can be efficiently completed, so that a required digital layout is obtained; excessive manual intervention is not needed, and the identification error rate is low.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a method, device, equipment and readable storage medium for generating a chip digital layout. Background Art

[0002] Chip layout reverse refers to the process of extracting chip image information from the chip's physical layout, and then deriving the chip's circuit schematic, logic design and other information. This process is often used in reverse engineering, fault analysis, compatibility design, education and research.

[0003] In the related art, the general process of layout reverse design includes: determining the physical layout hierarchy of the chip through optical microscopes, scanning electron microscopes, e-book testing and other technical means; then converting the physical layout into a digital layout, and then analyzing the logic, design methods and technologies of the chip. However, in the related art, after determining the hierarchy of the physical layout, it is usually necessary to manually identify the holes and complete the devices and routing, which is inefficient and prone to errors. Summary of the invention

[0004] The embodiments of the present application provide a method, device, equipment and readable storage medium for generating a digital layout of a chip, which can at least solve the problem in the related art that the conversion of the physical layout of the chip into the digital layout is overly dependent on manual labor, resulting in a large workload, low efficiency and low accuracy of the generated digital layout.

[0005] A first aspect of an embodiment of the present application provides a method for generating a digital layout of a chip, comprising:

[0006] Extract the contour features of the chip's layer structure and inter-layer connection structure from the chip's physical layout;

[0007] Generate a circuit netlist of the chip based on the contour features; wherein the content of the circuit netlist includes the position information and size information of the electronic components in the chip and the connection relationship between the associated electronic components;

[0008] Based on the circuit netlist, the PDK devices corresponding to each electronic component are placed in the preset layout model, and combined with the layout information extracted from the physical layout to generate a digital layout of the chip; among which, the layer information includes the information corresponding to the metal layer and the through-hole layer.

[0009] A second aspect of an embodiment of the present application provides a device for generating a chip digital layout, including:

[0010] A feature extraction module is used to extract the contour features of the chip's layer structure and inter-layer connection structure from the chip's physical layout;

[0011] A first generating module is used to generate a circuit netlist of the chip based on the outline features; wherein the content of the circuit netlist includes the position information and size information of the electronic components in the chip and the connection relationship between the associated electronic components;

[0012] The second generation module is used to place the PDK devices corresponding to each electronic component into a preset layout model based on the circuit netlist, and generate a digital layout of the chip in combination with the layout information extracted from the physical layout; wherein the layer information includes information corresponding to the metal layer and the through-hole layer.

[0013] A third aspect of an embodiment of the present application provides an electronic device, comprising: a memory and a processor, wherein the processor is used to execute a computer program stored in the memory, and when the processor executes the computer program, it implements each step of the method for generating a digital layout of a chip provided in the first aspect of the embodiment of the present application.

[0014] The fourth aspect of the embodiments of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, each step in the method for generating a digital layout of a chip provided in the first aspect of the embodiments of the present application is implemented.

[0015] As can be seen from the above, according to the method, device, equipment and readable storage medium for generating the digital layout of the chip provided by the scheme of the present application, the contour features of the layer structure and the interlayer connection structure of the chip are extracted from the physical layout of the chip; the circuit netlist of the chip is generated based on the contour features; wherein the content of the circuit netlist includes the position information, size information and the connection relationship between the associated electronic components in the chip; based on the circuit netlist, the PDK devices corresponding to each electronic component are placed in a preset layout model, and the digital layout of the chip is generated in combination with the layout information extracted from the physical layout. Through the implementation of the scheme of the present application, the contour features of the layer structure and the interlayer connection structure of the chip are first extracted from the physical layout, and the type, position, size and connection relationship between the electronic components of the chip are determined according to the extracted contour features, and the corresponding circuit netlist is generated, so that the corresponding PDK device is accurately laid out in the digital layout model, thereby generating a high-precision digital layout, which can effectively solve the problems of low efficiency and easy errors in manual operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A basic flow chart of a method for generating a digital layout of a chip provided in the first embodiment of the present application;

[0017] Figure 2 A schematic diagram of generating a circuit netlist provided in the first embodiment of the present application;

[0018] Figure 3 A schematic diagram of a MOS transistor PDK device layout provided in the first embodiment of the present application;

[0019] Figure 4 A schematic diagram of a polygonal circumscribed rectangle of an active layer and a polysilicon layer overlapping each other in a related layer of a physical layout provided in the first embodiment of the present application;

[0020] Figure 5 A detailed flow chart of a method for generating a digital layout of a chip provided in the second embodiment of the present application;

[0021] Figure 6 A schematic diagram of a program module of a device for generating a digital layout of a chip provided in a third embodiment of the present application;

[0022] Figure 7 A schematic diagram of the structure of an electronic device provided in the fourth embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0024] In the description of the embodiments of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0026] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0027] In the related art, the process of converting the physical layout into the digital layout usually includes the following steps: manually identifying and selecting the devices in the physical layout of the chip; manually identifying the holes, routing and other structural features in the chip to determine the connection relationship between the devices (that is, obtaining the chip's wire network); converting the wire network into a circuit netlist; manually performing a preliminary layout of the devices with reference to the physical layout of the chip; combining the converted circuit netlist and the layout obtained by the preliminary layout to complete the wiring work and realize the connection of the devices. In the process of generating digital chips using the above method, there are the following defects: it is necessary to identify the images corresponding to the layer structures of the chip's N-well layer, active layer, polysilicon layer, etc. and manually complete the device selection, which is time-consuming and inefficient; it is necessary to complete manual hole and routing, which is inefficient and prone to connection relationship judgment errors; after determining the connection relationship between devices, manually layout the devices, which is slow and inefficient.

[0028] In order to solve the problem in the related art that the conversion of the physical layout of the chip into the digital layout is too dependent on manual work, the workload is large, the efficiency is low, and the accuracy of the generated digital layout is low, the first embodiment of the present application provides a method for generating a digital layout of a chip, such as Figure 1 A basic flow chart of a method for generating a digital chip layout provided in this embodiment, wherein the method for generating a digital chip layout comprises the following steps:

[0029] Step 101: extracting contour features of the layer structure and inter-layer connection structure of the chip from the physical layout of the chip.

[0030] Specifically, when extracting contour features, this embodiment can use image recognition algorithms, machine learning algorithms, etc. to identify the chip structure graphics in the physical layout and extract the corresponding contour features. In addition, the contour features can be extracted by combining image recognition and manual recognition, which is not limited here. The chip in this embodiment can be a CMOS process chip, and the layer structure of the chip can include an active layer, a polysilicon layer, an N-well layer, a metal layer, etc. The interlayer connection structure can include through holes and / or metal fillings, etc., which are not limited here.

[0031] Step 102: Generate a circuit netlist of the chip based on the outline features.

[0032] Specifically, the content of the circuit netlist includes the type, location information, size information of the electronic components in the chip and the connection relationship between the associated electronic components.

[0033] Step 103: Based on the circuit netlist, the PDK devices corresponding to the electronic components are placed in a preset layout model, and the digital layout of the chip is generated by combining the layout information extracted from the physical layout.

[0034] Specifically, the layer information includes the information corresponding to the metal layer and the through-hole layer. PDK devices can refer to electrical component models and tool sets designed for specific CMOS processes, including transistors, interconnections, model parameters, design rules, etc., which can be used to lay out digital layouts and perform layout checks, and are a bridge between chip design and chip manufacturing. This embodiment can establish a connection between chip electronic components and PDK devices through the PDK device automatic layout system, and quickly and efficiently complete operations such as determining the orientation of the PDK device and placing the PDK device, thereby obtaining the desired digital chip.

[0035] In one implementation of the present embodiment, the above-mentioned layer structure includes a metal layer, and the interlayer connection structure includes a through hole; accordingly, the above-mentioned step of extracting the contour features of the layer structure and the interlayer connection structure of the chip from the physical layout of the chip includes: splicing the through hole layer and the metal layer layer of the physical layout of the chip, and converting the RGB image obtained after splicing into a grayscale image; based on the background grayscale value of the grayscale image, the grayscale value of the through hole area and the grayscale value of the metal layer area, converting the grayscale image into a binary image; extracting the contour features of the metal layer and the through hole from the binary image.

[0036] Specifically, in this embodiment, the process of extracting contour features can be completed by the layer extraction system. The above process of extracting the contour features of the metal layer and the through hole from the binary image can be completed by the following means: identifying the initial contour in the binary image, and approximating the initial contour into a polygonal contour; based on preset screening conditions (the screening conditions can be pre-determined based on the actual shape, size and other information of each electronic component), the target polygonal contour corresponding to the metal layer and the through hole is screened out from all polygonal contours, that is, the contour features of the metal layer and the through hole are determined.

[0037] Furthermore, in one implementation of the present embodiment, the step of converting the grayscale image into a binary image based on the background grayscale value of the grayscale image, the grayscale value of the through-hole area, and the grayscale value of the metal layer area includes: determining a grayscale value threshold for converting the image type based on the relative relationship between the background grayscale value of the grayscale image, the grayscale value of the through-hole area, and the grayscale value of the metal layer area; and converting the grayscale image into a binary image according to the grayscale value threshold.

[0038] Specifically, in some specific embodiments, the above-mentioned background grayscale value, through-hole area grayscale value and metal layer area grayscale value can respectively refer to the average grayscale value of the corresponding area. Based on the grayscale value characteristics of different areas in the grayscale image, a grayscale value threshold that can accurately distinguish different structures is determined, and then the grayscale image can be converted into a binary image with the grayscale value threshold as the boundary.

[0039] In one implementation of the present embodiment, the layer structure includes a metal layer, an N-well layer, an active layer and a polysilicon layer, and the interlayer connection structure includes a through hole; accordingly, the above-mentioned step of generating a circuit netlist of the chip based on the contour feature includes: based on the contour feature, performing Boolean relationship operations on the N-well layer layer, the active layer layer and the polysilicon layer layer in the physical layout to determine the position information and size information of each electronic component in the chip; based on the contour feature, performing Boolean relationship operations on the metal layer layer, the active layer layer, the polysilicon layer layer and the through hole layer in the physical layout to determine the connection relationship between the associated electronic components in the chip; combining the position information, size information and connection relationship to generate a circuit netlist of the chip.

[0040] Specifically, in some specific implementations, the contour features corresponding to the N-well layer, active layer, polysilicon layer, etc. can be obtained by manual recognition, image recognition, or machine recognition, without limitation. Preferably, in one implementation, the contour features corresponding to the active layer and polysilicon layer are extracted by manual recognition to ensure the accuracy and standardization of the device size. Figure 2 As shown, in this embodiment, the process of generating a circuit netlist can be completed by a layer operation system. A polygonal Boolean operation algorithm can be used to realize the identification of electronic components and the connection relationship between electronic components, and then the identified information can be written into the circuit netlist for subsequent establishment of a relationship comparison table between electronic components and PDK devices; and by performing Boolean relationship operations on the N-well layer, active layer, and polysilicon layer in the physical layout, not only the position information and size information of each electronic component can be identified, but also the type of the electronic component can be determined.

[0041] In one implementation of the present embodiment, the above-mentioned step of placing the PDK devices corresponding to each electronic component into a preset layout model based on the circuit netlist, and generating a digital layout of the chip in combination with the layout information extracted from the physical layout, includes: determining the target position parameters of the PDK devices corresponding to each electronic component based on the circuit netlist; adding the corresponding PDK devices to the preset layout model according to the target position parameters to obtain an initial digital layout; adding the layer information extracted from the physical layout to the initial digital layout to generate the digital layout of the chip; wherein the layer structure includes a metal layer, the interlayer connection structure includes a through hole, and the layer information includes information corresponding to the metal layer and the through hole layer.

[0042] Specifically, the above target position parameters refer to the position parameters of the PDK device in the digital layout, and the process of determining the above target position parameters includes determining the position information and orientation information of the PDK device. Before adding the PDK device to the layout model, the layout model of the chip can be created in advance, the PDK device can be exported in the layout model, and a relationship comparison table between the electronic components in the circuit netlist and the PDK device can be established; thereby the PDK device can be accurately placed at the target position in the layout model.

[0043] Furthermore, in one implementation of the present embodiment, the layer structure also includes an active layer and a polysilicon layer, and the content of the circuit netlist also includes first position parameters of a circumscribed rectangle corresponding to each electronic component, and the circumscribed rectangle is determined based on contour features of the overlapping area of ​​the electronic components corresponding to the active layer layer and the polysilicon layer layer in the physical layout; accordingly, the above-mentioned step of determining the target position parameters of the PDK device corresponding to each electronic component based on the circuit netlist includes: determining the second position parameters of the PDK device corresponding to each electronic component in a preset layout model based on the position information and size information of each electronic component in the circuit netlist; and determining the target position parameters of each PDK device in the digital layout of the chip in combination with the first position parameters and the second position parameters.

[0044] Specifically, in the process of common circuit netlist, the polygon corresponding to the overlapping area of ​​the electronic components corresponding to the active layer layer and the polysilicon layer layer can be written into the circuit netlist as device information in advance. In this embodiment, the target position of the PDK device is determined by means of the above-mentioned circumscribed rectangle, which can ensure that the PDK device in the digital layout and the electronic components in the physical layout are placed in the same direction and overlap, thereby improving the accuracy of the digital layout.

[0045] Further, in one implementation of the present embodiment, the channel shape of the PDK device is a rectangle; accordingly, the above-mentioned step of determining the target position parameters of each PDK device in the digital layout of the chip by combining the first position parameter and the second position parameter includes: calculating the first absolute value of the difference between the long side of the target PDK device and the long side of the corresponding circumscribed rectangle, the second absolute value of the difference between the wide side of the target PDK device and the wide side of the corresponding circumscribed rectangle, the third absolute value of the difference between the long side of the target PDK device and the wide side of the corresponding circumscribed rectangle, and the fourth absolute value of the difference between the wide side of the target PDK device and the long side of the corresponding circumscribed rectangle by combining the first absolute value, the second absolute value, the third absolute value and the fourth absolute value; determining the target orientation of the target PDK device by combining the first absolute value, the second absolute value, the third absolute value and the fourth absolute value; and calculating the target position parameters of the target PDK device in the digital layout of the chip based on the target orientation.

[0046] Specifically, Figure 3 and 4 As shown, in the physical layout and layout model, a coordinate system can be established with one end position of the target electronic component as the origin, and then the coordinate parameters of each end point of the target electronic component in the physical layout and the corresponding coordinate parameters of each end point of the target PDK device in the layout model can be determined, so that the size information (length and width) of the target electronic component and the target PDK device can be determined, and then the final orientation of the target PDK device can be determined based on the above size information.

[0047] Furthermore, in one implementation of the present embodiment, the above-mentioned combination of the first absolute value, the second absolute value, the third absolute value and the fourth absolute value to determine the target orientation of the target PDK device includes: if the sum of the first absolute value and the second absolute value is less than the sum of the third absolute value and the fourth absolute value, then the orientation of the target PDK device at the current position is determined as the target orientation of the target PDK device; if the sum of the first absolute value and the second absolute value is greater than the sum of the third absolute value and the fourth absolute value, then the corresponding orientation after the target PDK device is rotated 90° along the current position is determined as the target orientation of the target PDK device.

[0048] Specifically, the long side of the target PDK device at the current position (that is, the initial position of the target PDK device in the layout model) is h0, and the wide side is w0. The long side of the target electronic component in the physical layout is h, and the wide side is w. The coordinates corresponding to the lower left corner of the target PDK device at the target position are (x0, y0), the coordinates corresponding to the lower right corner of the target PDK device at the target position are (x1, y1), the coordinates corresponding to the lower left corner of the circumscribed rectangle are (x2, y2), and the coordinates corresponding to the lower right corner of the circumscribed rectangle are (x3, y3); then:

[0049] E1=|h0-h|+|w0-w|

[0050] E2 = |h0 - w| + |w0 - h|

[0051] Wherein, E1 represents the first orientation determination parameter, and E2 represents the second orientation determination parameter.

[0052] If E1 < E2, then determine the orientation of the target PDK device at the current position as the target orientation R0 of the target PDK device. Correspondingly, the parameters of the coordinates corresponding to the lower left corner of the target PDK device can be calculated using the following formula:

[0053]

[0054] If E1 < E2, then determine the orientation corresponding to the target PDK device after rotating 90° along the current position as the target orientation R90 of the target PDK device. Correspondingly, the parameters of the coordinates corresponding to the lower left corner of the target PDK device can be calculated using the following formula:

[0055]

[0056] Using the above method, the target position parameters of each PDK device in the digital layout can be calculated respectively, and then the PDK device can be accurately placed into the initial layout model. After the placement of the PDK device is completed, copy the via layer and metal layer extracted by the layer extraction system into the layout where the PDK device has been placed, and make a slight adjustment to complete the reverse of the chip physical layout.

[0057] Based on the technical solution of the embodiment of the present application above, extract the contour features of the layer structure and the inter-layer connection structure of the chip from the physical layout of the chip; generate a circuit netlist of the chip based on the contour features; wherein, the content of the circuit netlist includes the position information, size information of the electronic components in the chip, and the connection relationship between the associated electronic components; based on the circuit netlist, place the PDK devices corresponding to each electronic component into a preset layout model, and combine the layout information extracted from the physical layout to generate the digital layout of the chip. Through the implementation of the solution of the present application, first extract the contour features of the layer structure and the inter-layer connection structure of the chip from the physical layout, determine the type, position, size of the electronic components of the chip and the connection relationship between the electronic components according to these extracted contour features, and generate the corresponding circuit netlist, so as to accurately layout the corresponding PDK devices into the pre-created digital layout model, thereby generating a digital layout with high accuracy, which can effectively solve the problems of low efficiency and easy errors in manual operation.

[0058] Figure 5 The method in... provides a refined method for generating a digital layout of a chip according to the second embodiment of the present application. The method for generating the digital layout of the chip includes:

[0059] Step 501: extracting contour features of the layer structure and inter-layer connection structure of the chip from the physical layout of the chip.

[0060] Step 502: Based on the contour features, Boolean relationship operations are performed on the N-well layer, active layer and polysilicon layer in the physical layout to determine the position information and size information of each electronic component in the chip.

[0061] Step 503: Based on the contour features, Boolean relationship operations are performed on the metal layer layers, active layer layers, polysilicon layer layers and through-hole layer layers in the physical layout to determine the connection relationship between the associated electronic components in the chip.

[0062] Step 504: Determine first position parameters of the circumscribed rectangle corresponding to each electronic component according to the contour features of the overlapping region of the electronic components corresponding to the active layer layer and the polysilicon layer layer in the physical layout.

[0063] Step 505 : Generate a circuit netlist of the chip by combining the position information, size information, connection relationship and the first position parameter of the circumscribed rectangle.

[0064] Step 506: Determine the position information and orientation information of the PDK device corresponding to each electronic component based on the circuit netlist.

[0065] Step 507 : Combine the position information and the orientation information, add the corresponding PDK device to the preset layout model, and obtain an initial digital layout.

[0066] Step 508: Add the layer information corresponding to the metal layer and the through-hole layer in the physical layout to the initial digital layout to generate a digital layout of the chip.

[0067] Through the implementation of this embodiment, the layer extraction system is used to identify the contour features of the chip, and there is no need to manually identify the devices one by one, thereby improving the device recognition efficiency; the layer operation system is used to determine the size information, position information and connection relationship between electronic components, and mark and store them to generate a circuit netlist, further reducing the probability of recognition errors and improving recognition efficiency; the PDK device automatic layout system is used to automatically complete the layout and placement of PDK devices, which is conducive to greatly improving the layout efficiency of PDK devices with high accuracy.

[0068] It should be understood that the size of the serial number of each step in this embodiment does not mean the order of execution of the steps. The execution order of each step should be determined by its function and internal logic, and should not constitute a sole limitation on the implementation process of the embodiment of this application.

[0069] Figure 6A device for generating a chip digital layout is provided in the third embodiment of the present application. The device for generating a chip digital layout can be applied to the aforementioned method for generating a chip digital layout. Figure 6 As shown, the device for generating the chip digital layout mainly includes:

[0070] A feature extraction module 601 is used to extract the contour features of the layer structure and the inter-layer connection structure of the chip from the physical layout of the chip;

[0071] The first generating module 602 is used to generate a circuit netlist of the chip based on the outline features; wherein the content of the circuit netlist includes the position information and size information of the electronic components in the chip and the connection relationship between the associated electronic components;

[0072] The second generation module 603 is used to place the PDK devices corresponding to each electronic component into a preset layout model based on the circuit netlist, and generate a digital layout of the chip in combination with the layout information extracted from the physical layout; wherein the layer information includes information corresponding to the metal layer and the through-hole layer.

[0073] In some implementations of the present embodiment, the layer structure includes a metal layer, and the interlayer connection structure includes a through hole; the feature extraction module is specifically used to: splice the through hole layer and the metal layer layer of the physical layout of the chip, and convert the RGB image obtained after splicing into a grayscale image; based on the background grayscale value of the grayscale image, the grayscale value of the through hole area and the grayscale value of the metal layer area, convert the grayscale image into a binary image; extract the contour features of the metal layer and the through hole from the binary image.

[0074] Furthermore, in some implementations of the present embodiment, when the feature extraction module performs the above-mentioned function of converting the grayscale image into a binary image based on the background grayscale value of the grayscale image, the through-hole area grayscale value, and the metal layer area grayscale value, it is specifically used to: determine the grayscale value threshold for converting the image type based on the relative relationship between the background grayscale value of the grayscale image, the through-hole area grayscale value, and the metal layer area grayscale value; and convert the grayscale image into a binary image according to the grayscale value threshold.

[0075] In some implementations of this embodiment, the layer structure includes a metal layer, an N-well layer, an active layer and a polysilicon layer, and the interlayer connection structure includes a through hole; the first generation module is specifically used to: based on the contour features, perform Boolean relationship operations on the N-well layer layers, active layer layers and polysilicon layer layers in the physical layout to determine the position information and size information of each electronic component in the chip; based on the contour features, perform Boolean relationship operations on the metal layer layers, active layer layers, polysilicon layer layers and through hole layers in the physical layout to determine the connection relationship between associated electronic components in the chip; combine the position information, size information and connection relationship to generate a circuit netlist of the chip.

[0076] In some implementations of this embodiment, the second generation module is specifically used to: determine the target position parameters of the PDK device corresponding to each electronic component based on the circuit netlist; add the corresponding PDK device to the preset layout model according to the target position parameters to obtain an initial digital layout; add the layer information extracted from the physical layout to the initial digital layout to generate a digital layout of the chip; wherein the layer structure includes a metal layer, the interlayer connection structure includes a through hole, and the layer information includes information corresponding to the metal layer layer and the through hole layer.

[0077] Furthermore, in some implementations of the present embodiment, the layer structure also includes an active layer and a polysilicon layer, and the content of the circuit netlist also includes a first position parameter of a circumscribed rectangle corresponding to each electronic component, and the circumscribed rectangle is determined based on contour features of the overlapping area of ​​the electronic components corresponding to the active layer layer and the polysilicon layer layer in the physical layout; accordingly, when the second generation module executes the above-mentioned function of determining the target position parameters of the PDK device corresponding to each electronic component based on the circuit netlist, it is specifically used to: determine the second position parameters of the PDK device corresponding to each electronic component in a preset layout model based on the position information and size information of each electronic component in the circuit netlist; and determine the target position parameters of each PDK device in the digital layout of the chip in combination with the first position parameter and the second position parameter.

[0078] Furthermore, in some implementations of the present embodiment, the channel shape of the PDK device (i.e., the shape of the overlapping area of ​​the active layer and the polysilicon layer) is a rectangle; when the second generation module performs the above-mentioned function of combining the first position parameter and the second position parameter to determine the target position parameters of each PDK device in the digital layout of the chip, it is specifically used to: calculate the first absolute value of the difference between the long side of the target PDK device and the long side of the corresponding circumscribed rectangle, the second absolute value of the difference between the wide side of the target PDK device and the wide side of the corresponding circumscribed rectangle, the third absolute value of the difference between the long side of the target PDK device and the wide side of the corresponding circumscribed rectangle, and the fourth absolute value of the difference between the wide side of the target PDK device and the long side of the corresponding circumscribed rectangle in combination with the first absolute value, the second absolute value, the third absolute value and the fourth absolute value; determine the target orientation of the target PDK device in combination with the first absolute value, the second absolute value, the third absolute value and the fourth absolute value; and calculate the target position parameters of the target PDK device in the digital layout of the chip based on the target orientation.

[0079] Furthermore, in some implementations of the present embodiment, when the second generation module executes the above-mentioned function of determining the target orientation of the target PDK device by combining the first absolute value, the second absolute value, the third absolute value and the fourth absolute value, it is specifically used to: if the sum of the first absolute value and the second absolute value is less than the sum of the third absolute value and the fourth absolute value, then determine the orientation of the target PDK device at the current position as the target orientation of the target PDK device; if the sum of the first absolute value and the second absolute value is greater than the sum of the third absolute value and the fourth absolute value, then determine the corresponding orientation after the target PDK device is rotated 90° along the current position as the target orientation of the target PDK device.

[0080] According to the device for generating the digital layout of a chip provided in this embodiment, the contour features of the layer structure and the interlayer connection structure of the chip are extracted from the physical layout of the chip; the circuit netlist of the chip is generated based on the contour features; wherein the content of the circuit netlist includes the position information, size information and the connection relationship between the associated electronic components in the chip; based on the circuit netlist, the PDK devices corresponding to each electronic component are placed in a preset layout model, and the digital layout of the chip is generated in combination with the layout information extracted from the physical layout. Through the implementation of the scheme of this application, the contour features of the layer structure and the interlayer connection structure of the chip are first extracted from the physical layout, and the type, position, size and connection relationship between the electronic components of the chip are determined according to the extracted contour features, and the corresponding circuit netlist is generated, so that the corresponding PDK devices are accurately laid out in the pre-created digital layout model, thereby generating a high-precision digital layout, which can effectively solve the problems of low efficiency and easy errors in manual operation.

[0081] Figure 7 An electronic device is provided in the fourth embodiment of the present application. The electronic device can be used to implement the method for generating a digital layout of a chip in the aforementioned embodiment, mainly comprising:

[0082] The memory 701, the processor 702, and the computer program 703 stored in the memory 701 and executable on the processor 702, the memory 701 and the processor 702 are connected by communication. When the processor 702 executes the computer program 703, the method in the above-mentioned embodiment 1 or 2 is implemented. The number of processors can be one or more.

[0083] The memory 701 may be a high-speed random access memory (RAM) memory, or a non-volatile memory, such as a disk memory. The memory 701 is used to store executable program codes, and the processor 702 is coupled to the memory 701 .

[0084] Furthermore, the embodiment of the present application also provides a computer-readable storage medium, which may be provided in the above-mentioned electronic device. The computer-readable storage medium may be the above-mentioned Figure 7 Memory in the illustrated embodiment.

[0085] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the method for generating the digital layout of the chip in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0086] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0087] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0088] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0089] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a readable storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned readable storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0090] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] The above is a description of the chip digital layout generation method, device, equipment and readable storage medium provided in this application. For technicians in this field, according to the ideas of the embodiments of this application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A method for generating a digital layout of a chip, characterized in that: include: Extracting contour features of the layer structure and interlayer connection structure of the chip from the physical layout of the chip; Generate a circuit netlist of the chip based on the contour features; wherein the content of the circuit netlist includes position information and size information of electronic components in the chip and connection relationships between the associated electronic components; Based on the circuit netlist, the PDK devices corresponding to the electronic components are placed in a preset layout model, and combined with the layer information extracted from the physical layout, a digital layout of the chip is generated; wherein the layer information includes information corresponding to the metal layer and the through-hole layer.

2. The method for generating a digital chip layout according to claim 1, characterized in that: The layer structure includes a metal layer, and the interlayer connection structure includes a through hole; The step of extracting the contour features of the layer structure and the interlayer connection structure of the chip from the physical layout of the chip includes: Splicing the through hole layer and the metal layer of the physical layout of the chip, and converting the RGB image obtained after the splicing into a grayscale image; Based on the background grayscale value, the through-hole area grayscale value and the metal layer area grayscale value of the grayscale image, the grayscale image is converted into a binary image; The contour features of the metal layer and the through hole are extracted from the binary image.

3. The method for generating a chip digital layout according to claim 2, characterized in that: The step of converting the grayscale image into a binary image based on the background grayscale value, the through-hole area grayscale value, and the metal layer area grayscale value of the grayscale image comprises: Determine a grayscale value threshold for converting the image type based on a relative relationship between a background grayscale value, a through-hole area grayscale value, and a metal layer area grayscale value of the grayscale image; The grayscale image is converted into a binary image according to the grayscale value threshold.

4. The method for generating a chip digital layout according to claim 1, characterized in that: The layer structure includes a metal layer, an N-well layer, an active layer and a polysilicon layer, and the interlayer connection structure includes a through hole; The generating a circuit netlist of the chip based on the contour feature comprises: Based on the contour features, a Boolean relationship operation is performed on the N-well layer, the active layer and the polysilicon layer in the physical layout to determine the position information and size information of each electronic component in the chip; Based on the contour features, a Boolean relationship operation is performed on the metal layer, the active layer, the polysilicon layer and the through-hole layer in the physical layout to determine the connection relationship between the electronic components associated with the chip; A circuit netlist of the chip is generated by combining the position information, size information and the connection relationship.

5. The method for generating a chip digital layout according to claim 1, characterized in that: Based on the circuit netlist, the PDK devices corresponding to the electronic components are placed in a preset layout model, and combined with the layer information extracted from the physical layout, a digital layout of the chip is generated, including: Based on the circuit netlist, determining target position parameters of the PDK device corresponding to each of the electronic components; According to the target position parameters, adding corresponding PDK devices to a preset layout model to obtain an initial digital layout; The layer information extracted from the physical layout is added to the initial digital layout to generate a digital layout of the chip.

6. The method for generating a digital chip layout according to claim 5, characterized in that: The layer structure also includes an active layer and a polysilicon layer, and the content of the circuit netlist also includes a first position parameter of a circumscribed rectangle corresponding to each of the electronic components, and the circumscribed rectangle is determined according to the contour features of the overlapping area of ​​the electronic components corresponding to the active layer layer and the polysilicon layer layer in the physical layout; The determining, based on the circuit netlist, target position parameters of the PDK device corresponding to each of the electronic components includes: Based on the position information and size information of each of the electronic components in the circuit netlist, determine a second position parameter of the PDK device corresponding to each of the electronic components in a preset layout model; The target position parameters of each of the PDK components in the digital layout of the chip are determined by combining the first position parameter and the second position parameter.

7. The method for generating a chip digital layout according to claim 6, characterized in that: The channel shape of the PDK device is rectangular; Determining the target position parameters of each of the PDK devices in the digital layout of the chip by combining the first position parameter and the second position parameter includes: In combination with the first position parameter and the second position parameter, a first absolute value of the difference between the long side of the target PDK device and the long side of the corresponding circumscribed rectangle, a second absolute value of the difference between the wide side of the target PDK device and the wide side of the corresponding circumscribed rectangle, a third absolute value of the difference between the long side of the target PDK device and the wide side of the corresponding circumscribed rectangle, and a fourth absolute value of the difference between the wide side of the target PDK device and the long side of the corresponding circumscribed rectangle are calculated; Determine a target orientation of the target PDK device by combining the first absolute value, the second absolute value, the third absolute value, and the fourth absolute value; Based on the target orientation, target position parameters of the target PDK device in the digital layout of the chip are calculated.

8. The method for generating a digital chip layout according to claim 7, characterized in that: The determining the target orientation of the target PDK device by combining the first absolute value, the second absolute value, the third absolute value, and the fourth absolute value includes: If the sum of the first absolute value and the second absolute value is less than the sum of the third absolute value and the fourth absolute value, determining the orientation of the target PDK device at the current position as the target orientation of the target PDK device; If the sum of the first absolute value and the second absolute value is greater than the sum of the third absolute value and the fourth absolute value, an orientation corresponding to a rotation of the target PDK device by 90° along the current position is determined as the target orientation of the target PDK device.

9. A device for generating a digital layout of a chip, characterized in that: include: A feature extraction module, used to extract the contour features of the layer structure and interlayer connection structure of the chip from the physical layout of the chip; A first generating module, configured to generate a circuit netlist of the chip based on the outline features; wherein the content of the circuit netlist includes position information and size information of electronic components in the chip and connection relationships between the associated electronic components; The second generation module is used to place the PDK devices corresponding to each of the electronic components into a preset layout model based on the circuit netlist, and combine the layer information extracted from the physical layout to generate a digital layout of the chip; wherein the layer information includes information corresponding to the metal layer layer and the through-hole layer.

10. An electronic device, characterized in that: The device comprises a memory and a processor, wherein: The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the steps in the method according to any one of claims 1 to 8 are implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 1 to 8 are implemented.

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