Function simulation method and device for multi-cycle digital circuit

Abstract

The invention discloses a function simulation method of a multi-cycle digital circuit. And performing RTL description on the digital circuit by adopting a hardware description language. A portion of a multi-cycle circuit in the digital circuit is extracted. RTL-level function simulation is carried out on the whole digital circuit. A digital circuit simulation platform applies function simulation excitation to a starting path register of each multi-cycle circuit in a digital circuit, and meanwhile, an enable signal is added to an ending path register of each multi-cycle circuit to test whether the output of the ending path register of each multi-cycle circuit is influenced by an unstable state or not. On the premise of not changing function simulation, function simulation excitation and enable signals are directly applied to the multi-cycle circuit in a test platform, and the potential time sequence problem of the multi-cycle circuit can be found in advance in the function simulation.

Description

Technical Field

[0001] The present application relates to a simulation method for a digital circuit. Background Art

[0002] In large digital circuits, if there is combinatorial logic between registers, such as large-bit-width multipliers, dividers, large-bit-width shift logic, large selection logic, etc., and the delay of the combinatorial logic is greater than one clock cycle, it cannot be correctly sampled into the next-level register within one clock cycle. Or, due to the large scale of digital circuits, the signal cannot be correctly sampled by the next-level register within one clock cycle after propagating over a long distance. These digital circuits are called multi-cycle circuits.

[0003] Functional simulation of digital circuits is used to verify the functional correctness of RTL (register-transfer level) code design without adding delay information. It is also called behavioral simulation, RTL simulation, front-end simulation, pre-simulation, etc. Timing simulation of digital circuits is mainly aimed at the netlist after layout and routing, adding timing analysis to simulate and verify the timing correctness. It is also called dynamic timing simulation, post-layout simulation, back-end simulation, post-simulation, etc.

[0004] Since functional simulation does not have timing information, even if there are timing problems in multi-cycle digital circuits, they cannot be tested through functional simulation. Timing simulation carries timing information, but it is often performed close to the chip tape-out time. Due to limited time, timing simulation can only select a few simple test scenarios to perform, and cannot cover all test scenarios, so it is impossible to comprehensively test whether there are timing problems in multi-cycle circuits.

[0005] Some literature has disclosed methods for testing the timing of multi-cycle circuits in functional simulation. The core idea is to design a logic in the multi-cycle digital circuit that can simulate the front-end simulation of the multi-cycle circuit, rather than directly applying stimulus to the multi-cycle digital circuit in the test platform for functional simulation. Summary of the invention

[0006] The technical problem to be solved by the present application is: how to directly apply excitation to a multi-cycle digital circuit in a test platform to perform functional simulation, and timely discover the timing problems of the multi-cycle digital circuit in the functional simulation.

[0007] In order to solve the above technical problems, the present application proposes a functional simulation method for a multi-cycle digital circuit, comprising the following steps. Step S1: Use a hardware description language to perform RTL description on the digital circuit; the digital circuit at least includes a part of the multi-cycle circuit. Step S2: Extract the part of the multi-cycle circuit in the digital circuit; the digital circuit contains one or more multi-cycle circuits; each multi-cycle circuit starts from a starting path register and ends at an ending path register, and there is a combinational logic circuit between the two. Step S3: Perform RTL-level functional simulation on the entire digital circuit. Step S4: The digital circuit simulation platform applies functional simulation excitation to the starting path register of each multi-cycle circuit in the digital circuit, and at the same time adds an enable signal to the ending path register of each multi-cycle circuit to test whether the output of the ending path register of each multi-cycle circuit will be affected by an unstable state. Alternatively, the step S3 is changed to any position after step S1, and the step S4 is changed to any position after step S2.

[0008] Preferably, in step S1, the hardware description language adopts any one of VHDL and Verilog.

[0009] Furthermore, in step S1, the part of the multi-cycle circuit means that the signal generated by the part of the circuit in a certain clock cycle does not need to be sampled by the lower register in the next clock cycle, but is allowed to be sampled by the lower register after multiple clock cycles.

[0010] Furthermore, in step S1, the part of the multi-cycle circuit means that the establishment time of this part of the circuit does not need to be within one clock cycle, that is, the input signal does not need to remain stable before the rising edge of the next clock signal arrives, but remains stable before the rising edge of a clock signal after several clock signals arrives.

[0011] Furthermore, in step S2, the multi-cycle circuit includes a large combinational logic, which means that there is a large combinational logic digital circuit between the start path register and the end path register, and the timing requirement within one clock cycle cannot be met from the start path register to the end path register.

[0012] Furthermore, in step S2, the multi-cycle circuit includes long-distance combinational logic, which means that the combinational logic between the start path register and the end path register has a long wiring in the digital circuit, and the timing requirements within one clock cycle cannot be met from the start path register to the end path register.

[0013] Furthermore, in step S2, the multi-cycle circuit includes: a start path register in a certain part of the circuit generates an asynchronous level signal, and the asynchronous level signal is insensitive to the time of reaching the end path register.

[0014] Further, it is assumed that the signal generated by the starting path register of a multi-cycle digital circuit changes once every m clock cycles, and m is a positive integer greater than 1. In the step S4, the application of functional simulation excitation to the starting path register means: forcibly setting the signal generated by the starting path register of the multi-cycle digital circuit to an indefinite value X in the first m-1 clock cycles, and allowing the signal generated by the starting path register of the multi-cycle digital circuit to be output normally in the mth clock cycle. The addition of an enable signal to the ending path register means: the enable signal is invalid in the first m-1 clock cycles, and the value of the combinational logic in the multi-cycle circuit is not sampled to the ending path register; the enable signal is valid in the mth clock cycle, and the value of the combinational logic in the multi-cycle circuit is sampled to the ending path register. Once the digital circuit simulation platform detects that the output signal of the ending path register of a multi-cycle digital circuit is an indefinite value X in the first m-1 clock cycles, it indicates that there is a problem or defect in the multi-cycle circuit.

[0015] Furthermore, in step S4, if a signal in a multi-cycle circuit is followed by both a branch of a multi-cycle circuit and another branch of a non-multi-cycle circuit, a buffer is added to the multi-cycle circuit branch following the signal, and the digital circuit simulation platform is changed to apply functional simulation excitation to the newly added buffer.

[0016] The present application also proposes a functional simulation device for a multi-cycle digital circuit, comprising an RTL description unit, a multi-cycle circuit extraction unit, an overall circuit functional simulation unit, and a multi-cycle circuit functional simulation unit. The RTL description unit is used to perform RTL description of the digital circuit using a hardware description language; the digital circuit at least includes a portion of a multi-cycle circuit. The multi-cycle circuit extraction unit is used to extract a portion of a multi-cycle circuit from the digital circuit; the digital circuit includes one or more multi-cycle circuits; each multi-cycle circuit starts from a starting path register and ends at an ending path register, and a combinational logic circuit is between the two. The overall circuit functional simulation unit is used to perform RTL-level functional simulation of the entire digital circuit. The multi-cycle circuit functional simulation unit is used to apply functional simulation excitation to the starting path register of each multi-cycle circuit, and at the same time add an enable signal to the ending path register of each multi-cycle circuit to test whether the output of the ending path register of each multi-cycle circuit will be affected by an unstable state.

[0017] The technical effect achieved by the present application is: without changing the functional simulation, functional simulation excitation and enable signals are directly applied to the multi-cycle circuit in the test platform, so that potential timing problems of the multi-cycle circuit can be discovered in advance in the functional simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart of the functional simulation method of the multi-cycle digital circuit proposed in this application.

[0019] Figure 2 is a schematic diagram of an example of one type of multi-cycle circuit (large combinational logic).

[0020] Figure 3 yes Figure 2 The timing diagram obtained by using the existing functional simulation method when the multi-cycle circuit design in is correct.

[0021] Figure 4 yes Figure 2 The timing diagram obtained by using the existing functional simulation method when the multi-cycle circuit design in the circuit is wrong.

[0022] Figure 5 is a schematic diagram of an example of another type of multi-cycle circuit (long-distance combinational logic).

[0023] Figure 6 is a schematic diagram of an example of a mixture of multi-cycle circuits and non-multi-cycle circuits.

[0024] Figure 7 yes Figure 6 The timing diagram obtained by the functional simulation method of the present application is used when the multi-cycle circuit design in is correct.

[0025] Figure 8 yes Figure 6 A timing diagram obtained by using the functional simulation method of the present application when a multi-cycle circuit design in the embodiment of the present invention is wrong.

[0026] Fig. 9 It is a structural schematic diagram of a functional simulation device for a multi-cycle digital circuit proposed in this application.

[0027] Explanation of the reference numerals in the figure: RTL description unit 1, multi-cycle circuit extraction unit 2, overall circuit function simulation unit 3, multi-cycle power supply function simulation unit 4. DETAILED DESCRIPTION

[0028] See also Figure 1 , the functional simulation method of the multi-cycle digital circuit proposed in this application includes the following steps.

[0029] Step S1: Use a hardware description language, such as VHDL or Verilog, to perform RTL description (also called RTL level description) on the digital circuit. RTL description refers to the functional description of the digital circuit using a hardware description language. The RTL description mainly focuses on the transmission and operation of data between registers. The digital circuit includes at least a multi-cycle circuit part and may also include a non-multi-cycle circuit part.

[0030] The part of the multi-cycle circuit refers to: the signal generated by this part of the circuit in a certain clock cycle does not need to be sampled by the lower-level register in the next clock cycle, but is allowed to be successfully sampled by the lower-level register after multiple clock cycles.

[0031] Or, in another way of expression, the part of the multi-cycle circuit refers to: the setup time of this part of the circuit does not need to be within one clock cycle. The setup time refers to the time that the input signal needs to remain stable before the rising edge of the clock signal arrives in the digital circuit design. This time ensures that the input signal is stable when the clock edge arrives, thereby avoiding data loss or metastability problems. The setup time does not need to be within one clock cycle, which means that the input signal does not need to remain stable before the rising edge of the next clock signal arrives, but can remain stable before the rising edge of a clock signal after several clock signals arrives.

[0032] Step S2: extract the part of the multi-cycle circuit in the digital circuit. The digital circuit contains one or more parts of the multi-cycle circuit. Each multi-cycle circuit starts from a register A and ends at another register B. Register A is the starting path register of the multi-cycle circuit, and register B is the ending path register of the multi-cycle circuit. There is a combinational logic circuit between the starting path register and the ending path register of each multi-cycle circuit.

[0033] Common multi-cycle circuits include the following types.

[0034] The first type of multi-cycle circuit is large combinational logic, which means that there is a large combinational logic digital circuit between two registers - such as a large-bit-width multiplier, a large-bit-width divider, a large-bit-width shift circuit, more than a dozen levels of selection circuits, etc. The timing requirements within one clock cycle cannot be met from the previous register to the next register, that is, the signal generated by the previous register is difficult to be sampled by the next register within one clock cycle.

[0035] The second type of multi-cycle circuit is long-distance combinational logic, which means that the combinational logic between two registers is far away in the digital circuit - for example, two registers in two modules far away in a large chip are connected by a combinational logic circuit. This combinational logic circuit has a very long wiring, which is reflected in the circuit timing. The delay of this combinational logic circuit will be relatively large. The timing requirements within one clock cycle cannot be met from the previous register to the next register, that is, the signal generated by the previous register is difficult to be sampled by the next register within one clock cycle.

[0036] In addition to the above two typical types of multi-cycle circuits, multi-cycle circuits also include: a front register in a certain part of the circuit generates an asynchronous level signal, and the asynchronous level signal is not sensitive to the time when it reaches the rear register.

[0037] Step S3: Perform RTL-level functional simulation on the entire digital circuit to confirm that all outputs of the entire digital circuit meet the expected values ​​of the reference model. The reference model refers to a behavioral model described in a hardware description language or other high-level language in a digital circuit simulation platform, which reflects the expected output of the digital circuit when it functions normally. The reference model is used to verify the correctness of the digital circuit design in circuit simulation and is an ideal and fully verified model.

[0038] Step S4: The digital circuit simulation platform (i.e., the test platform) applies functional simulation stimulus to the starting path register of each multi-cycle circuit in the digital circuit, and adds an enable signal to the ending path register of each multi-cycle circuit to test whether the output of the ending path register of each multi-cycle circuit will be affected by the unstable state, thereby discovering problems and defects in the multi-cycle circuit design in advance in the functional simulation.

[0039] The application of functional simulation stimulus to the starting path register means: assuming that the signal generated by the starting path register of a multi-cycle digital circuit changes once every m clock cycles, and m is a positive integer greater than 1, then the signal generated by the starting path register of the multi-cycle digital circuit is forcibly set to an indefinite value X in the first m-1 clock cycles, and the signal generated by the starting path register of the multi-cycle digital circuit is allowed to be output normally in the mth clock cycle. In this way, in the first m-1 clock cycles, all combinational logic signals after the starting path register will become indefinite values ​​X, which can effectively simulate the unstable state of the back-end chip circuit in the first few clock cycles of the multi-cycle digital circuit. The characteristics of the multi-cycle circuit can only be truly reflected in the back-end chip circuit, because the RTL description is an ideal behavioral level description without timing delay information. Only after the back-end chip circuit is completed will there be circuit timing delay information.

[0040] The adding of the enable signal to the end path register means: assuming that the signal generated by the start path register of a multi-cycle digital circuit changes once every m clock cycles, m is a positive integer greater than 1, then in the first m-1 clock cycles, the enable signal is invalid, and the value of the combinational logic in the multi-cycle circuit is not sampled into the end path register; in the mth clock cycle, the enable signal is valid, and the value of the combinational logic in the multi-cycle circuit is sampled into the end path register.

[0041] Assume that the signal generated by the start path register of a multi-cycle digital circuit changes once every m clock cycles, where m is a positive integer greater than 1. If the end path register of the multi-cycle circuit mistakenly samples a signal that should not be sampled in the first m-1 clock cycles, an indeterminate value X will appear at the output of the end path register, and this indeterminate value X will propagate to the final output result. Therefore, once the digital circuit simulation platform detects that the output signal of the end path register of a multi-cycle digital circuit is an indeterminate value X, the test comparison result with the reference model will fail, indicating that there is a problem or defect in the multi-cycle circuit.

[0042] The step S3 can be placed at any position after the step S1, and the step S4 can be placed at any position after the step S2. There is no strict order restriction for the step S2 and the step S3, and they can be placed in front of each other or performed simultaneously. There is no strict order restriction for the step S3 and the step S4, and they can be placed in front of each other or performed simultaneously.

[0043] See also Figure 2 , which is an example of a large multi-cycle circuit of the combinational logic type. Figure 2 In the digital circuit shown, the portion between registers Q1, Q2, and Q3 is a multi-cycle circuit, and the portion between registers Q1 and Q4 is a non-multi-cycle circuit. Figure 2 The part of the multi-cycle circuit in is specifically a large-bit-width multiplication logic. When the clock frequency is relatively high, the delay of the multiplication logic will exceed one clock cycle. The starting path registers of this multi-cycle circuit are Q1 and Q2, and the ending path register is Q3. Assuming that the frequency of change of the input signals Q1 and Q2 of the multiplication logic is once every m clock cycles, in the first m-1 clock cycles, the input signals Q1 and Q2 are forcibly added with indeterminate values. At the same time, an enable signal EN is added to the input end of register Q3. The enable signal EN is only valid in the mth clock cycle. At this time, register Q3 samples the output signal of the multiplication logic. This shows that the enable signal EN enables register Q3 to sample the output signal of the multiplication logic in units of every m clock cycles, rather than sampling the output signal of the multiplication logic in each clock cycle, so that the delay of the multiplication logic does not need to meet the requirement within one clock cycle.

[0044] See also Figure 3 ,This is Figure 2 The timing diagram obtained by using the existing functional simulation method when the multi-cycle circuit design in is correct. Since the functional simulation tool defaults to 0 for the delay of the combinational logic, the delay of the combinational logic is 0 when registers Q1 and Q2 change. The result of the multiplier is sent to the input of register Q3 when registers Q1 and Q2 change. Register Q3 will sample the output change of the multiplier at the next rising edge of the clock signal. Figure 3 Indicates correct timing when a multi-cycle circuit is designed correctly.

[0045] See also Figure 4 ,This is Figure 2 The timing diagram obtained by using the existing functional simulation method when the multi-cycle circuit design in is wrong. Assuming that the design of the multi-cycle circuit is wrong, the enable signal EN is mistakenly designed one clock cycle in advance. For the functional simulation test platform, register Q3 still has correct output at the 5th clock signal, the 7th clock signal, and the 9th clock signal. Figure 4 When a multi-cycle circuit design error occurs, the existing functional simulation method cannot correctly detect the design error.

[0046] See also Figure 5 , which is an example of a multi-cycle circuit of the long-distance combinational logic type. Figure 5 In the digital circuit shown, registers Q1 and Q2 are isolated by multiple large modules. The output signal of register Q1 can only reach the input end of register Q2 after a long distance propagation. Due to the long propagation path distance, it is difficult to complete the signal propagation within one clock cycle. The starting path register of this multi-cycle circuit is Q1, and the ending path register is Q2. Assuming that the frequency of change of the input signal Q1 of the multiplication logic is once every m clock cycles, an indeterminate value is forcibly added to the input signal Q1 in the first m-1 clock cycles. At the same time, an enable signal EN is added to the input end of register Q2. The enable signal EN is only valid in the mth clock cycle, so that register Q2 samples the output signal of the long-distance combinational logic in units of every m clock cycles, so that the output of register Q1 does not need to be propagated to the input end of register Q2 within one clock cycle.

[0047] There is also a special case in the step S4, that is, a branch of a multi-cycle circuit and another branch of a non-multi-cycle circuit are simultaneously provided behind a certain signal in a multi-cycle circuit. At this time, in order to distinguish the multi-cycle circuit branch from the non-multi-cycle circuit branch, a buffer is added to the multi-cycle circuit branch after the signal. The buffer does not change the logic function on the original multi-cycle circuit branch, and the digital circuit simulation platform is changed to apply functional simulation excitation to the newly added buffer, that is: assuming that the signal of the multi-cycle digital circuit before the buffer changes once every m clock cycles, and m is a positive integer greater than 1, then the signal of the multi-cycle digital circuit is forcibly set to an indefinite value X in the first m-1 clock cycles, and the signal of the multi-cycle digital circuit is allowed to be output normally in the mth clock cycle. In this way, the functional simulation excitation only works on the multi-cycle circuit branch, and does not work on the non-multi-cycle circuit branch. At the same time, an enable signal is added to the end path register of the multi-cycle circuit, and the value of the combinational logic in the multi-cycle circuit is sampled to the end path register only when the enable signal is valid.

[0048] See also Figure 6 , which is an example of a mixture of multi-cycle and non-multi-cycle circuits. Figure 6 In the digital circuit shown, the part between registers Q1, Q2, and Q3 is a multi-cycle circuit, and the part between registers Q1 and Q4 is a non-multi-cycle circuit. The output signal of register Q1 is provided to both the multi-cycle circuit branch and the non-multi-cycle circuit branch. The present application adds a buffer to the multi-cycle circuit branch after the output signal of register Q1. Assuming that the frequency of change of the output signal of register Q1 changes once every m clock cycles, an indeterminate value is forcibly added to the input signal Q1 in the first m-1 clock cycles. At the same time, an enable signal EN is added to the input end of register Q3. The enable signal EN is only valid in the mth clock cycle, so that register Q3 samples the output signal of the multiplication logic in units of every m clock cycles.

[0049] See also Figure 7 ,This is Figure 6 The timing diagram obtained by the functional simulation method of the present application is used when the multi-cycle circuit in is designed correctly. The output signals of registers Q1 and Q2 change at the rising edge of the second clock signal, the rising edge of the fourth clock signal, and the rising edge of the sixth clock signal. The digital circuit simulation platform forcibly assigns the output signal of register Q1 to an indefinite value X from the second clock signal to the third clock signal, from the fourth clock signal to the fifth clock signal, and from the sixth clock signal to the seventh clock signal. If the multi-cycle circuit is designed correctly, the input of register Q3 will correctly sample the correct output value of the multiplication logic at the fourth clock signal, the sixth clock signal, and the eighth clock signal. Figure 7This shows that if the timing of the multi-cycle circuit is correct, the results of the functional simulation are also correct.

[0050] See also Figure 8 ,This is Figure 6 The timing diagram obtained by the functional simulation method of the present application when the multi-cycle circuit design in the embodiment is wrong. If the multi-cycle circuit is designed incorrectly, assuming that the enable signal EN is incorrectly advanced by one clock cycle, the input of the register Q3 will incorrectly sample the indefinite value X of the multiplication logic output at the 4th clock signal, the 6th clock signal, and the 8th clock signal. Figure 8 It shows that if the timing of a multi-cycle circuit is wrong, the results of functional simulation can detect it.

[0051] See also Fig. 9 The functional simulation device of the multi-cycle digital circuit proposed in the present application includes an RTL description unit 1, a multi-cycle circuit extraction unit 2, an overall circuit functional simulation unit 3, and a multi-cycle circuit functional simulation unit 4. Fig. 9 The device shown corresponds to Figure 1 The method shown.

[0052] The RTL description unit 1 is used to perform RTL description on the digital circuit using a hardware description language. The digital circuit at least includes a multi-cycle circuit part.

[0053] The multi-cycle circuit extraction unit 2 is used to extract a part of a multi-cycle circuit from the digital circuit. The digital circuit includes one or more multi-cycle circuits; each multi-cycle circuit starts from a start path register and ends at an end path register, with a combinational logic circuit between the two.

[0054] The overall circuit function simulation unit 3 is used to perform RTL level function simulation on the entire digital circuit.

[0055] The multi-cycle circuit functional simulation unit 4 is used to apply functional simulation stimulus to the starting path register of each multi-cycle circuit, and at the same time add an enable signal to the ending path register of each multi-cycle circuit to test whether the output of the ending path register of each multi-cycle circuit will be affected by the unstable state.

[0056] The present application takes into account various real multi-cycle circuit situations, such as large-scale combinational logic, long-distance combinational logic, etc., and distinguishes between the multi-cycle circuit part and the non-multi-cycle circuit part in the digital circuit, and applies functional simulation excitation and enable signals to the multi-cycle circuit without changing the actual logic function. In order to distinguish between multi-cycle circuit branches and non-multi-cycle circuit branches, some buffers are added to apply functional simulation excitation of multi-cycle circuits to real multi-cycle circuit branches without affecting the functional simulation of non-multi-cycle circuit branches. The logic with the added buffer can be directly used for chip back-end implementation without the need to additionally shield the logic of simulating multi-cycle circuit functional simulation as in the prior art.

[0057] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should all be included in the protection scope of the present application.

Claims

1. A functional simulation method for a multi-cycle digital circuit, characterized in that: The method comprises the following steps: Step S1: using a hardware description language to perform RTL description on a digital circuit; the digital circuit at least includes a multi-cycle circuit portion; Step S2: extracting a portion of a multi-cycle circuit in the digital circuit; the digital circuit includes one or more multi-cycle circuits; each multi-cycle circuit starts from a start path register and ends at an end path register, and a combinational logic circuit is between the two; Step S3: Perform RTL-level functional simulation on the entire digital circuit; Step S4: the digital circuit simulation platform applies functional simulation stimulus to the start path register of each multi-cycle circuit in the digital circuit, and adds an enable signal to the end path register of each multi-cycle circuit to test whether the output of the end path register of each multi-cycle circuit is affected by the unstable state; Alternatively, the step S3 is changed to any position after the step S1, and the step S4 is changed to any position after the step S2.

2. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: In the step S1, the hardware description language adopts either VHDL or Verilog.

3. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: In step S1, the part of the multi-cycle circuit means that the signal generated by the part of the circuit in a certain clock cycle does not need to be sampled by the lower register in the next clock cycle, but is allowed to be sampled by the lower register after multiple clock cycles.

4. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: In step S1, the part of the multi-cycle circuit means that the establishment time of this part of the circuit does not need to be within one clock cycle, that is, the input signal does not need to remain stable before the rising edge of the next clock signal arrives, but remains stable before the rising edge of a clock signal after several clock signals arrives.

5. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: In step S2, the multi-cycle circuit includes a large combinational logic, which means that there is a large combinational logic digital circuit between the start path register and the end path register, and the timing requirement within one clock cycle cannot be met from the start path register to the end path register.

6. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: In step S2, the multi-cycle circuit includes long-distance combinational logic, which means that the combinational logic between the start path register and the end path register has a long wiring in the digital circuit, and the timing requirements within one clock cycle cannot be met from the start path register to the end path register.

7. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: In step S2, the multi-cycle circuit includes: a start path register in a certain part of the circuit generates an asynchronous level signal, and the asynchronous level signal is insensitive to the time of reaching the end path register.

8. The functional simulation method of a multi-cycle digital circuit according to claim 1, characterized in that: Assume that the signal generated by the start path register of a multi-cycle digital circuit changes once every m clock cycles, where m is a positive integer greater than 1; In step S4, applying functional simulation stimulus to the starting path register means: forcibly setting the signal generated by the starting path register of the multi-cycle digital circuit in the first m-1 clock cycles to an indefinite value X, and allowing the signal generated by the starting path register of the multi-cycle digital circuit to be output normally in the mth clock cycle; The adding of the enable signal to the end path register means that: in the first m-1 clock cycles, the enable signal is invalid, and the value of the combinational logic in the multi-cycle circuit is not sampled into the end path register; in the mth clock cycle, the enable signal is valid, and the value of the combinational logic in the multi-cycle circuit is sampled into the end path register; Once the digital circuit simulation platform detects that the output signal of the end path register of a multi-cycle digital circuit is an indefinite value X within the first m-1 clock cycles, it indicates that there is a problem or defect in the multi-cycle circuit.

9. The method for functional simulation of a multi-cycle digital circuit according to claim 1, characterized in that: In step S4, if a signal in a multi-cycle circuit is followed by both a branch of a multi-cycle circuit and a branch of a non-multi-cycle circuit, a buffer is added to the multi-cycle circuit branch following the signal, and the digital circuit simulation platform is changed to apply functional simulation excitation to the newly added buffer.

10. A functional simulation device for a multi-cycle digital circuit, characterized in that: It includes RTL description unit, multi-cycle circuit extraction unit, overall circuit function simulation unit, and multi-cycle circuit function simulation unit; The RTL description unit is used to perform RTL description on the digital circuit using a hardware description language; the digital circuit at least includes a multi-cycle circuit portion; The multi-cycle circuit extraction unit is used to extract a part of a multi-cycle circuit from the digital circuit; the digital circuit includes one or more multi-cycle circuits; each multi-cycle circuit starts from a start path register and ends at an end path register, and there is a combinational logic circuit between the two; The overall circuit function simulation unit is used to perform RTL level function simulation on the entire digital circuit; The multi-cycle circuit functional simulation unit is used to apply functional simulation stimulus to the starting path register of each multi-cycle circuit, and at the same time add an enable signal to the ending path register of each multi-cycle circuit to test whether the output of the ending path register of each multi-cycle circuit will be affected by the unstable state.

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