PPU module verification system and method based on UVM verification platform

Abstract

The invention relates to a PPU module verification system and method based on a UVM verification platform, by establishing a module-level verification system, parallel access of a plurality of hosts to a PPU module can be simulated through random configuration, and various possible scenes are traversed, so that the verification efficiency is improved, and the verification integrity is ensured. Module-level simulation verification can be immediately carried out after development of the PPU module is completed, through parameterization processing on APB and AHB interfaces, the number change of cores can be flexibly coped, verification cases can be dynamically adjusted, a verification system does not need to be redesigned, and the reusability of the verification system is greatly improved. By directly generating a data packet of an effective protocol instead of initiating access depending on a system configuration core, comprehensive verification of storage spaces of all the PPU modules is ensured. Therefore, through technologies of module-level simulation, interface parameterization, automatic expected generation and the like, the verification capability of the PPU module is greatly improved.

Description

Technical Field

[0001] The invention belongs to the technical field of chip verification, and relates to a PPU module verification system and method based on a UVM verification platform. Background Art

[0002] With the rapid development of the electronic information market, the demand for chips in the industry continues to grow. In order to improve the processing power and efficiency of chips, modern chips usually adopt multi-core design to support more powerful functions. In a multi-core system, how to ensure information security, especially between cores and secure access to peripherals, has become an important challenge in chip design. The peripheral protection unit (PPU) plays a vital role in a multi-core system. It is responsible for managing the access rights of each core to the peripherals and controlling the write operation rights of registers in privileged mode. If illegal access is found, the PPU module will immediately intercept and record the error status. In addition, the PPU module can also fine-tune the access rights of different hosts. For example, the administrator host can access all peripherals, while the user host can only access specific peripherals or some peripherals, thereby enhancing the security of the system.

[0003] At present, the verification of the PPU module is usually carried out at the system level after the whole chip is integrated. During the verification process, different hosts are configured to simulate various access request scenarios to test the function of the PPU module. However, this traditional verification technology still has the technical problem of insufficient verification capability. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional technologies, the present invention proposes a PPU module verification system based on a UVM verification platform and a PPU module verification method based on the UVM verification platform, which can greatly improve the verification capability of the PPU module.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a PPU module verification system based on a UVM verification platform is provided, including a register model, a reference model, a scoreboard, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, multiple groups of APB selection output agents and a PPU module to be verified; The register model, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, and multiple groups of APB selection output agents are respectively connected to the PPU module to be verified, the reference model is respectively connected to the register model and the scoreboard, and the multiple groups of AHB selection output agents and the multiple groups of APB selection output agents are respectively connected to the scoreboard; The register model is used to randomize the different register configurations of the PPU module to be verified, and simulate various access scenarios of the PPU module to be verified. The reference model is used to obtain and parse the register configuration of the PPU module to be verified, and output the expected interception result to the scoreboard when the APB bus access or AHB bus access is intercepted; Multiple groups of APB input agents are used to use VIP to generate a group of SEL signals, PROT signals and WRITE signals that comply with the APB bus protocol standard, multiple groups of AHB input agents are used to use VIP to generate a group of SEL signals, TRANS signals, PROT signals and WRITE signals that comply with the AHB bus protocol standard, multiple groups of AHB selection input agents are used to output multiple groups of selection input signals generated by the SEL signal selection of the corresponding AHB input agents to the PPU module to be verified and the reference model, multiple groups of APB selection input agents are used to output multiple groups of selection input signals generated by the SEL signal selection of the corresponding APB input agents to the PPU module to be verified and the reference model, multiple groups of AHB selection output agents are used to monitor the output data of each AHB interface of the PPU module to be verified and send the actual interception results generated to the scoreboard, multiple groups of APB selection output agents are used to monitor the output data of each APB interface of the PPU module to be verified and send the actual interception results generated to the scoreboard, the scoreboard is used to compare the expected interception results with the actual interception results of the corresponding interfaces in real time, and if the interception results are inconsistent, error status information is output.

[0006] On the other hand, a PPU module verification method based on a UVM verification platform is also provided, which is applied to a PPU module verification system based on a UVM verification platform, including a register model, a reference model, a scoreboard, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, multiple groups of APB selection output agents and a PPU module to be verified; The register model, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, and multiple groups of APB selection output agents are respectively connected to the PPU module to be verified, the reference model is respectively connected to the register model and the scoreboard, and the multiple groups of AHB selection output agents and the multiple groups of APB selection output agents are respectively connected to the scoreboard; The register model is used to randomize the different register configurations of the PPU module to be verified, and simulate various access scenarios of the PPU module to be verified. The reference model is used to obtain and parse the register configuration of the PPU module to be verified, and output the expected interception result to the scoreboard when the APB bus access or AHB bus access is intercepted; Multiple groups of APB input agents are respectively used to use VIP to generate a group of SEL signals, PROT signals and WRITE signals that comply with the APB bus protocol standard. Multiple groups of AHB input agents are respectively used to use VIP to generate a group of SEL signals, TRANS signals, PROT signals and WRITE signals that comply with the AHB bus protocol standard. Multiple groups of AHB selection output agents are respectively used to monitor the output data of each AHB interface of the PPU module to be verified and send the generated actual interception results to the scoreboard. Multiple groups of APB selection output agents are respectively used to monitor the output data of each APB interface of the PPU module to be verified and send the generated actual interception results to the scoreboard. The scoreboard is used to compare the expected interception results with the actual interception results of the corresponding interfaces in real time. If the interception results are inconsistent, error status information is output; The above-mentioned PPU module verification method based on UVM verification platform includes the following steps: After the verification is started, the register configuration of the PPU module to be verified is randomly configured by configuring the register model; wherein the register configuration randomly configured by the register model is sent to the reference model and simultaneously written to the register of the PPU module to be verified through the APB bus; Outputting multiple groups of selection input signals generated by the SEL signal selection of the corresponding APB input agents to the PPU module to be verified and the reference model through multiple groups of APB selection input agents, and outputting multiple groups of selection input signals generated by the SEL signal selection of the corresponding AHB input agents to the PPU module to be verified and the reference model through multiple groups of AHB selection input agents; The reference model will calculate the required interception after each data stimulus and send the interception information to the scoreboard as the expected interception result; The actual interception result generated by the PPU module to be verified is sent to the scoreboard through the monitors of each AHB selection output agent and the APB selection output agent; The scoreboard compares the expected interception result with the corresponding actual interception result in real time to see if they are consistent. If they are inconsistent, an error is reported; Return to the step of configuring the register model to randomly configure the register of the PPU module to be verified, and end the simulation after all stimuli for this verification are sent.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned PPU module verification system and method based on the UVM verification platform, by establishing a module-level verification system, can simulate the parallel access of multiple hosts to the PPU module by configuring randomness, and traverse various possible scenarios, thereby improving the verification efficiency and ensuring the integrity of the verification. It supports module-level simulation verification immediately after the development of the PPU module is completed. Compared with the verification technology after the traditional integrated chip, it greatly advances the time to discover potential problems and facilitates early correction, avoiding high-cost modifications and long cycles in the later stage; through parameterization of the APB and AHB interfaces, it can flexibly respond to changes in the number of cores and dynamically adjust verification cases without redesigning the verification system, greatly improving the reusability of the verification system and reducing the workload of repeated verification in different projects and configurations. By directly generating data packets of valid protocols instead of relying on the system configuration core to initiate access, comprehensive verification of all PPU module storage spaces is ensured, covering various access scenarios such as read / write, user / privilege, and instruction / data. In this way, through technologies such as module-level simulation, interface parameterization and automatic expectation generation, the problems of delayed timing, insufficient coverage, poor reusability and low efficiency in traditional verification technology are effectively solved, the verification capability of the PPU module is greatly improved, and a more efficient, flexible and complete PPU module verification solution is provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 It is a structural block diagram of a PPU module verification system based on a UVM verification platform in one embodiment; Figure 2 A schematic diagram of a workflow of a PPU module verification system based on a UVM verification platform in one embodiment; Figure 3 The figure is a flow chart of a PPU module verification method based on a UVM verification platform in one embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In traditional verification technology, the verification of the PPU module is intervened late, and its verification can only be performed after the whole chip is integrated, which increases the risk of project delivery. The verification coverage of the PPU module is not comprehensive, and it is difficult to cover all access scenarios, especially illegal or erroneous access, and the completeness of the verification cannot be guaranteed. The verification means have poor reusability. Every time the number or configuration of hosts in the project changes, the verification cases and configuration process need to be readjusted, which increases the workload. The simulation efficiency of the PPU module is low, and the expected results in the verification process cannot be automatically generated. Manual calculation is required. After integrating the whole chip and all the cores, the increase of unrelated modules makes simulation and debugging slow, further increasing the workload and simulation time of the verification personnel.

[0014] Therefore, traditional verification technology has great limitations in terms of efficiency, reusability and comprehensiveness, resulting in serious lack of verification capabilities. It is necessary to seek more efficient and flexible verification technologies to improve the verification quality and efficiency of PPU modules in order to enhance the verification capabilities of PPU modules.

[0015] In one embodiment, Figure 1As shown, a PPU module verification system based on a UVM verification platform is provided, including a register model, a reference model, a scoreboard, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, multiple groups of APB selection output agents and a PPU module to be verified, wherein the register model, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents and multiple groups of APB selection output agents are respectively connected to the PPU module to be verified, the reference model is respectively connected to the register model and the scoreboard, and the multiple groups of AHB selection output agents and the multiple groups of APB selection output agents are respectively connected to the scoreboard.

[0016] The register model is used to randomize the different register configurations of the PPU module to be verified and simulate various access scenarios of the PPU module to be verified; the reference model is used to obtain and parse the register configuration of the PPU module to be verified, and output the expected interception result to the scoreboard when the APB bus access or AHB bus access is intercepted. Multiple groups of APB input agents are used to use VIP to generate a group of SEL signals, PROT signals and WRITE signals that comply with the APB bus protocol standard, multiple groups of AHB input agents are used to use VIP to generate a group of SEL signals, TRANS signals, PROT signals and WRITE signals that comply with the AHB bus protocol standard, multiple groups of AHB selection input agents are used to output multiple groups of selection input signals generated by the SEL signal selection of the corresponding AHB input agents to the PPU module to be verified and the reference model, multiple groups of APB selection input agents are used to output multiple groups of selection input signals generated by the SEL signal selection of the corresponding APB input agents to the PPU module to be verified and the reference model, multiple groups of AHB selection output agents are used to monitor the output data of each AHB interface of the PPU module to be verified and send the actual interception results generated to the scoreboard, and multiple groups of APB selection output agents are used to monitor the output data of each APB interface of the PPU module to be verified and send the actual interception results generated to the scoreboard. The scoreboard is used to compare the expected interception results with the actual interception results of the corresponding interfaces in real time. If the interception results are inconsistent, the verification system will output error status information.

[0017] It can be understood that the design of each component in the above-mentioned PPU module verification system based on the UVM verification platform follows the existing UVM verification methodology. According to the detailed verification needs of the PPU module function, the verification system is built based on the UVM verification platform to configure the components of the corresponding functions, and complete the connection and connectivity testing between the components and other basic operations to ensure the normal data flow between the components during the verification process. Specifically, the architecture of the PPU module verification system based on the UVM verification platform is as follows: Figure 1shown.

[0018] Components such as register model (i.e. reg_model), reference model (i.e. refer_model), scoreboard (i.e. scb), multiple groups of AHB input agents (i.e. ahb_agent*n), multiple groups of APB input agents (i.e. apb_agent*m), multiple groups of APB selection input agents (i.e. apb_selin_agent*i), multiple groups of AHB selection input agents (i.e. ahb_selin_agent*j), multiple groups of AHB selection output agents (i.e. ahb_selout_agent*j), and multiple groups of APB selection output agents (i.e. apb_selout_agent*i) will coordinate their work by deriving sub-cases (test cases) based on the basic case, and jointly complete the verification of the PPU module to be verified (i.e. the design under test).

[0019] The AHB input agent and the APB input agent use Verification IP (VIP, which refers to verification intellectual property) to generate a set of SEL signals, PROT signals, and WRITE signals that comply with the protocol standard, where the SEL signal is a selection signal used to specify the selected module. The TRANS signal is a transmission signal used to indicate the type or state of data transmission, for example but not limited to, when the value of the TRANS signal is 00, it indicates IDLE (data transmission is in idle state), when the value of the TRANS signal is 01, it indicates that the data transmission is in BUSY state, when the value of the TRANS signal is 10, it indicates single (i.e., single-bit transmission or the first bit of burst transmission), and when the value of the TRANS signal is 11, it indicates burst transmission. For the TRANS signal, you can only focus on the tran[0] signal during verification. If trans[0] is valid, it means that the corresponding peripheral connected to the AHB bus is valid (among which, the APB input agent does not generate a TRANS signal but observes the SEL signal to indicate whether the corresponding peripheral is valid; although the AHB input agent also has a SEL signal, it actually observes the corresponding trans[0] signal to determine whether the corresponding peripheral is valid). The AHB select output agent will detect the corresponding trans_out (output) signal after the tran[0] signal passes through the PPU module to be verified to check whether the corresponding peripheral is intercepted.

[0020] The PROT signal is related to data security, access rights, or data feature protection. It is usually used to indicate the data access level (such as read-only, read-write, or write-only), the data priority, or when encryption (or security mechanism) is involved, whether the data needs special security processing (such as encryption, decryption, or signature verification). The WRITE signal is used to indicate a data write operation.

[0021] Since a group of AHB input agents and APB input agents can only generate one sel signal respectively, multiple groups of APB selection input agents and AHB selection input agents are designed, so that the sel_in signal can be randomly selected by defining multi-bit (such as 16bit or 10bit) variables in the APB selection input agent and the AHB selection input agent, and the SEL signal of the AHB input agent and the APB input agent is used to select, so that the SEL signal that complies with the protocol (such as the APB bus protocol and the AHBAPB bus protocol) can be generated. In this way, the need to instantiate more groups of AHB input agents or APB input agents to increase the redundancy of the verification system can be effectively avoided, so as to improve the simulation speed.

[0022] The APB selection input agent and the AHB selection input agent are used to output multiple groups of sel_in (select input) signals generated by the SEL signal selection to the PPU module to be verified, and also to the reference model for use. The PPU module to be verified will give the sel_out (select output) signal corresponding to the sel_in signal according to the authority (that is, sel_out is 0 after interception, and sel_out is 1 if not intercepted). The sel_out signal is collected by the corresponding AHB selection output agent and APB selection output agent and sent to the scoreboard as the actual interception result. The reference model generates the expected sel_out signal after receiving the sel_in signal, and sends it to the scoreboard as the expected interception result of the corresponding port of the PPU module to be verified.

[0023] The PPU module usually communicates with other components through the AHB bus interface and the APB bus interface. In this embodiment, the PPU module to be verified as the design under test (DUT) is connected through multiple AHB input agents and APB input agents. Among the n groups of AHB input agents and m groups of APB input agents, n and m are both positive integers, and their specific values ​​can be configured according to the actual verification requirements of the PPU module to be verified. Each AHB input agent and APB input agent sends a data packet that complies with the bus protocol through a corresponding sequence. These data packets can include, but are not limited to, read and write operations, access types (prot) and target addresses. The content of the data packet can randomly simulate different access modes, such as privileged mode (or user mode), different read and write operations, and different transmission types (such as continuous transmission).

[0024] The access of different hosts to peripherals can be simulated by i groups of APB selection input agents and j groups of AHB selection input agents. The number of accesses, access targets, and host identity identifiers (i.e., master_id) used during access for each host can be randomly generated, so various possible access scenarios can be traversed and verified. Among them, i and j are both positive integers, and their specific values ​​can be configured according to the actual verification requirements of the PPU module to be verified.

[0025] The registers of the PPU module can be configured through the APB bus. Optionally, the permission configuration of the PPU module in each simulation can be performed through the random register model, such as but not limited to configuring channel switches, register privileged write permissions and host access permissions, etc. In this way, the verification system can randomize different register configurations of the PPU module through the register model to simulate multiple access scenarios.

[0026] About the reference model and interception mechanism: The reference model can obtain and parse the register configuration in the register model, and make interception judgments when receiving APB bus access or AHB bus access. The reference model is consistent with the data packets received by the DUT. The reference model determines whether access needs to be intercepted by calculating the received data packets. When the corresponding interface is intercepted, the reference model will pass the interception information to the scoreboard as the expected interception result.

[0027] The monitors of the i-group APB bus and the j-group AHB bus are respectively set in the multiple groups of AHB selection output agents and the multiple groups of APB selection output agents to monitor the SEL (selection) signal and TRANS signal (this signal only exists on the AHB bus) of the APB bus access and AHB bus access. When the access is intercepted, the corresponding monitor will send the actual interception result (that is, the interception information of the corresponding interface of the PPU module) to the scoreboard. The scoreboard will compare the expected interception result with the actual interception result of the corresponding interface in real time. If there is any inconsistency, the verification system will output the error status information, and can perform automatic checks to help the verification personnel quickly locate the problem corresponding to the error status information.

[0028] The base test case (i.e., base_testcase) provides a randomized verification method, including random constraints on the register configuration, data packet number, and data packet content of the PPU module (such as chip select sel, transmission type definition htrans, burst transmission type definition hburst, address and access permissions or attribute definition prot, etc.). The base test case can derive different sub-test cases to flexibly control data packets and verification strategies. This verification method can achieve comprehensive verification of the PPU module at the module level, while improving the flexibility and efficiency of verification.

[0029] The above-mentioned PPU module verification system based on the UVM verification platform can simulate the parallel access of multiple hosts to the PPU module by configuring randomness through the establishment of a module-level verification system, and traverse various possible scenarios, thereby improving the verification efficiency and ensuring the integrity of the verification. It supports module-level simulation verification immediately after the development of the PPU module is completed. Compared with the verification technology after the traditional integrated chip, it greatly advances the discovery time of potential problems to facilitate early correction, avoiding high-cost modifications and long cycles in the later stage; through the parameterization of the APB and AHB interfaces, it can flexibly respond to changes in the number of cores and dynamically adjust the verification cases without redesigning the verification system, which greatly improves the reusability of the verification system and reduces the workload of repeated verification in different projects and configurations. By directly generating data packets of valid protocols instead of relying on the system configuration core to initiate access, it ensures comprehensive verification of all PPU module storage spaces, covering various access scenarios such as read / write, user / privilege, and instruction / data. In this way, through technologies such as module-level simulation, interface parameterization and automatic expectation generation, the problems of delayed timing, insufficient coverage, poor reusability and low efficiency in traditional verification technology are effectively solved, the verification capability of the PPU module is greatly improved, and a more efficient, flexible and complete PPU module verification solution is provided.

[0030] In addition, VIP can be used to simulate burst transmission, further ensuring the completeness of verification. The verification system integrates the PPU module to be verified and automatically generates the expected interception results through the reference model, and automatically compares them with the actual interception results, which can significantly reduce the workload of verification personnel and speed up the simulation process. Compared with the traditional manual comparison method, it significantly improves the verification efficiency and shortens the simulation time.

[0031] The specific verification workflow of the PPU module verification system based on the UVM verification platform can be as follows: Figure 2As shown: After the verification system is started, the register configuration of the PPU module to be verified is randomly configured by configuring the register model, and the random register configuration of the register model is sent to the reference model and written to the register of the PPU module to be verified through the APB bus. Then, the corresponding AHB selection input agent and APB selection input agent output selection input signal are randomly selected through the APB input agent and the AHB input agent, so that the corresponding AHB selection input agent and the APB selection input agent respectively randomly generate corresponding AHB stimulus and APB stimulus, send the stimulus to the reference model, and send the stimulus to the PPU module to be verified through the respective drivers of the input agents based on their respective bus protocols. The reference model will calculate the interception required after each data stimulus and send the interception information as the expected interception result to the scoreboard. The monitors of each AHB selection output agent and APB selection output agent send the actual interception result generated by the PPU module to be verified to the scoreboard, and the scoreboard compares the expected interception result with the corresponding actual interception result in real time. If it is inconsistent (that is, the interception does not meet expectations), an error is reported, and then the above working steps are repeated until all the stimuli of this verification are sent, and the simulation ends.

[0032] In one embodiment, the scoreboard in the PPU module verification system based on the UVM verification platform is also used to locate errors according to the error status information.

[0033] Specifically, these error status information can be used to determine which link caused the error problem in the scoreboard. Whenever the input or output is valid, the scoreboard will count and determine whether the input and output data collected are equivalent, so as to determine whether the packet is lost; if it is a permission problem, the scoreboard will print the corresponding error information through the uvm_err message to determine which permission caused the error. In addition, the corresponding waveform will be generated based on the above platform operation. The input and output waveforms of the PPU module can be seen through the simulation tool Verdi, and because the PPU module responds immediately, it can be determined whether there is a corresponding sel_out (select output) signal output according to the permission when the SEL signal is input, so as to determine whether there is a problem. Among them, the Verification IP used by the APB input agent and the AHB input agent of the verification system will check the timing of the generated signal. The sel_in (select input) signal generated by the APB selection input agent and the AHB selection input agent is also generated by the Verification IP SEL signal selection, that is, when the SEL signal is valid, the sel_in signal is valid.

[0034] Each component in the PPU module verification system based on the UVM verification platform can be implemented in whole or in part by software, hardware and their combination. The above components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. The aforementioned device can be, but is not limited to, various types of chip verification computers available in the art.

[0035] In one embodiment, a PPU module verification method based on a UVM verification platform is provided, which is applied to a PPU module verification system based on a UVM verification platform, including a register model, a reference model, a scoreboard, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, multiple groups of APB selection output agents, and a PPU module to be verified. The register model, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, and multiple groups of APB selection output agents are respectively connected to the PPU module to be verified, the reference model is respectively connected to the register model and the scoreboard, and multiple groups of AHB selection output agents and multiple groups of APB selection output agents are respectively connected to the scoreboard. The register model is used to randomize the different register configurations of the PPU module to be verified and simulate various access scenarios of the PPU module to be verified. The reference model is used to obtain and parse the register configuration of the PPU module to be verified and output the expected interception result to the scoreboard when the APB bus access or AHB bus access is intercepted.

[0036] Multiple groups of APB input agents are used to use VIP to generate a group of SEL signals, PROT signals and WRITE signals that comply with the APB bus protocol standard. Multiple groups of AHB input agents are used to use VIP to generate a group of SEL signals, TRANS signals, PROT signals and WRITE signals that comply with the AHB bus protocol standard. Multiple groups of AHB selection output agents are used to monitor the output data of each AHB interface of the PPU module to be verified and send the actual interception results generated to the scoreboard. Multiple groups of APB selection output agents are used to monitor the output data of each APB interface of the PPU module to be verified and send the actual interception results generated to the scoreboard. The scoreboard is used to compare the expected interception results with the actual interception results of the corresponding interfaces in real time. If the interception results are inconsistent, error status information is output.

[0037] like Figure 3 As shown, the PPU module verification method based on the UVM verification platform may include the following steps S10 to S20: S10, after the current verification is started, the register configuration of the PPU module to be verified is randomly configured by configuring the register model; wherein the register configuration randomly configured by the register model is sent to the reference model and simultaneously written to the register of the PPU module to be verified through the APB bus; S12, respectively outputting multiple groups of selection input signals generated by the SEL signals of corresponding APB input agents to the PPU module to be verified and the reference model through multiple groups of APB selection input agents, and respectively outputting multiple groups of selection input signals generated by the SEL signals of corresponding AHB input agents to the PPU module to be verified and the reference model through multiple groups of AHB selection input agents; S14, calculating the interception required after each data stimulus through the reference model and sending the interception information as the expected interception result to the scoreboard; S16, sending the actual interception result generated by the PPU module to be verified to the scoreboard through the monitors of each AHB selection output agent and the APB selection output agent; S18, the scoreboard compares the expected interception result with the corresponding actual interception result in real time to see if they are consistent, and reports an error if they are inconsistent; S20, returning to the above step S10, and ending the simulation after all stimuli for this verification are sent.

[0038] The above-mentioned PPU module verification method based on the UVM verification platform, by establishing a module-level verification system, can simulate the parallel access of multiple hosts to the PPU module by configuring randomness, and traverse various possible scenarios, thereby improving the verification efficiency and ensuring the integrity of the verification. It supports module-level simulation verification immediately after the development of the PPU module is completed. Compared with the verification technology after the traditional integrated chip, it greatly advances the discovery time of potential problems to facilitate early correction, avoiding high-cost modifications and long cycles in the later stage; through parameterization of the APB and AHB interfaces, it can flexibly respond to changes in the number of cores and dynamically adjust verification cases without redesigning the verification system, greatly improving the reusability of the verification system and reducing the workload of repeated verification in different projects and configurations. By directly generating data packets of valid protocols instead of relying on the system configuration core to initiate access, comprehensive verification of all PPU module storage spaces is ensured, covering various access scenarios such as read / write, user / privilege, and instruction / data. In this way, through technologies such as module-level simulation, interface parameterization and automatic expectation generation, the problems of delayed timing, insufficient coverage, poor reusability and low efficiency in traditional verification technology are effectively solved, the verification capability of the PPU module is greatly improved, and a more efficient, flexible and complete PPU module verification solution is provided.

[0039] In one embodiment, the permission configuration of the PPU module in each random simulation of the register model includes configuring a channel switch, a register privilege write permission, and a host access permission.

[0040] In one embodiment, the above-mentioned PPU module verification method based on the UVM verification platform may also include the steps of: Use the scoreboard to locate errors based on error status information.

[0041] For the specific limitations of the PPU module verification method based on the UVM verification platform, please refer to the corresponding limitations of the PPU module verification system based on the UVM verification platform above, which will not be repeated here.

[0042] It should be understood that although Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0043] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0044] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A PPU module verification system based on UVM verification platform, characterized in that: Including register model, reference model, scoreboard, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, multiple groups of APB selection output agents and PPU modules to be verified; The register model, multiple groups of the AHB input agents, multiple groups of the APB input agents, multiple groups of the APB selection input agents, multiple groups of the AHB selection input agents, multiple groups of the AHB selection output agents, and multiple groups of the APB selection output agents are respectively connected to the PPU module to be verified, the reference model is respectively connected to the register model and the scoreboard, and multiple groups of the AHB selection output agents and multiple groups of the APB selection output agents are respectively connected to the scoreboard; The register model is used to randomize different register configurations of the PPU module to be verified, simulate various access scenarios of the PPU module to be verified, and the reference model is used to obtain and parse the register configuration of the PPU module to be verified, and output the expected interception result to the scoreboard when the APB bus access or AHB bus access is intercepted; The multiple groups of APB input agents are respectively used to use VIP to generate a group of SEL signals, PROT signals and WRITE signals that comply with the APB bus protocol standard. The multiple groups of AHB input agents are respectively used to use VIP to generate a group of SEL signals, TRANS signals, PROT signals and WRITE signals that comply with the AHB bus protocol standard. The multiple groups of AHB selection input agents are respectively used to output multiple groups of selection input signals generated by the SEL signal selection of the corresponding AHB input agents to the PPU module and the reference model to be verified. The multiple groups of APB selection input agents are respectively used to output multiple groups of selected input signals generated by the corresponding SEL signal selection of the AHB input agents to the PPU module and the reference model to be verified. The selection input signal generated by the SEL signal selection of the APB input agent is sent to the PPU module to be verified and the reference model, and multiple groups of the AHB selection output agents are respectively used to monitor the output data of each AHB interface of the PPU module to be verified and send the generated actual interception results to the scoreboard. Multiple groups of the APB selection output agents are respectively used to monitor the output data of each APB interface of the PPU module to be verified and send the generated actual interception results to the scoreboard. The scoreboard is used to compare the expected interception results with the actual interception results of the corresponding interfaces in real time. If the interception results are inconsistent, error status information is output.

2. The PPU module verification system based on the UVM verification platform according to claim 1, characterized in that, The register model randomly configures the permissions of the PPU module in each simulation, including configuring channel switches, register privileged write permissions, and host access permissions.

3. The PPU module verification system based on the UVM verification platform according to claim 1 or 2, characterized in that, The scoreboard is also used to locate errors according to the error status information.

4. A PPU module verification method based on UVM verification platform, characterized in that: The invention is applied to a PPU module verification system based on a UVM verification platform, including a register model, a reference model, a scoreboard, multiple groups of AHB input agents, multiple groups of APB input agents, multiple groups of APB selection input agents, multiple groups of AHB selection input agents, multiple groups of AHB selection output agents, multiple groups of APB selection output agents and a PPU module to be verified; The register model, multiple groups of the AHB input agents, multiple groups of the APB input agents, multiple groups of the APB selection input agents, multiple groups of the AHB selection input agents, multiple groups of the AHB selection output agents, and multiple groups of the APB selection output agents are respectively connected to the PPU module to be verified, the reference model is respectively connected to the register model and the scoreboard, and multiple groups of the AHB selection output agents and multiple groups of the APB selection output agents are respectively connected to the scoreboard; The register model is used to randomize different register configurations of the PPU module to be verified, simulate various access scenarios of the PPU module to be verified, and the reference model is used to obtain and parse the register configuration of the PPU module to be verified, and output the expected interception result to the scoreboard when the APB bus access or AHB bus access is intercepted; The multiple groups of APB input agents are respectively used to use VIP to generate a group of SEL signals, PROT signals and WRITE signals that comply with the APB bus protocol standard, the multiple groups of AHB input agents are respectively used to use VIP to generate a group of SEL signals, TRANS signals, PROT signals and WRITE signals that comply with the AHB bus protocol standard, the multiple groups of AHB selection output agents are respectively used to monitor the output data of each AHB interface of the PPU module to be verified and send the generated actual interception results to the scoreboard, the multiple groups of APB selection output agents are respectively used to monitor the output data of each APB interface of the PPU module to be verified and send the generated actual interception results to the scoreboard, the scoreboard is used to compare the expected interception results with the actual interception results of the corresponding interfaces in real time, and if the interception results are inconsistent, the error status information is output; The PPU module verification method based on the UVM verification platform comprises the following steps: After the current verification is started, the register configuration of the PPU module to be verified is randomly configured by configuring the register model; wherein the register configuration randomly configured by the register model is sent to the reference model and simultaneously written to the register of the PPU module to be verified through the APB bus; Outputting multiple groups of selection input signals generated by the SEL signals of the corresponding APB input agents to the PPU module and the reference model to be verified through multiple groups of the APB selection input agents, and outputting multiple groups of selection input signals generated by the SEL signals of the corresponding AHB input agents to the PPU module and the reference model to be verified through multiple groups of the AHB selection input agents; The reference model will calculate the required interception after each data stimulus and send the interception information to the scoreboard as the expected interception result; Sending the actual interception result generated by the PPU module to be verified to the scoreboard through the monitors of each AHB selection output agent and the APB selection output agent; The scoreboard compares the expected interception result with the corresponding actual interception result in real time to see if they are consistent, and reports an error if they are inconsistent; Return to the step of randomly configuring the register configuration of the PPU module to be verified by configuring the register model, and end the simulation after all stimuli for this verification are sent.

5. The PPU module verification method based on UVM verification platform according to claim 4, characterized in that, The register model randomly configures the permissions of the PPU module in each simulation, including configuring channel switches, register privileged write permissions, and host access permissions.

6. The PPU module verification method based on the UVM verification platform according to claim 4 or 5, characterized in that, Also includes the steps: The error is located according to the error status information through the scoreboard.

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