A hardware abstraction-based tensor computation compilation optimization method and system

Abstract

The application relates to a hardware abstraction-based tensor calculation compilation optimization method and system, and the method comprises the following steps: a hardware model is constructed to describe hardware-related information; an optimization abstraction method commonly used in operator optimization is constructed, the backend optimization of an operator by a compiler is decomposed into flexible combinations of a plurality of optimization abstraction methods; based on the hardware model and optimization abstraction method selection rules, a suitable optimization abstraction method combination is selected, a code generation skeleton is constructed; parameters in the code skeleton which are not determined are searched, a parameter search space is pruned by using the hardware model, and the pruned optional parameters are saved; and target code suitable for a target calculation platform is generated according to an intermediate representation after optimization by using the optimization abstraction method. Compared with the prior art, the application has strong adaptability, a flexible optimization mechanism and efficient tuning capability, and is particularly suitable for executing high-performance tensor calculation tasks on a multi-heterogeneous calculation platform.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer technology, and in particular to a tensor computing compilation optimization method and system based on hardware abstraction. BACKGROUND

[0002] With the increasing diversification of hardware architectures, how to efficiently execute deep learning tasks on multi-heterogeneous computing platforms has become a major challenge in current technology. The compiler community has successfully established a strong modern compiler infrastructure, such as GCC (GNU Compiler Collection), MLIR (Multi-Level Intermediate Representation), and LLVM.

[0003] MLIR (Multi-Level Intermediate Representation) is a general-purpose compiler infrastructure that supports multi-level and multi-domain optimization in a modular and extensible way. The design of MLIR allows the construction of different kinds of intermediate representations (IR) at different levels, which makes it very suitable for tensor computing compilation optimization methods based on hardware abstraction. Through MLIR, developers can define and use custom intermediate representations to describe hardware abstraction and optimization strategies, and can perform efficient optimization across multiple levels during compilation. At the same time, the flexibility of MLIR allows it to easily adapt to the characteristics of different hardware architectures, enabling efficient code generation for specific hardware platforms, thereby greatly improving the execution efficiency of tensor computing tasks. MLIR is tightly integrated with LLVM, allowing it to utilize LLVM's backend toolchain for code generation. The low-level IR in MLIR can be further converted to LLVM IR, taking advantage of LLVM's powerful backend support to generate highly optimized target code.

[0004] Modern compilers usually adopt a three-stage architecture, dividing the compiler into front-end, middle-end and back-end. The front-end and middle-end are often hardware-independent optimizations, which can be reused when supporting new target architectures. The back-end optimization is closely related to the hardware architecture and cannot be reused. This development mode, although to some extent, improves the portability of the compiler, but for heterogeneous computing platforms, the differences between different hardware architectures are huge, leading to complex and tedious back-end code generation and optimization work. Existing compiler back-ends usually need to be manually adapted for different hardware platforms, writing specific optimization code, which not only consumes time and effort, but also easily leads to poor reusability of optimization strategies between different platforms, reducing compilation efficiency.

[0005] In order to solve the above problems, there is an urgent need for a compilation optimization method that can automatically adapt to multi-heterogeneous computing platforms. SUMMARY

[0006] In order to solve the above technical problems, the present application provides a tensor calculation compilation optimization method and system based on hardware abstraction, to solve the tensor calculation compilation optimization problem on multiple heterogeneous computing platforms in the prior art. By introducing a hardware abstraction model and optimization abstraction technology, the present application can flexibly adjust the optimization strategy on multiple hardware platforms, and improve the execution efficiency of the tensor calculation task and the adaptability of the compiler.

[0007] The technical solution of the present application is: a tensor calculation compilation optimization method based on hardware abstraction, comprising:

[0008] Step S1: a hardware model is constructed to describe hardware-related information, and the hardware model comprises two parts: a module unit description part and an overall unit description part;

[0009] Step S2: an optimization abstraction method commonly used for operator optimization is constructed, the optimization abstraction method comprises a transformation rule for an intermediate representation and a condition required to be met by hardware when the optimization abstraction method is used, and the backend optimization of the compiler for the operator is decomposed into a flexible combination of several optimization abstraction methods;

[0010] Step S3: based on the hardware model and the optimization abstraction method selection rule, a suitable optimization abstraction method combination is selected, and a code generation skeleton is constructed;

[0011] Step S4: the parameters in the code skeleton that are not determined are searched, the parameter search space is pruned by using the hardware model, and the selected parameters after pruning are saved;

[0012] Step S5: target code suitable for a target computing platform is generated according to the intermediate representation after the optimization abstraction method is compiled and optimized.

[0013] Step S6: all generated target codes are evaluated, and the best configuration is selected.

[0014] A tensor calculation compilation optimization system based on hardware abstraction comprises the following modules:

[0015] A hardware model construction module is used to construct a hardware model to describe hardware-related information, and the hardware model comprises two parts: a module unit description part and an overall unit description part;

[0016] An optimization abstraction construction module is used to define and construct an optimization abstraction method, the optimization abstraction method comprises a transformation rule for an intermediate representation and a condition required to be met by hardware when the optimization abstraction method is used, and the backend optimization of the compiler for the operator is decomposed into a combination of several optimization abstraction methods;

[0017] A code skeleton construction module is used to select a suitable optimization abstraction method combination based on the hardware model and the optimization abstraction method selection rule, and construct a code generation skeleton.

[0018] Parameter pruning module: used for searching for undetermined parameters in the code generation skeleton, pruning the parameter search space by using the hardware model, and saving the pruned optional parameters;

[0019] Backend code generation module: used for generating target code suitable for the target hardware platform according to the optimized intermediate representation, and evaluating all generated target codes to select the best configuration.

[0020] Compared with the prior art, the present application has the following beneficial effects:

[0021] 1. The existing deep learning compiler directly divides the compilation stack into two layers of hardware-independent optimization and hardware-related optimization when performing deep learning model compilation optimization. Since the hardware-independent layer lacks hardware-related information, the optimization related to the compilation backend often needs to be calculated and one-to-one adapted to the backend, which not only brings a complex development workload, but also loses the ability to freely combine various optimization methods.

[0022] 2. The existing compilation framework needs to traverse a huge search space when performing automatic tuning of operators due to the lack of hardware information guidance, and the search time is too long.

[0023] 3. The present application introduces a hardware abstraction model to uniformly describe the computing units and memory structures of different hardware platforms, and combines optimization abstraction technology to automatically adjust the optimization strategy according to the hardware characteristics during the compilation process, thereby improving the adaptability and optimization efficiency of the compiler. Not only simplifies the development process of the compiler backend, but also can realize efficient tensor calculation optimization on different hardware platforms. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 The flowchart of the tensor calculation compilation optimization method based on hardware abstraction in the embodiment of the present application;

[0025] Figure 2 The hardware memory hierarchy construction diagram in the embodiment of the present application;

[0026] Figure 3 The schematic diagram of the computing hierarchy in the embodiment of the present application;

[0027] Figure 4 The schematic diagram of the overall hardware hierarchy in the embodiment of the present application;

[0028] Figure 5 The block optimization schematic diagram in the embodiment of the present application;

[0029] Figure 6 The memory localization optimization schematic diagram in the embodiment of the present application;

[0030] Figure 7 Schematic diagram of pipeline optimization in an embodiment of the present invention;

[0031] Figure 8 A schematic diagram of generating high-performance target code suitable for a target computing platform in an embodiment of the present invention;

[0032] Figure 9 Schematic block diagram of a tensor computing compilation and optimization system based on hardware abstraction in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention provides a tensor computing compilation optimization method and system based on hardware abstraction, designs a unified hardware abstraction applicable to different hardware, and builds a set of optimization pipelines based on it.

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below through specific implementation and in conjunction with the accompanying drawings.

[0035] Example 1

[0036] like Figure 1 As shown, an embodiment of the present invention provides a tensor calculation compilation optimization method based on hardware abstraction, comprising the following steps:

[0037] Step S1: Constructing a hardware model to describe hardware related information, wherein the hardware model includes two parts: a module unit description part and an overall unit description part;

[0038] Step S2: Construct an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware must meet when using the optimization abstraction method. The compiler's back-end optimization of the operator is decomposed into a combination of several optimization abstractions.

[0039] Step S3: Based on the hardware model and the optimization abstraction method selection rules, select a suitable combination of optimization abstraction methods to build a code generation skeleton; wherein, the optimization abstraction method selection rules refer to selecting a suitable optimization abstraction based on the limitations of the hardware model, combined with the experience of experts and existing performance analysis results.

[0040] Step S4: Search for undetermined parameters in the code skeleton, prune the parameter search space using the hardware model, and save the pruned optional parameters;

[0041] Step S5: Generate target code suitable for the target computing platform based on the optimized intermediate representation compiled by the optimization abstraction method.

[0042] Step S6: Evaluate all generated target codes and select the best configuration.

[0043] In one embodiment, the above step S1: constructing a hardware model to describe hardware related information, the hardware model includes two parts: a module unit description part and an overall unit description part, including: obtaining a complete hardware model by analyzing the target hardware, specifically including:

[0044] Step S11: Analyze the basic component modules of the target hardware, including analysis of the computing unit level and analysis of the storage unit level.

[0045] Storage units play a crucial role in hardware architecture, and their performance directly affects the computing efficiency of the entire system. Specifically, the properties of storage units include the following aspects:

[0046] Basic attributes: These include the name and type of the storage unit, such as cache, register, global memory, shared memory, etc. Each storage unit has a specific role and purpose and needs to be accurately identified and distinguished.

[0047] Size information: Describes the capacity of a storage unit. The size of a storage unit directly affects how data is stored and its availability during computation. For example, a larger cache or global memory can store more data but has higher access latency; while registers, while smaller in capacity, offer extremely fast access speeds.

[0048] Storage bandwidth: This refers to the data transfer capacity of a storage unit, typically measured in GB / s (gigabytes per second). Storage bandwidth affects the speed of data transfer and is crucial for data-intensive tasks in high-performance computing.

[0049] Programmability of the storage hierarchy: This property describes whether storage units can be explicitly allocated and managed. For example, some levels of storage (such as shared memory or registers) can be explicitly allocated and used by the programmer through a programming interface.

[0050] Concurrent read capability: The bank structure of a memory cell describes its concurrent access capability. Multiple banks allow multiple threads or computational units to access different data simultaneously, thereby improving the parallelism and data throughput of the memory cell.

[0051] A computational unit contains actual or logical computational units. Computational units typically have a multi-level organizational structure in the hardware architecture. These structures determine how computational tasks are divided and allocated to different hardware resources. In addition, the properties of a computational unit should also include a description of the nature of hardware instructions:

[0052] Vectorization width of instructions: The vectorization width of instructions describes the number of data elements that a single instruction can act on simultaneously. Modern computing units often support SIMD (Single Instruction, Multiple Data) instructions, which can process multiple data elements in a single operation, thereby improving computational efficiency.

[0053] Instruction latency and throughput: Instruction latency refers to the time required from the issuance of an instruction to its completion of execution, usually expressed in the number of clock cycles. Different types of instructions have different latency characteristics, with complex instructions such as floating-point division typically having longer latency, while simple instructions such as addition have shorter latency. Instruction throughput refers to the number of instructions that a computing unit can complete in a unit of time. High throughput means that the computing unit can quickly process a large number of instructions, improving overall computational efficiency.

[0054] Instruction-level parallelism: Instruction-level parallelism (ILP) refers to the ability of a computing unit to execute multiple instructions in parallel within the same clock cycle when executing a program.

[0055] Step S12: Construct the overall unit description part responsible for describing the hierarchical relationship between module units, according to the basic component modules of the target hardware obtained in S11, and combine the design of the target hardware to construct the organization information between modules.

[0056] The overall unit description part is responsible for describing the hierarchical relationship between module units and thread organization. The structure of the hardware is composed of multiple nestable hardware blocks. In each layer of hardware block, the processing unit organization and the contained module unit information at the current level are described. The module unit description part describes the computing unit situation and the memory unit situation at this level, and constructs the parent-child blocks of the hardware block. At the same time, for the processing unit at the innermost layer, the complete description of the hardware instruction related information is mounted to this block. After constructing the tree-like relationship between hardware blocks, the access relationship between hardware can be analyzed. The child hardware block can access the module units of the parent hardware block, and vice versa. Hardware blocks without parent-child relationship cannot access each other's internal module units.

[0057] The following describes the construction of the hardware model taking the NVIDIA GPU as an example.

[0058] Based on the above steps, the hardware model of the NVIDIA GPU is constructed. The memory hierarchy of the NVIDIA GPU is divided into three levels: global memory, shared memory, and register file. The attributes of the three levels are shown in Figure 2 The NVIDIA GPU is divided into several computing levels: thread grid, thread block, thread bundle, and thread. The attributes of the several computing levels are shown in Figure 3The overall unit description part of the hierarchy relationship between the module units is constructed based on a comprehensive analysis of the GPU hardware, as shown in FIG. 2. Figure 4

[0059] Step S2: An optimization abstraction method commonly used for optimization is constructed, the optimization abstraction method includes a transformation rule for the intermediate representation and a condition required to be met by the hardware when the optimization abstraction method is used, and the backend optimization of the compiler for the operator is decomposed into a flexible combination of several optimization abstraction methods.

[0060] In one embodiment, the above step S2 specifically includes:

[0061] Step S21: An optimization abstraction is defined, the optimization abstraction is expressed as a specific modification to the intermediate representation when a specific pattern in the intermediate representation is identified; and a hardware requirement capable of using the optimization abstraction method is set.

[0062] The definition of the optimization abstraction is to abstract the complex optimization process and express it as a mechanism for identifying a specific pattern in the intermediate representation (IR) and performing a corresponding transformation. Therefore, when the optimization abstraction identifies a certain pattern in the IR (such as a matrix multiplication or a data parallel operation), a specific modification is performed on these patterns to improve the computational efficiency, data locality, or resource utilization. The specific modification is a modification for a specific pattern, such as performing a blocking operation on the matrix multiplication when the pattern is an operation of identifying a matrix multiplication. In addition, in order to ensure the availability of the optimization, a corresponding hardware requirement is also set. These requirements usually include support for a specific instruction set, hardware features (such as local memory, vectorization capability), or configuration of parallel computing resources.

[0063] In the process of constructing the optimization abstraction method, the present application widely reuses the components of various dialects in MLIR. The dialect in MLIR can be regarded as a set of operators and types, which can provide support for a specific field or hardware architecture. When constructing the optimization abstraction, we prefer to use hardware-independent dialects, such as Linalg (used for the description of linear algebra operations), SCF (used for the representation of control flow), Vector (used for the representation of vectorization operations), and Memref (used for the description of memory references). Through these dialects, we can describe the logic and flow of the optimization abstraction without relying on specific hardware implementations.

[0064] Step S22: A general optimization abstraction method is constructed, including a blocking optimization, a local memory optimization, a pipeline optimization, and a vectorization optimization.

[0065] ​Definition of data blocking optimization: the blocking optimization requires that there is no data dependency in the dimension being blocked. The blocking technique decomposes a large data block into smaller sub-data blocks, so that these sub-data blocks can be on different levels of storage units and can be processed by different levels of computing units. Figure 5 The scenario of blocking optimization in optimizing matrix multiplication application is demonstrated, and the matrix multiplication operator is thread block, thread bundle, and instruction level blocking.

[0066] Definition of data localization optimization: the data localization optimization requires that the hardware unit has a local cache. The implementation of the optimization method is to detect the read and write of the higher layer memory in the IR, convert it to the copy of the higher layer memory to the local memory, and convert the read and write of the high layer memory in the IR to the read and write of the local memory. Figure 6 The modification of the data localization optimization to the IR is demonstrated.

[0067] Definition of computation pipeline optimization: the pipeline optimization requires that the hardware supports instruction set parallelism, allows multiple instructions to be completed on different execution units in the same clock cycle, so as to achieve the purpose of delay masking. Figure 7 The application scenario of the computation pipeline optimization is demonstrated.

[0068] Vectorization optimization requires that the hardware computing unit supports vectorization instructions and can operate multiple data in a single instruction. By blocking the vectorization computation size in the innermost layer of computation, the implementation of vectorization optimization can be quickly completed.

[0069] Step S23: According to the different computing tasks, the specific optimization method for specific tasks is realized based on the construction method of optimization abstraction method. This step includes: for some specific optimization scenarios, the compiler staff constructs new hardware-independent optimization according to the optimization abstraction construction method proposed in step S21, and completes the supplementary addition of new optimization.

[0070] In one embodiment, the above step S3: based on the hardware model and the optimization abstraction method selection rule, the appropriate optimization abstraction method combination is selected to construct the code generation skeleton, which specifically includes:

[0071] Step S31: Traverse all available optimization abstraction methods. Optimization abstraction includes a series of techniques that have been verified to improve computing performance, such as data blocking, instruction vectorization, data localization, and pipeline parallelism. Each optimization abstraction has its corresponding hardware requirements, for example, vectorization requires hardware support for SIMD (Single Instruction, Multiple Data) instruction sets, and data localization optimization requires the existence of low-latency local memory (such as shared memory or registers). During the traversal process, the system will evaluate each optimization abstraction method based on the characteristics of the current hardware model (such as the memory hierarchy of the hardware, parallel computing capability, instruction set support, etc.), and filter out those optimization abstraction methods that are feasible in the current hardware environment.

[0072] Step S32: Construct the most original optimization abstraction method selection rules based on expert experience, select the available optimization abstraction methods according to the optimization selection rules, and transform the intermediate representation to form the code skeleton. The system will construct the most original optimization abstraction method selection rules based on expert experience and existing performance analysis results. The rule set describes the conditions under which a specific combination of optimization abstraction methods should be selected to maximize hardware performance. Specifically, these rules will guide the selection of optimization abstraction methods based on hardware characteristics, the nature of the computing task, and the actual running environment.

[0073] 1. When the computing task involves large-scale matrix operations or convolution operations, preferentially select the data blocking abstraction to fully utilize the on-chip memory resources of the hardware and reduce dependence on global memory.

[0074] 2. When there are frequently accessed intermediate data in the task, select the data localization abstraction and place these data in the shared memory of the hardware to reduce the bottleneck of global memory access.

[0075] 3. Vectorization selection rule: for operations that can be executed on SIMD instructions (such as vector addition, multiplication), preferentially select the instruction vectorization abstraction to improve the parallelism and instruction execution efficiency of the computation.

[0076] 4. For complex computing tasks with explicit dependency relationships and capable of being executed in stages (such as hierarchical operations in deep learning), select the pipeline parallel abstraction to fully utilize the multiple execution units of the hardware and improve throughput.

[0077] These rules will be dynamically adjusted in actual application to form a more adaptive combination of optimization strategies. Through the combination of these optimization abstractions and rules, the IR is finally transformed to generate a code skeleton that conforms to the hardware characteristics, thereby maximizing the performance advantages of the hardware.

[0078] In one embodiment, the step S4 of searching for the undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters, specifically includes:

[0079] Step S41: Determine the parameter search space of the parameters to be optimized. First, identify the undetermined parameters in the code skeleton, which may include computation block size, thread number, memory allocation strategy, etc. These parameters have a significant impact on the performance of the final generated code, so their initial parameter search space needs to be defined. The parameter search space should cover all possible parameter configurations and ensure compatibility with the capacity and characteristics of hardware resources such as registers, shared memory, etc. At the same time, the computing requirements of the task should also be considered to define a sufficiently broad search space to ensure the flexibility and comprehensiveness of the optimization.

[0080] Step S42: Prune the parameter search space using the hardware model to exclude parameter combinations that cannot effectively utilize hardware resources. Since the complete parameter search space is usually too large and inefficient to search directly, pruning is needed with the help of a hardware model. The hardware model provides an abstract description of hardware characteristics and can predict the actual execution effect of different parameter combinations. By analyzing the hardware model, the system can identify parameter combinations that cannot fully utilize hardware resources, such as configurations that cause memory overload or cannot fully utilize computing units, and exclude these inappropriate combinations from the parameter search space. The pruned parameter search space is more compact, reducing unnecessary computational overhead and improving optimization efficiency.

[0081] Step S43: Calculate the data reuse score on each memory level using the hardware model to evaluate and obtain several configurations with higher data reuse scores. In the pruned parameter search space, further evaluate different parameter configurations using the hardware model. The core indicator of the evaluation is the data reuse score, which reflects the efficiency of data being used multiple times on different memory levels. By calculating the data reuse score of each configuration, the system can determine which parameter configurations can maximize memory bandwidth utilization and reduce memory access delay. Finally, save several configurations with higher data reuse scores to ensure that the generated code can run efficiently on the target hardware. Here, higher refers to, for example, the top 5-10% of scores, or other score configurations. Those skilled in the art can configure according to actual needs, and the present application is not limited in this regard.

[0082] In one embodiment, the step S5 of generating target code suitable for the target computing platform according to the optimized intermediate representation compiled using the optimization abstraction method, specifically includes the following steps:

[0083] Reference can be made to Figure 8 The following steps are described,Figure 8 The transformation of hardware-independent IR to hardware-dependent IR is shown.

[0084] Step S51: mapping hardware-independent computation unit index to hardware-specific computation unit index. The compiler first analyzes the computation unit index in the hardware-independent intermediate representation (IR), such as logical thread, block index, etc. These indexes are hardware-independent and not bound to a specific hardware platform. Next, the compiler maps these abstract indexes to specific physical computation unit indexes on the target hardware platform. For example, in a GPU architecture, a logical thread can be mapped to a specific thread index, and a logical block can be mapped to a specific thread block index.

[0085] Step S52: mapping hardware-independent computation and memory access instructions to computation and memory access instructions on specific hardware. The compiler converts the hardware-independent instructions in the intermediate representation to a low-level instruction set suitable for the target hardware platform. This includes mapping abstract computation instructions (such as matrix multiplication) to specific hardware-supported instructions (such as matrix multiply-add mma instructions), and mapping abstract memory access operations (such as load, store) to memory access instructions of the target platform.

[0086] In one embodiment, the above step S6: evaluating all generated target code to select the best configuration, specifically includes:

[0087] Performing actual measurements on the generated code to find the optimal configuration, and using the relevant information to optimize the selection rules of the abstract optimization during the generation of the code skeleton in step S3.

[0088] Embodiment two

[0089] As shown in Figure 9 The embodiment of the present application provides a hardware abstraction-based tensor computation compilation optimization system, which includes the following modules:

[0090] Hardware model construction module 81: used to construct a hardware model to describe hardware-related information, the hardware model includes two parts: module unit description part and overall unit description part. This module constructs a complete hardware model reflecting the characteristics of the hardware by analyzing the hierarchy of the computation unit and the storage unit of the hardware, as well as the hierarchical relationship between the module units.

[0091] Optimization abstraction construction module 82: used to define and construct optimization abstraction methods, which include transformation rules for the intermediate representation and conditions that the hardware needs to meet when using the optimization abstraction method. The back-end optimization of the compiler for the operator is decomposed into a combination of several optimization abstraction methods. This module includes general optimization methods such as block optimization, optimization using local memory, pipeline optimization, and vectorization optimization, and implements targeted optimization methods according to different computing tasks.

[0092] Code Skeleton Construction Module 83: Based on the hardware model and established optimization abstraction selection rules, it selects an appropriate combination of optimization abstractions to build a code generation skeleton. This module leverages expert experience and optimization selection rules to select the optimization abstractions that best suit the task at hand, resulting in an efficient code structure.

[0093] Parameter Pruning Module 84: This module searches for undetermined parameters in the code generation skeleton, prunes the parameter search space using the hardware model, and saves the pruned optional parameters. This module uses the hardware model to evaluate parameter feasibility, eliminating parameter combinations that don't effectively utilize hardware resources. It also optimizes parameter configurations based on data reuse scores at the memory level.

[0094] Backend Code Generation Module 85: This module generates target code suitable for the target hardware platform based on the optimized intermediate representation and evaluates all generated target code to select the optimal configuration. This module is responsible for mapping hardware-independent computational units and memory access instructions to hardware-specific computational and memory access instructions, ensuring that the generated code maximizes hardware resource utilization.

[0095] The above embodiments are provided for the purpose of describing the present invention only and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims. Various equivalent substitutions and modifications made without departing from the spirit and principles of the present invention are intended to be within the scope of the present invention.

Claims

1. A tensor computing compilation optimization method based on hardware abstraction, characterized in that: include: Step S1: Constructing a hardware model to describe hardware related information, wherein the hardware model includes two parts: a module unit description part and an overall unit description part; Step S2: Construct an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstraction method. The compiler's back-end optimization of the operator is decomposed into a flexible combination of several optimization abstractions. Step S3: Based on the hardware model and the optimization abstraction method selection rules, a suitable combination of optimization abstraction methods is selected to construct a code generation skeleton; Step S4: Search for undetermined parameters in the code skeleton, prune the parameter search space using the hardware model, and save the pruned optional parameters; Step S5: Generate target code suitable for the target computing platform according to the optimized intermediate representation compiled by the optimization abstraction method; Step S6: Evaluate all generated target codes and select the best configuration; Step S1: constructing a hardware model to describe hardware related information. The hardware model includes two parts: a module unit description part and an overall unit description part including: Step S11: analyzing the basic component modules of the target hardware, including analysis of the computing unit level and analysis of the storage unit level; Step S12: Constructing the overall unit description part responsible for describing the hierarchical relationship between the module units; constructing the organizational information between the modules based on the basic component modules of the target hardware analyzed in S11 and combining it with the design of the target hardware; The step S4: searching for undetermined parameters in the code skeleton, pruning the parameter search space using the hardware model, and saving the pruned optional parameters, includes: Step S41: determining a parameter search space of parameters to be optimized; Step S42: pruning the parameter search space using the hardware model to eliminate parameter combinations that cannot effectively utilize hardware resources; Step S43: Utilize the hardware model to evaluate data reuse scores at each memory level, and obtain several configurations with higher data reuse scores.

2. The tensor calculation compilation optimization method based on hardware abstraction according to claim 1 is characterized in that: Step S2: Constructing an optimization abstraction method commonly used for operator optimization. The optimization abstraction method includes the transformation rules for the intermediate representation and the conditions that the hardware needs to meet when using the optimization abstraction method. The compiler's back-end optimization of the operator is decomposed into a flexible combination of several optimization abstraction methods, including: Step S21: defining an optimization abstraction, expressing the optimization abstraction as identifying a certain pattern in the intermediate representation, making specific modifications to the intermediate representation, and setting the hardware requirements for using the optimization method; Step S22: constructing a general optimization abstraction method, including block optimization, local memory optimization, pipeline optimization, and vectorization optimization; Step S23: According to different computing tasks, a specific optimization method for a certain task is implemented based on the construction method of the optimization abstraction method.

3. The tensor calculation compilation optimization method based on hardware abstraction according to claim 1, characterized in that: In step S3, based on the hardware model and the optimization abstraction method selection rule, a suitable combination of optimization abstraction methods is selected to construct a code generation skeleton, including: Step S31: traverse all available optimization abstraction methods and select available optimization abstraction methods according to their requirements on the hardware model; Step S32: Construct the most original optimization abstraction method selection rules based on the expert's experience, select the available optimization abstraction methods according to the optimization selection rules, and transform the intermediate representation to form a code skeleton.

4. The tensor calculation compilation optimization method based on hardware abstraction according to claim 1, characterized in that: Step S5: generating target code suitable for the target computing platform according to the optimized intermediate representation compiled by the optimization abstraction method, including: Step S51: Mapping the hardware-independent computing unit index to a hardware-specific computing unit index; Step S52: Mapping hardware-independent calculation and memory access instructions to calculation and memory access instructions on specific hardware.

5. A tensor computing compilation optimization system based on hardware abstraction, characterized in that: The method for executing any one of claims 1 to 4 comprises the following modules: Hardware model construction module: used to construct a hardware model to describe hardware related information. The hardware model includes two parts: a module unit description part and an overall unit description part; Optimization abstraction building module: used to define and build optimization abstraction methods. Optimization abstraction methods contain transformation rules for intermediate representations and the conditions that the hardware must meet when using the optimization abstraction methods. This module decomposes the compiler's back-end optimization of operators into a combination of several optimization abstraction methods. Code skeleton construction module: used to select appropriate optimization abstraction method combinations based on the hardware model and established optimization abstraction method selection rules to build a code generation skeleton; Parameter pruning module: used to search for undetermined parameters in the code generation skeleton, prune the parameter search space using the hardware model, and save the pruned optional parameters; Backend code generation module: used to generate target code suitable for the target hardware platform based on the optimized intermediate representation, and evaluate all generated target codes to select the best configuration.

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