Multi-prediction-frame real-time display method for target detection algorithm acceleration based on FPGA

Abstract

The invention provides a multi-prediction-frame real-time display method for target detection algorithm acceleration based on an FPGA, and relates to the technical field of target detection deep learning algorithms, and the method comprises the steps: carrying out the post-processing of each block feature map of a regression branch, and generating N prediction frames; the coordinate [(x11, y11), (x21, y21)] of the prediction frame bbox1 is analyzed, the original y11 row mask is read from the BRAM to the one-dimensional register set to serve as an initial value, and the y11 row mask is updated on the one-dimensional register set from the x11 column to the x21 column and written back to the BRAM; updating masks of all the remaining rows from y11 + 1 to y21 in the prediction frame bbox1 row by row and writing the masks back to the BRAM; according to the method, mask updating of the remaining bbox < 2 >-bbox < N > is completed one by one and written back to the BRAM; and carrying out picture drawing on the video stream according to all the updated masks, if the mask is 0, passing through the original picture data, and if the mask is 1, replacing the original picture data with the color of the prediction frame. According to the method, the mask of the picture can be generated in real time, the mask does not need to be generated after all prediction frames are generated, and the reasoning speed can be effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of deep learning algorithms for target detection, and in particular to a method for real-time display of multiple prediction frames based on FPGA-based target detection algorithm acceleration. Background Art

[0002] In the field of computer vision, deep learning algorithms for target detection have become mainstream algorithms. They include the backbone network, the neck network, and the detection head. The current mainstream detection head uses an anchor-free decoupled structure, which separates classification and regression. The detection head will generate a large number of candidate boxes with different confidence levels for the same target, and there will be overlaps between these candidate boxes. Through post-processing (such as non-maximum suppression, NMS), the best target prediction box can be found and redundant prediction boxes can be removed.

[0003] At the edge, FPGA-based target detection deep learning algorithm acceleration needs to meet real-time requirements, which requires not only optimization of the target detection deep learning algorithm (e.g., quantization), but also real-time processing of the display of the prediction box. For images with a high density of detection targets, which contain a large number of prediction boxes, if the mask is generated after all prediction boxes are generated, it will take a long time to calculate and the real-time performance will be poor. Summary of the invention

[0004] Based on the above problems, the purpose of the present invention is to propose a multi-prediction frame real-time display method based on FPGA target detection algorithm acceleration, which can generate image masks in real time without the need to generate masks after all prediction frames are generated, and can effectively improve the reasoning speed.

[0005] The technical solution adopted by the present invention to achieve its invention object is a multi-prediction frame real-time display method based on FPGA target detection algorithm acceleration, comprising the following steps:

[0006] S1, dividing the regression branch feature map of the detection head into several block feature maps;

[0007] S2, each block feature map is post-processed to generate N prediction boxes bbox1~bboxN, where the coordinate information of the nth prediction box bboxN is [(x1 n ,y1 n ),(x2 n ,y2 n )], where (x1 n ,y1 n ) is the coordinate of the upper left corner, (x2 n ,y2 n ) is the coordinate of the lower right corner, 1≤n≤N, N is a positive integer;

[0008] S3, write all prediction boxes into FIFO;

[0009] S4, detect the empty signal of FIFO, when empty is "0", that is, not empty, go to step S5;

[0010] S5. Analyze the coordinates of the prediction box bbox1 [(x1 1 ,y1 1 ),(x2 1 ,y2 1 )];

[0011] S6, read the original y1 from the 640×640 BRAM 1 The row mask is stored in the one-dimensional register group DFF640 as y1 1 The initial value of the row; because the y1 1 Rows may contain masks of previously predicted boxes;

[0012] On the one-dimensional register bank DFF640 from x1 1 Start of column, to x2 1 Column end complete y1 1 The row mask is updated and the updated y1 of the one-dimensional register group DFF640 is 1 The row mask value is written back to y1 of the 640×640 BRAM 1 OK;

[0013] S7, according to the method of step S6, complete the remaining y1 in the prediction box bbox1 line by line 1 +1 to y2 1 The masks of all rows are updated and written back to y1 of the 640×640 BRAM accordingly 1 +1 to y2 1 OK;

[0014] At this time, after steps S6 and S7, the mask update of bbox1 is completed in the 640×640 BRAM;

[0015] S8. According to the method of steps S5 to S7, the mask updates of the remaining prediction boxes bbox2 to bboxN are completed one by one, and the masks are written back to the corresponding positions of the 640×640 BRAM;

[0016] S9. The video stream is framed according to all updated masks in step S8. If the mask is 0, the original image data is used. If the mask is 1, the original image data is replaced with the color of the predicted frame, such as red.

[0017] Furthermore, there are three sizes of the regression branch feature map of the detection head, which are 20×20, 40×40, or 80×80.

[0018] Furthermore, the size of the block feature map is 8×8, and the sizes of the 20×20, 40×40, and 80×80 feature maps after being divided into 8×8 blocks are 3×3, 5×5, and 10×10 respectively. If there are blocks smaller than 8×8 after the division, a "0" operation is performed to fill the size to 8×8.

[0019] Furthermore, the mask update in steps S6 and S7 is performed for y1 1 row and y2 1 row, is from x1 1 to x2 1 All columns of y1 are updated column by column. 1 and y2 1 The rows between them only have x1 1 and x2 1 Two columns update mask;

[0020] Furthermore, the specific logic of the mask update, that is, converting the predicted box coordinates into the mask, is as follows:

[0021] In the idle state, the row address addr_y is 0, the column address addr_x is 0, and the FIFO read enable fifo_rd_en is 0. If the FIFO is not empty, that is, empty == 0, it enters the bbox_loop state;

[0022] In the bbox_loop state, if the FIFO is not empty, that is, empty == 0, it enters the fifo_wait state, the FIFO read enable fifo_rd_en is 1, and the mask completion mask_done is 0. If the FIFO is empty, that is, empty == 1, the FIFO read enable fifo_rd_en is 0. At this time, if all bboxes are generated, that is, bbox_done_flag == 1, the mask completion mask_done is 1, and it enters the idle state;

[0023] In the fifo_wait state, enter the bram_wait state, the FIFO read enable fifo_rd_en is 0, the row address addr_y is y1, and the column address addr_x is x1;

[0024] In the bram_wait state, enter the y_loop state, and the original mask read enable old640_rd_en is 1;

[0025] In the y_loop state, the original mask read enable old640_rd_en is 0. If addr_y == y1 || addr_y == y2, it enters the top_down state. If addr_y < y2 && addr_y > y1, it enters the left state. Otherwise, it enters the mask_update state;

[0026] In the top_down state, the data din_x corresponding to addr_x is 1, the column write enable we_x is 1, and it enters the x_incr state;

[0027] In the x_incr state, the write enable we_x is 0. If addr_x >= x1 && addr_x < x2, the column address addr_x is incremented by 1. Otherwise, it enters the x_loop_end state;

[0028] In the left state, addr_x is x1, the data din_x is 1, the column write enable we_x is 1, and it enters the right state;

[0029] In the right state, addr_x is x2, the data din_x is 1, the column write enable we_x is 1, and it enters the x_loop_end state;

[0030] In the x_loop_end state, addr_x is x1, the data din_x is 0, the column write enable we_x is 0, the row write enable we_y is 1, and it enters the mask_update state;

[0031] In the mask_update state, the row write enable we_y is 0, the row address addr_y is incremented by 1, and it is judged whether addr_y == y2. If true, it enters the y_loop_end state. If false, it enters the bram_wait state to update the mask of the next row;

[0032] In the y_loop_end state, the number of processed bboxes is incremented by 1, and it enters the bbox_loop state;

[0033] Among them:

[0034] idle is the idle state, bbox_loop is the bbox frame traversal state, fifo_wait is the bbox FIFO read state, bram_wait is the original mask read state, y_loop is the row address addr_y loop state, top_down is the bbox upper and lower border state, x_incr is the column address addr_x increase state, left is the bbox left border state, right is the bbox right border state, x_loop_end is the column address addr_x termination state, mask_update is the mask update state, and y_loop_end is the row address addr_y termination state.

[0035] The beneficial effects of the present invention are:

[0036] When accelerating the deep learning algorithm of target detection based on FPGA, the FPGA hardware cannot generate 20×20, 40×40, 80×80 feature maps at one time, and the feature maps need to be calculated in blocks. For example, if a block feature map of 8×8 size is generated in one calculation, the feature map of N×N size is divided into multiple block feature maps of 8×8 size for calculation. In the present invention, when the block feature map of 8×8 size of the regression branch of target detection generates a prediction frame after post-processing, a mask is generated for the prediction frame, and the mask update is completed in real time and efficiently through FIFO, one-dimensional register group and two-dimensional BRAM. This method can generate the mask of the prediction frame in real time in a pipeline manner, without the need to generate the mask after all prediction frames are generated, reducing the calculation steps, effectively improving the reasoning speed, and improving the real-time performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Schematic diagram of two branches of the detection head decoupling structure according to an embodiment of the present invention;

[0038] Figure 2 640×640 is a mask schematic diagram of an embodiment of the present invention;

[0039] Figure 3 Schematic diagram of a 640×640 two-dimensional mask BRAM according to an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of a process of framing a video stream according to an updated mask according to an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of a flow chart of a method for generating a multi-prediction frame real-time mask according to an embodiment of the present invention;

[0042] Figure 6 A state transition diagram for mask update according to an embodiment of the present invention;

[0043] Figure 7A schematic diagram of a process for generating prediction frame coordinates from a block feature map and writing them into a FIFO according to an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of converting prediction box coordinates into a mask according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Example

[0047] The decoupled structure of the detection head of the deep learning algorithm for object detection contains two branches: classification and regression. The classification branch of the detection head outputs three feature maps of different sizes, namely 20×20, 40×40, and 80×80. For the COCO dataset, each feature map of the classification branch contains 80 channels, i.e., 80 categories. The regression branch of the detection head outputs three feature maps of different sizes, namely 20×20, 40×40, and 80×80. Each feature map of the regression branch contains 4 channels, i.e., 4 distances of up, down, left, and right.

[0048] Because FPGA hardware cannot generate 20×20, 40×40, and 80×80 feature maps at one time, it is necessary to perform block calculations on the feature maps. For example, a block feature map of 8×8 size is generated at one time. The 20×20 feature map is decomposed into 3×3 8×8 feature maps. For blocks smaller than 8×8, a "0" operation is performed to fill them up to 8×8 size. The 40×40 feature map is decomposed into 5×5 8×8 feature maps. The 80×80 feature map is decomposed into 10×10 8×8 feature maps.

[0049] like Figure 1 As shown in the figure, the two branches of the decoupled structure of the detection head are classification and regression. Taking the feature map size of 20×20 as an example, it is divided into 3×3 8×8 block feature maps. r8x8 and c8x8 are the row and column coordinates of the 8×8 block, and the range is 0 to 2. The coordinates of the 3×3 8×8 block feature maps are (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1), (2,2). Classification corresponds to 80 output channels OC (Output Channel), and regression corresponds to 4 output channels OC.

[0050] The YOLO algorithm inputs a 640×640 image, and finally marks the predicted box for the detected target object on the original image. This requires creating a 640×640 mask. If the mask is "0", the original image is displayed, and if the mask is "1", the color of the predicted box (for example, red) is displayed. The 640×640 mask is as follows: Figure 2 shown.

[0051] The storage of 640×640 mask is implemented using dual-port BRAM, such as Figure 3 As shown in the figure, the data width is 640 bits, corresponding to 640 columns in a row. The depth is 640, representing 640 rows. The A port of the BRAM completes the writing of the mask, and the B port of the BRAM completes the reading of the mask.

[0052] Figure 4 and Figure 5 A specific implementation of the method for real-time display of multiple prediction frames based on FPGA-based target detection algorithm acceleration of the present invention is shown, comprising the following steps:

[0053] S1, dividing the regression branch feature map of the detection head into several block feature maps;

[0054] The 20×20 feature map of the regression branch contains 4 output channels OC. The 20×20 feature map is divided into 3×3 8×8 block feature maps. The calculation order is (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1), (2,2);

[0055] S2, each 8×8 block feature map is post-processed to generate N prediction boxes bbox1~bboxN, where the coordinate information of the nth prediction box bboxN is [(x1 n ,y1 n ),(x2 n ,y2 n )], where (x1 n ,y1 n ) is the coordinate of the upper left corner, (x2 n ,y2 n ) is the coordinate of the lower right corner, 1≤n≤N, N is a positive integer;

[0056] In this embodiment, it is assumed that (0,0) corresponds to an 8×8 block feature map, and a prediction box bbox1 is generated after post-processing, and its coordinates are [(1,1), (7,8)]; it is assumed that (0,1) corresponds to an 8×8 block feature map, and a prediction box bbox2 is generated after post-processing, and its coordinates are [(5,2), (11,6)]; it is assumed that no corresponding prediction box is generated for other 8×8 block feature maps;

[0057] S3, write the prediction boxes bbox1 and bbox2 into FIFO; steps S2 and S3 are as follows Figure 7 As shown;

[0058] S4, detect the empty signal of FIFO, when empty is "0", that is, not empty, go to step S5;

[0059] S5. Analyze the coordinates of the prediction box bbox1 [(1,1), (7,8)];

[0060] S6, read the original first row mask from the 640×640 BRAM into the one-dimensional register group DFF640 as the initial value of the first row;

[0061] The mask value of the first row is updated starting from the first column to the seventh column on the one-dimensional register group DFF640, and the mask value of the first row after the update of the one-dimensional register group DFF640 is written back to the first row of the 640×640 BRAM;

[0062] S7, according to the method of step S6, continue to complete the mask update of the remaining 2nd to 8th rows in the prediction box bbox1 row by row, and write back the 1st to 8th rows of the 640×640 BRAM accordingly;

[0063] In the mask update in the above steps S6 and S7, for rows 1 and 8, all columns from column 1 to column 7 are updated with masks column by column, and for rows 2 to 7, only columns 1 and 7 are updated with masks;

[0064] After steps S6 and S7, the mask update of the prediction box bbox1 is completed in the 640×640 BRAM;

[0065] S8, then follow the method of steps S5 to S7 to complete the mask update of the prediction box bbox2, and write it back to the corresponding position of the 640×640 BRAM; the specific steps of the mask update of the prediction box bbox2 are:

[0066] Parse the coordinates of the prediction box bbox2 [(5,2), (11,6)];

[0067] Read the original second row mask from the 640×640 BRAM into the one-dimensional register group DFF640 as the initial value of the second row; it contains the original mask information of bbox2;

[0068] The second row mask is updated starting from the fifth column to the eleventh column on the one-dimensional register group DFF640, and the second row mask value after the one-dimensional register group DFF640 is updated is written back to the second row of the 640×640 BRAM;

[0069] According to the above method, continue to complete the mask update of the 3rd to 6th rows in the prediction box bbox2 row by row, and write back the 2nd to 6th rows of the 640×640 BRAM accordingly;

[0070] For the 2nd and 6th rows, the masks of all columns from the 5th to the 11th are updated column by column, and for the 3rd to the 5th rows, only the 5th and 11th columns are updated; at this time, the mask update of bbox2 is completed in the 640×640 BRAM.

[0071] Figure 8 The process of converting the coordinates of the prediction boxes bbox1 and bbox2 into masks in this embodiment is shown, as well as the masks of the two prediction boxes finally generated. Figure 8 The coordinates with a mask of “1” in the figure show the color of the predicted box.

[0072] S9. The video stream is framed according to the updated masks for the prediction boxes bbox1 and bbox2 in the above steps. If the mask is 0, the original image data is passed. If the mask is 1, the original image data is replaced with the color of the prediction box.

[0073] The specific implementation process of the picture frame is as follows Figure 4 As shown: the video stream passes through AXI VDMA (Video Direct Memory Access) and then through the frame logic. The frame logic analyzes the control and data signals of the video stream, wherein the row address generator generates a row address for one row, reads a row of 640-bit masks in a 640×640 two-dimensional mask BRAM, and the column address generator generates a column address for one column, reads a 1-bit mask in a row of 640-bit masks, and uses the read 1-bit mask as the control signal of the 2-to-1 selector MUX. The video stream and the preset prediction frame color data (for example, red) are respectively used as the two input signals of the 2-to-1 selector MUX. If the mask is 0, the MUX passes the original image data, and if the mask is 1, the MUX passes the prediction frame color data, that is, the original image data is replaced with the color of the prediction frame (for example, red). The video stream after the frame is then passed through AXI4-Stream to Video Out and waits for HDMI (High Definition Multimedia Interface) display.

[0074] Figure 6 It is shown that in this embodiment, the specific logic of the mask update is:

[0075] In the idle state, the row address addr_y is 0, the column address addr_x is 0, and the FIFO read enable fifo_rd_en is 0. If the FIFO is not empty, that is, empty == 0, it enters the bbox_loop state;

[0076] In the bbox_loop state, if the FIFO is not empty (i.e., empty == 0), it enters the fifo_wait state. The FIFO read enable fifo_rd_en is 1, and the mask completion mask_done is 0. If the FIFO is empty (i.e., empty == 1), the FIFO read enable fifo_rd_en is 0. At this time, if all bboxes are generated (i.e., bbox_done_flag == 1), the mask completion mask_done is 1, and it enters the idle state;

[0077] In the fifo_wait state, it enters the bram_wait state. The FIFO read enable fifo_rd_en is 0, the row address addr_y is y1, and the column address addr_x is x1;

[0078] In the bram_wait state, it enters the y_loop state. The original mask read enable old640_rd_en is 1;

[0079] In the y_loop state, the original mask read enable old640_rd_en is 0. If addr_y == y1 || addr_y == y2, it enters the top_down state. If addr_y < y2 && addr_y > y1, it enters the left state. Otherwise, it enters the mask_update state;

[0080] In the top_down state, the data din_x corresponding to addr_x is 1, the column write enable we_x is 1, and it enters the x_incr state;

[0081] In the x_incr state, the write enable we_x is 0. If addr_x >= x1 && addr_x < x2, the column address addr_x is incremented by 1. Otherwise, it enters the x_loop_end state;

[0082] In the left state, addr_x is x1, the data din_x is 1, the column write enable we_x is 1, and it enters the right state;

[0083] In the right state, addr_x is x2, the data din_x is 1, the column write enable we_x is 1, and it enters the x_loop_end state;

[0084] In the x_loop_end state, addr_x is x1, the data din_x is 0, the column write enable we_x is 0, the row write enable we_y is 1, and it enters the mask_update state;

[0085] In the mask_update state, the row write enable we_y is 0, the row address addr_y is increased by 1, and addr_y == y2 is judged. If it is true, it enters the y_loop_end state. If it is false, it enters the bram_wait state and updates the mask of the next row.

[0086] In the y_loop_end state, the number of bboxes processed is increased by 1, and the bbox_loop state is entered;

[0087] in:

[0088] idle is the idle state, bbox_loop is the bbox frame traversal state, fifo_wait is the bbox FIFO read state, bram_wait is the original mask read state, y_loop is the row address addr_y loop state, top_down is the bbox upper and lower border state, x_incr is the column address addr_x increase state, left is the bbox left border state, right is the bbox right border state, x_loop_end is the column address addr_x termination state, mask_update is the mask update state, and y_loop_end is the row address addr_y termination state.

Claims

1. A multi-prediction frame real-time display method based on FPGA-based target detection algorithm acceleration, characterized in that: The steps include: S1, dividing the regression branch feature map of the detection head into several block feature maps; S2, each block feature map is post-processed to generate N prediction boxes bbox1~bboxN, where the coordinate information of the nth prediction box bboxN is [(x1 n ,y1 n ),(x2 n ,y2 n )], where (x1 n ,y1 n ) is the coordinate of the upper left corner, (x2 n ,y2 n ) is the coordinate of the lower right corner, 1≤n≤N, N is a positive integer; S3, write all prediction boxes into FIFO; S4, detect the empty signal of FIFO, when empty is "0", that is, not empty, go to step S5; S5. Analyze the coordinates of the prediction box bbox1 [(x1 1 ,y1 1 ),(x2 1 ,y2 1 )]; S6, read the original y1 from the 640×640 BRAM 1 The row mask is stored in the one-dimensional register group DFF640 as y1 1 The initial value of the row; On the one-dimensional register bank DFF640 from x1 1 Start of column, to x2 1 Column end complete y1 1 The row mask is updated and the updated y1 of the one-dimensional register group DFF640 is 1 The row mask value is written back to y1 of the 640×640 BRAM 1 OK; S7, according to the method of step S6, complete the remaining y1 in the prediction box bbox1 line by line 1 +1 to y2 1 The masks of all rows are updated and written back to y1 of the 640×640 BRAM accordingly 1 +1 to y2 1 OK; S8. According to the method of steps S5 to S7, the mask updates of the remaining prediction boxes bbox2 to bboxN are completed one by one, and the masks are written back to the corresponding positions of the 640×640 BRAM; S9. The video stream is framed according to all updated masks in step S8. If the mask is 0, the original image data is used. If the mask is 1, the original image data is replaced with the color of the predicted frame.

2. The method for real-time display of multiple prediction frames based on FPGA-based target detection algorithm acceleration according to claim 1, characterized in that: There are three sizes of the regression branch feature map of the detection head, which are 20×20, 40×40, or 80×80.

3. The method for real-time display of multiple prediction frames based on FPGA-based target detection algorithm acceleration according to claim 2, characterized in that: The size of the block feature map is 8×8, and the sizes of the 20×20, 40×40, and 80×80 feature maps after being divided into 8×8 blocks are 3×3, 5×5, and 10×10 respectively. If there are blocks smaller than 8×8 among the blocks generated after the division, a "0" padding operation is performed to fill the size to 8×8.

4. The method for real-time display of multiple prediction frames based on FPGA-based target detection algorithm acceleration according to claim 1, characterized in that: The mask update in steps S6 and S7 is for y1 1 row and y2 1 row, is from x1 1 to x2 1 All columns of y1 are updated column by column. 1 and y2 1 The rows between them only have x1 1 and x2 1 Two-column update mask.

5. The method for real-time display of multiple prediction frames based on FPGA-based target detection algorithm acceleration according to claim 1, characterized in that: The specific logic of the mask update is: In the idle state, the row address addr_y is 0, the column address addr_x is 0, and the FIFO read enable fifo_rd_en is 0. If the FIFO is not empty, that is, empty == 0, it enters the bbox_loop state; In the bbox_loop state, if the FIFO is not empty, that is, empty == 0, it enters the fifo_wait state, the FIFO read enable fifo_rd_en is 1, and the mask completion mask_done is 0. If the FIFO is empty, that is, empty == 1, the FIFO read enable fifo_rd_en is 0. At this time, if all bboxes are generated, that is, bbox_done_flag == 1, the mask completion mask_done is 1, and it enters the idle state; In the fifo_wait state, enter the bram_wait state, the FIFO read enable fifo_rd_en is 0, the row address addr_y is y1, and the column address addr_x is x1; In the bram_wait state, enter the y_loop state, and the original mask read enable old640_rd_en is 1; In the y_loop state, the original mask read enable old640_rd_en is 0, if addr_y==y1||addr_y==y2, enter the top_down state, if addr_y<y2&&addr_y> y1, enter the left state, otherwise enter the mask_update state; In the top_down state, the data din_x corresponding to addr_x is 1, the column write enable we_x is 1, and the x_incr state is entered; In the x_incr state, the write enable we_x is 0. If addr_x >= x1 && addr_x < x2, the column address addr_x is incremented by 1; otherwise, it enters the x_loop_end state. In the left state, addr_x is x1, the data din_x is 1, the column write enable we_x is 1, and it enters the right state. In the right state, addr_x is x2, the data din_x is 1, the column write enable we_x is 1, and it enters the x_loop_end state. In the x_loop_end state, addr_x is x1, the data din_x is 0, the column write enable we_x is 0, the row write enable we_y is 1, and it enters the mask_update state. In the mask_update state, the row write enable we_y is 0, the row address addr_y is incremented by 1, and it is judged whether addr_y == y2. If true, it enters the y_loop_end state; if false, it enters the bram_wait state to update the mask of the next row. In the y_loop_end state, the number of processed bboxes is incremented by 1, and it enters the bbox_loop state. Where: idle is the idle state, bbox_loop is the bbox traversal state, fifo_wait is the bbox FIFO read state, bram_wait is the original mask read state, y_loop is the row address addr_y loop state, top_down is the bbox upper and lower border state, x_incr is the column address addr_x increment state, left is the bbox left border state, right is the bbox right border state, x_loop_end is the column address addr_x termination state, mask_update is the mask update state, y_loop_end is the row address addr_y termination state.

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