Display panel and display device

Abstract

The invention provides a display panel and a display device, and the display panel comprises a plurality of sub-pixels, a plurality of corresponding pixel circuits, and a power line used for transmitting a power signal to a common electrode, each pixel circuit comprises a corresponding capacitor, and in the plurality of pixel circuits, a plurality of capacitors are arranged in the plurality of sub-pixels. The capacitance value of the capacitor of the first pixel circuit is different from the capacitance value of the capacitor of the second pixel circuit, two power supply signals transmitted by the two power supply lines respectively connected to the first pixel circuit and the second pixel circuit are different, and the flicker phenomenon of the display panel is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to reduce production costs, a mask splicing exposure method is generally used to prepare larger panels. However, in the splicing exposure process, different exposure areas are exposed through different mask plates or exposed in batches, resulting in differences in the size of some metal layers, causing flickering in some areas of the panel, affecting the VRR (Variable Refresh Rate) effect of the gaming screen. Summary of the invention

[0003] An object of the present invention is to provide a display panel and a display device to improve the technical problem of flickering phenomenon of the existing display panel.

[0004] The present invention provides a display panel, wherein a display area of ​​the display panel includes a first display area and a second display area, including:

[0005] A plurality of pixel electrodes, including a plurality of first pixel electrodes located in the first display area and a plurality of second pixel electrodes located in the second display area;

[0006] a plurality of pixel circuits corresponding to the plurality of pixel electrodes, including a plurality of first pixel circuits electrically connected to the plurality of first pixel electrodes, and a plurality of second pixel circuits electrically connected to the plurality of second pixel electrodes, each of the pixel circuits including a capacitor, and a capacitance value of the capacitor of the first pixel circuit is different from a capacitance value of the capacitor of the second pixel circuit;

[0007] A first power line, used for transmitting a first power signal;

[0008] A second power line, used for transmitting a second power signal;

[0009] Wherein, the plurality of first pixel circuits include a first sub-common electrode having an area facing the plurality of first pixel electrodes, and a second sub-common electrode having an area facing the plurality of second pixel electrodes;

[0010] Wherein, the first power signal transmitted by the power line to the first sub-common electrode and the second power signal transmitted to the second sub-common electrode are different.

[0011] In some embodiments, the pixel circuit includes a driving transistor, and one of a source and a drain of the driving transistor is electrically connected to the pixel electrode;

[0012] The capacitor comprises a first capacitor, a first plate of the first capacitor is one of a source and a drain of the driving transistor, and a second plate of the first capacitor is a gate of the driving transistor;

[0013] The area facing one of the source and drain of the driving transistor in the first pixel circuit and the gate is different from the area facing one of the source and drain of the driving transistor in the second pixel circuit and the gate.

[0014] In some embodiments, the pixel circuit comprises:

[0015] A first common electrode is arranged in the same layer as the plurality of pixel electrodes;

[0016] a second common electrode, disposed opposite to the plurality of pixel electrodes and the first common electrode;

[0017] The capacitor further includes a second capacitor and a third capacitor, the first plate of the second capacitor and the first plate of the third capacitor both include the pixel electrode, the second plate of the second capacitor is the first common electrode, and the second plate of the third capacitor is the second common electrode;

[0018] Wherein, an area directly facing the first pixel electrode and the first common electrode is different from an area directly facing the second pixel electrode and the first common electrode;

[0019] And / or, an area where the first pixel electrode faces the second common electrode is different from an area where the second pixel electrode faces the second common electrode.

[0020] In some embodiments, the first sub-common electrode is disposed opposite to the plurality of first pixel electrodes, and the second sub-common electrode is disposed opposite to the plurality of second pixel electrodes.

[0021] In some embodiments, the display panel further comprises:

[0022] a power manager, connected to the first sub-common voltage line, and configured to output the first power signal to the first power line;

[0023] The signal processing circuit is connected between the power manager and the second power line, and is used to generate the second power signal output to the second power line according to the first power signal.

[0024] In some embodiments, the plurality of sub-pixels include a plurality of first color sub-pixels corresponding to the same color, and the display panel further includes:

[0025] a plurality of data lines, each of the data lines being electrically connected to a corresponding plurality of the pixel circuits and configured to transmit a plurality of data signals, the data signals comprising a plurality of data voltages corresponding to the plurality of the sub-pixels;

[0026] When the grayscale values ​​of the two first color sub-pixels, which are the first pixel electrode and the second pixel electrode respectively, are the same at the same refresh rate, the two data voltages corresponding to the two data signals corresponding to the two first color sub-pixels are different.

[0027] In some embodiments, the display panel further comprises:

[0028] a source driver, comprising a gamma circuit for generating a first gamma binding point voltage and a second gamma binding point voltage, the source driver being used to generate the data signal as a first data signal according to a grayscale signal and the first gamma binding point voltage, and further being used to generate the data signal as a second data signal according to the grayscale signal and the second gamma binding point voltage;

[0029] The data line electrically connected to the first pixel circuit is used to transmit the first data signal, and the data line electrically connected to the second pixel circuit is used to transmit the second data signal.

[0030] In some embodiments, the first gamma tie point voltage includes a first sub-gamma tie point voltage and a second sub-gamma tie point voltage, and the second gamma tie point voltage includes a third sub-gamma tie point voltage and a fourth sub-gamma tie point voltage;

[0031] At a first refresh rate, the source driver is used to generate the first data signal according to the grayscale signal and the first sub-gamma binding point voltage, and is also used to generate the second data signal according to the grayscale signal and the third sub-gamma binding point voltage;

[0032] At the second refresh rate, the source driver is used to generate the first data signal according to the grayscale signal and the second sub-gamma binding point voltage, and is also used to generate the second data signal according to the grayscale signal and the fourth sub-gamma binding point voltage.

[0033] The present invention provides a display device, comprising:

[0034] A display panel as described in any one of the above;

[0035] The housing is used to accommodate the display panel.

[0036] The present invention provides a display panel and a display device, comprising a plurality of sub-pixels, a plurality of pixel circuits corresponding to the plurality of sub-pixels, and a power line for transmitting a power signal to a common electrode in the plurality of pixel circuits, wherein each of the pixel circuits is electrically connected to the corresponding sub-pixel, and the plurality of pixel circuits include at least one first pixel circuit located in a first display area and at least one second pixel circuit located in a second display area, and the capacitance value of the capacitor of the first pixel circuit is different from the capacitance value of the capacitor of the second pixel circuit. By setting the power signal transmitted by the power line electrically connected to the first pixel circuit and the power signal transmitted by the power line electrically connected to the second pixel circuit to be different, the voltages loaded on the common electrodes corresponding to the first display area and the second display area are different, thereby improving the flickering phenomenon existing in some areas of the existing display panel due to factors such as splicing exposure process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The present invention is further described below by means of the accompanying drawings. It should be noted that the accompanying drawings described below are only used to explain some embodiments of the present invention, and those skilled in the art can also obtain other accompanying drawings based on these accompanying drawings without creative work.

[0038] Figure 1 , Figure 6 and Figure 7 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention.

[0039] Figure 2 A circuit diagram of a pixel circuit provided by an embodiment of the present invention.

[0040] Figure 3 A layout diagram of an array substrate provided in an embodiment of the present invention.

[0041] Figure 4 A timing diagram of some signals in a display panel provided by an embodiment of the present invention.

[0042] Figure 5 A schematic cross-sectional view of a display panel provided by an embodiment of the present invention.

[0043] Figure 8 A schematic top view of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0045] In the description of the present invention, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the said features. In addition, it should be noted that the drawings only provide structures that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is the same as the attached structure. Figure 1 The same is not a limitation of the actual device.

[0046] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0047] The present invention provides a display panel, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0048] In one embodiment, in combination Figure 1 to Figure 2 As shown, the display panel 100 includes: a plurality of sub-pixels P; a plurality of pixel circuits 40, corresponding to the plurality of sub-pixels P, each of the pixel circuits 40 is electrically connected to the corresponding sub-pixel P, and each of the pixel circuits 40 includes a corresponding capacitor C; a power line 20, electrically connected to the plurality of pixel circuits 40, for transmitting a power signal; wherein the plurality of pixel circuits 40 include at least one first pixel circuit 401 and at least one second pixel circuit 402, and the capacitance value of the capacitor C of the first pixel circuit 401 is different from the capacitance value of the capacitor C of the second pixel circuit 402; wherein the power signal (referred to as the first power signal at this time) transmitted by the power line 20 (i.e., the first power line 201) electrically connected to the first pixel circuit 401 and the power signal (referred to as the second power signal at this time) transmitted by the power line 20 (i.e., the second power line 202) electrically connected to the second pixel circuit 402 are different.

[0049] The display panel 100 may be, but is not limited to, a liquid crystal display panel, an organic self-luminous display panel, or an inorganic self-luminous direct display panel. Figure 1 As shown, here, it is taken that a plurality of sub-pixels P in the display area A of the display panel 100 are arranged in an array of n rows, m columns as an example, where n and m are both positive integers. Correspondingly, the display panel 100 may also include a plurality of data lines (DL1 to DLm), a plurality of gate lines (GL1 to GLn), a source driver 301 electrically connected to the plurality of data lines, and a gate driver 50 electrically connected to the plurality of gate lines. The gate driver 50 may be a gate driving circuit included in the array substrate 10 of the display panel 100 or a chip ( Figure 1 Only the former case is taken as an example).

[0050] Specifically, each gate line (each of GL1 to GLn) is electrically connected to a plurality of pixel circuits 40 corresponding to a plurality of sub-pixels P located in a corresponding row to output a corresponding gate signal gate thereto. In each frame, the gate signal gate includes a gate pulse for controlling the corresponding plurality of pixel circuits 40 to be turned on. The plurality of rows of pixel circuits 40 are turned on in sequence under the control of a plurality of gate pulses in the plurality of gate signals. Each data line (each of DL1 to DLm) is connected to a plurality of pixel circuits 40 corresponding to a plurality of sub-pixels P located in a corresponding column to output a corresponding data signal data thereto. The plurality of data signals corresponding to the plurality of columns of sub-pixels P are set such that when each row of pixel circuits 40 is turned on, the plurality of data signals data also transmit a plurality of data voltages Vdata corresponding to the row of sub-pixels P. Thus, when each row of pixel circuits 40 is turned on, the plurality of sub-pixels P in the row are respectively driven by the corresponding plurality of data voltages Vdata to emit light. By analogy, ultimately, the plurality of rows of sub-pixels P all emit light to display the picture of the frame.

[0051] Furthermore, the display panel 100 may further include a timing controller 302 electrically connected to the source driver 301 and the gate driver 50, and a power manager 303 electrically connected to the source driver 301, the gate driver 50, the timing controller 302, and the plurality of pixel circuits 40, wherein the plurality of pixel circuits 40 are electrically connected to the power manager 303 through a plurality of power lines 20. The power manager 303 may supply power to the entire display panel 100, the timing controller 302 may generate a grayscale signal Sg and a corresponding first control signal acting on the source driver 301, and may also generate a corresponding second control signal acting on the gate driver 50, and then the source driver 301 generates the plurality of data signals data at least according to the grayscale signal Sg and the first control signal, and the gate driver 50 generates the plurality of gate signals gate according to the second control signal.

[0052] Combined with the above discussion, it can be known that the pixel circuit 40 is controlled by the gate signal gate to turn on, and controls the corresponding sub-pixel P to emit light according to the corresponding data voltage Vdata in the data signal data. However, when the potential of the gate signal gate or other signals acting on the pixel circuit 40 jumps, since each pixel circuit 40 includes a corresponding capacitor C, if no interference is added, the coupling effect of the capacitor C causes the potential of the signal of the node in the pixel circuit 40 that is acted by the data voltage Vdata to also jump accordingly, causing the brightness of the corresponding sub-pixel P to also change, showing a flickering phenomenon. In this regard, the global data voltage Vdata and power supply signal of the display area A can be uniformly compensated to uniformly improve the global brightness.

[0053] It should be noted that factors such as the manufacturing process may cause differences in the capacitance values ​​of the capacitors C of different pixel circuits 40. Therefore, for different pixel circuits 40, even if the potential of the gate signal gate or other acting signals undergoes the same jump, and other influencing factors are also the same, the jump amount of the potential of the signal at the node acted by the data voltage Vdata in the pixel circuit 40 is also different. Therefore, even if the global data voltage Vdata and power supply signal of the display area A are uniformly compensated to uniformly improve the global brightness, at least one of the two sub-pixels P corresponding to the capacitor C with different capacitance values ​​still flickers.

[0054] It can be understood that this embodiment takes into account that the power signal will also affect the brightness of the corresponding sub-pixel P by acting on the pixel circuit 40. Based on the different capacitance values ​​of the capacitor C of the first pixel circuit 401 and the capacitor C of the second pixel circuit 402, the power signal transmitted by the first power line 201 electrically connected to the first pixel circuit 401 and the power signal transmitted by the second power line 202 electrically connected to the second pixel circuit 402 are set to be different, so as to compensate for the difference in the jump amount of the potential of the signal of the node acted by the data voltage Vdata in the first pixel circuit 401 and the second pixel circuit 402, thereby improving the flickering phenomenon of the sub-pixel P corresponding to the first pixel circuit 401 or the second pixel circuit 402 when displaying the picture.

[0055] In some embodiments, in combination Figure 1 to Figure 2 As shown, the display area A of the display panel 100 includes a first display area A1 and a second display area A2; wherein the plurality of sub-pixels P in the first display area A1 are electrically connected to the plurality of first pixel circuits 401, and the plurality of sub-pixels P in the second display area A2 are electrically connected to the plurality of second pixel circuits 402. That is, the capacitance values ​​of the capacitors C in the pixel circuits 40 of the first display area A1 and the second display area A2 are different.

[0056] Specifically, for the display panel 100 prepared by the mask splicing exposure method, since different exposure areas are exposed through different mask plates or exposed in batches, the display panel 100 will form different areas of capacitors C with different capacitance values. It can be considered that multiple first pixel circuits 401 are continuously arranged to form a continuous first display area A1, and multiple second pixel circuits 402 are continuously arranged to form a continuous second display area A2.

[0057] It can be understood that in this embodiment, for the display panel 100 prepared by mask splicing exposure, the power signal transmitted to the first pixel circuit 401 in the first display area A1 and the power signal transmitted to the second pixel circuit 402 in the second display area A2 are set to be different, which can improve the flickering phenomenon of at least part of the display panel 100 caused by the mask splicing exposure.

[0058] In some embodiments, in combination Figures 1 to 3 As shown, the sub-pixel P includes a pixel electrode, the pixel circuit 40 includes a driving transistor Td, and one of the source s and the drain d of the driving transistor Td (the former is taken as an example here) is electrically connected to the pixel electrode; wherein the capacitor C includes a first capacitor Cgs, the first plate of the first capacitor Cgs is one of the source s and the drain d of the driving transistor Td, and the second plate of the first capacitor Cgs is the gate g of the driving transistor Td; wherein the area facing one of the source s and the drain d of the driving transistor Td in the first pixel circuit 401 and the gate g is different from the area facing one of the source s and the drain d of the driving transistor Td in the second pixel circuit 402 and the gate g. That is, the display panel 100 is taken as an example of a liquid crystal display panel for explanation.

[0059] Among them, Figure 3 As shown, the driving transistor Td can be arranged in the same layer as multiple gate lines (GL1 to GLn) and multiple data lines (DL1 to DLm), the gate g of the driving transistor Td is electrically connected to the corresponding gate line, one of the source s and the drain d of the driving transistor Td (the former is taken as an example here) is electrically connected to the corresponding pixel electrode, and the other of the source s and the drain d of the driving transistor Td (the latter is taken as an example here) is electrically connected to the corresponding data line.

[0060] In combination with the above discussion, it can be known that the multiple rows of driving transistors Td corresponding to the multiple rows of pixel electrodes are turned on in sequence under the action of multiple gate signals gate. When each row of driving transistors Td is turned on, multiple data signals data are also transmitting multiple data voltages Vdata corresponding to the multiple pixel electrodes of the row, and then the pixel electrodes of the row are respectively loaded with the corresponding multiple data voltages Vdata. The multiple liquid crystal molecules corresponding to each pixel electrode are deflected by a corresponding angle under the action of the voltage difference between the pixel electrode and the common electrode (the second common electrode 103 below) so that the corresponding amount of light emitted by the backlight module is transmitted, and the corresponding color filter is combined to present the corresponding light, and so on. Finally, the multiple rows of pixel electrodes are deflected to enable the display panel 100 to display a frame of the picture.

[0061] Among them, combined Figures 1 to 4 As shown, to ensure that the image driving transistor Td can be fully turned on, the starting time of the gate pulse of the gate signal gate can be earlier than the starting time of the corresponding data voltage Vdata in the data signal data, and to ensure that the data voltage Vdata can be fully written, the ending time of the corresponding data voltage Vdata in the data signal data can be later than the ending time of the gate pulse. In which, at the falling edge of the gate pulse, through the coupling effect of the first capacitor Cgs between the source s and the gate g of the driving transistor Td, the potential of the signal data' at the node acted by the data voltage Vdata in the pixel circuit 40 also jumps accordingly, thereby presenting a flickering phenomenon.

[0062] It should be noted that due to factors such as the manufacturing process (including but not limited to the above-mentioned mask splicing exposure), there may be differences in the opposing areas of the source s and the drain d of the driving transistor Td in different areas of the display panel 100 and the gate g of the driving transistor Td, thereby causing differences in the capacitance values ​​of the first capacitor Cgs in different areas. After the flicker phenomenon of one of the first display area A1 and the second display area A2 is improved through global compensation, the other one still has flickering phenomenon.

[0063] Further, combined with Figures 1 to 5As shown, the pixel circuit 40 also includes: a first common electrode 102, which is arranged in the same layer as the plurality of pixel electrodes (i.e., sub-pixels P); a second common electrode 103, which is arranged opposite to the plurality of pixel electrodes and the first common electrode 102; wherein the capacitor C also includes a second capacitor Cst and a third capacitor Clc, the first plate of the second capacitor Cst and the first plate of the third capacitor Clc both include the pixel electrode (i.e., sub-pixel P), the second plate of the second capacitor Cst is the first common electrode 102, and the second plate of the third capacitor Clc is the second common electrode 103; wherein the area of ​​the pixel electrode corresponding to the first pixel circuit 401 facing the first common electrode 102 is different from the area of ​​the pixel electrode corresponding to the second pixel circuit 402 facing the first common electrode 102; and / or the area of ​​the pixel electrode corresponding to the first pixel circuit 401 facing the second common electrode 103 is different from the area of ​​the pixel electrode corresponding to the second pixel circuit 402 facing the second common electrode 103.

[0064] Specifically, since the power line 20 also transmits corresponding power signals to the first common electrode 102 and the second common electrode 103, a corresponding second capacitor Cst can be formed between the first common electrode 102 and each pixel electrode, and a corresponding third capacitor Clc can be formed between the second common electrode 103 and each pixel electrode. Similarly, due to factors such as the manufacturing process (including but not limited to the above-mentioned mask splicing exposure), the pixel electrodes in different areas of the display panel 100 may also have different areas facing at least one of the first common electrode 102 and the second common electrode 103. Similarly, after the flicker phenomenon of one of the first display area A1 and the second display area A2 is improved by global compensation, the other still has flicker phenomenon.

[0065] Among them, if the coupling effect of the first capacitor Cgs, the second capacitor Cst and the third capacitor Clc is considered at the same time, at the falling edge of the gate pulse, the jump value corresponding to the potential of the signal data' of the node acted by the data voltage Vdata in the pixel circuit 40 is Δ V is (Vgh - Vgl)×Cgs0 / (Cgs0+Clc0+Cst0), Cgs0, Cst0, Clc0 are the capacitance values ​​of the first capacitor Cgs, the second capacitor Cst and the third capacitor Clc respectively.

[0066] It can be seen that due to factors such as the manufacturing process (including but not limited to the mask splicing exposure mentioned above), the capacitance value of any of the above three capacitors is different in different regions, which will cause flickering in at least one region when displaying the picture.

[0067] Of course, when the display panel 100 is a self-luminous display panel, different from the above description about Figure 2 and Figure 3 As discussed above, the pixel circuit 40 at this time includes at least two transistors and one capacitor, and the sub-pixel P is a self-luminous element. However, due to factors such as the process (including but not limited to the above-mentioned mask splicing exposure), the capacitance value of at least one capacitor of the pixel circuit 40 in different areas will still be different, which will cause the potential jump amount of the signal of the node acted by the data voltage Vdata in the pixel circuit 40 to be different. Therefore, there is still a flickering phenomenon in at least one area of ​​the self-luminous element when emitting light.

[0068] In some embodiments, in combination Figures 1 to 5 As shown, the sub-pixel P includes the above-mentioned pixel electrode, and the plurality of pixel electrodes include a plurality of first pixel electrodes corresponding to the plurality of first pixel circuits 401 (the corresponding sub-pixels P are the first sub-pixels P1), and a plurality of second pixel electrodes corresponding to the plurality of second pixel circuits 402 (the corresponding sub-pixels P are the second sub-pixels P2), and the pixel circuit 40 includes: a first sub-common electrode 1031 (included in the above-mentioned second common electrode 103), which is arranged opposite to the plurality of the first pixel electrodes (i.e., the first sub-pixels P1), and is electrically connected to the first sub-common voltage line in the power line 20 (for example, the above-mentioned first power line 201); a second sub-common electrode 1032 (included in the above-mentioned second common electrode 103), which is arranged opposite to the plurality of the second pixel electrodes (i.e., the second sub-pixels P2), and is electrically connected to the second sub-common voltage line in the power line 20 (for example, the above-mentioned second power line 202); wherein the first sub-common signal CFVCOM1 transmitted by the first sub-common voltage line and the second sub-common signal CFVCOM2 transmitted by the second sub-common voltage line are different.

[0069] In combination with the above discussion, it can be known that the number of the first common electrodes 102 can be multiple, and each pixel electrode can form a corresponding second capacitor Cst with the nearest first common electrode 102 (loading the corresponding first common voltage through the power line 20) for storing the data voltage Vdata. The second common electrode 103 (loading the corresponding second common voltage through the power line 20) can be set in a whole layer or its number can also be multiple (respectively arranged opposite to multiple pixel electrodes), which can be used to store the data voltage Vdata and can also form a corresponding voltage difference with each pixel electrode to drive the deflection of multiple liquid crystal molecules in the corresponding area, so that the area in the display panel 100 presents the corresponding brightness.

[0070] Furthermore, the first sub-common electrode 1031 and the second sub-common electrode 1032 may be disposed separately to reduce the influence of the first sub-common signal CFVCOM1 and the second sub-common signal CFVCOM2 on each other.

[0071] Based on the above Figure 4 Further, in order to prevent the liquid crystal molecules from deflecting in the same direction for a long time, the polarity of the data voltage Vdata corresponding to the sub-pixel P in two adjacent frames is generally set to be opposite to the second common voltage. Here, the first display area A1 is taken as an example that the flicker phenomenon no longer exists after the global flicker improvement, that is, it is assumed that the absolute value of the difference between the data voltage Vdata of both polarities and the first sub-common signal CFVCOM1 of the sub-pixel P of the same color at the same grayscale value is the same.

[0072] That is, if no interference is made to the second display area A, there will still be a flicker problem. Specifically, if the first sub-common signal CFVCOM1 is also loaded to the first sub-common electrode 1031, then in the current frame F1, when the polarity is positive, the difference between the signal data' at the node acted by the data voltage Vdata in the pixel circuit 40 and the first sub-common signal CFVCOM1 becomes smaller after the jump. However, in the next frame F2, when the polarity is negative, the difference between the signal data' at the node acted by the data voltage Vdata in the pixel circuit 40 and the first sub-common signal CFVCOM1 becomes larger after the jump, causing the voltage difference used to drive the liquid crystal molecules to change from a larger voltage difference in the current frame to a smaller voltage difference in the next frame, thereby causing the flicker phenomenon.

[0073] Therefore, in this embodiment, for the first pixel circuit 401 and the second pixel circuit 402 including capacitors C with different capacitance values, the second sub-common signal CFVCOM2 acting on the second pixel circuit 402 is set to be different from the first sub-common signal CFVCOM1 acting on the first pixel circuit 401, for example Figure 4 When the gate pulse is a positive pulse, since the jump direction of the signal data' at the node acted by the data voltage Vdata in the pixel circuit 40 is negative, the amplitude of the second sub-common signal CFVCOM2 can be smaller than the first sub-common signal CFVCOM1, so that the amplitude of the second sub-common signal CFVCOM2 is close to the difference between the positive polarity amplitude and the negative polarity amplitude of "the signal data' at the node acted by the data voltage Vdata in the pixel circuit 40" after the jump, thereby improving the flickering phenomenon of the second display area A2.

[0074] Of course, when the gate pulse is a negative pulse, the amplitude of the second sub-common signal CFVCOM2 may be greater than that of the first sub-common signal CFVCOM1.

[0075] It should be noted that when the first sub-common electrode 1031 and the second sub-common electrode 1032 are both included in the second common electrode 103, that is, the liquid crystal molecules work in the vertical electric field, it can be considered that the liquid crystal display panel works in VA (Vertical Alignment, vertical alignment mode); however, if the liquid crystal display panel works in IPS (In-plane Switching, in-plane switching mode), that is, the liquid crystal molecules work in the vertical electric field, then this is different from Figure 5 As shown, the first sub-common electrode 1031 and the second sub-common electrode 1032 are both included in the first common electrode 102 . Correspondingly, the potentials of the second common electrodes 103 in the first display area A1 and the second display area A2 can be equal.

[0076] Furthermore, when the liquid crystal display panel operates in VA (Vertical Alignment) mode and the liquid crystal molecules operate alternately under positive voltage and negative voltage in multiple frames (that is, the potentials of multiple pixel electrodes are alternately greater than the potential of the first sub-common electrode 1031 and the potential of the second sub-common electrode 1032, and less than the potential of the first sub-common electrode 1031 and the potential of the second sub-common electrode 1032 in multiple frames), on the basis of differentially setting the potential of the second common electrode 103 in the first display area A1 and the second display area A2, the power line alternately transmits a third power signal and a fourth power signal with different amplitudes to the first common electrode 102 in multiple frames to compensate for the leakage differences of multiple pixel circuits 40 operating under positive voltage and negative voltage.

[0077] In some embodiments, in combination Figures 1 to 6 As shown, the display panel 100 also includes: the above-mentioned power manager 303, connected to the first sub-common voltage line (for example, the above-mentioned first power line 201), and used to generate the first sub-common signal CFVCOM1 (for example, the above-mentioned first power signal) output to the first sub-common voltage line; the signal processing circuit 304, connected between the power manager 303 and the second sub-common voltage line (for example, the above-mentioned second power line 202), and used to generate the second sub-common signal CFVCOM2 (for example, the above-mentioned second power signal) output to the second sub-common voltage line according to the first sub-common signal CFVCOM1.

[0078] The circuit board 300 for carrying the source driver 301 and the array substrate 10 may be electrically connected via a chip-on-film 400 , and the source drivers 301 on different circuit boards 300 may be connected via conductive connecting wires 500 .

[0079] It can be understood that, here, taking the example that the amplitude of the second sub-common signal CFVCOM2 is smaller than the first sub-common signal CFVCOM1, this embodiment sets a signal processing circuit 304 electrically connected between the power manager 303 and the display panel 100, and processes the first sub-common signal CFVCOM1 generated by the power manager 303 to generate the second sub-common signal CFVCOM2 acting on the second sub-common electrode 1032, thereby achieving the first sub-common electrode 1031 and the second sub-common electrode 1032 being acted upon by the first sub-common signal CFVCOM1 and the second sub-common signal CFVCOM2 with different amplitudes, respectively.

[0080] Specifically, Figure 6 As shown, the signal processing circuit 304 may include a first resistor R1 and a second resistor R2 arranged in series, one end of the first resistor R1 is connected to the ground GND, and the other end is connected to the second sub-common voltage line, one end of the second resistor R2 is connected to the power manager 303 and the first sub-common voltage line, and the other end is connected to the second sub-common voltage line, that is, the first resistor R1 and the second resistor R2 are connected in series to divide the voltage to generate a second sub-common signal CFVCOM2 with an amplitude smaller than the first sub-common signal CFVCOM1.

[0081] Furthermore, when the size of the first display area A1 is large, in order to prevent the first sub-common signal CFVCOM1 from being greatly attenuated due to the large impedance of the first sub-common electrode 1031, the number of the first sub-common voltage lines (for example, the first power line 201 described above) can be set to multiple ( Figure 6 Two examples are used in this paper.)

[0082] It should be noted that this embodiment is merely described by taking the signal processing circuit 304 being independent of the power manager 303 as an example. In fact, the power manager 303 can also perform the function of the signal processing circuit 304 .

[0083] In some embodiments, in combination Figures 1 to 4 , Figure 7 As shown, the multiple sub-pixels P include multiple first color sub-pixels corresponding to the same color (not shown), and the display panel 100 also includes: multiple data lines (DL1 to DLm) mentioned above, each of the data lines is electrically connected to the corresponding multiple pixel circuits 40, and is used to transmit the multiple data signals data mentioned above, and the data signals data include the multiple data voltages Vdata corresponding to the multiple sub-pixels P; wherein, at the same refresh rate and when the grayscale values ​​of the two first sub-pixels corresponding to the first pixel circuit 401 and the second pixel circuit 402 are the same, the two data voltages Vdata corresponding to the two first color sub-pixels are different.

[0084] In combination with the above discussion, it can be known that, whether in the pixel circuit 40 of the liquid crystal display panel or the self-luminous display panel, the brightness presented by the sub-pixel P is related to the data voltage Vdata. Therefore, in this embodiment, when flickering occurs in the second display area A2, under the condition that the refresh rate, the color corresponding to the sub-pixel P, the grayscale value of the sub-pixel P and other factors are the same, the data voltage Vdata acting on the second display area A2 is set to be different from the data voltage Vdata acting on the first display area A1, thereby compensating for the difference in the capacitance value of the capacitor C in the second display area A2 relative to the capacitance value of the capacitor C in the first display area A1, thereby improving the flickering phenomenon of the second display area A2 relative to the first display area A1.

[0085] In some embodiments, in combination Figures 1 to 4 , Figure 7 As shown, the display panel 100 also includes: a gamma circuit 305, used to generate a first gamma binding point voltage Gamma 1 and a second gamma binding point voltage Gamma2; the above-mentioned source driver 301, electrically connected to the gamma circuit 305, used to generate the data signal data as the first data signal data1 according to the above-mentioned grayscale signal Sg and the first gamma binding point voltage Gamma 1, and also used to generate the data signal data1 as the second data signal data2 according to the grayscale signal Sg and the second gamma binding point voltage Gamma2; wherein the data line electrically connected to the first pixel circuit 401 is used to transmit the first data signal data1, and the data line electrically connected to the second pixel circuit 402 is used to transmit the second data signal data2.

[0086] Specifically, the gamma circuit 305 can generate at least a first gamma binding point voltage Gamma 1 and a second gamma binding point voltage Gamma 2 corresponding to the first color sub-pixel according to the power supply voltage provided by the power manager 303. Each of the first gamma binding point voltage Gamma 1 and the second gamma binding point voltage Gamma 2 may include multiple binding point voltages. Under the same grayscale value of the same refresh rate, the source driver 301 can also generate a first data signal voltage Vdata1 and a second data voltage Vata2 with different amplitudes based on the first gamma binding point voltage Gamma 1 and the second gamma binding point voltage Gamma 2, respectively, so that the first data signal data1 output by the data line connected to the first pixel circuit 401 and the second data signal data2 output by the data line connected to the second pixel circuit 402 are also different.

[0087] It should be noted that the present embodiment is merely described by taking the gamma circuit 305 being independent of the source driver 301 as an example. In fact, the source driver 301 can also perform the function of the gamma circuit 305 .

[0088] Further, combined with Figures 1 to 4 , Figure 7 As shown, the first gamma binding point voltage Gamma 1 includes a first sub-gamma binding point voltage Gamma 1a and a second sub-gamma binding point voltage Gamma 1b, and the second gamma binding point voltage Gamma 2 includes a third sub-gamma binding point voltage Gamma 2a and a fourth sub-gamma binding point voltage Gamma 2b; at a first refresh rate f1, the source driver 301 is used to generate the first data signal data1 according to the grayscale signal Sg and the first sub-gamma binding point voltage Gamma 1a, and is also used to generate the second data signal data2 according to the grayscale signal Sg and the third sub-gamma binding point voltage Gamma 2a; at a second refresh rate f2, the source driver 301 is used to generate the first data signal data1 according to the grayscale signal Sg and the second sub-gamma binding point voltage Gamma 1b, and is also used to generate the second data signal data2 according to the grayscale signal Sg and the fourth sub-gamma binding point voltage Gamma 2b.

[0089] That is, in this embodiment, the first gamma binding point voltage Gamma 1 and the second gamma binding point voltage Gamma 2 are refined from the refresh rate dimension. When factors such as the color corresponding to the sub-pixel P and the grayscale value of the sub-pixel P are the same, whether it is the first gamma binding point voltage Gamma 1 acting on the first display area A1 or the second gamma binding point voltage Gamma 2 acting on the second display area A2, both are further refined to include corresponding multiple sub-gamma binding point voltages according to the difference in refresh rate. Similarly, each sub-gamma binding point voltage still includes multiple binding point voltages.

[0090] Of course, if Figure 6 As shown, the first gamma binding point voltage Gamma 1 may further include a fifth sub-gamma binding point voltage Gamma 1c corresponding to the third refresh rate f3, and the second gamma binding point voltage Gamma 2 may further include a sixth sub-gamma binding point voltage Gamma 1c corresponding to the third refresh rate f3. The first refresh rate f1, the second refresh rate f2, and the third refresh rate f3 may be, but are not limited to, 60HZ, 120HZ, and 240HZ, respectively.

[0091] It can be understood that this embodiment sets the gamma binding point voltages of different regions differently according to the refresh rate differences. In the process of generating the data signal data, both the regional differences and the refresh rate differences need to be considered, which can improve the screen flickering problem caused by both the regional differences and the refresh rate differences.

[0092] The present invention provides a display device, such as Figure 8As shown, the display device 1000 comprises: a display panel 100 as described above; and a housing 200 for accommodating the display panel 100. The housing 200 may cover a non-display area around a display area A of the display panel 100.

[0093] The display panel and the display device provided in the embodiments of the present invention are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The display area of ​​the display panel includes a first display area and a second display area, including: A plurality of pixel electrodes, including a plurality of first pixel electrodes located in the first display area and a plurality of second pixel electrodes located in the second display area; a plurality of pixel circuits corresponding to the plurality of pixel electrodes, including a plurality of first pixel circuits electrically connected to the plurality of first pixel electrodes, and a plurality of second pixel circuits electrically connected to the plurality of second pixel electrodes, each of the pixel circuits including a capacitor, and a capacitance value of the capacitor of the first pixel circuit is different from a capacitance value of the capacitor of the second pixel circuit; A first power line, used for transmitting a first power signal; A second power line, used for transmitting a second power signal; Wherein, the plurality of first pixel circuits include a first sub-common electrode having an area facing the plurality of first pixel electrodes, and a second sub-common electrode having an area facing the plurality of second pixel electrodes; Wherein, the first power signal transmitted by the power line to the first sub-common electrode and the second power signal transmitted to the second sub-common electrode are different.

2. The display panel according to claim 1, wherein: The pixel circuit includes a driving transistor, one of a source and a drain of the driving transistor is electrically connected to the pixel electrode; The capacitor comprises a first capacitor, a first plate of the first capacitor is one of a source and a drain of the driving transistor, and a second plate of the first capacitor is a gate of the driving transistor; The area facing one of the source and drain of the driving transistor in the first pixel circuit and the gate is different from the area facing one of the source and drain of the driving transistor in the second pixel circuit and the gate.

3. The display panel according to claim 2, wherein: The pixel circuit comprises: A first common electrode is arranged in the same layer as the plurality of pixel electrodes; a second common electrode, disposed opposite to the plurality of pixel electrodes and the first common electrode; The capacitor further includes a second capacitor and a third capacitor, the first plate of the second capacitor and the first plate of the third capacitor both include the pixel electrode, the second plate of the second capacitor is the first common electrode, and the second plate of the third capacitor is the second common electrode; Wherein, an area directly facing the first pixel electrode and the first common electrode is different from an area directly facing the second pixel electrode and the first common electrode; And / or, an area where the first pixel electrode faces the second common electrode is different from an area where the second pixel electrode faces the second common electrode.

4. The display panel according to claim 1, wherein: The first sub-common electrode is disposed opposite to the plurality of first pixel electrodes, and the second sub-common electrode is disposed opposite to the plurality of second pixel electrodes.

5. The display panel according to claim 4, wherein: The pixel circuit further comprises a first common electrode disposed in the same layer as the plurality of pixel electrodes, wherein the potentials of the plurality of pixel electrodes are alternately greater than the potentials of the first sub-common electrode and the second sub-common electrode, and less than the potentials of the first sub-common electrode and the second sub-common electrode in multiple frames; The power line transmits a third power signal and a fourth power signal to the first common electrode alternately within a plurality of frames.

6. The display panel according to claim 1, wherein: Also includes: A power manager, configured to output the first power signal to the first power line; The signal processing circuit is connected between the power manager and the second power line, and is used to generate the second power signal output to the second power line according to the first power signal.

7. The display panel according to any one of claims 1 to 6, characterized in that: The plurality of sub-pixels include a plurality of first color sub-pixels corresponding to the same color, and the display panel further includes: a plurality of data lines, each of the data lines being electrically connected to a corresponding plurality of the pixel circuits and configured to transmit a plurality of data signals, the data signals comprising a plurality of data voltages corresponding to the plurality of the sub-pixels; When the grayscale values ​​of the two first color sub-pixels, which are the first pixel electrode and the second pixel electrode respectively, are the same at the same refresh rate, the two data voltages corresponding to the two data signals corresponding to the two first color sub-pixels are different.

8. The display panel according to claim 7, wherein: Also includes: a source driver, comprising a gamma circuit for generating a first gamma binding point voltage and a second gamma binding point voltage, the source driver being used to generate the data signal as a first data signal according to a grayscale signal and the first gamma binding point voltage, and further being used to generate the data signal as a second data signal according to the grayscale signal and the second gamma binding point voltage; The data line electrically connected to the first pixel circuit is used to transmit the first data signal, and the data line electrically connected to the second pixel circuit is used to transmit the second data signal.

9. The display panel according to claim 8, wherein: The first gamma binding point voltage includes a first sub-gamma binding point voltage and a second sub-gamma binding point voltage, and the second gamma binding point voltage includes a third sub-gamma binding point voltage and a fourth sub-gamma binding point voltage; At a first refresh rate, the source driver is used to generate the first data signal according to the grayscale signal and the first sub-gamma binding point voltage, and is also used to generate the second data signal according to the grayscale signal and the third sub-gamma binding point voltage; At the second refresh rate, the source driver is used to generate the first data signal according to the grayscale signal and the second sub-gamma binding point voltage, and is also used to generate the second data signal according to the grayscale signal and the fourth sub-gamma binding point voltage.

10. A display device, characterized in that: include: The display panel according to any one of claims 1 to 9; The housing is used to accommodate the display panel.

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