Gate drive circuit and display device

Abstract

The application provides a gate driving circuit and a display device. The gate driving circuit comprises a first node control circuit, a first maintaining circuit, a first output circuit and a first node stabilizing circuit. The first node control circuit is configured to control the voltage level of the first node. The first maintaining circuit is configured to maintain the voltage level of the first node according to the voltage level of the second node. The first output circuit is configured to output a gate signal from a gate signal output end according to the voltage level of the first node. The first node stabilizing circuit is configured to be turned on according to a touch signal of the first level during a touch period to control the voltage level of the second node, so that the first maintaining circuit is turned off, and the voltage level of the first node is stabilized. In this way, the first node stabilizing circuit improves the problem of current leakage of the first node through the first maintaining circuit during the touch period, stabilizes the voltage level of the first node during the touch period, and further improves the display abnormality problem of the voltage level of the first node caused by current leakage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of gate driving circuit, and in particular to a gate driving circuit and a display device. BACKGROUND

[0002] Generally, the gate driving circuit in the display device is composed of multiple levels of gate driving units connected in series. Each level of gate driving unit is used to output a gate driving signal, and the corresponding pixel row is turned on by the gate driving signal, so that each pixel in the pixel row can write the required display data.

[0003] However, in the touch state, the touch signal will affect the gate driving signal output by the gate driving circuit, thereby causing display abnormalities. SUMMARY

[0004] The embodiments of the present application provide a gate driving circuit and a display device to improve the display abnormality problem of the voltage level of the first node of the gate driving circuit caused by leakage, to at least solve part of the above problems.

[0005] In a first aspect, the embodiments of the present application provide a gate driving circuit. The gate driving circuit includes a first node control circuit, a first maintenance circuit, a first output circuit, and a first node voltage stabilizing circuit. The first node control circuit is configured to control the voltage level of the first node. The first maintenance circuit is configured to maintain the voltage level of the first node according to the voltage level of the second node. The first output circuit is configured to output a gate signal from a gate signal output terminal according to the voltage level of the first node. The first node voltage stabilizing circuit is configured to turn on to control the voltage level of the second node according to the first level touch signal input from the touch signal input terminal in the touch period, so that the first maintenance circuit is closed, and the voltage level of the first node is stabilized.

[0006] In a second aspect, the embodiments of the present application also provide a display device. The display device includes the above-mentioned gate driving circuit.

[0007] In the gate driving circuit and the display device of the embodiments of the present application, the first node voltage stabilizing circuit improves the problem of leakage of the first node through the first maintenance circuit in the touch period, stabilizes the voltage level of the first node in the touch period, and further improves the display abnormality problem of the voltage level of the first node caused by leakage. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 The structural schematic diagram of the gate driving circuit provided by the embodiments of the present application is shown in the figure;

[0009] Figure 2 The circuit schematic diagram of the Nth gate driving unit provided by the embodiments of the present application is shown in the figure;

[0010] Figure 3 A timing diagram of the gate drive circuit is provided for the embodiments of the present application.

[0011] Figure 4 A cross-sectional structure schematic diagram of the display device is provided for the embodiments of the present application.

[0012] The reference signs are as follows:

[0013] 100, the gate drive circuit;

[0014] 200, the gate drive unit; 210, the (N-i)th gate drive unit; 220, the Nth gate drive unit; 230, the (N+j)th gate drive unit;

[0015] 301, the first node control circuit; T11, the first node control transistor;

[0016] 302, the first sustain circuit; T42, T43, the first sustain transistor;

[0017] 303, the first output circuit; T21, the first output transistor; T31, the second output transistor;

[0018] 304, the first node voltage stabilizing circuit; T91, T92, the first node voltage stabilizing transistor;

[0019] 305, the reset circuit; TrQ, the reset transistor;

[0020] 306, the second sustain circuit; T41, the second sustain transistor;

[0021] 307, the second node control circuit; 3071, the first inverter; 3072, the second inverter; T51, T61, the first transistor; T52, T62, the second transistor; T54, T64, the third transistor; T53, T63, the fourth transistor;

[0022] 308, the third sustain circuit; T32, T33, the third sustain transistor;

[0023] 309, the second output circuit; T22, the third output transistor;

[0024] 310, the fourth sustain circuit; T72, T73, the fourth sustain transistor;

[0025] 311, the touch voltage stabilizing circuit; T81, the touch voltage stabilizing transistor;

[0026] Cb, the capacitor;

[0027] VGL, the first voltage input terminal;

[0028] TP, touch signal input end;

[0029] ST(N+j), first-stage transmission signal; ST(n+j), first-stage transmission signal input end;

[0030] ST(N-i), second-stage transmission signal; ST(n-i), second-stage transmission signal input end;

[0031] ST(N), third-stage transmission signal; ST(n), third-stage transmission signal output end;

[0032] CK(n), clock signal input end;

[0033] G(n), gate signal output end; Reset, reset signal input end;

[0034] LC1, LC2, second voltage input end;

[0035] Q(n), first node; K(n), P(n), second node;

[0036] 400, display device; 500, display panel; 501, substrate; 502, counter substrate; 503, pixel electrode layer; 504, drive circuit layer; 600, touch layer. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0038] Please refer to Figure 1 As shown in the figure, the embodiment of the present application provides a gate drive circuit 100. The gate drive circuit 100 is applied to a display panel including a touch layer. In other words, the gate drive circuit 100 is applied to a display panel with touch function.

[0039] The display panel can be at least one of a liquid crystal display panel, an organic light emitting diode display panel, a micro light emitting diode display panel, a sub-millimeter light emitting diode display panel, and a quantum dot display panel. The touch layer can be integrated in the inside of the display panel, and the touch layer can also be externally hung on the outside of the display panel.

[0040] The gate drive circuit 100 includes a plurality of gate drive units 200. The plurality of gate drive units 200 are used to output multi-stage scanning signals. For example, refer to Figure 1As shown, the plurality of gate driving units 200 includes an (N-i)th gate driving unit 210, an Nth gate driving unit 220, and an (N+j)th gate driving unit 230, i and j are integers greater than or equal to 1, and N is an integer greater than or equal to 2. The (N+j)th gate driving unit 230 outputs a scan signal G(N+j) and a first-stage transmission signal ST(N+j). The (N-i)th gate driving unit 210 outputs a scan signal G(N-i) and a second-stage transmission signal ST(N-i). The Nth gate driving unit 220 outputs a scan signal G(N) and a third-stage transmission signal ST(N). The first-stage transmission signal ST(N+j) is a post-stage transmission signal of the third-stage transmission signal ST(N). The second-stage transmission signal ST(N-i) is a pre-stage transmission signal of the third-stage transmission signal ST(N).

[0041] In order to describe the technical solutions of the embodiments of the present application, the Nth gate driving unit is taken as an example for description, and N is an integer greater than or equal to 2.

[0042] Please refer to Figure 2 As shown, the gate driving circuit 100 includes a first node control circuit 301, a first maintenance circuit 302, a first output circuit 303, and a first node voltage stabilizing circuit 304.

[0043] The first node control circuit 301 is configured to control the voltage level of the first node Q(n). The first maintenance circuit 302 is configured to maintain the voltage level of the first node Q(n) according to the voltage level of the second node ((K(n), P(n))). The first output circuit 303 is configured to output a gate signal from a gate signal output terminal G(n) according to the voltage level of the first node Q(n). The first node voltage stabilizing circuit 304 is configured to be turned on to control the voltage level of the second node ((K(n), P(n))) according to a first-level touch signal input from a touch signal input terminal TP in a touch period, so that the first maintenance circuit 302 is turned off, and the voltage level of the first node Q(n) is stabilized.

[0044] The first node voltage stabilizing circuit 304 of the gate driving unit 200 pulls down the second node ((K(n), P(n))) to a low level according to the first-level touch signal, and the first maintenance circuit 302 is turned off according to the low level of the second node ((K(n), P(n))), which improves the problem of leakage of the first node Q(n) through the first maintenance circuit 302 in the touch period, stabilizes the voltage level of the first node Q(n) in the touch period, and further improves the display abnormality problem of the voltage level of the first node Q(n) caused by leakage.

[0045] It should be noted that, in the touch period, in order to reduce the influence of touch on the display process, the selected scanning line is usually paused in the touch stage. For example, the pause gate drive circuit continues to output the on scanning signal to the selected scanning line. However, in the pre-charge period of the first node of the current stage gate drive circuit, the first node is at a high potential, and the pause operation will cause the risk of leakage of the first node. The leakage of the first node will cause the level of the output current stage transmission signal to be low, causing the charging rate of the lower stage gate drive circuit charged according to the current stage transmission signal to decrease, or causing the lower stage gate drive circuit opened according to the current stage transmission signal to fail to open, thereby causing display abnormal problems such as horizontal lines or row constant black.

[0046] In addition, for the non-selected scanning line, when the voltage level of the first node of the gate drive unit connected by the non-selected scanning line is low, the voltage level of the second node is high. If the first node stabilizing circuit 304 is not additionally provided, the first maintaining circuit 302 will be turned on according to the high level of the second node, so that the voltage level of the first node Q(n) is pulled down to low.

[0047] In the embodiments of the present application, whether the scanning line connected by the gate drive unit is selected or not, in the touch stage, the first node stabilizing circuit 304 additionally provided pulls down the voltage level of the second node (K(n), P(n)) according to the first level of the touch signal, and the first maintaining circuit 302 is in the off state according to the level pulled down by the second node (K(n), P(n)), so that the first node Q(n) is hardly leaked from the first maintaining circuit 302. Therefore, after the first node Q(n) is switched from the pre-charge period of the display stage to the touch stage, the voltage level of the first node Q(n) is hardly stable in the touch stage, which improves the display abnormal problems such as horizontal lines or row constant black caused by leakage when the first node Q(n) is switched from the pre-charge period of the display stage to the touch stage.

[0048] In some embodiments, the first node stabilizing circuit 304 is further configured to be turned off in the display stage according to the second level of the touch signal input from the touch signal input terminal TP. The second level is lower than the first level. That is, the first node stabilizing circuit 304 is turned on in the touch stage according to the high level of the touch signal, and is turned off in the display stage according to the low level of the touch signal, which improves the display abnormal problems caused by the leakage of the voltage level of the first node Q(n) in the touch stage, and reduces the influence of the first node stabilizing circuit 304 on the display process.

[0049] In some embodiments, the first node voltage stabilizing circuit 304 comprises first node voltage stabilizing transistors (T91, T92). The source and drain of the first node voltage stabilizing transistors (T91, T92) are connected between the second node (K(n), P(n)) and the first voltage input VGL. The gate of the first node voltage stabilizing transistors (T91, T92) is connected to the touch signal input TP.

[0050] In some embodiments, the first voltage input VGL is configured to input a first level signal. The first level signal has a low level.

[0051] In some embodiments, the first node voltage stabilizing circuit 304 can comprise one or more first node voltage stabilizing transistors (T91, T92).

[0052] In one example embodiment, as shown in FIG. 4, the first node voltage stabilizing circuit 304 can comprise a first node voltage stabilizing transistor T91 and a first node voltage stabilizing transistor T92. The first node voltage stabilizing transistor T91 and the first node voltage stabilizing transistor T92 are periodically alternately operated. The source and drain of the first node voltage stabilizing transistor T91 are connected between the second node K(n) and the first voltage input VGL. The source and drain of the first node voltage stabilizing transistor T92 are connected between the second node P(n) and the first voltage input VGL. The gates of the first node voltage stabilizing transistor T91 and the first node voltage stabilizing transistor T92 are both connected to the touch signal input TP. Figure 2

[0053] In some embodiments, the first node voltage stabilizing transistors (T91, T92) are N-type transistors or P-type transistors. The first node voltage stabilizing transistors (T91, T92) are selected from any one of low temperature poly-silicon transistors, metal-oxide transistors, and single-crystal silicon transistors. Exemplarily, the first node voltage stabilizing transistors (T91, T92) are N-type low temperature poly-silicon transistors.

[0054] In some embodiments, referring to FIG. 4, the first node voltage stabilizing circuit 304 can comprise a first node voltage stabilizing transistor T91 and a first node voltage stabilizing transistor T92. The first node voltage stabilizing transistor T91 and the first node voltage stabilizing transistor T92 are periodically alternately operated. The source and drain of the first node voltage stabilizing transistor T91 are connected between the second node K(n) and the first voltage input VGL. The source and drain of the first node voltage stabilizing transistor T92 are connected between the second node P(n) and the first voltage input VGL. The gates of the first node voltage stabilizing transistor T91 and the first node voltage stabilizing transistor T92 are both connected to the touch signal input TP. Figure 2 ​As shown, the first node control circuit 301 comprises a first node control transistor T11. The source and drain of the first node control transistor T11 are connected between the first node Q(n) and the second stage transmission signal input terminal ST(n-i) or the start signal input terminal STV. The gate of the first node control transistor T11 is connected with the second stage transmission signal input terminal ST(n-i) or the start signal input terminal STV. In this way, the first node control transistor T11 controls the voltage level of the first node Q(n) according to the second stage transmission signal ST(N-i) input by the second stage transmission signal input terminal ST(n-i) or the start signal input by the start signal input terminal STV. For example, the high level second stage transmission signal ST(N-i) or the start signal is output to the first node Q(n), which pulls up the voltage level of the first node Q(n) and pre-charges the first node Q(n) in turn.

[0055] It should be noted that for the first several stage gate drive units of the gate drive circuit 100, for example, the first stage gate drive unit, the source and drain of the first node control transistor T11 can be connected between the start signal input terminal STV and the first node Q(n), and the gate of the first node control transistor T11 can be connected between the start signal input terminal STV and the first node Q(n).

[0056] For the gate drive units other than the first several stage gate drive units, for example, the Nth stage gate drive unit, the source and drain of the first node control transistor T11 can be connected between the second stage transmission signal input terminal ST(n-i) and the first node Q(n), and the gate of the first node control transistor T11 is connected with the second stage transmission signal input terminal ST(n-i).

[0057] In some embodiments, the second stage transmission signal input terminal ST(n-i) inputs a second stage transmission signal, which is a previous stage transmission signal output by a previous stage gate drive unit (the (N-i)th stage gate drive unit) of the Nth stage gate drive unit. In the case that the second stage transmission signal is the previous stage transmission signal, the first node control circuit 301 can realize pre-charging of the first node Q(n) according to the previous stage transmission signal, and improve the charging rate of the first node Q(n).

[0058] In an exemplary embodiment, i is equal to 4, but is not limited thereto. It can be understood that i can also be 1, 2, 3 or 8, etc.

[0059] In some embodiments, the first node control transistor T11 is an N-type transistor or a P-type transistor. The first node control transistor T11 is selected from any one of a low temperature poly-silicon transistor, a metal oxide transistor and a single crystal silicon transistor. Exemplarily, the first node control transistor T11 is an N-type low temperature poly-silicon transistor.

[0060] In some embodiments, referring to Figure 2 As shown in FIG. 3, the first output circuit 303 includes a first output transistor T21. The source and drain of the first output transistor T21 are connected between the clock signal input terminal CK(n) and the gate signal output terminal G(n). The gate of the first output transistor T21 is connected to the first node Q(n). In this way, the first output transistor T21 can disconnect or connect the clock signal input terminal CK(n) and the gate signal output terminal G(n) according to the voltage level of the first node Q(n).

[0061] The clock signal input terminal CK(n) is configured to output a clock signal. The clock signal includes a high-level clock signal and a low-level clock signal. In some embodiments, the plurality of clock signal input terminals CK(n) includes a first clock signal input terminal CK(1) to an eighth clock signal input terminal CK(8), but is not limited thereto.

[0062] In an exemplary embodiment, the first output transistor T21 turns on according to the high level of the first node Q(n), outputs the high-level clock signal to the gate signal output terminal G(n) as a high-level scan signal, the high-level scan signal is a turn-on scan signal, can select the pixel connected to the scan line, so that the pixel receives the data signal. Also, the first output transistor T21 also turns on according to the high level of the first node Q(n), outputs the low-level clock signal to the gate signal output terminal G(n) as a low-level scan signal, the low-level scan signal is a turn-off scan signal, cannot select the pixel connected to the scan line, so that the pixel cannot receive the data signal. Therefore, the scan signal is output by the first output transistor T21.

[0063] In some embodiments, referring to Figure 2 As shown in FIG. 3, the first output circuit 303 can also include a second output transistor T31. The source and drain of the second output transistor T31 are connected between the first voltage input terminal VGL and the gate signal output terminal G(n). The gate of the second output transistor T31 is connected to the first-stage transmission signal input terminal ST(n+j). In this way, the second output transistor T31 can pull the voltage level of the gate signal output terminal G(n) to the low level corresponding to the first-level signal according to the first-stage transmission signal.

[0064] The first-stage transmission signal input terminal ST(n+j) inputs a first-stage transmission signal ST(N+j). The first-stage transmission signal ST(N+j) is a back-stage transmission signal output by a back-stage gate driving unit of the Nth-stage gate driving unit (the (N+j)th gate driving unit). In the case that the first-stage transmission signal ST(N+j) is a back-stage transmission signal, the first output circuit 303 can pull down the first node Q(n) to the low level according to the back-stage transmission signal.

[0065] In one exemplary embodiment, j is equal to i, and is equal to 4, but is not limited thereto. It can be appreciated that j can also be 1, 2, 3, or 8, etc.

[0066] In another exemplary embodiment, in the case that the first output transistor T21 outputs a high level clock signal as a high level scan signal to the gate signal output terminal G(n), i.e., the first output transistor T21 functions to pull up the level of the gate signal output terminal G(n), the second output transistor T31 can output a low level first level signal as a low level scan signal to the gate signal output terminal G(n), i.e., the second output transistor T31 functions to pull down the level of the gate signal output terminal G(n).

[0067] In some embodiments, the gate driving circuit 100 further comprises a capacitor Cb. Two electrodes of the capacitor Cb are connected between the first node Q(n) and the gate signal output terminal G(n). In the case that the gate signal output terminal G(n) outputs a high level scan signal, the capacitor Cb raises the voltage level of the first node Q(n) through its own coupling effect, improving the stability of the first output transistor T21 outputting a high level scan signal.

[0068] In some embodiments, the first maintaining circuit 302 comprises a first maintaining transistor (T42, T43). The source and drain of the first maintaining transistor (T42, T43) are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the first maintaining transistor (T42, T43) is connected with the second node (K(n), P(n)). When switching from the pre-charge period of the display stage to the touch stage, the source and drain of the first maintaining transistor (T42, T43) are respectively the high level of the first node Q(n) and the first level of the touch signal, and the voltage difference between the two is small, reducing the risk of the first node Q(n) leaking through the first maintaining circuit 302 in the touch stage.

[0069] Also, in the display stage, when the voltage level of the first node Q(n) is high and the voltage level of the second node (K(n), P(n)) is low, the first maintaining transistor (T42, T43) is in the off state to maintain the high level state of the first node Q(n). When the voltage level of the first node Q(n) is low and the voltage level of the second node (K(n), P(n)) is high, the first maintaining transistor (T42, T43) is in the on state, which outputs the second level of the touch signal as a low level to the first node Q(n) to maintain the low level state of the first node Q(n).

[0070] In some embodiments, the first sustain circuit 302 can include one or more first sustain transistors (T42, T43).

[0071] In some embodiments, the first sustain circuit 302 can include one or more first sustain transistors (T42, T43).

[0072] In some embodiments, the first sustain circuit 302 can include one or more first sustain transistors (T42, T43).

[0073] In some embodiments, the first sustain circuit 302 can include one or more first sustain transistors (T42, T43). Figure 2 As shown, the gate driving circuit 100 further includes a reset circuit 305. The reset circuit 305 is configured to connect the touch signal input terminal TP and the first node Q(n) according to the reset signal of the third level input by the reset signal input terminal Reset in the display stage, so as to reset the voltage level of the first node Q(n) and improve the performance influence of the first node Q(n) on the gate driving circuit. Therefore, the touch signal of the second level input by the touch signal input terminal TP is fully utilized as the reset signal of the first node in the display stage.

[0074] In some embodiments, the reset circuit 305 is further configured to disconnect the first node Q(n) from the touch signal input terminal TP according to a fourth level reset signal inputted by the reset signal input terminal Reset during the touch period. The fourth level is lower than the third level. In this way, the reset circuit 305 is turned on according to the high level reset signal during the display stage, and is turned off according to the low level reset signal during the touch stage, so as to make full use of the first level touch signal or the second level touch signal outputted by the touch signal input terminal TP. Moreover, when switching from the pre-charge period of the display stage to the touch stage, the high level of the first node Q(n) and the first level touch signal inputted by the reset circuit 305 are connected to both ends of the reset circuit 305, and the voltage difference between the two is small, thereby reducing the risk of leakage of the first node Q(n) through the reset circuit 305 during the touch stage.

[0075] In some embodiments, the reset circuit 305 comprises a reset transistor TrQ. The source and drain of the reset transistor TrQ are connected between the first node Q(n) and the touch signal input terminal TP. The gate of the reset transistor TrQ is connected to the reset signal input terminal Reset. In this way, the reset transistor TrQ can reset the voltage level of the first node during the display stage, and reduce the risk of leakage of the first node Q(n) during the touch stage.

[0076] In some other embodiments, the reset circuit 305 comprises a reset transistor TrQ. The source and drain of the reset transistor TrQ are connected between the first node Q(n) and the first voltage input terminal VGL. The gate of the reset transistor TrQ is connected to the reset signal input terminal Reset. In this way, when the reset transistor TrQ is turned on according to the high level reset signal during the display stage, the first level signal is outputted to the first node Q(n) to reset the first node Q(n).

[0077] In some embodiments, referring to Figure 2 As shown, the gate drive circuit 100 further comprises a second maintaining circuit 306. The second maintaining circuit 306 is configured to connect the touch signal input terminal TP and the first node Q(n) according to the fifth level first stage transmission signal ST(N+j) inputted by the first stage transmission signal input terminal ST(n+j) during the display stage, so as to maintain the potential of the first node Q(n). Therefore, during the display stage, when the voltage level of the first node Q(n) is low, the second maintaining circuit 306 is turned on to output the second level touch signal to the first node Q(n), thereby maintaining the low level state of the first node Q(n).

[0078] In some embodiments, the second sustain circuit 306 is further configured to disconnect the first node Q(n) from the touch signal input TP according to the sixth level of the first stage signaling signal ST(N+j) inputted by the first stage signaling signal input ST(n+j) during the touch period. The sixth level is lower than the fifth level. Therefore, when switching from the pre-charge period of the display stage to the touch stage, the voltage difference between the high level of the first node and the first level of the touch signal inputted by the two ends of the turned-off second sustain circuit 306 is smaller, which reduces the risk of the first node Q(n) leaking through the second sustain circuit 306 during the touch stage.

[0079] In some embodiments, the second sustain circuit 306 includes a second sustain transistor T41. The source and the drain of the second sustain transistor T41 are connected between the first node Q(n) and the touch signal input TP. The gate of the second sustain transistor T41 is connected with the first stage signaling signal input ST(n+j). In this way, the second sustain transistor T41 is connected or disconnected between the touch signal input TP and the first node according to the fifth level or the sixth level of the first stage signaling signal ST(N+j) inputted by the first stage signaling signal input ST(n+j).

[0080] In some other embodiments, the second sustain circuit 306 includes a second sustain transistor T41. The source and the drain of the second sustain transistor T41 can be connected between the first node Q(n) and the first voltage input VGL. The gate of the second sustain transistor T41 is connected with the first stage signaling signal input ST(n+j). In this way, during the display stage, when the voltage level of the first node Q(n) is low, the second sustain transistor T41 is turned on according to the fifth level of the first stage signaling signal ST(N+j) to output the first level signal to the first node Q(n) to maintain the low level state of the first node Q(n).

[0081] In some embodiments, referring to Figure 2 As shown, the gate driving circuit 100 further includes a second node control circuit 307. The second node control circuit 307 is configured to make the phase of the voltage level of the second node (K(n), P(n)) opposite to the phase of the voltage level of the first node Q(n) according to the voltage level of the first node Q(n). Therefore, the second node control circuit 307 can function as an inverter.

[0082] In some embodiments, the second node control circuit 307 includes a first transistor (T51, T61) and a second transistor (T52, T62). The source and drain of the first transistor (T51, T61) are connected between the second node (K(n), P(n)) and the second voltage input terminal (LC1, LC2). The gate of the first transistor (T51, T61) is connected to the second voltage input terminal (LC1, LC2). The source and drain of the second transistor (T52, T62) are connected between the second node (K(n), P(n)) and the first voltage input terminal VGL, and the gate of the second transistor (T52, T62) is connected to the first node Q(n). During the display and touch phases, when the voltage level of the first node Q(n) is high, the second transistor (T52, T62) is turned on, outputting a first-level signal to the second node (K(n), P(n)), making the voltage level of the second node (K(n), P(n)) low. During the display and touch phases, when the voltage level of the first node Q(n) is low, the second thin-film transistor (T52, T62) is turned off, and the first transistor (T51, T61) is turned on, outputting the second level signal to the second node (K(n), P(n)), making the voltage level of the second node (K(n), P(n)) high.

[0083] In some embodiments, the second voltage input terminals (LC1, LC2) output a second level signal. During the display phase, the second level signal can be a high level signal. During the touch phase, the second level signal can be a low level signal.

[0084] In some embodiments, see Figure 2 As shown, the second node control circuit 307 may further include a fourth transistor (T53, T63). The source and drain of the fourth transistor (T53, T63) are connected between the second node (K(n), P(n)) and one of the source and drain of the first transistor (T51, T61). The gate of the fourth transistor (T53, T63) is connected to the second voltage input terminals (LC1, LC2). In this way, the driving capability of the fourth transistor (T53, T63) and the first transistor (T51, T61) can be reduced, ensuring that the second transistor (T52, T62) can pull down the voltage level of the second node (K(n), P(n)).

[0085] In one exemplary embodiment, the second node control circuit 307 may include a first inverter 3071 and a second inverter 3072. The first inverter 3071 and the second inverter 3072 operate alternately periodically.

[0086] The first inverter 3071 includes a first transistor T51, a fourth transistor T53, and a second transistor T52. The gates of the first transistor T51 and the fourth transistor T53 are connected to the second voltage input terminal LC1. The source and drain of the first transistor T51 and the source and drain of the fourth transistor T53 are connected between the second voltage input terminal LC1 and the second node K(n). The source and drain of the second transistor T52 are connected between the second node K(n) and the first voltage input terminal VGL, and the gate of the second transistor T52 is connected to the first node Q(n).

[0087] The second inverter 3072 includes a first transistor T61, a fourth transistor T63, and a second transistor T62. The gates of the first transistor T61 and the fourth transistor T63 are connected to the second voltage input terminal LC2. The source and drain of the first transistor T61 and the source and drain of the fourth transistor T63 are connected between the second voltage input terminal LC2 and the second node P(n). The source and drain of the second transistor T62 are connected between the second node P(n) and the first voltage input terminal VGL, and the gate of the second transistor T62 is connected to the first node Q(n).

[0088] In some embodiments, see Figure 2 As shown, the second node control circuit 307 is also configured to pull down the voltage level of the second node (K(n), P(n)) according to the second-level transmission signal ST(Ni) before the voltage level of the first node Q(n) is pulled up. Pulling down the voltage level of the second node (K(n), P(n)) before the voltage level of the first node Q(n) is pulled up can reduce the risk of leakage current from the first node Q(n) through the first sustaining circuit 302, thereby ensuring the charging rate of the first node Q(n) by the first node control circuit 301 according to the second-level transmission signal ST(Ni).

[0089] In some embodiments, the second node control circuit 307 further includes a third transistor (T54, T64). The source and drain of the third transistor (T54, T64) are connected between the second node (K(n), P(n)) and the first voltage input terminal VGL, and the gate of the third transistor (T54, T64) is connected to the second stage transmission signal input terminal ST(ni). Thus, before the voltage level of the first node Q(n) is pulled high, the third transistor (T54, T64) pulls down the voltage level of the second node (K(n), P(n)) according to the second stage transmission signal ST(ni), which can reduce the risk of leakage current of the first node Q(n) through the first sustaining circuit 302, so as to ensure the charging rate of the first node Q(n) by the first node control circuit 301 according to the second stage transmission signal ST(ni).

[0090] In some embodiments, the number of third transistors (T54, T64) can be one or more.

[0091] In one exemplary embodiment, the second node control circuit 307 includes a third transistor T54 and a third transistor T64. The third transistor T54 and the third transistor T64 work periodically and alternately. The source and the drain of the third transistor T54 are connected between the second node K(n) and the first voltage input terminal VGL. The source and the drain of the third transistor T64 are connected between the second node P(n) and the first voltage input terminal VGL.

[0092] In some embodiments, any one of the first transistor (T51, T61) to the fourth transistor (T53, T63) is an N-type transistor or a P-type transistor. Any one of the first transistor (T51, T61) to the fourth transistor (T53, T63) is selected from any one of a low-temperature polysilicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, the first transistor (T51, T61) to the fourth transistor (T53, T63) are N-type low-temperature polysilicon transistors.

[0093] In some embodiments, the gate driving circuit 100 further includes a third maintaining circuit 308. The third maintaining circuit 308 is configured to maintain the level voltage of the gate signal output terminal G(n) according to the voltage level of the second node (K(n), P(n)). In the display stage, when the voltage level of the second node (K(n), P(n)) is low, the third maintaining circuit 308 is closed, ensuring that the gate signal output terminal G(n) stably outputs a high voltage level. In the display stage, when the voltage level of the second node (K(n), P(n)) is high, the third maintaining circuit 308 is opened, and the third maintaining circuit 308 pulls down the level voltage of the gate signal output terminal G(n) to maintain the level voltage of the gate signal output terminal G(n) at a low voltage.

[0094] In some embodiments, the third maintaining circuit 308 includes a third maintaining transistor (T32, T33). The source and the drain of the third maintaining transistor (T32, T33) are connected between the gate signal output terminal G(n) and the first voltage input terminal VGL, and the gate of the third maintaining transistor (T32, T33) is connected with the second node (K(n), P(n)).

[0095] In one exemplary embodiment, the third maintaining circuit 308 includes a third maintaining transistor T32 and a third maintaining transistor T33. The third maintaining transistor T32 and the third maintaining transistor T33 work periodically and alternately. The source and the drain of the third maintaining transistor T32 are connected between the second node K(n) and the first voltage input terminal VGL. The source and the drain of the third maintaining transistor T33 are connected between the second node P(n) and the first voltage input terminal VGL.

[0096] In some embodiments, the gate driving circuit 100 further comprises a second output circuit 309. The second output circuit 309 is configured to output a third stage signal ST(N) from the third stage signal output terminal ST(n) according to the voltage level of the first node Q(n). In this way, the second output circuit 309 outputs the third stage signal ST(N) as the current stage signal to be the signal of other stage gate driving circuit 100.

[0097] In some embodiments, the second output circuit 309 comprises a third output transistor T22. The source and drain of the third output transistor T22 are connected between the third stage signal output terminal ST(n) and the clock signal input terminal CK(n), and the gate of the third output transistor T22 is connected with the first node Q(n). In this way, the third output transistor T22 connects or disconnects the third stage signal output terminal ST(n) and the clock signal input terminal CK(n) according to the voltage level of the first node Q(n).

[0098] In some embodiments, any one of the first output transistor T21 and the third output transistor T22 is an N-type transistor or a P-type transistor. Any one of the first output transistor T21 and the third output transistor T22 is selected from any one of a low temperature poly-silicon transistor, a metal oxide transistor and a single crystal silicon transistor. Exemplarily, the first output transistor T21 to the third output transistor T22 are all N-type low temperature poly-silicon transistors.

[0099] In some embodiments, the gate driving circuit 100 further comprises a fourth maintaining circuit 310. The fourth maintaining circuit 310 is configured to maintain the voltage level of the third stage signal output terminal ST(n) according to the voltage level of the second node (K(n), P(n)). In this way, in the display stage, when the voltage level of the second node (K(n), P(n)) is low, the fourth maintaining circuit 310 is turned off to maintain the third stage signal output terminal ST(n) to output the third stage signal ST(N) with high level. In the display stage, when the voltage level of the second node (K(n), P(n)) is high, the fourth maintaining circuit 310 is turned on to pull down the third stage signal ST(N) to maintain the third stage signal ST(N) with low voltage level.

[0100] In some embodiments, the fourth maintaining circuit 310 comprises a fourth maintaining transistor (T72, T73). The source and drain of the fourth maintaining transistor (T72, T73) are connected between the third stage signal output terminal ST(n) and the first voltage input terminal VGL inputting the first level signal, and the gate of the fourth maintaining transistor (T72, T73) is connected with the second node (K(n), P(n)).

[0101] In some embodiments, the fourth sustain circuit 310 can include one or more fourth sustain transistors (T72, T73).

[0102] In one exemplary embodiment, the fourth sustain circuit 310 includes a fourth sustain transistor T72 and a fourth sustain transistor T73. The source and drain of the fourth sustain transistor T72 are connected between the third stage transmission signal output end ST(n) and the first voltage input end VGL, and the gate of the fourth sustain transistor T72 is connected with the second node K(n). The source and drain of the fourth sustain transistor T73 are connected between the third stage transmission signal output end ST(n) and the first voltage input end VGL, and the gate of the fourth sustain transistor T73 is connected with the second node P(n).

[0103] In some embodiments, any one of the first sustain transistor (T42, T43) to the fourth sustain transistor (T72, T73) is an N-type transistor or a P-type transistor. Any one of the first sustain transistor (T42, T43) to the fourth sustain transistor (T72, T73) is selected from any one of a low temperature poly-silicon transistor, a metal oxide transistor, and a single crystal silicon transistor. Exemplarily, any one of the first sustain transistor (T42, T43) to the fourth sustain transistor (T72, T73) is an N-type low temperature poly-silicon transistor.

[0104] It should be noted that the first node stabilizing transistor T91, the first inverter 3071, the third transistor T54, the first sustain transistor T42, the fourth sustain transistor T72, and the third sustain transistor T32 constitute a first sustain circuit group. The transistors in the first sustain circuit group work coordinately in a period. The first node stabilizing transistor T92, the second inverter 3072, the third transistor T64, the first sustain transistor T43, the fourth sustain transistor T73, and the third sustain transistor T33 constitute a second sustain circuit group. The transistors in the second sustain circuit group work coordinately in a period. The first sustain circuit group and the second sustain circuit group work alternately periodically, for example, alternately work in a period of 100 frames, prolonging the service life of the first sustain circuit group and the second sustain circuit group, and further improving the service life of the gate drive circuit 100.

[0105] In some embodiments, the gate driving circuit 100 further comprises a touch voltage stabilizing circuit 311. The touch voltage stabilizing circuit 311 is configured to be turned on according to a first level of touch signal in a touch period to stabilize the voltage level of the gate signal output terminal G(n). The touch voltage stabilizing circuit 311 is further configured to be turned off according to a second level of touch signal input from the touch signal input terminal TP in a display period, the second level being lower than the first level. In this way, in the display period, the touch voltage stabilizing circuit 311 is turned off to reduce its influence on the display process. In the touch period, the touch voltage stabilizing circuit 311 is turned on to pull down the voltage level of the gate signal output terminal G(n) to suspend the selection process of the scan line by the gate driving circuit 100.

[0106] In some embodiments, the touch voltage stabilizing circuit 311 comprises a touch voltage stabilizing transistor T81. The source and drain of the touch voltage stabilizing transistor T81 are connected between the gate signal output terminal G(n) and the first voltage input terminal VGL. The gate of the touch voltage stabilizing transistor T81 is connected to the touch signal input terminal TP.

[0107] In some embodiments, the touch voltage stabilizing transistor T81 is an N-type transistor or a P-type transistor. The touch voltage stabilizing transistor T81 is selected from any one of a low temperature poly-silicon transistor, a metal oxide transistor and a single crystal silicon transistor. Exemplarily, the touch voltage stabilizing transistor T81 is an N-type low temperature poly-silicon transistor.

[0108] The working process of the gate driving circuit 100 of the embodiments of the present application in the display period (e.g. display period 1 and display period 2) and the touch period (e.g. touch period 1 and touch period 2) is described below. Figure 2 Figure 3 The working process of the gate driving circuit 100 of the embodiments of the present application in the display period (e.g. display period 1 and display period 2) and the touch period (e.g. touch period 1 and touch period 2) is described below. Figure 3 In the first period, i.e. the reset period, the reset signal input terminal Reset outputs a third level of reset signal, the reset transistor TrQ is turned on and outputs the second level of touch signal to the first node, so as to reset the first node.

[0109] In the second period, i.e. the pre-charge period, the second stage transmission signal input terminal ST(n-i) inputs a high level of second stage transmission signal, the first node control transistor T11 is turned on and charges the first node Q(n) to pull up the voltage level of the first node Q(n).

[0110] In the second period, i.e. the pre-charge period, the second stage transmission signal input terminal ST(n-i) inputs a high level of second stage transmission signal, the first node control transistor T11 is turned on and charges the first node Q(n) to pull up the voltage level of the first node Q(n).

[0111] ​In the third stage, i.e. the pull-up period, the first node Q(n) has a high voltage level, and the clock signal input end CK(n) inputs a high level clock signal, the first output transistor T21 outputs the high level clock signal as the first level transmission signal ST(N+j) to the first level transmission signal input end ST(n+j), and the third output transistor T22 outputs the high level clock signal as the gate signal to the gate signal output end G(n). Moreover, the capacitor Cb boosts the voltage level of the first node Q(n) according to the high level clock signal output by the gate signal, and further pulls up the voltage level of the first node Q(n). Therefore, the voltage levels of the gate signal output end G(n) and the first level transmission signal input end ST(n+j) are pulled up to high level.

[0112] In the fourth stage, i.e. the pull-down period, the first node Q(n) has a high voltage level, and the clock signal input end CK(n) inputs a low level clock signal, the first output transistor T21 outputs the low level clock signal as the first level transmission signal ST(N+j) to the first level transmission signal input end ST(n+j), and the third output transistor T22 outputs the low level clock signal as the gate signal to the gate signal output end G(n). Therefore, the voltage levels of the gate signal output end G(n) and the first level transmission signal input end ST(n+j) are pulled down to low level.

[0113] In the fifth stage, i.e. the pull-down maintaining period, the second voltage input end LC1 outputs a high level second level signal, the first transistor T51 and the fourth transistor T53 are turned on to pull up the voltage level of the second node K(n). The first maintaining transistor T42 and the second maintaining transistor T41 are turned on according to the high level of the second node K(n) to pull down the voltage level of the first node Q(n) to the low level first level signal. The third maintaining transistor T32 is turned on according to the high level of the second node K(n) to pull down the voltage level of the gate signal output end G(n) to the low level first level signal. The fourth maintaining transistor T72 is turned on according to the high level of the second node to pull down the voltage level of the third level transmission signal output end ST(n) to the low level first level signal. Therefore, the voltage levels of the first node Q(n), the gate signal output end G(n) and the third level transmission signal output end ST(n) are maintained at low level.

[0114] In addition, in the whole display stage, the second level touch signal input by the input touch signal input end TP makes the first node stabilizing transistor (T91, T92) in the off state.

[0115] In the touch phase, the clock signal input terminal CK(n) outputs a low-level pulse signal, for example, CK1 to CK8 are low-level pulse signals. And, the reset signal input terminal Reset, the first voltage input terminal VGL and the second voltage input terminal LC1 also output low-level pulse signals. Therefore, the gate driving unit stops outputting high-level scanning signals. At the same time, the touch signal input terminal TP inputs a first-level touch signal, and the touch voltage stabilizing transistor T81 is turned on, outputting the low-level pulse signal input from the first voltage input terminal VGL to the gate signal output terminal G(n), and stabilizing the voltage level of the gate signal output terminal G(n) at a low level.

[0116] Based on the same inventive concept, please refer to Figure 4 As shown in the figure, the embodiments of the present application also provide a display device 400. The display device 400 includes a display panel 500 and a touch layer 600. The touch layer 600 can be used with a touch pen and sense the touch signal emitted by the touch pen to display the information input by the user through the touch pen on the display panel 500.

[0117] The touch layer 600 includes a plurality of touch electrodes. In some embodiments, the touch electrodes can be self-capacitive touch electrodes or mutual-capacitive touch electrodes. In an exemplary embodiment, the touch electrodes are self-capacitive touch electrodes.

[0118] In some embodiments, as shown in the figure, the touch layer 600 can be integrated inside the display panel 500 to thin the thickness of the display device 400. Figure 4

[0119] In some embodiments, in the case that the touch layer 600 can be integrated inside the display panel 500, the touch layer 600 can be reused as an electrode layer.

[0120] In some embodiments, the touch layer 600 can be reused as a common electrode layer. At this time, the plurality of touch electrodes are reused as a plurality of common electrodes. With the design of the above-mentioned gate driving circuit 100, in the case that the plurality of touch electrodes are reused as a plurality of common electrodes, the display abnormality problem caused by stopping the selected scanning line in the touch phase can be improved.

[0121] In some embodiments, the display panel 500 further includes a substrate 501. In the case that the touch layer 600 can be integrated inside the display panel 500, the touch layer 600 can be located on the substrate 501.

[0122] In some embodiments, the display panel 500 can include a pixel electrode layer 503, and the pixel electrode layer 503 and the common electrode layer are insulated by an insulating layer. The pixel electrode layer 503 is located on the substrate 501.

[0123] ​In some embodiments, the display panel 500 can further include a driving circuit layer 504. The driving circuit layer 504 includes pixel driving circuits. The driving circuit layer 504 is located between the pixel electrode layer 503 and the substrate 501, and between the common electrode layer and the substrate 501.

[0124] In some embodiments, the display panel 500 can further include a counter substrate 502. The substrate 501 is oppositely arranged with the counter substrate 502.

[0125] In some embodiments, a liquid crystal layer (not shown in the figure) can be arranged between the counter substrate 502 and the substrate 501. At this time, the display panel 500 is a liquid crystal display panel.

[0126] In some embodiments, the touch layer 600 can be located outside the display panel 500. The touch layer 600 can be formed on the display panel 500 through a panel process, or can be adhered to the display panel 500 through an adhesive layer.

[0127] The above description of the embodiments is only used to help understand the technical solutions of the present application and its core idea; those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit characterized by comprising: The gate drive circuit comprises: a first node control circuit configured to control a voltage level of a first node; a first maintaining circuit configured to maintain the voltage level of the first node according to a voltage level of a second node; the first maintaining circuit comprises a first maintaining transistor, a source and a drain of the first maintaining transistor are connected between the first node and a touch signal input terminal, and a gate of the first maintaining transistor is connected with the second node; a first output circuit configured to output a gate signal from a gate signal output terminal according to the voltage level of the first node; a first node voltage stabilizing circuit configured to be turned on according to a first level touch signal input from the touch signal input terminal in a touch period to control a voltage level of the second node to turn off the first maintaining circuit, thereby stabilizing the voltage level of the first node; and a touch voltage stabilizing circuit configured to be turned on according to the first level touch signal in the touch period to stabilize a voltage level of the gate signal output terminal, and the touch voltage stabilizing circuit is further configured to be turned off according to a second level touch signal input from the touch signal input terminal in a display stage, the second level being lower than the first level; wherein the touch voltage stabilizing circuit comprises a touch voltage stabilizing transistor, a source and a drain of the touch voltage stabilizing transistor are connected between the gate signal output terminal and a first voltage input terminal, and a gate of the touch voltage stabilizing transistor is connected with the touch signal input terminal.

2. The gate drive circuit according to claim 1, characterized by The first node voltage stabilizing circuit is further configured to be turned off according to a second level touch signal input from the touch signal input terminal in a display stage, the second level being lower than the first level.

3. The gate drive circuit according to claim 2, characterized by The first node voltage stabilizing circuit comprises a first node voltage stabilizing transistor, a source and a drain of the first node voltage stabilizing transistor are connected between the second node and the first voltage input terminal, and a gate of the first node voltage stabilizing transistor is connected with the touch signal input terminal.

4. The gate drive circuit according to claim 1 or 2, characterized by The first maintaining transistor is an N-type low-temperature polysilicon transistor.

5. The gate drive circuit according to claim 1 or 2, characterized by The gate drive circuit further comprises a reset circuit configured to connect the first node and the touch signal input terminal according to a third level reset signal input from a reset signal input terminal in a display stage to reset the voltage level of the first node; and / or, The reset circuit is further configured to disconnect the first node and the touch signal input terminal according to a fourth level reset signal input from the reset signal input terminal in the touch period, the fourth level being lower than the third level.

6. The gate drive circuit according to claim 5, characterized by The reset circuit comprises a reset transistor, a source and a drain of the reset transistor are connected between the first node and the touch signal input terminal, and a gate of the reset transistor is connected with the reset signal input terminal.

7. The gate drive circuit according to claim 1 or 2, characterized by The gate drive circuit further comprises a second maintaining circuit configured to connect the touch signal input terminal and the first node according to a fifth level first stage signal input from a first stage signal input terminal in a display stage to maintain the potential of the first node; and / or, The second maintaining circuit is further configured to disconnect the first node and the touch signal input end according to a sixth level first stage signaling input by the first stage signaling input end in the touch period, and the sixth level is less than the fifth level.

8. The gate drive circuit according to claim 7, characterized by The second maintaining circuit comprises a second maintaining transistor, a source and a drain of the second maintaining transistor are connected between the first node and the touch signal input end, and a gate of the second maintaining transistor is connected with the first stage signaling input end.

9. The gate drive circuit according to claim 1 or 2, characterized by The gate drive circuit further comprises a second node control circuit, and the second node control circuit is configured to make a phase of a voltage level of the second node opposite to a phase of a voltage level of the first node according to the voltage level of the first node.

10. The gate drive circuit according to claim 9, wherein The second node control circuit comprises a first transistor and a second transistor; a source and a drain of the first transistor are connected between the second node and a second voltage input end, and a gate of the first transistor is connected with the second voltage input end; a source and a drain of the second transistor are connected between the second node and a first voltage input end, and a gate of the second transistor is connected with the first node.

11. The gate drive circuit according to claim 10, characterized by The second node control circuit further comprises a third transistor, a source and a drain of the third transistor are connected between the second node and the first voltage input end, and a gate of the third transistor is connected with a second stage signaling input end.

12. The gate drive circuit according to claim 1 or 2, characterized by The first node control circuit comprises a first node control transistor, a source and a drain of the first node control transistor are connected between the first node and a second stage signaling input end or a start signal input end, and a gate of the first node control transistor is connected with the second stage signaling input end or the start signal input end; and / or, The first output circuit comprises a first output transistor, a source and a drain of the first output transistor are connected between a clock signal input end of an input clock signal and the gate signal output end, and a gate of the first output transistor is connected with the first node; and / or, The first output circuit comprises a second output transistor, a source and a drain of the second output transistor are connected between a first voltage input end of an input first level signal and the gate signal output end, and a gate of the second output transistor is connected with a first stage signaling input end of the input first stage signaling; and / or, The gate drive circuit further comprises a capacitor, two electrodes of the capacitor are connected between the first node and the gate signal output end.

13. The gate drive circuit according to claim 1 or 2, characterized by The gate drive circuit further comprises a third maintaining circuit, and the third maintaining circuit is configured to maintain a level voltage of the gate signal output end according to a voltage level of the second node.

14. The gate drive circuit according to claim 13, characterized by The third maintaining circuit comprises a third maintaining transistor, a source and a drain of the third maintaining transistor are connected between the gate signal output end and a first voltage input end, and a gate of the third maintaining transistor is connected with the second node.

15. The gate drive circuit according to claim 1 or 2, characterized by The gate drive circuit further comprises a second output circuit configured to output a third stage signal from a third stage signal output terminal according to a voltage level of the first node.

16. The gate drive circuit of claim 15, wherein, The gate drive circuit further comprises a fourth maintaining circuit configured to maintain a level voltage of the third stage signal output terminal according to a level voltage of the second node.

17. The gate drive circuit of claim 16, wherein, The second output circuit comprises a third output transistor, a source and a drain of the third output transistor being connected between the third stage signal output terminal and a clock signal input terminal, a gate of the third output transistor being connected with the first node; and / or, The fourth maintaining circuit comprises a fourth maintaining transistor, a source and a drain of the fourth maintaining transistor being connected between the third stage signal output terminal and a first voltage input terminal, a gate of the fourth maintaining transistor being connected with the second node.

18. A display device comprising: The display device comprises the gate drive circuit according to any one of claims 1 to 17.

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