Gate drive circuit and abnormality positioning method, display panel and detection method and device

Abstract

A gate driving circuit and an abnormality positioning method thereof, a display panel and an abnormality detection method thereof, and a display device. The gate driving circuit comprises a plurality of shift register units, a first signal line, the plurality of shift register units being connected in parallel through the first signal line; a second signal line, the plurality of shift register units being connected in series through the second signal line; a signal turning unit being connected in series on the first signal line between two adjacent shift register units; and / or being connected in series on the second signal line between two adjacent shift register units; the signal turning unit can change the transmission path of the signal on the first signal line passing therethrough, so as to prevent the signal on the first signal line from transmitting to the next shift register unit; and / or the signal turning unit can change the transmission path of the signal on the second signal line passing therethrough, so as to prevent the signal on the second signal line from transmitting to the next shift register unit.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of display, and particularly relates to a gate driving circuit and an abnormality positioning method thereof, a display panel and an abnormality detection method thereof, and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display screens are widely concerned due to their advantages of self-luminous, low power consumption, thinness, flexibility, bright colors, high contrast, fast response rate and the like. SUMMARY

[0003] In a first aspect, the embodiment of the present disclosure provides a gate driving circuit, comprising a plurality of shift register units,

[0004] a first signal line, wherein the plurality of shift register units are connected in parallel through the first signal line;

[0005] a second signal line, wherein the plurality of shift register units are connected in series through the second signal line;

[0006] a signal turning unit, which is connected in series on the first signal line between adjacent two shift register units, and / or which is connected in series on the second signal line between adjacent two shift register units;

[0007] The signal turning unit can change the transmission path of the signal on the first signal line passing therethrough, so as to prevent the signal on the first signal line from being transmitted to the next shift register unit.

[0008] And / or, the signal turning unit can change the transmission path of the signal on the second signal line passing therethrough, so as to prevent the signal on the second signal line from being transmitted to the next shift register unit.

[0009] In some embodiments, the signal turning unit comprises a first signal turning unit.

[0010] The first signal turning unit comprises a first transistor and a second transistor,

[0011] a first control end is connected to the gate of the first transistor and the gate of the second transistor; and a first electrode of the first transistor and a first electrode of the second transistor are connected to the first signal line.

[0012] a second electrode of the first transistor is connected to the first signal line; and a second electrode of the second transistor is connected to a first test end.

[0013] In some embodiments, the signal steering unit further comprises a second signal steering unit;

[0014] The second signal steering unit comprises a third transistor and a fourth transistor,

[0015] The gate of the third transistor and the gate of the fourth transistor are connected to a second control terminal; the first pole of the third transistor and the first pole of the fourth transistor are connected to the second signal line;

[0016] The second pole of the third transistor is connected to the second signal line; the second pole of the fourth transistor is connected to a second test terminal.

[0017] In some embodiments, the first transistor and the third transistor are P-type transistors or N-type transistors;

[0018] The second transistor and the fourth transistor are N-type transistors or P-type transistors.

[0019] In some embodiments, the plurality of shift register units are arranged in a first direction in sequence,

[0020] The first signal steering unit is located between two adjacent shift register units in the middle position in the first direction;

[0021] And / or, the second signal steering unit is located between two adjacent shift register units in the middle position in the first direction.

[0022] In some embodiments, the first signal line comprises a clock signal line, a reset signal line and a power supply line;

[0023] The second signal line comprises a cascade signal line.

[0024] In some embodiments, the number of first signal steering units is multiple, and the number of second signal steering units is multiple;

[0025] There are multiple first signal lines and multiple second signal lines;

[0026] Different first signal lines are connected to different first signal steering units;

[0027] Different second signal lines are connected to different second signal steering units.

[0028] In some embodiments, at least part of the first signal steering units and / or at least part of the second signal steering units are located between different shift register units.

[0029] In a second aspect, the display panel is provided.

[0030] In some embodiments, the display panel has a display area and a frame area surrounding the display area;

[0031] The display panel further comprises a plurality of pixel units arranged in an array in the display area.

[0032] The gate drive circuit comprises a first part.

[0033] The first part comprises a plurality of shift register units connected in series.

[0034] The first part is located in a first side frame area surrounding the display area,

[0035] One of the shift register units in the first part corresponds to at least one row of the pixel units; and / or, one of the shift register units in the first part corresponds to at least part of the pixel units in one row.

[0036] In some embodiments, the gate drive circuit further comprises a second part.

[0037] The second part comprises a plurality of shift register units connected in series.

[0038] The second part is located in a second side frame area surrounding the display area, the second side frame area being opposite to the first side frame area.

[0039] One of the shift register units in the second part corresponds to at least one row of the pixel units; and / or, one of the shift register units in the second part corresponds to at least part of the pixel units in one row.

[0040] In some embodiments, the gate drive circuit comprises a first gate drive circuit and a second gate drive circuit,

[0041] The first gate drive circuit is configured to provide a gate control cascade signal to the pixel units.

[0042] The second gate drive circuit is configured to provide a light-emitting control cascade signal to the pixel units.

[0043] In some embodiments, the display panel further comprises a timing control circuit and a flexible printed circuit.

[0044] The first signal turning unit in the gate drive circuit is connected to the timing control circuit through a first control terminal.

[0045] The first signal turning unit in the gate drive circuit is connected to the flexible printed circuit through a first test terminal;

[0046] The second signal turning unit in the gate drive circuit is connected to the timing control circuit through a second control terminal;

[0047] The second signal turning unit in the gate drive circuit is connected to the flexible printed circuit through a second test terminal.

[0048] In a third aspect, the embodiments of the present disclosure further provide a display device, comprising the display panel.

[0049] In a fourth aspect, the embodiments of the present disclosure further provide an abnormality positioning method of a gate drive circuit, wherein the gate drive circuit comprises a plurality of shift register units,

[0050] A first signal line, the plurality of shift register units are connected in parallel through the first signal line;

[0051] A second signal line, the plurality of shift register units are connected in series through the second signal line;

[0052] A signal turning unit, connected in series on the first signal line between adjacent two shift register units; and / or, connected in series on the second signal line between adjacent two shift register units;

[0053] The abnormality positioning method comprises:

[0054] Controlling the signal turning unit to change the transmission path of the signal on the first signal line, preventing the signal on the first signal line from transmitting to the next shift register unit, and the first signal line has a signal abnormality;

[0055] And / or, controlling the signal turning unit to change the transmission path of the signal on the second signal line, preventing the signal on the second signal line from transmitting to the next shift register unit, and the second signal line has a signal abnormality.

[0056] In some embodiments, the signal turning unit comprises a first signal turning unit;

[0057] The first signal turning unit comprises a first transistor and a second transistor,

[0058] The gate of the first transistor and the gate of the second transistor are connected to a first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line;

[0059] The second electrode of the first transistor is connected to the first signal line; and the second electrode of the second transistor is connected to a first test terminal.

[0060] The abnormality positioning method comprises: the first control terminal controls the first transistor to be turned off, and controls the second transistor to be turned on, the first signal line is disconnected, and the signal on the first signal line is transmitted to the first test terminal through the second transistor.

[0061] In some embodiments, the signal steering unit further comprises a second signal steering unit;

[0062] The second signal steering unit comprises a third transistor and a fourth transistor,

[0063] The gate of the third transistor and the gate of the fourth transistor are connected to a second control terminal; and the first electrode of the third transistor and the first electrode of the fourth transistor are connected to a second signal line.

[0064] The second electrode of the third transistor is connected to the second signal line; and the second electrode of the fourth transistor is connected to a second test terminal.

[0065] The abnormality positioning method further comprises: the second control terminal controls the third transistor to be turned off, and controls the fourth transistor to be turned on, the second signal line is disconnected, and the signal on the second signal line is transmitted to the second test terminal through the fourth transistor.

[0066] In a fifth aspect, the embodiments of the present disclosure further provide an abnormality detection method of a display panel, wherein the display panel comprises the above-mentioned gate driving circuit; and the abnormality detection method comprises:

[0067] Controlling a signal steering unit in the gate driving circuit to change a transmission path of a signal on a first signal line, so that the first signal line is disconnected, and the display panel has a first abnormality;

[0068] Comparing the first abnormality with an abnormal state of a faulty display panel, to determine whether the first abnormality is consistent with the abnormal state of the faulty display panel;

[0069] If yes, it is determined that the first signal line of the faulty display panel is abnormal; and if no, it is determined that the first signal line of the faulty display panel is normal.

[0070] And / or, controlling a signal steering unit in the gate driving circuit to change a transmission path of a signal on a second signal line, so that the second signal line is disconnected, and the display panel has a second abnormality;

[0071] comparing the second abnormality with an abnormal state of the faulty display panel, to determine whether the second abnormality is consistent with the abnormal state of the faulty display panel;

[0072] If yes, it is determined that the second signal line of the faulty display panel is abnormal; if no, it is determined that the second signal line of the faulty display panel is normal.

[0073] In some embodiments, the first signal line has a plurality of signal lines, and the second signal line has a plurality of signal lines.

[0074] Different first signal lines and different second signal lines are respectively connected to different signal turning units.

[0075] The abnormality detection method comprises: performing abnormality detection on the first signal line and the second signal line one by one.

[0076] In some embodiments, the gate driving circuit comprises a first gate driving circuit and a second gate driving circuit,

[0077] The first gate driving circuit provides a gate control cascade signal to the pixel unit.

[0078] The second gate driving circuit provides a light-emitting control cascade signal to the pixel unit.

[0079] The abnormality detection method comprises: performing abnormality detection on the first signal line and the second signal line in the first gate driving circuit one by one.

[0080] Performing abnormality detection on the first signal line and the second signal line in the second gate driving circuit one by one.

[0081] The gate driving circuit provided by the embodiments of the present disclosure can accurately locate the abnormal signal on the first signal line and / or the second signal line when the first signal line and / or the second signal line is broken, so as to actively reproduce the display defects caused by the abnormal signal, and further help the analyst to quickly locate the abnormal signal, thereby improving the analysis efficiency of the display defects caused by the abnormal signal.

[0082] The display panel provided by the embodiments of the present disclosure can accurately locate the abnormal signal on the first signal line and / or the second signal line when the signal turning unit in the gate driving circuit causes the first signal line and / or the second signal line to be broken, so as to actively reproduce the display defects caused by the abnormal signal, and further help the analyst to quickly locate the abnormal signal, thereby improving the analysis efficiency of the display defects caused by the abnormal signal.

[0083] The display device provided by the embodiments of the present disclosure improves the analysis efficiency of display defects of the display device by using the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0084] The accompanying drawings are included to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification, which are used to explain the present disclosure together with the embodiments of the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed description of the specific embodiments described below, taken in conjunction with the accompanying drawings, in which:

[0085] Figure 1a It is a circuit diagram of a pixel circuit in the related art.

[0086] Figure 1b It is a circuit diagram of a light-emitting control gate drive circuit in the related art.

[0087] Figure 1c It is a circuit connection schematic diagram of a gate drive circuit in the display panel in the related art.

[0088] Figure 2a It is a circuit connection schematic diagram of a gate drive circuit in the embodiments of the present disclosure.

[0089] Figure 2b It is a circuit connection schematic diagram of another gate drive circuit in the embodiments of the present disclosure.

[0090] Figure 2c It is a circuit connection schematic diagram of another gate drive circuit in the embodiments of the present disclosure.

[0091] Figure 2d It is a circuit connection schematic diagram of another gate drive circuit in the embodiments of the present disclosure.

[0092] Figure 3a It is a circuit diagram of a first signal turning unit in the embodiments of the present disclosure.

[0093] Figure 3b It is a circuit diagram of a second signal turning unit in the embodiments of the present disclosure.

[0094] Figure 3c It is a circuit connection schematic diagram of another gate drive circuit in the embodiments of the present disclosure.

[0095] Figure 4a It is a schematic diagram of a display panel in the embodiments of the present disclosure.

[0096] Figure 4b It is a schematic diagram of another display panel in the embodiments of the present disclosure.

[0097] Figure 4cA schematic diagram of still another display panel in embodiments of the present disclosure.

[0098] Figure 4d A schematic diagram of still another display panel in embodiments of the present disclosure.

[0099] Figure 4e A schematic diagram of still another display panel in embodiments of the present disclosure.

[0100] Figure 5a A flowchart of a first signal line abnormality detection method in a display panel in embodiments of the present disclosure.

[0101] Figure 5b A flowchart of a second signal line abnormality detection method in a display panel in embodiments of the present disclosure. DETAILED DESCRIPTION

[0102] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a gate drive circuit and an abnormality positioning method thereof, a display panel and an abnormality detection method thereof, and a display device provided by the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and specific embodiments.

[0103] The embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. The embodiments of the present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0104] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Therefore, the regions exemplified in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of the regions, but is not intended to be restrictive.

[0105] In the related art, with reference to Figure 1a and Figure 1b , a display panel (such as an OLED display panel) includes a gate drive circuit, which provides two necessary driving signals, i.e., a Gate signal (a gate control signal) and an Emission signal (a light emission control signal), for a pixel circuit. The Gate signal is used for driving the pixel circuit in a data writing stage, and the Emission signal is used for driving the pixel circuit in a light emission stage; whether the display panel can display normally is closely related to the two signals, and when an abnormality occurs, the display of the display panel will appear Y line (horizontal bright line), split screen (color or brightness inconsistency between the upper and lower screen areas), no display (whole screen black screen), and other undesirable phenomena.

[0106] The Gate signal and the Emission signal are generated by two different gate driving circuits. For the gate driving circuit generating the Gate signal, the input signals thereof include GSTV (gate control cascade signal), GCK (first clock signal), and GCB (second clock signal), which jointly act on the gate driving circuit to generate the Gate signal; and for the gate driving circuit generating the Emission signal, the input signals thereof include ESTV (emission control cascade signal), ECK (third clock signal), and ECB (fourth clock signal), which jointly act on the gate driving circuit to generate the Emission signal. Figure 1c The positions of these input signals in the gate driving circuit are shown in FIG. 1. Since the macroscopic structures of the gate driving circuits generating the Gate signal and the Emission signal are similar (i.e., both are composed of a plurality of cascade shift register units), for the sake of simplicity, Figure 1c In FIG. 1, GSTV and ESTV are collectively referred to as STV signals; GCK and ECK are collectively referred to as CK signals; and GCB and ECB are collectively referred to as CB signals.

[0107] In the process of display of the display panel, due to factors such as electrochemical corrosion and crack, any input signal of the gate driving circuit may be abnormal, thereby affecting the Gate signal and the Emission signal provided by the gate driving circuit, and further causing display defects. In the related art, with reference to Figure 1c The gate driving circuit includes a plurality of shift register units (gate driving 0 to gate driving n, i.e., GOA0 to GOAn or EOA0 to EOAn) 1, which are connected in a cascade manner to sequentially transmit the Gate signal or the Emission signal row by row; however, when the Gate signal and the Emission signal are abnormal, it is not possible to accurately determine which input signal line (GSTV, GCK, GCB, ESTV, ECK, and ECB) is abnormal. In the analysis process of this type of display defect, currently, each input signal line is sequentially checked by a microscope, and some small abnormal points on the input signal line may be ignored after a long time of observation. In addition, currently, when this type of display defect is reproduced, a laser device needs to be accurately hit on the corresponding input signal line to disconnect the corresponding input signal line, so that the display defect caused by disconnection of the corresponding input signal line is reproduced. If the laser device is deviated to hit other signal lines, the reproduction screen of the display defect will be directly scrapped. This display defect reproduction operation has a very high requirement for the analyst, and a large amount of time cost will be generated.

[0108] How to accurately locate the abnormal input signal in the gate driving circuit becomes a problem to be solved at present.

[0109] To solve the problems in the related art, in a first aspect, the embodiments of the present disclosure provide a gate drive circuit, referring to Figure 2a 、 Figure 2b 、 Figure 2c and Figure 2d , wherein the gate drive circuit comprises a plurality of shift register units 1, a first signal line 2, the plurality of shift register units 1 are connected in parallel through the first signal line 2; a second signal line 3, the plurality of shift register units 1 are connected in series through the second signal line 3; a signal turning unit 4, which is connected in series on the first signal line 2 between adjacent two shift register units 1; and / or, which is connected in series on the second signal line 3 between adjacent two shift register units 1; the signal turning unit 4 can change the transmission path of the signal on the first signal line 2 passing through it, so as to prevent the signal on the first signal line 2 from transmitting to the next shift register unit 1; and / or, the signal turning unit 4 can change the transmission path of the signal on the second signal line 3 passing through it, so as to prevent the signal on the second signal line 3 from transmitting to the next shift register unit 1.

[0110] , wherein the first signal line 2 refers to any signal line in the gate drive circuit through which the plurality of shift register units 1 can be connected in parallel. Such as clock signal line, reset signal line, power line, etc. The second signal line 3 refers to any signal line in the gate drive circuit through which the plurality of shift register units 1 can be connected in series. Such as gate control cascade signal line, emission control cascade signal line, etc.

[0111] In the embodiments, Figure 2a and Figure 2b , the first signal line (GCK, GCB) 2 and the second signal line (GSTV) 3 in the gate drive circuit for generating Gate signal; the gate drive circuit for generating Gate signal comprises a plurality of shift register units (GOA0-GOAn) 1. Figure 2c and Figure 2d , the first signal line (ECK, ECB) 2 and the second signal line (ESTV) 3 in the gate drive circuit for generating Emission signal; the gate drive circuit for generating Emission signal comprises a plurality of shift register units (EOA0-EOAn) 1.

[0112] In the embodiment, when the signal turning unit 4 changes the transmission path of the signal on the first signal line 2 passing therethrough, the signal on the first signal line 2 can be prevented from being transmitted to the next shift register unit 1, and then the first signal line 2 can be disconnected, and further the display panel including the gate drive circuit can have display defects in the case of disconnection of the first signal line 2. Similarly, when the signal turning unit 4 changes the transmission path of the signal on the second signal line 3 passing therethrough, the signal on the second signal line 3 can be prevented from being transmitted to the next shift register unit 1, and then the second signal line 3 can be disconnected, and further the display panel including the gate drive circuit can have display defects in the case of disconnection of the second signal line 3. In summary, the signal turning unit 4 can make the display panel including the gate drive circuit reproduce the display defects in the case of disconnection of the first signal line 2 and / or the second signal line 3.

[0113] In the embodiment, by setting the signal turning unit 4, when the first signal line 2 and / or the second signal line 3 is disconnected, the abnormal signal on the first signal line 2 and / or the second signal line 3 can be accurately located, and thus the display defects caused by the abnormal signal can be actively reproduced, and further the abnormal signal can be quickly located by the analyst, and the analysis efficiency of the display defects caused by the abnormal signal can be improved.

[0114] In some embodiments, referring to Figure 3a , the signal turning unit 4 includes a first signal turning unit 41; the first signal turning unit 41 includes a first transistor Ta and a second transistor Tb, a gate of the first transistor Ta and a gate of the second transistor Tb are connected to a first control end A; a first electrode of the first transistor Ta and a first electrode of the second transistor Tb are connected to the first signal line 2; a second electrode of the first transistor Ta is connected to the first signal line 2; and a second electrode of the second transistor Tb is connected to a first test end B.

[0115] In some embodiments, the first transistor Ta is a P-type transistor or an N-type transistor; and the second transistor Tb is an N-type transistor or a P-type transistor.

[0116] In some embodiments, the first transistor Ta is a P-type transistor, and the second transistor Tb is an N-type transistor. When the first control end A provides a low-level signal through path ①, the first transistor Ta is turned on, the second transistor Tb is turned off, the transmission path of the signal on the first signal line 2 remains unchanged, and the signal on the first signal line 2 is transmitted along path ④→②, i.e., the signal on the first signal line 2 is still transmitted to the next shift register unit 1 through the first signal line 2. When the first control end A provides a high-level signal through path ①, the second transistor Tb is turned on, the first transistor Ta is turned off, the transmission path of the signal on the first signal line 2 changes, and the signal on the first signal line 2 is transmitted along path ④→③, i.e., the signal on the first signal line 2 is directly transmitted to the first test end B through path ③. At the first test end B, the output signal of the first test end B can be tested by a detection device to determine whether the first signal steering unit 41 changes the transmission path of the signal on the first signal line 2.

[0117] In some embodiments, referring to Figure 3b , the signal steering unit 4 further comprises a second signal steering unit 42; the second signal steering unit 42 comprises a third transistor Tc and a fourth transistor Td, the gate of the third transistor Tc and the gate of the fourth transistor Td are connected to the second control end C; the first pole of the third transistor Tc and the first pole of the fourth transistor Td are connected to the second signal line 3; the second pole of the third transistor Tc is connected to the second signal line 3; and the second pole of the fourth transistor Td is connected to the second test end D.

[0118] In some embodiments, the third transistor Tc is a P-type transistor or an N-type transistor, and the fourth transistor Td is an N-type transistor or a P-type transistor.

[0119] In some embodiments, the third transistor Tc is a P-type transistor, and the fourth transistor Td is an N-type transistor. When the second control end C provides a low-level signal through path ①, the third transistor Tc is turned on, the fourth transistor Td is turned off, the transmission path of the signal on the second signal line 3 remains unchanged, and the signal on the second signal line 3 is transmitted along path ④→②, i.e., the signal on the second signal line 3 is still transmitted to the next shift register unit 1 through the second signal line 3. When the second control end C provides a high-level signal through path ①, the fourth transistor Td is turned on, the third transistor Tc is turned off, the transmission path of the signal on the second signal line 3 changes, and the signal on the second signal line 3 is transmitted along path ④→③, i.e., the signal on the second signal line 3 is directly transmitted to the second test end D through path ③. At the second test end D, the output signal of the second test end D can be tested by a detection device to determine whether the second signal steering unit 42 changes the transmission path of the signal on the second signal line 3.

[0120] In some embodiments, the plurality of shift register units 1 are arranged in sequence along a first direction Z, the first signal turning unit 41 is located between two adjacent shift register units 1 at a middle position along the first direction Z; and / or, the second signal turning unit 42 is located between two adjacent shift register units 1 at a middle position along the first direction Z.

[0121] In this way, the display defect caused by the disconnection of the first signal line 2 can be reproduced in the middle area of the display area of the display panel, thereby facilitating better observation, comparison and analysis of the display defect; similarly, the display defect caused by the disconnection of the second signal line 3 can be reproduced in the middle area of the display area of the display panel, thereby facilitating better observation, comparison and analysis of the display defect.

[0122] In some embodiments, referring to Figure 3c , the first signal line 2 includes a clock signal line (such as GCK, GCB, ECK, ECB), a reset signal line (such as Reset) and a power supply line (such as VGH, VGL); the second signal line 3 includes a cascade signal line (such as GSTV, ESTV).

[0123] In some embodiments, the number of first signal turning units 41 is multiple, the number of second signal turning units 42 is multiple; there are multiple first signal lines 2 and multiple second signal lines 3; different first signal lines 2 are connected to different first signal turning units 41; different second signal lines 3 are connected to different second signal turning units 42. In this way, the abnormal signals of the multiple first signal lines 2 and the multiple second signal lines 3 can be positioned one by one, so that the display defects caused by the abnormal signals of different first signal lines 2 and different second signal lines 3 can be reproduced one by one, thereby helping analysts to quickly locate the abnormal signals and improving the analysis efficiency of the display defects caused by the abnormal signals.

[0124] In some embodiments, at least part of the first signal turning units 41 and / or at least part of the second signal turning units 42 are located between different shift register units 1. In this way, it is avoided that the multiple first signal turning units 41 and / or the multiple second signal turning units 42 are all arranged between the same group of adjacent shift register units 1, thereby avoiding the situation that the space between the same group of adjacent shift register units 1 is insufficient to accommodate multiple signal turning units 4.

[0125] Based on the above structure of the gate driving circuit, the embodiment of the present disclosure further provides an abnormality positioning method of the gate driving circuit, comprising: a control signal turning unit changes the transmission path of the signal on the first signal line, prevents the signal on the first signal line from transmitting to the next shift register unit, and the first signal line has a signal abnormality; and / or, the control signal turning unit changes the transmission path of the signal on the second signal line, prevents the signal on the second signal line from transmitting to the next shift register unit, and the second signal line has a signal abnormality.

[0126] In some embodiments, the abnormality positioning method comprises: the first control end controls the first transistor to be off, and controls the second transistor to be on at the same time, the first signal line has a disconnection, and the signal on the first signal line is transmitted to the first test end through the second transistor.

[0127] In some embodiments, the abnormality positioning method further comprises: the second control end controls the third transistor to be off, and controls the fourth transistor to be on at the same time, the second signal line has a disconnection, and the signal on the second signal line is transmitted to the second test end through the fourth transistor.

[0128] The gate driving circuit provided by the embodiment of the present disclosure can accurately locate the abnormal signal on the first signal line and / or the second signal line when the first signal line and / or the second signal line has a disconnection through the setting of the signal turning unit, so as to actively reproduce the display defect caused by the abnormal signal, and further help the analyst to quickly locate the abnormal signal, and improve the analysis efficiency of the display defect caused by the abnormal signal.

[0129] In the second aspect, the embodiment of the present disclosure further provides a display panel comprising the gate driving circuit in the above embodiments.

[0130] By using the gate driving circuit in the above embodiments, when the signal turning unit in the gate driving circuit causes the first signal line and / or the second signal line to have a disconnection, the abnormal signal on the first signal line and / or the second signal line can be accurately located, so as to actively reproduce the display defect caused by the abnormal signal, and further help the analyst to quickly locate the abnormal signal, and improve the analysis efficiency of the display defect caused by the abnormal signal.

[0131] In some embodiments, with reference to Figure 4a , Figure 4b , Figure 4c , Figure 4d and Figure 4eThe display panel has a display area 100 and a frame area 101 surrounding the display area 100; the display panel further includes a plurality of pixel units 10 arranged in an array in the display area 100; the gate drive circuit includes a first part 51; the first part 51 includes a plurality of shift register units 1 connected in cascade; the first part 51 is located at a first side frame area 101A surrounding the display area 100; one shift register unit 1 in the first part 51 is connected to at least one row of pixel units 10; and / or one shift register unit 1 in the first part 51 is connected to at least part of the pixel units 10 in one row.

[0132] In some embodiments, one shift register unit 1 in the first part 51 can be connected to one row of pixel units 10 or multiple rows (such as two rows or four rows) of pixel units 10; one shift register unit 1 in the first part 51 can be connected to all pixel units 10 in one row or part of the pixel units 10 in one row, such as one shift register unit 1 in the first part 51 being connected to an odd number of pixel units 10 or an even number of pixel units 10 in one row; or one shift register unit 1 in the first part 51 being connected to 1 / 2 of the pixel units 10 arranged in sequence in one row.

[0133] In some embodiments, if only the first part 51 is provided in the gate drive circuit, the connection mode of the first part 51 and the pixel units 10 corresponds to the mode of the gate drive circuit driving the pixel unit array from one side.

[0134] In some embodiments, the gate drive circuit further includes a second part 52; the second part 52 includes a plurality of shift register units 1 connected in cascade; the second part 52 is located at a second side frame area 101B surrounding the display area 100, the second side frame area 101B being opposite to the first side frame area 101A; one shift register unit 1 in the second part 52 is connected to at least one row of pixel units 10; and / or one shift register unit 1 in the second part 52 is connected to at least part of the pixel units 10 in one row.

[0135] In some embodiments, one shift register unit 1 in the second part 52 can correspond to one row of pixel units 10, or can correspond to multiple rows (such as 2 rows or 4 rows) of pixel units 10; one shift register unit 1 in the second part 52 can correspond to all pixel units 10 in one row, or can correspond to part of the pixel units 10 in one row, such as one shift register unit 1 in the second part 52 corresponding to odd pixel units 10 or even pixel units 10 in one row; or one shift register unit 1 in the second part 52 corresponding to 1 / 2 of the pixel units 10 arranged in sequence in one row.

[0136] In some embodiments, when the gate driving circuit includes the first part 51 and the second part 52, the connection mode of the first part 51, the second part 52 and the pixel units 10 corresponds to the mode of the gate driving circuit driving the pixel unit array from both sides.

[0137] In some embodiments, the gate driving circuit includes a first gate driving circuit 8 and a second gate driving circuit 9, the first gate driving circuit 8 is used to provide a gate control cascade signal (Gate) to the pixel units 10; the second gate driving circuit 9 is used to provide an emission control cascade signal (EM) to the pixel units 10.

[0138] In some embodiments, referring to Figure 1a , the pixel unit includes a pixel circuit and a light emitting element D', Figure 1a The pixel circuit in the above formula (1) is a 7T1C (7 thin film transistors and 1 capacitor) circuit, and the light emitting element D' can be an OLED element (organic electroluminescent element). The GLn signal (gate control cascade signal) and the GLn-1 signal (gate control cascade signal) in the pixel circuit are respectively provided by the nth shift register unit and the (n-1)th shift register unit in the first gate driving circuit, and the GLn signal and the GLn-1 signal are used for driving the pixel circuit in the data writing stage; the EM signal (emission control cascade signal) in the pixel circuit is provided by the shift register unit in the second gate driving circuit, and the EM signal is used for driving the pixel circuit in the light emitting stage.

[0139] In some embodiments, referring to Figures 4b-4e , the display panel further includes a timing control circuit 6 and a flexible printed circuit 7; the first signal turning unit 41 in the gate driving circuit is connected to the timing control circuit 6 through a first control end A; the first signal turning unit 41 in the gate driving circuit is connected to the flexible printed circuit 7 through a first test end B; the second signal turning unit 42 in the gate driving circuit is connected to the timing control circuit 6 through a second control end C; the second signal turning unit 42 in the gate driving circuit is connected to the flexible printed circuit 7 through a second test end D.

[0140] The first control end A and the second control end C can be arranged in the timing control circuit 6, and the timing control circuit 6 provides a control signal to the first signal steering unit 41 and the second signal steering unit 42 through the first control end A and the second control end C, respectively, when the first signal steering unit 41 and the second signal steering unit 42 work. The first test end B and the second test end D can be arranged in the flexible printed circuit 7, and the flexible printed circuit 7 receives the signals on the first signal line 2 and the second signal line 3 through the first test end B and the second test end D, respectively, when the first signal steering unit 41 and the second signal steering unit 42 work.

[0141] Based on the above structure of the display panel, the embodiment of the present disclosure further provides an abnormality detection method of the display panel, referring to Figure 5a and Figure 5b comprising: step S101: controlling the signal steering unit in the gate drive circuit to change the transmission path of the signal on the first signal line, so that the first signal line is disconnected, and the display panel has a first abnormality.

[0142] Step S102: comparing the first abnormality with the abnormal state of the faulty display panel to determine whether the first abnormality is consistent with the abnormal state of the faulty display panel.

[0143] If yes, step S103 is performed: determining that the first signal line of the faulty display panel is abnormal; if no, step S104 is performed: determining that the first signal line of the faulty display panel is normal.

[0144] and / or, step S201: controlling the signal steering unit in the gate drive circuit to change the transmission path of the signal on the second signal line, so that the second signal line is disconnected, and the display panel has a second abnormality.

[0145] Step S202: comparing the second abnormality with the abnormal state of the faulty display panel to determine whether the second abnormality is consistent with the abnormal state of the faulty display panel.

[0146] If yes, step S203 is performed: determining that the second signal line of the faulty display panel is abnormal; if no, step S204 is performed: determining that the second signal line of the faulty display panel is normal.

[0147] In some embodiments, there are multiple first signal lines and multiple second signal lines; different first signal lines and different second signal lines are connected to different signal steering units, respectively; and the abnormality detection method comprises: performing abnormality detection on the first signal lines and the second signal lines one by one. Thus, the multiple first signal lines and the multiple second signal lines can be individually detected for abnormality, and the signal line with abnormality can be more accurately located.

[0148] In some embodiments, the gate driving circuit includes a first gate driving circuit and a second gate driving circuit, the first gate driving circuit provides a gate control cascade signal to the pixel unit, and the second gate driving circuit provides a light-emitting control cascade signal to the pixel unit; the abnormality detection method includes: performing abnormality detection on each of the first signal lines and the second signal lines in the first gate driving circuit; and performing abnormality detection on each of the first signal lines and the second signal lines in the second gate driving circuit.

[0149] The display panel provided by the embodiments of the present disclosure can accurately locate the abnormal signal on the first signal line and / or the second signal line when the signal turning unit in the gate driving circuit causes the first signal line and / or the second signal line to be disconnected, thereby actively reproducing the display defect caused by the abnormal signal, and further helping the analyst to quickly locate the abnormal signal and improving the analysis efficiency of the display defect caused by the abnormal signal.

[0150] In a third aspect, the embodiments of the present disclosure further provide a display device including the display panel in the above embodiments.

[0151] By using the display panel in the above embodiments, the analysis efficiency of the display defect of the display device is improved.

[0152] The display device provided by the embodiments of the present disclosure can be an OLED panel, an OLED television, an OLED billboard, a display, a mobile phone, a navigator, or any product or component having a display function.

[0153] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A gate drive circuit, wherein, The plurality of shift register units comprises a plurality of shift register units, a first signal line, the plurality of shift register units being connected in parallel through the first signal line; a second signal line, the plurality of shift register units being connected in series through the second signal line; a signal steering unit, which is connected in series on the first signal line between two adjacent shift register units; and / or, which is connected in series on the second signal line between two adjacent shift register units; the signal steering unit is capable of changing the transmission path of the signal on the first signal line passing through it, so as to prevent the signal on the first signal line from being transmitted to the next shift register unit; and / or, the signal steering unit is capable of changing the transmission path of the signal on the second signal line passing through it, so as to prevent the signal on the second signal line from being transmitted to the next shift register unit; the signal steering unit comprises a first signal steering unit; the first signal steering unit comprises a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are connected to a first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line; the second electrode of the first transistor is connected to the first signal line; the second electrode of the second transistor is connected to a first test terminal; the signal steering unit further comprises a second signal steering unit; the second signal steering unit comprises a third transistor and a fourth transistor, the gate of the third transistor and the gate of the fourth transistor are connected to a second control terminal; the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the second signal line; the second electrode of the third transistor is connected to the second signal line; the second electrode of the fourth transistor is connected to a second test terminal.

2. The gate drive circuit according to claim 1, wherein The first transistor and the third transistor are P-type transistors or N-type transistors; The second transistor and the fourth transistor are N-type transistors or P-type transistors.

3. The gate drive circuit according to claim 1, wherein The plurality of shift register units are arranged in series along a first direction, The first signal steering unit is located between two adjacent shift register units at a middle position along the first direction; and / or, the second signal steering unit is located between two adjacent shift register units at a middle position along the first direction.

4. The gate drive circuit of claim 1, wherein, The first signal line comprises a clock signal line, a reset signal line and a power supply line; The second signal line comprises a cascade signal line.

5. The gate drive circuit of claim 1, wherein, The number of the first signal steering units is a plurality, and the number of the second signal steering units is a plurality; There are a plurality of first signal lines and a plurality of second signal lines; Different first signal lines are connected to different first signal steering units; Different second signal lines are connected to different second signal steering units.

6. The gate drive circuit of claim 5, wherein, At least part of the first signal steering units and / or at least part of the second signal steering units are located between different shift register units.

7. A display panel, wherein, The gate driving circuit of any one of claims 1-6 is included.

8. The display panel of claim 7, wherein, There is a display area and a frame area, and the frame area surrounds the periphery of the display area; There is a display area and a frame area, and the frame area surrounds the periphery of the display area; The display panel further comprises a plurality of pixel units arranged in an array in the display area; The gate drive circuit comprises a first part; The first part comprises a plurality of shift register units connected in cascade; The first part is located in a first side frame area outside the display area, One of the shift register units in the first part corresponds to at least one row of the pixel units; and / or one of the shift register units in the first part corresponds to at least part of the pixel units in one row.

9. The display panel of claim 8, wherein, The gate drive circuit further comprises a second part; The second part comprises a plurality of shift register units connected in cascade; The second part is located in a second side frame area outside the display area, the second side frame area being opposite to the first side frame area; One of the shift register units in the second part corresponds to at least one row of the pixel units; And / or one of the shift register units in the second part corresponds to at least part of the pixel units in one row.

10. The display panel of claim 9, wherein, The gate drive circuit comprises a first gate drive circuit and a second gate drive circuit, The first gate drive circuit is configured to provide a gate control cascade signal to the pixel units; The second gate drive circuit is configured to provide a light-emitting control cascade signal to the pixel units.

11. The display panel of claim 7, wherein, Further comprising a timing control circuit and a flexible printed circuit; A first signal turning unit in the gate drive circuit is connected to the timing control circuit through a first control terminal; A first signal turning unit in the gate drive circuit is connected to the flexible printed circuit through a first test terminal; A second signal turning unit in the gate drive circuit is connected to the timing control circuit through a second control terminal; A second signal turning unit in the gate drive circuit is connected to the flexible printed circuit through a second test terminal.

12. A display device, wherein, The display panel of any one of claims 7-11.

13. A method of abnormality positioning of a gate drive circuit, wherein The gate drive circuit comprises a plurality of shift register units, A first signal line, the plurality of shift register units being connected in parallel through the first signal line; A second signal line, the plurality of shift register units being connected in cascade through the second signal line; A signal turning unit connected in series between the first signal line of adjacent two shift register units; And / or a signal turning unit connected in series between the second signal line of adjacent two shift register units; The abnormality positioning method comprises: Controlling the signal turning unit to change the transmission path of the signal on the first signal line, preventing the signal on the first signal line from being transmitted to the next shift register unit, and the first signal line being abnormal; And / or controlling the signal turning unit to change the transmission path of the signal on the second signal line, preventing the signal on the second signal line from being transmitted to the next shift register unit, and the second signal line being abnormal; The signal turning unit comprises a first signal turning unit; The first signal turning unit comprises a first transistor and a second transistor, The gate of the first transistor and the gate of the second transistor are connected to a first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line; The second electrode of the first transistor is connected to the first signal line; the second electrode of the second transistor is connected to a first test terminal; The abnormality positioning method comprises: the first control terminal controls the first transistor to be turned off while controlling the second transistor to be turned on, the first signal line is disconnected, and the signal on the first signal line is transmitted to the first test terminal through the second transistor; The signal steering unit further comprises a second signal steering unit; The second signal steering unit comprises a third transistor and a fourth transistor, The gate of the third transistor and the gate of the fourth transistor are connected to a second control terminal; the first electrode of the third transistor and the first electrode of the fourth transistor are connected to the second signal line; The second electrode of the third transistor is connected to the second signal line; the second electrode of the fourth transistor is connected to a second test terminal; The abnormality positioning method further comprises: the second control terminal controls the third transistor to be turned off while controlling the fourth transistor to be turned on, the second signal line is disconnected, and the signal on the second signal line is transmitted to the second test terminal through the fourth transistor.

14. A method of detecting an abnormality of a display panel, wherein The display panel comprises the gate drive circuit according to any one of claims 1-6; The abnormality detection method comprises: controlling a signal steering unit in the gate drive circuit to change the transmission path of the signal on the first signal line, so that the first signal line is disconnected, and the display panel exhibits a first abnormality; comparing the first abnormality with the abnormal state of the faulty display panel to determine whether the first abnormality is consistent with the abnormal state of the faulty display panel; if yes, it is determined that the first signal line of the faulty display panel is abnormal; if no, it is determined that the first signal line of the faulty display panel is normal; and / or, controlling a signal steering unit in the gate drive circuit to change the transmission path of the signal on the second signal line, so that the second signal line is disconnected, and the display panel exhibits a second abnormality; comparing the second abnormality with the abnormal state of the faulty display panel to determine whether the second abnormality is consistent with the abnormal state of the faulty display panel; if yes, it is determined that the second signal line of the faulty display panel is abnormal; if no, it is determined that the second signal line of the faulty display panel is normal; The signal steering unit comprises a first signal steering unit; The first signal steering unit comprises a first transistor and a second transistor, The gate of the first transistor and the gate of the second transistor are connected to a first control terminal; the first electrode of the first transistor and the first electrode of the second transistor are connected to the first signal line; The second electrode of the first transistor is connected to the first signal line; the second electrode of the second transistor is connected to a first test terminal; The abnormality detection method comprises: the first control end controls the first transistor to be off, and controls the second transistor to be on at the same time, the first signal line is disconnected, and the signal on the first signal line is transmitted to the first test end through the second transistor; The signal steering unit further comprises a second signal steering unit; The second signal steering unit comprises a third transistor and a fourth transistor, The gate of the third transistor and the gate of the fourth transistor are connected to a second control end; the first pole of the third transistor and the first pole of the fourth transistor are connected to the second signal line; The second pole of the third transistor is connected to the second signal line; the second pole of the fourth transistor is connected to a second test end; The abnormality detection method further comprises: the second control end controls the third transistor to be off, and controls the fourth transistor to be on at the same time, the second signal line is disconnected, and the signal on the second signal line is transmitted to the second test end through the fourth transistor.

15. The anomaly detection method of claim 14, wherein, The first signal line has multiple lines, and the second signal line has multiple lines; Different first signal lines and different second signal lines are respectively connected to different signal steering units; The abnormality detection method comprises: performing abnormality detection on the first signal lines and the second signal lines one by one.

16. The anomaly detection method of claim 14, wherein, The gate drive circuit comprises a first gate drive circuit and a second gate drive circuit, The first gate drive circuit provides a gate control cascade signal to a pixel unit; The second gate drive circuit provides a light-emitting control cascade signal to the pixel unit; The abnormality detection method comprises: performing abnormality detection on the first signal lines and the second signal lines in the first gate drive circuit one by one; Performing abnormality detection on the first signal lines and the second signal lines in the second gate drive circuit one by one.

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