Pixel circuit, pixel circuit driving method and display substrate

Abstract

This application discloses a pixel circuit, a driving method for the pixel circuit, and a display substrate. The pixel circuit includes a data writing module, a storage module, a bias module, and a driving module. The bias module is coupled to at least one control signal, a first power supply terminal, a reference voltage signal, a bias voltage signal, and a fifth node. It is configured to provide one of the reference voltage signal, the bias voltage signal, and the first power supply terminal signal to the fifth node in time-segmented manner under the control of at least one control signal. The bias module can provide one of the reference voltage signal, the bias voltage signal, and the first power supply terminal signal to the fifth node in time-segmented manner. The storage module adjusts the potential of the first node to bias the gate of the driving transistor, enabling the pixel circuit to compensate for current unevenness caused by the voltage drop at the first power supply terminal when driving the light-emitting module to emit light, thereby improving display unevenness and enhancing the uniformity of the displayed image.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a pixel circuit, a driving method for the pixel circuit, and a display substrate. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are widely used in the display field. In the pixel circuits of these technologies, the current (Ioled) flowing through the light-emitting device during emission is related to the power supply VDD. This can cause uneven display due to a voltage drop across the VDD voltage in the far-end display area. To eliminate the influence of VDD on the current, these technologies employ multiple capacitors, but this approach is detrimental to resolution improvement.

[0003] The above statements are for the purpose of providing background information in relation to this application only and do not necessarily constitute prior art. Summary of the Invention

[0004] The purpose of this application is to provide a pixel circuit, a driving method for the pixel circuit, and a display substrate. To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general description, nor is it intended to identify key / important components or describe the scope of protection of these embodiments. Its sole purpose is to present some concepts in a simple form as a prelude to the detailed description that follows.

[0005] According to one aspect of the embodiments of this application, a pixel circuit is provided, comprising:

[0006] The write data module is coupled to the first scan signal terminal, the second scan signal terminal, the data signal terminal, the second node, the third node, and the first node, and is configured to provide the data signal terminal to the first node through the second node and the third node under the signal control of the first scan signal terminal and the second scan signal terminal.

[0007] A storage module, the two ends of which are respectively coupled to the first node and the fifth node, is configured to store the signal of the first node;

[0008] A bias module, coupled to at least one control signal, a first power supply terminal, a reference voltage signal, a bias voltage signal, and a fifth node, is configured to provide one of the reference voltage signal, the bias voltage signal, and the first power supply terminal signal to the fifth node in time intervals under the control of the at least one control signal.

[0009] The drive module, coupled to the first node, the second node and the third node, is configured to provide a drive electrical signal to the third node based on the signal of the second node under the signal control of the first node.

[0010] In some embodiments of this application, the bias module includes a first bias submodule and a second bias submodule;

[0011] The first bias submodule, coupled to a first control signal, a first power supply terminal, and a fifth node, is configured to provide the signal from the first power supply terminal to the fifth node under the control of the first control signal during a first preset phase.

[0012] The second bias submodule, coupled to the second control signal, the voltage signal terminal and the fifth node, is configured to provide the signal of the voltage signal terminal to the fifth node under the control of the second control signal. The voltage signal terminal is capable of providing the reference voltage signal or the bias voltage signal to the fifth node in time periods.

[0013] In some embodiments of this application, both the first bias submodule and the second bias submodule are connected to a first signal terminal, which provides the first control signal during the first preset phase and provides the second control signal during periods outside the first preset phase.

[0014] In some embodiments of this application, the first bias submodule includes an eighth transistor, and the second bias submodule includes a ninth transistor, wherein one of the eighth transistor and the ninth transistor is a PMOS and the other is an NMOS.

[0015] In some embodiments of this application, the second bias submodule includes a first unit and a second unit, and the second control signal includes a first control sub-signal and a second control sub-signal;

[0016] The first unit is coupled to the first control sub-signal, the reference voltage terminal and the fifth node, and is configured to provide the reference voltage signal of the reference voltage terminal to the fifth node under the control of the first control sub-signal in a second preset stage;

[0017] The second unit is coupled to the second control sub-signal, the bias voltage terminal and the fifth node, and is configured to provide the bias voltage signal of the bias voltage terminal to the fifth node under the control of the second control sub-signal in a third preset stage.

[0018] In some embodiments of this application, the second bias submodule includes at least one of the following:

[0019] The first unit includes a ninth transistor, the gate of which is coupled to the first control sub-signal, and the first and second terminals of the ninth transistor are coupled to the reference voltage terminal and the fifth node, respectively.

[0020] The second unit includes a tenth transistor, the gate of which is coupled to the second control sub-signal, and the first and second terminals of which are coupled to the bias voltage terminal and the fifth node, respectively.

[0021] In some embodiments of this application, when both the first scan signal and the second scan signal provide valid signals, the bias module is configured to provide the reference voltage signal to the fifth node under the control of at least one control signal in a second preset stage.

[0022] In some embodiments of this application, the bias module is further configured to provide the bias voltage signal to the fifth node under the control of the at least one control signal in a third preset phase, the third preset phase being located after the write data period in the second preset phase within a light emission cycle.

[0023] In some embodiments of this application, the bias module is further configured to provide the reference voltage signal to the fifth node under the control of at least one control signal during the bias reset period of the second preset stage, wherein the bias reset period is located after the third preset stage and before the first preset stage.

[0024] In some embodiments of this application, the pixel circuit further includes:

[0025] A first switching module, coupled to an enable signal terminal, a first power supply terminal and a second node, is configured to provide a signal from the first power supply terminal to the second node under the signal control of the enable signal terminal.

[0026] The second switching module, coupled to the enable signal terminal, the third node, and the fourth node, is configured to provide the driving electrical signal of the third node to the fourth node under the signal control of the enable signal terminal to drive the light-emitting module to emit light.

[0027] In some embodiments of this application, the pixel circuit further includes:

[0028] A first reset module, coupled to a first reset signal terminal, a first initial signal terminal, and the third node, is configured to provide the signal from the first initial signal terminal to the third node under the signal control of the first reset signal terminal.

[0029] The second reset module, coupled to the second reset signal terminal, the second initial signal terminal and the fourth node, is configured to provide the signal of the second initial signal terminal to the fourth node under the signal control of the second reset signal terminal;

[0030] The bias module is further configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal, provided that a valid signal is provided at the first reset signal terminal and / or the second reset signal terminal.

[0031] In some embodiments of this application, at least one of the following is satisfied:

[0032] The write data module includes a second transistor and a fourth transistor. The gate of the second transistor is coupled to the second scan signal terminal. The first and second terminals of the second transistor are coupled to the third node and the first node, respectively. The gate of the fourth transistor is coupled to the first scan signal terminal. The first and second terminals of the fourth transistor are coupled to the data signal terminal and the second node, respectively.

[0033] The first switching module includes a fifth transistor, the gate of which is coupled to the enable signal terminal, and the first and second terminals of which are coupled to the first power supply terminal and the second node, respectively.

[0034] The driving module includes a third transistor, the gate of which is coupled to the first node, and the first and second terminals of which are coupled to the second node and the third node, respectively.

[0035] The second switching module includes a sixth transistor, the gate of which is coupled to the enable signal terminal, and the first and second terminals of which are coupled to the third node and the fourth node, respectively.

[0036] The first reset module includes a first transistor, the gate of the first transistor is coupled to the first reset signal terminal, and the first terminal and the second terminal of the first transistor are coupled to the first initial signal terminal and the first node, respectively.

[0037] The second reset module includes a seventh transistor, the gate of which is coupled to the second reset signal terminal, and the first and second terminals of which are coupled to the second initial signal terminal and the fourth node, respectively.

[0038] According to another aspect of the embodiments of this application, a driving method for a pixel circuit is provided, applied to the pixel circuit described in any embodiment of this application, the driving method comprising:

[0039] During the data writing period, corresponding valid signals are provided to both the first and second scan signal terminals, so that the signal at the data signal terminal is written to the first node through the data writing module; and a first valid signal is provided to the bias module, so that the reference voltage signal is provided to the fifth node through the bias module;

[0040] During the bias period, a second valid signal is provided to the bias module, so that the bias voltage signal is provided to the fifth node through the bias module;

[0041] At the end of the biasing phase, a first valid signal is provided to the biasing module, so that the reference voltage signal is provided to the fifth node through the biasing module;

[0042] During the coupling and emission periods, a third valid signal is provided to the bias module, so that the signal at the first power supply terminal is provided to the fifth node through the bias module; and during the emission period, a corresponding valid signal is provided to the enable signal terminal, so that the fourth node is provided with a driving electrical signal to drive the emission module to emit light.

[0043] According to another aspect of the embodiments of this application, a display substrate is provided, including the pixel circuit described in any embodiment of this application.

[0044] One aspect of the technical solution provided in this application embodiment may include the following beneficial effects:

[0045] The pixel circuit provided in this application embodiment can provide one of a reference voltage signal, a bias voltage signal, and a first power supply signal to the fifth node in time intervals through a bias module. Furthermore, the potential of the first node can be adjusted through a storage module to bias the gate of the driving transistor. This allows the pixel circuit to compensate for current unevenness caused by the voltage drop at the first power supply when driving the light-emitting module to emit light, improving display unevenness and enhancing the uniformity of the displayed image. Compared to pixel circuits in related technologies, the solution disclosed in this application does not require additional capacitors, which helps to improve the resolution of the display panel.

[0046] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A block diagram of a pixel circuit according to an embodiment of this application is shown.

[0049] Figure 2 A block diagram of a pixel circuit according to another embodiment of this application is shown.

[0050] Figure 3 A circuit diagram of a pixel circuit according to an embodiment of this application is shown.

[0051] Figure 4 A circuit diagram of a pixel circuit according to another embodiment of this application is shown.

[0052] Figure 5 A timing diagram of a pixel circuit according to an embodiment of this application is shown.

[0053] Figure 6 A timing diagram of a pixel circuit according to another embodiment of this application is shown. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0055] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have a meaning consistent with their meaning in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0056] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate (also called the gate electrode), the signal input terminal is the source, and the signal output terminal is the drain. The switching transistors used in these embodiments can be P-type transistors (PMOS) or N-type transistors (NMOS). P-type transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal and do not imply that the first potential or the second potential has a specific numerical value throughout the text. In this embodiment of the invention, the first potential is used as an example for illustration.

[0057] In related technologies, some OLED products use an 8T1C pixel circuit, which uses a single thin-film transistor (TFT) to directly bias the source of the driving transistor. In this type of pixel circuit, the current flowing through the light-emitting device during emission is related to the power supply VDD. The voltage drop across VDD in the far-end display area can cause uneven display. To eliminate the influence of VDD on the current, two capacitors (i.e., a separate circuit) can be used, but this is detrimental to resolution improvement.

[0058] To address some problems in the related technologies, this disclosure provides a pixel circuit, a driving method for the pixel circuit, and a display substrate.

[0059] The following description, in conjunction with the accompanying drawings, describes a pixel circuit, a driving method for the pixel circuit, and a display substrate according to embodiments of this application.

[0060] One embodiment of this application provides a pixel circuit that can bias the driving transistor (DTFT) through a bias module without adding capacitors, enabling the driving transistor to have a variable refresh rate (VRR). It can also compensate for the voltage drop of the power supply VDD, thereby improving the uneven display quality caused by the VDD voltage drop in the far-end display area.

[0061] refer to Figure 1As shown, one embodiment of this application provides a pixel circuit, including a data writing module 20, a storage module 30, a bias module 80, and a driving module 60.

[0062] The write data module 20, coupled to the first scan signal terminal Gate_P, the second scan signal terminal Gate_N, the data signal terminal Data, the second node N2, the third node N3, and the first node N1, is configured to provide the data signal terminal Data to the first node N1 through the second node N2 and the third node N3, under the signal control of the first scan signal terminal Gate_P and the second scan signal terminal Gate_N. For example, when both the first scan signal terminal Gate_P and the second scan signal terminal Gate_N provide corresponding valid signals, the data signal terminal Data is written to the first node N1 through the data module 20, the second node N2, and the third node N3. When either the first scan signal terminal Gate_P or the second scan signal terminal Gate_N provides a corresponding invalid signal, the data signal terminal Data cannot be written to the first node N1.

[0063] Storage module 30, with its two ends coupled to the first node N1 and the fifth node N5 respectively, is configured to store the signal of the first node N1.

[0064] A bias module 80, coupled to at least one control signal, a first power supply terminal VDD, a reference voltage signal, a bias voltage signal, and a fifth node N5, is configured to provide one of the reference voltage signal, the bias voltage signal, and the first power supply terminal VDD signal to the fifth node N5 in time-sharing periods under the control of at least one control signal. For example, in a first preset time period, the bias module 80 provides the first power supply terminal VDD signal to the fifth node N5 under the control of at least one control signal; in a second preset time period, the bias module 80 provides the reference voltage signal to the fifth node N5 under the control of at least one control signal; and in a third preset time period, the bias module 80 provides the bias voltage signal to the fifth node N5 under the control of at least one control signal.

[0065] The drive module 60, coupled to the first node N1, the second node N2, and the third node N3, is configured to provide a drive electrical signal to the third node N3 based on the signal from the second node N2, under the signal control of the first node N1. For example, the drive module 60 provides a drive electrical signal to the third node N3 when both the first node N1 and the second node N2 provide valid signals.

[0066] For example, the pixel circuit may also include a first switch module 40 and a second switch module 70.

[0067] The first switching module 40 is coupled to the enable signal terminal EM, the first power supply terminal VDD, and the second node N2, and is configured to provide the first power supply terminal VDD signal to the second node N2 under the signal control of the enable signal terminal EM. For example, when the enable signal terminal EM provides a valid signal, the first switching module 40 is turned on, and the first power supply terminal VDD signal is provided to the second node N2; when the enable signal terminal EM provides an invalid signal, the first switching module 40 disconnects the first power supply terminal VDD from the second node N2.

[0068] The second switch module 70, coupled to the enable signal terminal EM, the third node N3, and the fourth node N4, is configured to provide the driving electrical signal of the third node N3 to the fourth node N4 under the signal control of the enable signal terminal EM, thereby driving the light-emitting module 90 to emit light. For example, when the enable signal terminal EM provides a valid signal, the second switch module 70 is turned on, providing the driving electrical signal of the third node N3 to the fourth node N4, and the driving electrical signal of the fourth node N4 drives the light-emitting module 90 to emit light.

[0069] The pixel circuit provided in this application embodiment can provide one of a reference voltage signal, a bias voltage signal, and a first power supply signal to the fifth node N5 in time intervals through a bias module. Furthermore, the potential of the first node N1 can be adjusted through a storage module to bias the gate of the driving transistor. This allows the pixel circuit to compensate for the current unevenness caused by the voltage drop at the first power supply terminal VDD when driving the light-emitting module 90 to emit light, improving display unevenness and enhancing the uniformity of the displayed image. Compared to pixel circuits in related technologies, the solution disclosed in this application does not require additional capacitors, which helps to improve the resolution of the display panel.

[0070] For example, the pixel circuit in this application embodiment may use LTPO technology. LTPO stands for Low Temperature Polycrystalline Oxide.

[0071] refer to Figure 2 As shown, in some embodiments, the pixel circuit includes a data writing module 20, a storage module 30, a bias module 80, a first switch module 40, a driving module 60, and a second switch module 70, and further includes:

[0072] The first reset module 10 is coupled to the first reset signal terminal Reset_P1, the first initial signal terminal Vinit1 and the third node N3, and is configured to provide the signal of the first initial signal terminal to the third node N3 under the signal control of the first reset signal terminal Reset_P1.

[0073] The second reset module 50 is coupled to the second reset signal terminal Reset_P2, the second initial signal terminal Vinit2 and the fourth node N4, and is configured to provide the signal of the second initial signal terminal to the fourth node N4 under the signal control of the second reset signal terminal Reset_P2.

[0074] The bias module 80 is also configured to provide a reference voltage signal to the fifth node N5 under the control of at least one control signal, provided that a valid signal is provided at the first reset signal terminal Reset_P1 and / or the second reset signal terminal Reset_P2.

[0075] The first reset signal terminal Reset_P1 and the second reset signal terminal Reset_P2 can be the same reset signal terminal Reset_P.

[0076] For example, refer to Figure 3 As shown, the write data module 20 may include a second transistor T2 and a fourth transistor T4. The gate of the second transistor T2 is coupled to the second scan signal terminal Gate_N. The first and second terminals of the second transistor T2 are coupled to the third node N3 and the first node N1, respectively. The gate of the fourth transistor T4 is coupled to the first scan signal terminal Gate_P. The first and second terminals of the fourth transistor T4 are coupled to the data signal terminal Data and the second node N2, respectively.

[0077] The first switching module 40 includes a fifth transistor T5. The gate of the fifth transistor T5 is coupled to the enable signal terminal EM. The first terminal and the second terminal of the fifth transistor T5 are coupled to the first power supply terminal VDD and the second node N2, respectively.

[0078] The driving module 60 may include a third transistor T3, the gate of which is coupled to the first node N1, and the first and second terminals of the third transistor T3 are coupled to the second node N2 and the third node N3, respectively.

[0079] The second switching module 70 may include a sixth transistor T6, the gate of which is coupled to an enable signal terminal EM, and the first and second terminals of the sixth transistor T6 are coupled to the third node N3 and the fourth node N4, respectively.

[0080] The first reset module 10 may include a first transistor T1, the gate of the first transistor T1 is coupled to the first reset signal terminal Reset_P1, and the first terminal and the second terminal of the first transistor T1 are coupled to the first initial signal terminal and the first node N1, respectively.

[0081] The second reset module 50 may include a seventh transistor T7, the gate of which is coupled to the second reset signal terminal Reset_P2, and the first and second terminals of the seventh transistor T7 are coupled to the second initial signal terminal and the fourth node N4, respectively.

[0082] The storage module 30 may include a capacitor Cst.

[0083] For example, the bias module 80 may include a first bias submodule and a second bias submodule; the first bias submodule is coupled to a first control signal, a first power supply terminal VDD, and a fifth node N5, and is configured to provide the first power supply terminal VDD signal to the fifth node N5 under the control of the first control signal during a first preset phase; the second bias submodule is coupled to a second control signal, a voltage signal terminal, and the fifth node N5, and is configured to provide the voltage signal terminal signal to the fifth node N5 under the control of the second control signal, wherein the voltage signal terminal can provide a reference voltage signal or a bias voltage signal to the fifth node N5 in time periods. Both the first bias submodule and the second bias submodule may be connected to the first signal terminal, which provides the first control signal during the first preset phase and the second control signal during time periods outside the first preset phase.

[0084] Specifically, refer to Figure 3 As shown, the first bias submodule may include an eighth transistor T8, and the second bias submodule may include a ninth transistor T9. One of the eighth transistor T8 and the ninth transistor T9 is a PMOS, and the other is an NMOS.

[0085] Among them, the second transistor T2 and the ninth transistor T9 are Oxide TFTs (oxide thin film transistors), and the remaining transistors can be low-temperature polycrystalline silicon LTPS transistors. The gates of the eighth transistor T8 and the ninth transistor T9 are both connected to the first control sub-signal s1. One end of the channel of the ninth transistor T9 is directly connected to the drive signal terminal Gate_B of GOA (Gate Driven on Array, i.e., gate drive integration on array substrate).

[0086] For example, the second bias submodule may include a first unit and / or a second unit, and the second control signal includes a first control sub-signal s1 and a second control sub-signal s2;

[0087] The first unit is coupled to the first control sub-signal s1, the reference voltage terminal and the fifth node N5, and is configured to provide the reference voltage signal Vref of the reference voltage terminal to the fifth node N5 under the control of the first control sub-signal s1 in the second preset stage.

[0088] The second unit is coupled to the second control sub-signal s2, the bias voltage terminal and the fifth node N5, and is configured to provide the bias voltage signal Vbias of the bias voltage terminal to the fifth node N5 under the control of the second control sub-signal s2 in the third preset stage.

[0089] Specifically, refer to Figure 4 As shown, the first unit may include a ninth transistor T9, the gate of which is coupled to a first control sub-signal s1, and the first and second terminals of which are coupled to a reference voltage terminal and a fifth node N5, respectively; the second unit may include a tenth transistor T10, the gate of which is coupled to a second control sub-signal s2, and the first and second terminals of which are coupled to a bias voltage terminal and a fifth node N5, respectively.

[0090] When both the first scan signal and the second scan signal provide valid signals, the bias module 80 is configured to provide a reference voltage signal to the fifth node N5 under the control of at least one control signal in a second preset phase.

[0091] The bias module 80 is also configured to provide a bias voltage signal to the fifth node N5 under the control of at least one control signal in a third preset phase, which is located after the write data period in the second preset phase within one light emission cycle.

[0092] The bias module 80 is also configured to provide a reference voltage signal to the fifth node N5 under the control of at least one control signal during the bias reset period of the second preset stage, the bias reset period being after the third preset stage and before the first preset stage.

[0093] For example, transistor T2 is an oxide thin-film transistor (Oxide TFT), while the other transistors can be low-temperature poly-silicon (LTPS) transistors.

[0094] The pixel circuit of this application embodiment can bias the gate of the driving transistor in a capacitive coupling manner through the bias module, so that it has a variable refresh rate without the need to add an additional capacitor, which helps to improve the resolution of the display panel.

[0095] Another embodiment of this application provides a driving method for a pixel circuit, applicable to the pixel circuit of any embodiment of this application. The driving method may include:

[0096] S10. During the data writing period, provide corresponding valid signals to both the first scan signal terminal Gate_P and the second scan signal terminal Gate_N, so that the signal of the data signal terminal Data is written to the first node N1 through the data writing module 20; and provide a first valid signal to the bias module 80, so that the reference voltage signal is provided to the fifth node N5 through the bias module 80.

[0097] S20. During the bias period, a second valid signal is provided to the bias module 80 so that the bias voltage signal is provided to the fifth node N5 through the bias module 80.

[0098] S30. At the end of the biasing process, a first valid signal is provided to the biasing module 80, so that the reference voltage signal is provided to the fifth node N5 through the biasing module 80.

[0099] S40. During the coupling and light emission periods, a third valid signal is provided to the bias module 80, so that the signal of the first power supply terminal VDD is provided to the fifth node N5 through the bias module 80; and during the light emission period, a corresponding valid signal is provided to the enable signal terminal EM, so that the fourth node N4 is provided with a driving electrical signal to drive the light emission module 90 to emit light.

[0100] For example, the bias module 80 in the pixel circuit includes a first bias submodule and a second bias submodule, both of which are coupled to a first signal terminal. The method includes:

[0101] Providing a first valid signal to the bias module 80 may include: providing a valid signal for the second bias submodule to the first signal terminal and providing a reference voltage signal to the voltage signal terminal;

[0102] Providing a second valid signal to the bias module 80 may include: providing a valid signal for the second bias submodule to the first signal terminal and providing a bias voltage signal to the voltage signal terminal;

[0103] Providing a third valid signal to the bias module 80 may include: providing a valid signal to the first signal terminal for the first bias submodule.

[0104] For example, the bias module 80 in the pixel circuit includes a first bias submodule and a second bias submodule, the second bias submodule including a first unit and a second unit, the method including:

[0105] Providing a first valid signal to the bias module 80 includes: providing a corresponding valid signal to the first control sub-signal s1;

[0106] Providing a second valid signal to the bias module 80 includes: providing a corresponding valid signal to the second control sub-signal s2;

[0107] Providing a third valid signal to the bias module 80 includes providing a corresponding valid signal to the first control signal.

[0108] For example, the pixel circuit further includes a first reset module 10 and / or a second reset module 50. The method may further include: during the reset period, providing corresponding valid signals to the first reset signal terminal Reset_P1 and / or the second reset signal terminal Reset_P2, and providing a first valid signal to the bias module 80.

[0109] refer to Figure 5 As shown, Figure 5 for Figure 3 The timing diagram of the corresponding pixel circuit is shown below. The first preset stage includes time periods t5 and t6; the second preset stage includes time periods t1, t2, and t4; and the third preset stage includes time period t3. The first reset signal terminal Reset_P1 and the second reset signal terminal Reset_P2 are the same reset signal terminal Reset_P. Specifically, each time period is described below:

[0110] t1 time period: The process of resetting and resetting.

[0111] When the reset signal terminal Reset_P is low, the second scan signal terminal Gate_N is high, the first control sub-signal s1 is low, and the second and third control sub-signals s2 and s3 are high, the eighth transistor T8 and the tenth transistor T10 are off, and the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 are on. The voltage of the first node N1 and the third node N3 is reset to Vinit1, the voltage of N4 is reset to Vint2, and the voltage of the fifth node N5 is Vref.

[0112] t2 time period: The process of writing data and voltage compensation.

[0113] The first scan signal terminal Gate_P is low, the second scan signal terminal Gate_N is high, the first control sub-signal s1 is low, the second control sub-signal s2 and the third control sub-signal s3 are high, the second transistor T2, the third transistor T3, the fourth transistor T4 and the ninth transistor T9 are turned on, the eighth transistor T8 and the tenth transistor T10 are turned off, the voltage of the second node N2 is Vdata, the voltage of the first node N1 is Vdata+Vth, where Vth is the compensation voltage, and the voltage of the fifth node N5 is Vref.

[0114] t3 time period: The process of achieving DTFT bias.

[0115] The first control sub-signal s1 and the third control sub-signal s3 are at high level, the second control sub-signal s2 is at low level, the eighth transistor T8 and the ninth transistor T9 are off, and the tenth transistor T10 is on. The voltage of the fifth node N5 changes from Vref to Vbias, the voltage of the first node N1 jumps to Vdata+Vth+(Vbias-Vref) through the capacitor Cst, and the voltage of the second node N2 remains at Vdata. At this time, the voltage difference Vgs between the first node N1 and the second node N2 is Vth+(Vbias-Vref), which biases the DTFT.

[0116] t4 time period: the bias ends.

[0117] The first control sub-signal s1 is low, the second control sub-signal s2 and the third control sub-signal s3 are high, the eighth transistor T8 and the tenth transistor T10 are off, and the ninth transistor T9 is on. The voltage at the fifth node N5 changes from Vbias to Vref, and the voltage at the first node N1 jumps back to Vdata+Vth, while stabilizing at the reference voltage terminal.

[0118] t5 time period: The process of achieving VDD coupling.

[0119] The third control sub-signal s3 is low, while the first control sub-signal s1 and the second control sub-signal s2 are high. The eighth transistor T8 is turned on, and the ninth transistor T9 and the tenth transistor T10 are turned off. The voltage at the fifth node N5 changes from Vref to VDD, and the voltage at the first node N1 changes to...

[0120] Vdata+Vth+(VDD-Vref).

[0121] t6 time period: the process of achieving light emission.

[0122] When the enable signal EM is low, transistors T5 and T6 are turned on. The voltage at the second node N2 becomes VDD. At this time, the voltage difference between the first node N1 and the second node N2 is Vgs = VN1 - VN2 = Vdata + Vth + (VDD - Vref) - VDD = Vdata + Vth - Vref. The current flowing through the third transistor T3 is K*(Vgs - Vth)^2 = K*(Vdata - Vref)^2. The magnitude of the current is independent of VDD, which can improve the uneven display caused by the uneven current due to the voltage drop of VDD.

[0123] The frame holding phase only involves reset and biasing processes.

[0124] refer to Figure 6 As shown, Figure 6 for Figure 4The timing diagram of the pixel circuit is shown. The first preset stage includes time periods t5 and t6; the second preset stage includes time periods t1, t2, and t4; and the third preset stage includes time period t3. The descriptions of each time period in this timing diagram are as follows:

[0125] t1 time period: The process of resetting and resetting.

[0126] The reset signal terminal Reset_P is low, the second scan signal terminal Gate_N is high, the first control sub-signal s1 is high, the eighth transistor T8 is off, and the first transistor T1, the second transistor T2, the seventh transistor T7, and the ninth transistor T9 are on. The first node N1 / the third node N3 are reset to Vinit1, the fourth node N4 is reset to Vint2, and the fifth node N5 is the VGH (Gate High Voltage) of the drive signal terminal Gate_B.

[0127] t2 time period: The process of writing data and compensating Vth.

[0128] The first scan signal terminal Gate_P is at a low level, the second scan signal terminal Gate_N is at a high level, the first control sub-signal s1 is at a high level, the second transistor T2, the third transistor T3, the fourth transistor T4, and the ninth transistor T9 are turned on, the eighth transistor T8 is turned off, the voltage of the second node N2 is Vdata, the voltage of the first node N1 is Vdata+Vth, and the voltage of the fifth node N5 is the gate high voltage of the drive signal terminal Gate_B.

[0129] t3 time period: The process of DTFT biasing.

[0130] When the first control sub-signal s1 is high, the eighth transistor T8 is off and the ninth transistor T9 is on. The voltage at the drive signal terminal Gate_B changes from VGH2 to VGL2, the voltage at the fifth node N5 changes from VGH2 to VGL2, the voltage at the first node N1 jumps to Vdata+Vth+(VGL2-VGH2) through capacitor Cst, the voltage at the second node N2 remains at Vdata, and at this time the voltage at Vgs is Vth+(VGL2-VGH2), which biases the DTFT.

[0131] t4 time period: the bias ends.

[0132] When the first control sub-signal s1 is high, the eighth transistor T8 is off, and the ninth transistor T9 is on. The driving signal terminal Gate_B of GOA changes from VGL2 to VGH2, the voltage of the fifth node N5 changes from VGL2 to VGH2, and the voltage of the first node N1 jumps back to Vdata+Vth, which is simultaneously stabilized by the high level of the driving signal terminal Gate_B of GOA.

[0133] t5 time period: The process of achieving VDD coupling.

[0134] When the first control sub-signal s1 is low, the eighth transistor T8 is turned on, and the ninth transistor T9 is turned off. The voltage of the fifth node N5 changes from VGH2 at the drive signal terminal Gate_B to VDD, and the voltage of the first node N1 jumps to Vdata+Vth+(VDD-VGH2).

[0135] t6 time period: the process of achieving light emission.

[0136] When the enable signal EM is low, transistors T5 and T6 are turned on. The voltage at node N2 becomes VDD, at which point Vgs = VN1 - VN2 = Vdata + Vth + (VDD - VGH2) - VDD =

[0137] Vdata + Vth - VGH2. The current flowing through the third transistor T3 is...

[0138] K*(Vgs-Vth)^2=K*(Vdata-VGH2)^2, the current magnitude is independent of VDD, and can compensate for the uneven display caused by the uneven current due to the voltage drop of VDD.

[0139] During the frame holding phase, only the Reset_P signal terminal, the Gate_B drive signal terminal, and the first control sub-signal s1 are enabled, meaning only the reset and bias processes are performed.

[0140] This bias is not limited to the first node N1, but can also be used for the second node N2 and the third node N3.

[0141] Thus, the pixel circuit of this application embodiment can compensate for the VDD voltage drop while simultaneously biasing the gate of the driving transistor (DTFT) through capacitive coupling.

[0142] The pixel circuit driving method of this application embodiment can bias the gate of the driving transistor through the bias module, so that it has a variable refresh rate without the need to add an additional capacitor, which helps to improve the resolution of the display panel.

[0143] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0144] Those skilled in the art will understand that Figure 3 and Figure 4 The illustrated module structures are simplified versions of each module. Those skilled in the art, based on conventional techniques, can further elaborate on these simplified structures. Figure 3 and Figure 4 The structure of each module is modified by adding components to achieve the function of each module. Therefore, the specific structure of each module is not limited to... Figure 3 and Figure 4 Any structure shown can achieve its function.

[0145] Another embodiment of this application provides a display substrate including the pixel circuit of any embodiment of this application. The display substrate of this application embodiment can achieve the same beneficial effects as the pixel circuit of this application embodiment.

[0146] Another embodiment of this application provides a display device including a display substrate according to any embodiment of this application. The display substrate of this application embodiment can achieve the same beneficial effects as the pixel circuit of this application embodiment.

[0147] It should be noted that the above embodiments merely illustrate the implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of this patent application. It should be pointed out that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: The write data module is coupled to the first scan signal terminal, the second scan signal terminal, the data signal terminal, the second node, the third node, and the first node, and is configured to provide the data signal terminal to the first node through the second node and the third node under the signal control of the first scan signal terminal and the second scan signal terminal. A storage module, the two ends of which are respectively coupled to the first node and the fifth node, is configured to store the signal of the first node; A bias module, coupled to at least one control signal, a first power supply terminal, a reference voltage signal, a bias voltage signal, and a fifth node, is configured to provide one of the reference voltage signal, the bias voltage signal, and the first power supply terminal signal to the fifth node in time intervals under the control of the at least one control signal. A drive module, coupled to the first node, the second node and the third node, is configured to provide a drive electrical signal to the third node based on the signal of the second node under the signal control of the first node; The bias module includes a first bias submodule and a second bias submodule; The first bias submodule, coupled to a first control signal, a first power supply terminal, and a fifth node, is configured to provide the signal from the first power supply terminal to the fifth node under the control of the first control signal during a first preset phase. The second bias submodule is coupled to the second control signal, the voltage signal terminal and the fifth node, and is configured to provide the signal of the voltage signal terminal to the fifth node under the control of the second control signal. The voltage signal terminal can provide the reference voltage signal or the bias voltage signal to the fifth node in time periods. Both the first bias submodule and the second bias submodule are connected to the first signal terminal. The first signal terminal provides the first control signal during the first preset phase and provides the second control signal during periods other than the first preset phase. The second bias submodule includes a first unit and a second unit, and the second control signal includes a first control sub-signal and a second control sub-signal; The first unit is coupled to the first control sub-signal, the reference voltage terminal and the fifth node, and is configured to provide the reference voltage signal of the reference voltage terminal to the fifth node under the control of the first control sub-signal in a second preset stage; The second unit is coupled to the second control sub-signal, the bias voltage terminal and the fifth node, and is configured to provide the bias voltage signal of the bias voltage terminal to the fifth node under the control of the second control sub-signal in a third preset stage.

2. The pixel circuit according to claim 1, characterized in that, The first bias submodule includes an eighth transistor, and the second bias submodule includes a ninth transistor, wherein one of the eighth transistor and the ninth transistor is a PMOS and the other is an NMOS.

3. The pixel circuit according to claim 1, characterized in that, The second bias submodule includes at least one of the following: The first unit includes a ninth transistor, the gate of which is coupled to the first control sub-signal, and the first and second terminals of the ninth transistor are coupled to the reference voltage terminal and the fifth node, respectively. The second unit includes a tenth transistor, the gate of which is coupled to the second control sub-signal, and the first and second terminals of which are coupled to the bias voltage terminal and the fifth node, respectively.

4. The pixel circuit according to any one of claims 1-3, characterized in that, When both the first scan signal and the second scan signal provide valid signals, the bias module is configured to provide the reference voltage signal to the fifth node under the control of at least one control signal during a second preset phase.

5. The pixel circuit according to claim 4, characterized in that, The bias module is further configured to provide the bias voltage signal to the fifth node under the control of the at least one control signal in a third preset phase, the third preset phase being located after the write data period in the second preset phase within one light emission cycle.

6. The pixel circuit according to claim 5, characterized in that, The bias module is further configured to provide the reference voltage signal to the fifth node under the control of at least one control signal during the bias reset period of the second preset stage, wherein the bias reset period is located after the third preset stage and before the first preset stage.

7. The pixel circuit according to any one of claims 1-3, characterized in that, The pixel circuit also includes: A first switching module, coupled to an enable signal terminal, a first power supply terminal and a second node, is configured to provide a signal from the first power supply terminal to the second node under the signal control of the enable signal terminal. The second switching module, coupled to the enable signal terminal, the third node, and the fourth node, is configured to provide the driving electrical signal of the third node to the fourth node under the signal control of the enable signal terminal to drive the light-emitting module to emit light.

8. The pixel circuit according to any one of claims 1-3, characterized in that, The pixel circuit also includes: A first reset module, coupled to a first reset signal terminal, a first initial signal terminal, and the third node, is configured to provide the signal from the first initial signal terminal to the third node under the signal control of the first reset signal terminal. The second reset module, coupled to the second reset signal terminal, the second initial signal terminal and the fourth node, is configured to provide the signal of the second initial signal terminal to the fourth node under the signal control of the second reset signal terminal; The bias module is further configured to provide the reference voltage signal to the fifth node under the control of the at least one control signal, provided that a valid signal is provided at the first reset signal terminal and / or the second reset signal terminal.

9. The pixel circuit according to claim 8, characterized in that, The write data module includes a second transistor and a fourth transistor. The gate of the second transistor is coupled to the second scan signal terminal. The first and second terminals of the second transistor are coupled to the third node and the first node, respectively. The gate of the fourth transistor is coupled to the first scan signal terminal. The first and second terminals of the fourth transistor are coupled to the data signal terminal and the second node, respectively. The first switching module includes a fifth transistor, the gate of which is coupled to an enable signal terminal, and the first and second terminals of which are coupled to the first power supply terminal and the second node, respectively. The driving module includes a third transistor, the gate of which is coupled to the first node, and the first and second terminals of which are coupled to the second node and the third node, respectively. The second switching module includes a sixth transistor, the gate of which is coupled to the enable signal terminal, and the first and second terminals of which are coupled to the third node and the fourth node, respectively. The first reset module includes a first transistor, the gate of the first transistor is coupled to the first reset signal terminal, and the first terminal and the second terminal of the first transistor are coupled to the first initial signal terminal and the first node, respectively. The second reset module includes a seventh transistor, the gate of which is coupled to the second reset signal terminal, and the first and second terminals of which are coupled to the second initial signal terminal and the fourth node, respectively.

10. A driving method for a pixel circuit, characterized in that, The driving method, applied to the pixel circuit of any one of claims 1-9, comprises: During the data writing period, corresponding valid signals are provided to both the first and second scan signal terminals, so that the signal at the data signal terminal is written to the first node through the data writing module; and a first valid signal is provided to the bias module, so that the reference voltage signal is provided to the fifth node through the bias module; During the bias period, a second valid signal is provided to the bias module, so that the bias voltage signal is provided to the fifth node through the bias module; At the end of the biasing phase, a first valid signal is provided to the biasing module, so that the reference voltage signal is provided to the fifth node through the biasing module; During the coupling and emission periods, a third valid signal is provided to the bias module, so that the signal from the first power supply terminal is provided to the fifth node through the bias module; and during the emission period, a corresponding valid signal is provided to the enable signal terminal, so that the fourth node is provided with a driving electrical signal to drive the emission module to emit light.

11. A display substrate, characterized in that, Includes the pixel circuit as described in any one of claims 1-9.

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