Calculation system, calculation method thereof, and search memory

Abstract

The invention provides an operation system, an operation method thereof and a search memory. A non-volatile 3D memory search architecture for receiving a plurality of searches for application to a plurality of select lines and a plurality of word lines of a non-volatile 3D memory. This architecture uses two word lines per cell of multiple searched information, and two memory devices per cell of a storage feature for reverse search. This architecture uses a plurality of corresponding bit lines of a non-volatile 3D memory array as a plurality of corresponding match lines for search. A plurality of corresponding memory strings (e.g., a plurality of NAND memory strings) of a non-volatile 3D memory array may be used to store a plurality of corresponding data values, e.g., corresponding to a plurality of elements to be searched. The plurality of corresponding memory strings are coupled in parallel to the plurality of corresponding common bit lines. In addition to searching in application areas such as artificial intelligence (AI) and big data, the architecture has application capabilities of comparison and sorting.

Description

Technical Field

[0001] The present invention is for searching within a 3D memory and can be implemented using a 3D NAND memory and applied to big data and / or artificial intelligence (AI) processing. Background Art

[0002] The growth of big data and AI (eg, AI hardware accelerators) has increased the importance of searching, comparing, and / or storing data. Conventional systems use ternary content addressable memory (TCAM) technology to implement parallel (concurrent) searches.

[0003] Conventional TCAM technology is implemented using static random access memory (SRAM) technology, and thus has relatively low memory density (eg, 16 transistors are used to form a single TCAM memory cell) and relatively high power consumption.

[0004] Recently proposed TCAM technologies are implemented using non-volatile memory technologies, such as 2-transistor and 2-resistor (2T2R) based technologies and 2-ferroelectric field effect transistor (2FeFET) technologies. However, TCAM technologies implemented with non-volatility require paired memories for a single TCAM cell (or paired memory cells to implement a search bit or a data bit), thus limiting the efficiency of search and data storage.

[0005] Example techniques for using in-NAND flash memory search capabilities enabled to perform exact match and approximate match operations are described in “PHTseng et al., In-Memory-Searching Architecture Based on 3D-NAND Technology with Ultra-high Parallelism, 2020 IEDM” and “PHTseng et al., In-Memory Approximate Computing Architecture Based on 3D-NAND Flash Memories, 2022 VLSI”.

[0006] Therefore, for example, with respect to big data and / or AI processing, techniques capable of high-performance searching, comparing and / or sorting are needed. Summary of the invention

[0007] A system of one or more computers is used to implement specific operations and / or actions by having software, firmware, hardware or a combination thereof installed on the system, which enables the system to perform and / or control operations and / or actions when in operation. One or more computer programs are used to perform specific operations and / or actions by containing instructions, which enable the device to perform operations and / or actions when executed.

[0008] A first aspect of an operation system includes a bit line and a source line; a paired memory string includes a first memory string and a second memory string connected in parallel between the bit line and the source line, wherein the first memory string includes at least one selection device responsive to a selection input, and the at least one selection device is connected in series to a plurality of programmable devices connected in series, each programmable device responds to a corresponding programmed state and a corresponding control input, and wherein the second memory string is the same as the first memory string; a sense amplifier is connected to the bit line and is enabled to provide one of a plurality of match indications; a data encoding circuit is responsive to at least one data input and is enabled according to a selection code to provide programming data to a plurality of the first memory string and the second memory string; a programmable device; and a search data encoding circuit, enabled to (i) drive the select inputs of the first memory string and the second memory string in response to a search range of the search condition, and enabled to (ii) drive the control input in response to the search value of the search condition according to the select code, wherein the paired memory strings are enabled to couple to the bit line and the source line through a corresponding one of a plurality of string pair currents in response to the select inputs, the control inputs and the programmed state of the first memory string and the second memory string, wherein the plurality of string pair currents include an exact match current and a no match current, and wherein the plurality of match indications include an exact match indicated in response to the exact match current and a no match indicated in response to the no match current. Other variations of this aspect include corresponding computer systems, devices and computer programs recorded in one or more computer storage devices, each for implementing the actions of this method.

[0009] The plurality of variations selectively include one or more of the following features. The string pair current of the computer system further includes at least a portion of the matching current, and the plurality of match indications include at least a portion of the matching current being indicated in response to the at least a portion of the matching current. The plurality of programmable devices connected in series are arranged in a plurality of layers, and the data encoding circuit is further enabled to drive the selection inputs of the first memory string and the second memory string in response to the search depth of the search condition, and the search depth indicates how many of the plurality of layers are searched. The data encoding circuit is further enabled to drive the selection inputs of the first memory string and the second memory string in response to the search start of the search condition, and the search start indicates to start the search from one of the plurality of layers. The page buffer further includes a priority encoder enabled to preferentially encode the plurality of matching results of the plurality of sense amplifiers. The accurate matching current is greater than the no matching current. Each of the plurality of programmable devices connected in series is programmed by adjusting the corresponding threshold voltage to one of at least two threshold levels, and the selection code indicates how to encode binary logic 0 and binary logic 1 to corresponding two of the at least two threshold levels, respectively, and the at least two threshold levels are distinguishable from each other. Each of the plurality of programmable devices connected in series is programmed by adjusting a corresponding threshold voltage to one of at least eight threshold levels, the selection code indicating how to encode octal logic 0, octal logic 1, octal logic 2, octal logic 3, octal logic 4, octal logic 5, octal logic 6, and octal logic 7 to corresponding eight of the at least eight threshold levels, and the at least eight threshold levels are mutually distinct. Each of the plurality of programmable devices connected in series is programmed by adjusting a corresponding threshold voltage to one of a plurality of analog threshold levels, the selection code indicating how to encode corresponding multiple analog data values ​​to corresponding ones of the plurality of analog threshold levels, and the plurality of analog threshold levels are mutually distinct. The data encoding circuit is further enabled to provide additional programming data (1) to the plurality of programmable devices of a first memory string of the plurality of memory string pairs and (2) to the plurality of programmable devices of a second memory string of the plurality of memory string pairs in response to at least one data input and based on the selection code. The computing system further includes a plurality of 2D memory arrays, a first of the plurality of 2D memory arrays comprising a plurality of memory string pairs and paired memory strings. Each of the plurality of bit lines of the plurality of 2D memory arrays is connected to a corresponding one of the plurality of sense amplifiers. The operating system includes a page buffer, the page buffer includes a priority encoder, and is enabled to preferentially encode the plurality of matching results of the plurality of sense amplifiers. The variations of the technology selectively include hardware, method or program, or computer software in a computer-accessible medium.

[0010] The second aspect of the operation method includes receiving at least data input; receiving search conditions including a search range and a search value; providing programming data to a plurality of programmable devices of a first memory string and a second memory string in response to at least one data input based on a selection code; driving a plurality of selection inputs of the first memory string and the second memory string in response to the search range; driving a plurality of control inputs of the first memory string and the second memory string based on the selection code and in response to the search value; sensing a bit line to provide an indication of one of a plurality of match indications, and wherein the first memory string and the second memory string are connected in parallel between the bit line and the source line; providing an indication as an output, wherein the paired memory string includes a first memory string and a second memory string, the first memory string The memory string includes at least one selection device and is responsive to a corresponding one of a plurality of selection inputs, and is serially connected to a plurality of programmable devices connected in series, each of the plurality of programmable devices being responsive to a corresponding programmed state and a corresponding one of a plurality of control inputs, and the second memory string is identical to the first memory string, wherein the paired memory strings are enabled to couple to the bit line and the source line through a corresponding one of a plurality of string pair currents in response to the plurality of selection inputs, the plurality of control inputs, and the plurality of programmed states of the first memory string and the second memory string, wherein the plurality of string pair currents include an exact match current and a no match current, and wherein the plurality of match indications include an exact match indicated in response to the exact match current and a no match indicated in response to the no match current. Other variations of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each for performing the actions of this method.

[0011] The plurality of variations optionally include one or more of the following features. The plurality of string pair currents of the operation method further include at least a portion of matching currents, and the plurality of match indications include at least a portion of matching in response to at least a portion of matching currents being indicated. The plurality of programmable devices connected in series are arranged in a plurality of layers, the search condition further includes a search depth, the plurality of control inputs are driven further in response to the search depth, and the search depth indicates how many of the plurality of layers are searched. The convenience of the technology optionally includes hardware, method or program, or computer software in a computer-accessible medium.

[0012] A third aspect includes a search memory comprising a plurality of sense amplifiers; a plurality of 2D memory arrays each comprising: a corresponding bit line connected to a corresponding one of the plurality of sense amplifiers, a corresponding source line, and a corresponding plurality of memory strings, each of the plurality of memory strings being coupled to (a) a corresponding bit line and (b) a corresponding source line, and each of the plurality of memory strings comprising (1) a corresponding plurality of floating gate transistors connected in series, each of the plurality of floating gate transistors having and responsive to (c) a corresponding set state and (d) a corresponding control input, and each of the plurality of memory strings further comprising (2) a corresponding selection device connected in series between the corresponding plurality of floating gate transistors connected in series and the corresponding bit line, wherein each of the plurality of selection devices has and responsive to a corresponding selection line; a plurality of word lines, each of the plurality of word lines being coupled to a corresponding one of a corresponding plurality of control inputs of each of the plurality of floating gate transistors connected in series; a data encoder enabled to program data to the plurality of floating gate transistors connected in series, and responsive to at least the data input and based on a selection code; and a search encoder enabled to receive The invention relates to a method for controlling a plurality of memory strings to receive a search and drive a plurality of word lines according to the search and selection code, and further enabled to drive a plurality of select lines according to the search; and wherein, (e) corresponding to each of the plurality of memory strings, driving the corresponding each of the plurality of memory strings to be coupled to the corresponding bit lines and source lines by match finding currents, in response to the plurality of set states of the memory strings precisely matching the plurality of control inputs of the plurality of floating gate transistors connected in series to the memory strings, and (f) each of the plurality of sense amplifiers is enabled to generate a corresponding indication of whether the bit lines coupled to the respective plurality of sense amplifiers are coupled to the source lines by the match finding currents; and wherein, (g) each of the memory strings is further enabled to couple the corresponding each of the plurality of memory strings to be coupled to the corresponding bit lines and source lines by no match finding currents, in response to the plurality of set states of the memory strings not precisely matching the plurality of control inputs of the plurality of floating gate transistors connected in series to the memory strings, and (h) each of the plurality of sense amplifiers is further enabled to generate a corresponding indication of whether the bit lines coupled to the respective plurality of sense amplifiers are coupled to the source lines by the no match finding currents. Other variations of this aspect include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each for implementing the actions of this method.

[0013] The plurality of variations optionally include one or more of the following features. The corresponding memory strings of the search memory are further enabled to couple the corresponding plurality of memory strings to the corresponding bit lines and source lines through a portion of the matching discovery current, in response to the plurality of set states of the memory strings partially matching the corresponding plurality of control inputs of the plurality of floating gate transistors connected in series to the memory strings, and each sense amplifier is further enabled to generate a corresponding indication of whether the bit line coupled to each sense amplifier is coupled to the source line through the portion of the matching discovery current. The plurality of floating gate transistors connected in series are arranged in a plurality of layers, the search encoder is enabled to drive the plurality of select lines in response to the search depth, and the search depth indicates how many of the plurality of layers are searched. The variations of the technology optionally include hardware, methods or programs, or computer software in a computer accessible medium.

[0014] Other features, aspects, and advantages will be more clearly understood through the embodiments, drawings, and patent claims. In order to have a better understanding of the above and other aspects of the present invention, the following embodiments are specifically cited and described in detail with the accompanying drawings as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram illustrating an example of a 3D search memory is shown.

[0016] Figure 2 A schematic diagram showing selected details of an example of a 2D memory array is shown.

[0017] Figure 3 A schematic diagram is shown showing selected details of an example 3D memory array.

[0018] Figure 4 A schematic diagram illustrating an in-memory search through the contents of a pair of memory strings connected to a bit line (BL) is shown.

[0019] Figure 5A and Figure 5B A schematic diagram is shown of an example of an encoding technique using two threshold levels and providing a high current indication of no match between search data and stored data.

[0020] Fig. 6A , Figure 6B and Figure 6C Also shown are schematic diagrams of examples of encoding techniques using eight threshold levels and providing a larger current indication of no match between search data and stored data.

[0021] Fig. 7A and Figure 7B Also shown are schematic diagrams of examples of p-level encoding techniques using a p-threshold level and providing a larger current indication of no match between search data and stored data.

[0022] Figure 8 A schematic diagram is shown of an example of an encoding technique using analog levels and providing a larger current indication of no match between search data and stored data.

[0023] Fig.9A and Fig. 9B A schematic diagram is shown of an example of an encoding technique using two threshold levels and providing a small current indication of no match between search data and stored data.

[0024] Fig. 10A , Fig. 10B and Fig. 10C Also shown are schematic diagrams of examples of encoding techniques using eight threshold levels and providing a small current indication of no match between search data and stored data.

[0025] Fig.11A and Fig. 11B Also shown are schematic diagrams of examples of p-level encoding techniques using a p-threshold level and providing a small current indication of no match between search data and stored data.

[0026] Fig. 12A , Fig. 12B and Fig. 12C A schematic diagram illustrating a multi-layer search operation is shown.

[0027] Fig.13A , Fig. 13B and Fig. 13C A schematic diagram illustrating multiple two-level search operations according to the two-threshold large current no-match encoding technique is shown.

[0028] Fig.14A , Fig. 14B and Fig. 14C A schematic diagram illustrating a plurality of two-layer search operations according to the two-threshold small current no-match encoding technique is shown.

[0029] Fig.15A , Fig. 15B and Fig. 15C A schematic diagram is shown of multiple two-layer search operations according to the eight-threshold small current no-match encoding technique.

[0030] Fig.15D and Fig.15E A matching example and a non-matching example according to the eight-threshold small current non-matching encoding technique are respectively illustrated.

[0031] Fig.16A , Fig. 16B and Fig. 16C Schematic diagrams are shown of various search operations according to any high current no-match encoding technique.

[0032] Fig.17A , Fig. 17B and Fig. 17CSchematic diagrams are shown of various search operations according to any high current no-match encoding technique.

[0033] Fig.18A and Fig.18B Schematic diagrams are shown of various search operations according to any high current no-match encoding technique.

[0034] Fig. 18C Schematic diagrams are shown of various search operations according to any high current no-match encoding technique.

[0035] Fig.19 A schematic diagram illustrating a whole-plane or whole-chip search operation is shown.

[0036] Fig. 20 A schematic diagram illustrating a full-chip search operation is shown.

[0037] Fig.21 A schematic diagram illustrating a full-chip search operation is shown.

[0038] Fig. 22 An example operational flow chart for a 3D search memory is shown.

[0039]

Explanation of symbols

[0040] 100: 3D search memory

[0041] 110: Data

[0042] 111: Encoded data

[0043] 120: Search

[0044] 130: Page Cache

[0045] 140: Encoding

[0046] 150: 3D memory array

[0047] 160: Data encoder

[0048] 170: Search encoder

[0049] 171, SSL_1, SSL_2, SSL_3, SSL_4, SSL_509, SSL_510,

[0050] SSL_511, SSL_512: string select line

[0051] 172, WL1_1…WL1_256,WL1_1'…WL1_256',

[0052] WL2_1…WL2_256, WL2_1'…WL2_256',

[0053] WL255_1…WL255_256, WL255_1’…WL255_256’

[0054] WL256_1…WL256_256, WL256_1’…WL256_256’

[0055] Word line

[0056] 180: Bit line

[0057] 199, 391, 392, 397, 398, 399, 1901, 1902, 1903, 2001, 2002

[0058] 2003, 2101, 2102, 2103: 2D

[0059] 231, 232, 238, 239: MemStrPr

[0060] 249: IMS

[0061] 281, 1381, 1383, 1385, 1481, 1483, 1485, 1581, 1583, 1585

[0062] BL

[0063] 282: Ground

[0064] 480: IMS Cell

[0065] 481, 881: WL

[0066] 482, 882: WL’

[0067] 483: FG

[0068] 484: FG’

[0069] 572, 972: Memory State LVT

[0070] 583, 973: Memory State HVT

[0071] 670~677, 1070~1077: Vt 0~Vt 7

[0072] 770~776, 1170~1176: Vt 0~Vt p

[0073] 810, 883: Current

[0074] 878, 879: Tunable Vt

[0075] 884:Current’

[0076] 885,887:Mismatch

[0077] 886:Match

[0078] 888,889,1970,2070,2170:WL+WL’

[0079] 1201,1601,1701:IMS cell1-1

[0080] 1202,1702:IMS cell1-2

[0081] 1211,1213:Vpass

[0082] 1212,1214:Vpass’

[0083] 1221:Vsearch[2:1]

[0084] 1222:Vsearch’[2:1]

[0085] 1223:Vsearch[8:1]

[0086] 1224:Vsearch’[8:1]

[0087] 1225:Vsearch[256:1]

[0088] 1226:Vsearch’[256:1]

[0089] 1382,1384,1386,1482,1484,1486,1582,1584,1586:

[0090] Pair Current

[0091] 1511,1512:8 OD

[0092] 1513:10 OD

[0093] 1514:5 OD

[0094] 1609,1708:IMS cell256-1

[0095] 1611, 1612, 1613, 1614, 1615, 1711, 1712, 1713, 1714, 1715, 1811, 1812, 1911, 1912, 1913, 2011, 2012, 2013: Vpass+Vpass'

[0096] 1621, 1622, 1623, 1624, 1625, 1626, 1721, 1722:

[0097] Vsearch+Vsearch'

[0098] 1709: IMS cell256-2

[0099] 1723, 1724, 1725, 1726: Vsearch[2:1]+Vsearch'[2:1]

[0100] 1821, 1822, 1823, 1824: Vsearch[5:1]+Vsearch'[5:1]

[0101] 1825, 1826: Vsearch[256:1]+Vsearch'[256:1]

[0102] 1910, 2010, 2110: Search In

[0103] 2200: Search Process

[0104] 2201, 2202, 2203, 2204, 2205, 2206, 2207: Steps

[0105] CSL_1, CSL_2, CSL_3, CSL_4, CSL_511, CSL_512: Common select lines

[0106] GSL_1, GSL_2, GSL_3, GSL_4: Ground selection lines DETAILED DESCRIPTION

[0107] A technical description of a non-volatile 3D memory search architecture is provided in reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 8 , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig. 12C , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.15D , Fig.15E , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig. 18C , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 supply.

[0108] A non-volatile 3D memory search architecture provides multiple select lines and multiple word lines for receiving multiple searches to apply to a non-volatile 3D memory array. This architecture uses two word lines per unit of information for multiple searches, and two memory devices per unit of storage features for search. This architecture uses multiple corresponding bit lines of the non-volatile 3D memory array as multiple corresponding match lines for searching. Multiple corresponding memory strings (e.g., multiple NAND memory strings) of the non-volatile 3D memory array can be used to store multiple corresponding data values, such as corresponding to multiple elements to be searched. Multiple corresponding memory strings are coupled in parallel to multiple corresponding common bit lines. In addition to searching in application areas such as artificial intelligence (AI) and big data, this architecture has application capabilities for comparing and sorting.

[0109] One or more flow charts are described herein. The processing described in the flow chart is implementable and / or can be directly used by a programmable processor, which uses a computer program stored in an accessible memory of a computer system and can be executed by a processor, uses dedicated logic hardware (including field programmable integrated circuits (FPGA)), and uses various combinations thereof. Multiple actions are combinable, can be executed in parallel, and / or can be executed in different orders without affecting the processing achieved. In some cases, the rearranged multiple actions can achieve the same result only when specific other changes are made at the same time. In other cases, the rearranged multiple actions can achieve the same result only when specific conditions are met. Further, for the sake of clarity of description, some flow charts herein omit specific unnecessary actions to understand the disclosed technology. Multiple additional actions can be performed before, after, and / or during the described actions.

[0110] Examples of selected acronyms, mnemonics and abbreviations used for the purposes of this description are listed below.

[0111]

[0112]

[0113] An example of a memory string is a plurality of memory devices connected in series. An example of a memory device is a device enabled to store data to indicate one of at least two mutually exclusive states of the memory device. These states are settable by programming the memory device and are readable by activating a control input of the memory device. In many types of memory devices (such as floating gate memory devices), programming is by setting a threshold voltage of the memory device, and the control input is a control gate input. Setting may also refer to programming a memory device (e.g., programming to 1 or 0 or some other value), and may also refer to storing a value (e.g., storing 1 or 0 or some other value).

[0114] An example of a search condition is an acquisition of data indicating one of the data to be searched and how to perform the search. The search condition includes any combination of a search value, a search depth, a search start point, and a search range. The search value indicates, for example, one of the stored data to be searched. The search depth indicates, for example, how many layers of the memory array are searched. The search start point indicates, for example, in which layer the search begins. The search range indicates, for example, which of the multiple memory strings is started for the search.

[0115] 3D Memory Search Concept

[0116] Disclosed herein is a non-volatile 3D memory search that can be implemented using a 3D search memory (e.g., 3D-NAND memory) that enables high-performance searching, comparing, and / or sorting, such as for big data and / or AI processing. This architecture provides low latency, high resolution, high content density, multi-block functionality, and robust reliability. This architecture can be applied to a variety of fields, such as big data search, AI hardware accelerators and / or classifiers, approximate computing, associative memory, few-shot learning, SSD data management, DNA matching, data screening, high-dimensional computing, and other applications that can benefit from in-memory computing enabled with long search keywords and large data volumes.

[0117] The host agent directs the storage of data in the 3D search memory. In response, the 3D search memory stores the data. Then, the host agent provides multiple searches to the 3D search memory. In response, the 3D search memory processes the multiple searches by determining zero or more matches in the stored data according to the multiple searches.

[0118] A control agent of the 3D search memory receives data for storage from a host agent and, in response, directs the 3D search memory to configure memory devices contained therein to store data (e.g., programming circuits contained therein). The control agent receives a plurality of searches and, in response, directs one or more 2D memory resources of the 3D search memory to provide search results (e.g., match indications) to the host agent based on the plurality of searches.

[0119] Various techniques for 3D memory search architectures are provided to efficiently search a 3D search memory for matching data stored in the 3D search memory based on any combination of search conditions, such as a search value, a search depth, a search start point, and a search range. The search value specifies one of a 3D memory array of the 3D search memory to be searched. The 3D memory array includes a plurality of horizontally-stacked layers. The search depth specifies how many layers to search. The search start point specifies where the search begins in one of the plurality of stacked layers. The search range specifies which portion of the 3D memory array to search.

[0120] For example, a 3D memory array is implemented using NVM technology, such as including floating gate programmable memory devices. The three dimensions of a 3D memory array are referred to herein as X, Y, and Z. One or more 3D search memories and / or 3D memory array examples may be implemented as all or any portion of an integrated circuit fabricated from wafer material using planar process technology. Dimensions X and Y correspond to horizontal planes of a planar process. Dimension Z corresponds to a vertical plane of a planar process, such as multiple vertically stacked layers of material.

[0121] The 3D memory array includes multiple 2D memory arrays. Each 2D memory array includes multiple memory string pairs. Each memory string includes source / drain series-connected non-volatile memory devices, each having a corresponding control gate input. The control gate input is connected to a corresponding word line and is operated in pairs according to the pairing of the memory strings and the corresponding pairing of the devices therein. Each string additionally includes a string selection device in which the source / drain is connected in series to the non-volatile memory device. The string selection device has a gate input connected to the string selection control input. Each string additionally includes one or more source / drain series-connected control devices with corresponding gates and associated control inputs.

[0122] The search condition includes a search value, and optionally one or more of a search depth, a search start point, and a search range. The search value is one of the 3D search memories to be searched. The search depth is how many layers (adjacent) in the 3D search memory to search. The search start point is where the search starts. The search range indicates the string selection line to start the search.

[0123] Search values ​​have a length, such as a number of words, and are sometimes referred to as bits. The number of bits is based on the numerical representation system, such as binary for two bits, or octal for eight bits.

[0124] The encoding of the search input and data value is based on how much circuitry determines a match (no match), such as by a large / larger or small / smaller current. For example, a portion of a page buffer (such as a sense amplifier) ​​determines a match is indicated by a larger current than no match. In another example, the page buffer determines a match is indicated by a smaller current than no match.

[0125] The encoding of the search input and data value is further based on a unique representation of each bit. Each unique representation corresponds to a level. The encoding can be implemented as two-level, eight-level, p-level (multi-level) and analog technology.

[0126] Techniques associated with a 3D memory search architecture enable high-speed searches for matching long word strings in large amounts of stored data.

[0127] In some use cases, the read latency of the 3D search memory is reduced by operating multiple blocks simultaneously (at the expense of relatively large current transients). The simultaneous operation is performed by switching multiple activation controls, such as multiple string select lines SSL.

[0128] 3D Memory Search Example Implementation

[0129] Figure 1 An example of a 3D search memory is shown, such as 3D search memory 100. 3D search memory 100 is implemented in three dimensions (X, Y, and Z) and includes encoding, storage / search, and output resources. The encoding resources include a data encoder 160 (e.g., a data encoding circuit) enabled to receive data 110 and in response to provide encoded data 111 (e.g., programming data) to the storage / search resources. The encoding resources further include a search encoder 170 enabled to receive search 120 and in response to provide string search lines such as string select lines 171 as shown and paired word lines such as word lines 172 as shown to the storage / search resources. The encoding performed by the encoding resources is according to a specific encoding technique, such as encoding 140 shown in the dashed box. The storage / search resources include a 3D memory array 150, which includes multiple 2D memory arrays, one of which is specifically considered to be a 2D memory array (2D 199). The output resources include a page buffer 130 (which includes, for example, a sense amplifier) ​​enabled to receive bit line information from each 2D memory array of the 3D memory array 150, such as the bit line 180 shown.

[0130] For clarity, the figures omit details regarding programming the programmable memory devices of the 2D memory array.

[0131] In some examples, search encoder 170 (which includes, for example, search encoding circuitry) and / or bit lines 180 are enabled to sequentially traverse multiple layers, such as switching searches from layer 1 to layer 2 and / or layer 7 and so on.

[0132] Figure 2 Select details of an example of a 2D memory array are shown, such as a 2D memory array (2D 199).

[0133] 2D 199 includes 256 memory string pairs. For clarity, the figure explicitly shows 4 pairs, memory string pairs MemStrPr 231, MemStrPr 232, MemStrPr 238 and MemStrPr 239. Each memory string pair includes a series-connected string of devices connected between a bit line (BL 281) and a ground (Ground 282). Each series-connected string of multiple devices includes a plurality of source / drain non-volatile memory devices connected in series, for a total of 256 devices. Each non-volatile memory device has a corresponding control gate input connected to a corresponding word line. As shown in the specific example in the figure, MemStrPr 231 includes 256 non-volatile memory devices in the left-hand memory string of the memory string pair, and includes 256 non-volatile memory devices in the right-hand memory string of the memory string pair. For clarity, subsets of devices are explicitly shown.

[0134] The control gate inputs of the non-volatile memory devices of the left-hand memory string of MemStrPr 231 are connected to word lines WL1_1 to WL1_256, respectively.

[0135] Similarly, the control gate inputs of the nonvolatile memory devices of the right hand memory string of MemStrPr 231 are connected to word lines WL1_1' through WL1_256', respectively. Note that the prime "'" indicates the relationship of paired word lines, e.g., WL1_1 and WL1_1' are associated as corresponding memory devices coupled to the same in-memory search unit.

[0136] Note that character lines are identified by two integers, the number (CharacterNumber) and the layer (LayerNumber), and an optional trailing apostrophe:

[0137] WL<number>_<layer>[']. For example, WL1_8 corresponds to number 1 (e.g., the number of input search characters) and layer 8 (the layer of the 3D memory array 150). No trailing apostrophe indicates the left-hand memory string of the memory string pair. For another example, WL1_8' corresponds to number 1 and layer 8. The trailing apostrophe indicates the right-hand memory string of the memory string pair.

[0138] As described in more detail elsewhere herein, the non-volatile memory devices of the left-hand and right-hand memory strings are encoded according to a particular encoding technique (e.g. Figure 1The coding 140) is used in pairs to perform comparisons for search operations. An example of one of the plurality of paired non-volatile memory devices is shown as an in-memory search unit (IMS249). The gate of the left-hand non-volatile memory device of the pair is connected to a word line WL1_249, and the gate of the right-hand non-volatile memory device of the pair is connected to a word line WL1_249'.

[0139] Each series connected string of the plurality of devices additionally includes a string select device with source / drain connected in series to the plurality of non-volatile memory devices. The string select device has a gate input connected to a string select control input (e.g., string select line SSL_1 for the left hand memory string of MemStrPr 231 and string select line SSL_2 for the right hand memory string of MemStrPr 231). The paired string select lines (e.g., string select line SSL_1 and string select line SSL_2) of each memory string pair are operable as a pair (e.g., in response to a search operation) to simultaneously activate (deactivate) the left and right hand memory strings of the memory string pair.

[0140] Each series connected string of the plurality of devices additionally includes a ground select device with source / drain connected in series to the plurality of non-volatile memory devices. The ground select device has a gate input connected to a ground select control input (e.g., ground select line GSL_1 for the left hand memory string of MemStrPr 231 and ground select line GSL_2 for the right hand memory string of MemStrPr 231). The paired ground select lines (e.g., ground select line GSL_1 and ground select line GSL_2) of each memory string pair are operable as a pair (e.g., in response to a search operation) to simultaneously activate (deactivate) the left and right hand memory strings of the memory string pair.

[0141] Each series connected string of the plurality of devices additionally includes a universal selection device with source / drain connected in series to the plurality of non-volatile memory devices. The universal selection device has a gate input connected to a universal selection control input (e.g., universal selection line CSL_1 for the left hand memory string of MemStrPr 231 and universal selection line CSL_2 for the right hand memory string of MemStrPr 231). The paired universal selection lines (e.g., universal selection line GSL_1 and universal selection line GSL_2) of each memory string pair are operable as a pair (e.g., in response to a search operation) to simultaneously activate (deactivate) the left and right hand memory strings of the memory string pair.

[0142] Each element of the paired string select lines (e.g., string select line SSL_1 and string select line SSL_2) of each memory string pair may be operated individually (e.g., in response to other non-search operations such as erase and / or program operations). For example, string select line SSL_1 may be operated independently of string select line SSL_2 to enable programming of multiple devices in the left-hand memory string of MemStrPr 231. Similarly, each element of the paired ground select lines and universal select lines may be operated independently of and / or dependent upon the other elements of the pair.

[0143] The diagram shows 2D 199 having 256 memory string pairs, each having 256 non-volatile memory devices connected in series. Other examples have other numbers of memory string pairs and / or other numbers of non-volatile memory devices connected in series.

[0144] Figure 3 Select details of an example 3D memory array, such as 3D memory array 150 , are shown.

[0145] The diagram shows multiple representative examples of 2D memory arrays of the 3D memory array 150, specifically 2D 391, 2D 392, D 199, 2D 397, 2D 398, and 2D 399. The diagram also shows multiple representative interconnection points of multiple devices of the multiple 2D memory arrays. Specifically, all gates of multiple devices in a particular X, Y region of each 2D memory array are connected in parallel. The diagram shows multiple representative parallel connections of string select lines SSL_1, string select lines SSL_2, string select lines SSL_511, and string select lines SSL_512; pairs of word lines WL1_8 and word lines WL1_8', pairs of word lines WL256_8 and word lines WL256_8'; and universal select lines CSL_1, universal select lines CSL_2, universal select lines CSL_511, and universal select lines CSL_512.

[0146] Thus, in one example having a 128K 2D memory array, each string select line is connected to a 128K gate, each word line of each pair of word lines is connected to a 128k gate, etc. Other examples have other numbers of 2D memory arrays.

[0147] 3D memory search In-memory search unit

[0148] Figure 4An intra-memory search cell (IMS Cell 480) is shown in the context of a memory string pair connected to a bit line BL. A floating gate device (FG 483) (included in the left-hand memory string of the memory string pair) is connected to a word line (WL 481). A floating gate device (FG' 484) (included in the right-hand memory string of the memory string pair) is connected to the word line (WL' 481). FG 483 and FG' 484 are programmable, for example, by adjusting the threshold voltage by charging / discharging the floating gates included therein. Thus, FG 483 and FG' 484 can be collectively programmed to store a plurality of specific symbol reference levels.

[0149] For example, Figure 5A and Figure 5B and Fig.9A and Fig. 9B Two-level technology is shown. In other examples, Fig. 6A , Figure 6B and Figure 6C and Fig. 10A , Fig. 10B and Fig. 10C Eight-level technology is shown. In other examples, Fig. 7A and Figure 7B and Fig.11A and Fig. 11B P level technology is shown. In other examples, Figure 8 Shows analog level technique.

[0150] The two-level, eight-level, P-level and analog level technologies are based on the following Figure 1 The corresponding specific encoding implemented by the data encoder 160 and the search encoder 170 in.

[0151] 3D memory search large no match current

[0152] Figure 5A and Figure 5B An example of an encoding technique using two threshold levels and providing a high current indication of no match between search data and stored data is shown. This encoding technique is referred to as a two-threshold high current no match encoding technique. The diagram corresponds to Figure 4 The IMS Cell 480 is a two-threshold high current unmatched implementation.

[0153] Figure 5A Two threshold levels are shown, Memory State LVT 572 and Memory State HVT 573. The diagram also shows the generation of a voltage across FG 483 and FG′ 484 (at Figure 4 )'s large current indicating no match between the search input and the stored data, and the small current produced through FG 483 and FG' 484 indicating a match between the search input and the stored data.

[0154] Figure 5B The search data encoding and storage data encoding based on the two-threshold large current no-match encoding technology are shown.

[0155] Fig. 6A , Figure 6B and Figure 6C Also shown is an example of an encoding technique using eight threshold levels and providing a larger current indication of no match between the search data and the stored data. This encoding is referred to as an eight threshold larger current no match encoding technique. The diagram corresponds to Figure 4 The IMS Cell 480 has eight thresholds for larger current without matching implementation.

[0156] Fig. 6A Eight threshold levels are shown, such as Vt1 671 to Vt7 677 and Vt0 670, which also correspond to the encoding voltages V0 to V7. The diagram also shows the generation of the voltages through FG 483 and FG' 484 (at Figure 4 ) A relatively small current represents no match between the search input and the stored data, and a relatively large current through FG 483 and FG' 484 represents a match between the search input and the stored data.

[0157] Figure 6B The search data encoding and the storage data encoding according to the eight-threshold larger current no-match encoding technique are shown.

[0158] Figure 6C An example of the total current passing through FG 483 and FG' 484 together for multiple combinations of search input and stored data is shown. Darker colored boxes schematically represent smaller currents. For example, the comparison along the descending diagonal line between the search input and stored data results in the minimum total current, Ioff.

[0159] Fig. 7A and Figure 7B An example of a p-level encoding technique using a p-threshold level and providing a larger current indication of no match between the search data and the stored data is also shown. This encoding is referred to as a p-threshold larger current no match encoding technique. The diagram corresponds to Figure 4 The p-threshold larger current of the IMS Cell 480 is not matched. Correspondingly, this diagram corresponds to the p-level summarized in Fig. 6A , Figure 6B and Figure 6C Eight-level technology.

[0160] Fig. 7AThe p threshold levels Vt1 771 to Vtp 776 and the zero threshold level Vt0 770 are shown, also corresponding to the coded voltages V0, V1 to V(p-2), V(p-1), V(p) and V(p+1). The diagram also shows the generation of the voltages through FG 483 and FG' 484 (at Figure 4 ) indicating no match between the search input and the stored data, and producing a relatively large current through FG 483 and FG' 484 indicating a match between the search input and the stored data.

[0161] Figure 7B The search data encoding and the storage data encoding according to the p-threshold larger current no-match encoding technique are shown.

[0162] Figure 8 An example of an encoding technique using analog levels and providing a larger current indication of no match between search data and stored data is shown. This encoding is referred to as an analog larger current no match encoding technique. The figure corresponds to Figure 4 The IMS Cell 480 simulates larger currents without a matching implementation.

[0163] Current 810 represents the vertical direction for the source / drain current of the memory device plotted against the horizontal direction for the control gate voltage of the memory device. The two graphs show the current (Current 883) at Figure 4 The source-drain current of FG483, and the current (Current'884) at Figure 4 Corresponding to FG 483, Current 883 is the source-drain current affected by a voltage applied to the word line (WL 481) represented by word line (WL 881) in a range (e.g., 4 to 0 V). Similarly, corresponding to FG'484, Current'884 is the source-drain current affected by a voltage applied to the word line (WL'482) represented by word line (WL'882) in a range (e.g., 0 to 4 V).

[0164] The word line voltage has two regions, indicating no match between the search input and the stored data (the stored data as indicated by the adjusted threshold voltage). The first of the two regions, Mismatch 885, indicates that it is turned on, enabling a larger current. The second of the two regions, Mismatch 887, indicates that FG' 484 is turned on, enabling a larger current. The single middle region indicates a match between the search input and the stored data. The middle region, Match 886, indicates that FG 483 and FG' 484 are turned off, resulting in a smaller current.

[0165] Thus, WL+WL' 888 represents the combination of voltages on WL 481 and WL' 482 which produce a smaller current from IMS Cell 480, indicating a match between the search input and the stored data. WL+WL' 889 represents the combination of voltages on WL 481 and WL' 482 which produce a larger current from IMS Cell 480, indicating no match between the search input and the stored data.

[0166] FG 483 is shown as having an adjustable threshold voltage in a range, represented by Tunable Vt 878. Similarly, FG' 484 is shown as having an adjustable threshold voltage in a range, represented by Tunable Vt 879. The adjustable threshold voltage enables adjustment of the width of Mismatch 885, Match 886, and Mismatch 887.

[0167] 3D memory search small no match current

[0168] Fig.9A and Fig. 9B An example of an encoding technique using two threshold levels and providing a small current indication of no match between search data and stored data is shown. This encoding technique is called a two-threshold small current no-match encoding technique. The figure corresponds to Figure 4 The IMS Cell 480 has a two-threshold small current unmatched implementation.

[0169] Fig.9A Two threshold levels are shown, Memory State LVT 972 and Memory State HVT 973. The diagram also shows the generation of a voltage across FG 483 and FG′ 484 (at Figure 4 ) indicating no match between the search input and the stored data, and producing a large current through FG 483 and FG' 484 indicating a match between the search input and the stored data.

[0170] Fig. 9B The search data encoding and storage data encoding based on the two-threshold small current no-match encoding technology are shown.

[0171] Fig. 10A , Fig. 10B and Fig. 10C An example of an encoding technique using eight threshold levels and providing a small current indication of no match between the search data and the stored data is also shown. This encoding is referred to as an eight-threshold small current no match encoding technique. The figure corresponds to Figure 4 The IMS Cell 480 is an eight-threshold small current unmatched implementation.

[0172] Fig. 10AEight threshold levels are shown, such as Vt 0 1070 to Vt 7 1077, which also correspond to the encoding voltages V0 to V7. The figure also shows the generation of the voltage across FG 483 and FG' 484 (at Figure 4 ) A relatively small current represents no match between the search input and the stored data, and a relatively large current through FG 483 and FG' 484 represents a match between the search input and the stored data.

[0173] Fig. 10B The search data encoding and the storage data encoding according to the eight-threshold smaller current no-match encoding technique are shown.

[0174] Fig. 10C An example of the total current passing through FG 483 and FG' 484 together for multiple combinations of search input and stored data is shown. Darker colored boxes schematically represent larger currents. For example, the comparison along the descending diagonal line between the search input and stored data results in the maximum total current, I7.

[0175] Fig.11A and Fig. 11B An example of a p-level encoding technique using a p-threshold level and providing a small current indication of no match between the search data and the stored data is also shown. This encoding is referred to as a p-threshold small current no match encoding technique. The diagram corresponds to Figure 4 The p-threshold of the IMS Cell 480 is smaller than the current without matching implementation. Correspondingly, this diagram corresponds to the p-level summarized in Fig. 10A , Fig. 10B and Fig. 10C Eight-level technology.

[0176] Fig.11A The p threshold levels are shown as Vt1 1171 to Vtp 1176 and the zero threshold level is shown as Vt0 1170, also corresponding to the encoding voltages V0 to Vp. The figure also shows the generation of the voltages through FG 483 and FG' 484 (at Figure 4 ) indicating no match between the search input and the stored data, and producing a relatively large current through FG 483 and FG' 484 indicating a match between the search input and the stored data.

[0177] Fig. 11B The search data encoding and the storage data encoding according to the p-threshold smaller current no-match encoding technique are shown.

[0178] 3D memory search multiple layers

[0179] Fig. 12A , Fig. 12B and Fig. 12C shows a multi-layer search operation, such as using a connection to Figure 2 BL 281, MemStrPr 238.

[0180] Fig. 12A MemStrPr 238 and BL 281 are shown to be used to perform a two-layer search. The searched data is encoded according to a specific encoding technique and stored in IMS cell1-1 1201 and IMS cell1-2 1202. The search condition includes an indication of the search depth of the two layers and an indication of the search start point of the first layer. The search condition also includes an indication of the search depth of the two layers according to a specific encoding (e.g., by Figure 1 The encoded search value is applied to MemStrPr 238 via two word lines, one for each left-hand and right-hand memory string. The encoded search value applied to the word line of the left-hand memory string is represented by Vsearch[2:1] 1221. The encoded search value applied to the word line of the right-hand memory string is represented by Vsearch'[2:1] 1222. The remaining word lines are driven with a voltage that enables current to pass through the left-hand and right-hand memory strings. The enable voltages are represented in the figure by Vpass 1211 and Vpass' 1212.

[0181] Fig. 12B MemStrPr 238 and BL 281 are shown to be used to perform an eight-level search. The searched data is encoded according to a specific encoding technique and stored in a memory device acted upon by Vsearch[8:1] 1223 and Vsearch'[8:1] 1224. The search condition includes an indication of a search depth of eight levels and an indication of a search start point for the first level. The search condition also includes an indication of a search depth of eight levels (e.g., by a specific encoding technique). Figure 1 The encoded search values ​​are applied to MemStrPr 238 via eight word lines, one each for the left-hand and right-hand memory strings. The encoded search values ​​applied to the word lines of the left-hand memory string are represented by Vsearch[8:1] 1223. The encoded search values ​​applied to the word lines of the right-hand memory string are represented by Vsearch'[8:1] 1224. The remaining word lines are driven with a voltage that enables current to pass through the left-hand and right-hand memory strings. The enable voltages are represented in the figure by Vpass 1213 and Vpass' 1214.

[0182] Fig. 12CMemStrPr 238 and BL 281 are shown to be used to perform a search of all layers (e.g., 256 layers). The data to be searched is encoded according to a specific encoding technique and is stored in all memory devices of MemStrPr 238. The search condition includes an indication of the search depth of 256 layers and an indication of the search start point of the first layer. The search condition also includes an indication of the search depth of 256 layers according to a specific encoding (e.g., by Figure 1 The encoded search values ​​are applied to MemStrPr 238 via 256 word lines for the left and right memory strings, respectively. The encoded search values ​​applied to the word lines of the left memory string are represented by Vsearch[256:1] 1225. The encoded search values ​​applied to the word lines of the right memory string are represented by Vsearch'[256:1] 1226.

[0183] The search depth indicates any number of layers from one to all layers (eg, 1, 2, 3, 4, 96, 192, 232, 256, and so on), respectively. The search start point indicates any number from the first layer to the last layer, respectively.

[0184] 3D memory search two layers / large no match current

[0185] Fig.13A , Fig. 13B and Fig. 13C Multiple two-level search operations according to the two-threshold large current no-match encoding technique are shown. Each diagram represents a binary (two-bit) search for "10" where the most significant bit (MSB) of the search data is "1" and the second most significant bit (MSB-1) of the search data is "0". The diagrams are different in the stored data.

[0186] Fig.13A The operation is shown to produce a perfect match at the stored value "10" and thus at the search value "10". In response to the match, the pair current (Pair Current 1382) is a small value, thus outputting a small current to the bit line (BL 1381).

[0187] Fig. 13B The operation is shown to produce a partial match on the stored value "11" and thus the search value "10", where the most significant bit matches and the second most significant bit does not match. In response to the partial match, the pair current (Pair Current 1384) is an intermediate value between the small value and the large value, thereby outputting an intermediate current to the bit line (BL 1383).

[0188] Fig. 13CThe operation is shown to produce no match at the stored value "01" and thus at the search value "10". In response to the complete no match, the pair current (Pair Current 1386) is large, thus outputting a large value current to the bit line (BL 1385).

[0189] 3D memory search two layers / small no match current

[0190] Fig.14A , Fig. 14B and Fig. 14C FIG. 1 shows multiple two-layer search operations based on a two-threshold small current no-match encoding technique. Fig.13A , Fig. 13B and Fig. 13C In the figure, each pattern represents a binary (two-bit) search for "10", and the patterns are different in the stored data.

[0191] Fig.14A The operation is shown to produce a perfect match at the stored value "10" and thus at the search value "10". In response to the match, the pair current (Pair Current 1482) is large, thus outputting a large value current to the bit line (BL 1481).

[0192] Fig. 14B The operation is shown to produce a partial match on the stored value "11" and thus the search value "10", where the most significant bit matches and the second most significant bit does not match. In response to the partial match, the pair current (Pair Current 1484) is an intermediate value between the small value and the large value, thus outputting an intermediate current to the bit line (BL 1483).

[0193] Fig. 14C The operation is shown to produce no match at the stored value "01" and thus at the search value "10". In response to a complete no match, the pair current (Pair Current 1486) is small, thus outputting a small value current to the bit line (BL 1485).

[0194] Fig.15A , Fig. 15B and Fig. 15C Schematic diagrams showing multiple two-level search operations according to the eight-threshold small current no-match encoding technique. Each diagram represents an octal search for "25", where the most significant bit (MSB) of the search data is "2", and the second most significant bit (MSB-1) of the search data is "5". The diagrams are different in the stored data.

[0195] Fig.15AThe operation is shown storing an octal value of "25" and thus generating a perfect match in the search for an octal value of "10". In response to the match, the pair current (Pair Current 1582) is large, thus outputting a large value current to the bit line (BL1581).

[0196] Fig. 15B The operation is shown storing an octal value of "25" and thus generating a partial match in searching for an octal value of "35", where the most significant bit matches and the second most significant bit does not match. In response to the partial match, the paired current (PairCurrent 1584) is an intermediate value between the small value and the large value, thus outputting an intermediate current to the bit line (BL 1583).

[0197] Fig. 15C The operation is shown storing an octal value of "25" and thus generating a no match when searching for an octal value of "47". In response to a complete no match, the pair current (Pair Current 1586) is small, thus outputting a small value current to the bit line (BL 1585).

[0198] Fig.15D and Fig.15E A matching example and a non-matching example according to the eight-threshold small current non-matching encoding technology are shown respectively.

[0199] Fig.15D A matching example is shown. The first memory device from the left-hand memory string of the memory string pair and the second memory device from the right-hand memory string of the memory string pair are programmed as a whole to store an octal value of "2". In response to the matching search input of the octal value "2", "8 times" of overdrive are generated in each of the first memory device and the second memory device. Vt 5 and V5 are the programmed threshold of the first memory device and the word line voltage applied to the control gate of the first memory, respectively. Vt 2 and V2 are the programmed threshold of the second memory device and the word line voltage applied to the control gate of the second memory, respectively. Overdrive is conceptually represented as 8 Overdrive (8OD 1511) and 8OverDrive (8OD 1512) in the figure.

[0200] Fig.15EA no-match example is shown. The first memory device from the left-hand memory string of the memory string pair and the second memory device from the right-hand memory string of the memory string pair are programmed as a whole to store an octal value of "4". In response to the match search input of the octal value "2", a "10" overdrive is generated in the first memory device and a "5" overdrive is generated in the second memory device. Vt 3 and V5 are the programmed threshold of the first memory device and the word line voltage applied to the control gate of the first memory, respectively. Vt 5 and V2 are the programmed threshold of the second memory device and the word line voltage applied to the control gate of the second memory, respectively. The overdrive is conceptually represented as 10 overdrive 10OverDrive (10OD 1513) and 5OverDrive (5OD 1514) in the figure.

[0201] In an example implementation of multiple memory devices, the multiple currents for the "8 times" overdrive through the "10 times" overdrive are nearly the same as the multiple memory devices operate in the saturation region. Therefore, the current is low from either of the two memory devices.

[0202] 3D memory search multiple layers / multiple string search lines

[0203] Fig.16A , Fig. 16B and Fig. 16C Various search operations according to any of the high current no-match coding techniques are shown. Each diagram shows a search at a search depth of 1 (searching one layer). The diagrams differ according to the search starting point (starting the search at one of the layers). Figure 1 The contents of 2D 199 are shown in Figure 2 The memory string pair MemStrPr 231 and MemStrPr 239 connected to the bit line BL 281. For clarity, the figure shows only two memory string pairs, but this description is also applicable to other numbers of memory string pairs.

[0204] Fig.16A The operation at search start point 1 (starting the search at the first layer and the search depth is 1, and then only searching the first layer) is shown. The searched data is encoded according to a specific encoding technique and stored in IMS cell 1-1 1601 and IMS cell 256-1 1609. The search condition includes a search depth indicating a layer and a search start point indicating the first layer. The search condition also includes a search condition according to a specific encoding (e.g., by Figure 11621). A portion of the encoded search value is applied to MemStrPr 231 via a word line for each of the left and right memory strings, represented as Vsearch+Vsearch' 1621. Another portion of the encoded search value is applied to MemStrPr 239 via a word line for each of the left and right memory strings, represented as Vsearch+Vsearch' 1622. The remaining word lines of the left and right memory strings of MemStrPr 231 and MemStrPr 239 are driven with a voltage to enable current to pass through the left and right memory strings. The enable voltage is represented in the figure by Vpass+Vpass' 1611.

[0205] Fig. 16B The operation is shown at search start 2 (starting the search at the second layer, with a search depth of 1, and then searching only the second layer). The operation is similar to Fig.16A Specifically, a portion of the encoded search value is applied to MemStrPr 231 via a word line for each of the left and right hand memory strings, represented as Vsearch+Vsearch' 1623. Another portion of the encoded search value is applied to MemStrPr 239 via a word line for each of the left and right hand memory strings, represented as Vsearch+Vsearch' 1624. The remaining word lines of the left and right hand memory strings of MemStrPr 231 and MemStrPr 239 are driven with a voltage to enable current to pass through the left and right hand memory strings. The enable voltages are represented in the figure by Vpass+Vpass' 1612 and Vpass+Vpass' 1613.

[0206] Fig. 16C The operation is shown at the search start point 7 (starting the search at the seventh layer, and the search depth is 1, and then only searching the seventh layer). The operation is similar to Fig.16ASpecifically, a portion of the encoded search value is applied to MemStrPr 231 via a word line for each of the left and right hand memory strings, represented as Vsearch+Vsearch' 1625. Another portion of the encoded search value is applied to MemStrPr 239 via a word line for each of the left and right hand memory strings, represented as Vsearch+Vsearch' 1626. The remaining word lines of the left and right hand memory strings of MemStrPr 231 and MemStrPr 239 are driven with a voltage to enable current to pass through the left and right hand memory strings. The enable voltages are represented in the figure by Vpass+Vpass' 1614 and Vpass+Vpass' 1615.

[0207] Fig.17A , Fig. 17B and Fig. 17C Shows various search operations based on any high current no-match encoding technique, similar to Fig.16A , Fig. 16B and Fig. 16C However, it is not shown at search depth 1 (as in Fig.16A , Fig. 16B and Fig. 16C Search for Fig.17A , Fig. 17B and Fig. 17C Each diagram shows a search at a search depth of 2 (searching two layers). The diagrams differ according to the search starting point (starting the search at one of the layers). Fig.16A , Fig. 16B and Fig. 16C middle, Fig.17A , Fig. 17B and Fig. 17C For Figure 1 The contents of 2D199 are shown in Figure 2 The memory string pair MemStrPr 231 and MemStrPr 239 connected to the bit line BL 281. For clarity, the figure shows only two memory string pairs, but this description is also applicable to other numbers of memory string pairs.

[0208] Fig.17A The operation at search start point 1 (starting the search at the first layer) is shown. The searched data is encoded according to a specific encoding technique and stored in IMS cell 1-1 1701, IMS cell 1-2 1702, IMS cell 256-1 1708, and IMS cell 256-2 1709. The search condition includes an indication of the search depth of the two layers and an indication of the search start point of the first layer. The search condition also includes an indication of the search depth of the two layers according to a specific encoding technique (e.g., by Figure 1170) is an encoded search value. A portion of the encoded search value is applied to MemStrPr 231 via two word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch+Vsearch' 1721. Another portion of the encoded search value is applied to MemStrPr 239 via two word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch+Vsearch' 1722. The remaining word lines are driven with a voltage that enables current to pass through the left-hand and right-hand memory strings. The enable voltage is represented in the figure by Vpass+Vpass' 1711.

[0209] Fig. 17B The operation is shown at search start 3 (starting the search at the third layer). The operation is similar to Fig.17A Specifically, a portion of the encoded search value is applied to MemStrPr 231 via two word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[2:1]+Vsearch'[2:1] 1723. Another portion of the encoded search value is applied to MemStrPr 239 via two word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[2:1]+Vsearch'[2:1] 1724. The remaining word lines are driven with a voltage that enables current to flow through the left-hand and right-hand memory strings. The enable voltages are represented in the diagram by Vpass+Vpass' 1712 and Vpass+Vpass' 1713.

[0210] Fig. 17C The operation is shown at the search start point 249 (starting the search at the 249th level). The operation is similar to Fig.17A Specifically, a portion of the encoded search value is applied to MemStrPr 231 via two word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[2:1]+Vsearch'[2:1] 1725. Another portion of the encoded search value is applied to MemStrPr 239 via two word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[2:1]+Vsearch'[2:1] 1726. The remaining word lines are driven with a voltage that enables current to flow through the left-hand and right-hand memory strings. The enable voltages are represented in the figure by Vpass+Vpass' 1714 and Vpass+Vpass' 1715.

[0211] Figure 1The search encoder 170 is enabled to selectively activate the string selection line SSL (eg, any one or more of the string selection line SSL_1, the string selection line SSL_2 to the string selection line SSL_511, and the string selection line SSL_512) as shown in FIG. Figure 2 The string select line 171 of the MemStrPr 231 is indicated according to the search range portion of the search 120. The selective activation of the string select line SSL enables adjustment of the search word, which is provided as the search value of the search condition. The adjustment can be used to mask one or more portions of the search word. For example, all search words except one bit are masked by activating two string select lines SSL (e.g., string select line SSL_1 and string select line SSL_2 of MemStrPr 231). In another example, no search word is masked by activating all string select lines SSL (e.g., all words / numbers / bits of the search word are used for the search). In another example, any one or more portions of the search word are maskable by not activating the corresponding range of string select lines SSL. Any number of string select lines SSL can be activated (e.g., 2, 4, 6, 512, 1024, 2048 or more) according to different usage scenarios.

[0212] Fig.18A and Fig.18B Shows various search operations based on any high current no-match encoding technique, similar to Fig.16A , Fig. 16B and Fig. 16C However, it is not shown at search depth 1 (as in Fig.16A , Fig. 16B and Fig. 16C Search for Fig.18A and Fig.18B Each diagram shows a search at a search depth of 6 (searching six layers). The diagrams differ according to the search starting point (starting the search at one of the layers). Fig.16A , Fig. 16B and Fig. 16C middle, Fig.18A and Fig.18B For Figure 1 The contents of 2D 199 are shown in Figure 2 The memory string pair MemStrPr 231 and MemStrPr 239 connected to the bit line BL 281. For clarity, the figure shows only two memory string pairs, but this description is also applicable to other numbers of memory string pairs.

[0213] Fig.18AThe operation at search start point 1 (starting the search at the first layer) is shown. The searched data is encoded according to a specific encoding technique and stored in a memory device acted upon by Vsearch[5:1]+Vsearch'[5:1] 1821 and Vsearch[5:1]+Vsearch'[5:1] 1822. The search condition includes an indication of a search depth of six layers and an indication of a search start point of the first layer. The search condition also includes an indication of a search depth of six layers (e.g., by Figure 1 1 ) is encoded search value. A portion of the encoded search value is applied to MemStrPr 231 via six word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[5:1]+Vsearch'[5:1]1821. Another portion of the encoded search value is applied to MemStrPr 239 via six word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[5:1]+Vsearch'[5:1]1822. The remaining word lines are driven with a voltage that enables current to pass through the left-hand and right-hand memory strings. The enable voltage is represented in the figure by Vpass+Vpass'1811.

[0214] Fig.18B The operation is shown at the search start point 251 (searching at the 251st layer). The searched data is encoded according to a specific encoding technique and stored in the memory device via Vsearch[5:1]+Vsearch'[5:1] 1823 and Vsearch[5:1]+Vsearch'[5:1] 1824. The operation is similar except that the encoded information is provided to the 251st layer instead of the first layer. Fig.18A . Thus, the last six layers are searched instead of the first six layers. Specifically, a portion of the encoded search value is applied to MemStrPr 231 via six word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[5:1]+Vsearch'[5:1]1823. Another portion of the encoded search value is applied to MemStrPr 239 via six word lines, one each for the left-hand and right-hand memory strings, represented as Vsearch[5:1]+Vsearch'[5:1]1824. The remaining word lines are driven with a voltage that enables current to pass through the left-hand and right-hand memory strings. The enable voltage is represented in the figure by Vsearch[5:1]+Vsearch'[5:1]1823.

[0215] Fig. 18CVarious search operations are shown according to any high current no-match encoding technique. The searched data is encoded according to a particular encoding technique and stored in all memory devices of MemStrPr 231 and MemStrPr 239. Operations are similar to Fig.18A However, it is not shown at search depth 6 (as in Fig.18A Search for Fig. 18C The search is shown at a search depth of 256 (searching two hundred and fifty-six layers), which in this example corresponds to all layers. Fig.18A middle, Fig. 18C For Figure 1 The contents of 2D199 are shown in Figure 2 The memory string pair MemStrPr 231 and MemStrPr 239 connected to the bit line BL 281. For clarity, the figure shows only two memory string pairs, but this description is also applicable to other numbers of memory string pairs.

[0216] 3D memory search full plane / chip

[0217] Fig.19 A whole-plane or whole-chip search operation is shown. Figure 1 The contents of the 3D memory array 150 are shown in FIG. 2D memory arrays are shown as 2D memory arrays (2D 1901), 2D 1902, and 2D 1903.

[0218] Before searching, the data to be searched (e.g., to be compared) is encoded by a data encoder (in Fig.19 (not shown) is encoded, for example Figure 1 The data encoder 160 in the embodiment encodes the data 110. For example, the specific encoding technique is based on the reference Figure 4 , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 8 , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B Any encoding technique shown and described in any of the.

[0219] The search conditions include a search value, a search depth, a search start point, and a search range. The search conditions are indicated by Search In 1910 which is then provided to WL+WL'1970. Search In 1910 represents Figure 1 Search 120. WL+WL'1970 is Figure 1 The operation of the search encoder 170 is represented with emphasis on generating word lines for left and right memory strings of a corresponding memory string pair, specifically within a single layer.

[0220] Search In 1910 includes a search value, and according to the example shown, the search value is a 256-word (e.g., 256-bit) search word. WL+WL' 1970 encodes the search word according to a specific encoding and provides the encoding result to drive word lines WL1_1, word lines WL1_1' to word lines WL256_1 and word lines WL256_1', thereby enabling a first level search.

[0221] Search In 1910 further includes a search depth and a search starting point, which are generally indicated as one level deep and starting at the first level. Thus, the first level of word lines (word line WL1_1, word line WL1_1' to word line WL256_1 and word line WL256_1') are driven according to a specific code, enabling a plurality of memory devices in the first level to participate in the search. The remaining word lines of the left-hand and right-hand memory strings are driven with a voltage that enables current from the enabled plurality of memory devices to pass through corresponding bit lines of the 2D memory array. The enable voltages are represented in the diagram by Vpass+Vpass' 1911, Vpass+Vpass' 1912, and Vpass+Vpass' 1913.

[0222] Search In 1910 further includes a search scope, indicating which of the 2D memory arrays are enabled to participate in the search. The search scope enables the activation of all or part of the 2D memory array selected by the selected enabled string select lines SSL (e.g., string select lines SSL_1 to string select lines SSL_512). For example, enabling all string select lines SSL enables searching the entire 3D memory array 150. Therefore, in an embodiment having a 128K 2D memory array, a single search operation enables a comparison of 128 length values ​​at a time.

[0223] like Figure 1 As shown in the middle line 180, each 2D memory array has a plurality of 2D memory arrays coupled to the same Figure 1The page buffer 130 is enabled (e.g., by a sense amplifier, a comparator, a priority encoder, and the like) to detect the match current to determine whether zero or more stored data values ​​match as compared to the search value according to the search depth, the search start point, and the search range.

[0224] In various embodiments, the stored data and stored values ​​are based on two-level values ​​(e.g., referring to Figure 5A and Figure 5B and Fig.9A and Fig. 9B any of the shown and described), eight level values ​​(for example, refer to Fig. 6A and Figure 6B and Fig. 10A and Fig. 10B any of the shown and described), p level value (for example, refer to Fig. 7A and Figure 7B and Fig.11A and Fig. 11B Any of the shown and described) and simulated values ​​(for example, referring to Figure 8 shown and described).

[0225] Fig. 20 The full chip search operation is shown in Figure 1 The contents of the 3D memory array 150 are shown in FIG. 2D 2001, 2D 2002, and 2D 2003.

[0226] The search operation is similar to Fig.19 , and the following description focuses on Fig.19 The difference between Fig.19 In , the search depth is 1, so WL+WL' starts a single layer to search. Fig. 20 In , the search depth is 2, so WL+WL'2070 starts two layers to search.

[0227] As in Fig.19 In the embodiment, before searching, data is stored by a data encoder (not shown).

[0228] Further as Fig.19 In the WL+WL'2070, the search condition includes a search value, a search depth, a search start point, and a search range. The search condition is indicated by Search In 2010 which is then provided to WL+WL'2070. Search In 2010 represents Figure 1 Search 120. WL+WL'2070 is Figure 1 The operation of the search encoder 170 is represented with emphasis on generating word lines for the left and right memory strings of a corresponding memory string pair, specifically in two layers.

[0229] As in Fig.19 In the search condition, 256 words (eg, 256 digits) of search characters are search values ​​included in the search condition.

[0230] Search In 2010 includes a search value, and according to the example shown, the search value is a 256-word (eg, 256-bit number) search character.

[0231] WL+WL' 2070 encodes the search word according to a specific code and provides the encoding result to drive word lines WL1_1, WL1_1' to WL256_1 and WL256_1' and WL1_2, WL1_2' to WL256_2 and WL256_2', thereby enabling the first and second level searches.

[0232] Search In 2010 further includes a search depth and a search starting point, which are generally indicated as two levels deep and starting at the first level. Therefore, the first level of word lines (word line WL1_1, word line WL1_1' to word line WL256_1 and word line WL256_1') and the second level of word lines (word line WL1_2, word line WL1_2' to word line WL256_2 and word line WL256_2') are driven according to a specific code, enabling multiple memory devices in the first and second levels to participate in the search. The remaining word lines of the left-hand and right-hand memory strings are driven with a voltage that enables current from the enabled multiple memory devices to pass through corresponding bit lines of the 2D memory array. The enable voltages are represented in the figure by Vpass+Vpass'2011, Vpass+Vpass'2012 and Vpass+Vpass'2013.

[0233] Search In 2010 further includes a search range, and in this context, the entire 2D memory array is activated by activating all string selection lines SSL (eg, string selection lines SSL_1 to SSL_512 ).

[0234] As in Fig.19 middle, Fig. 20 A plurality of 2D memory arrays having a plurality of 2D memory arrays coupled to Figure 1 The plurality of bit lines of the page buffer 130 are detected to determine whether zero or more stored data values ​​match the search value as compared with the search value according to the search depth, the search starting point and the search range.

[0235] Likewise as Fig.19 In Fig. 20 In multiple implementations, the stored data and stored values ​​are based on two-level values, eight-level values, p-level values ​​and analog values.

[0236] Fig.21 The full chip search operation is shown in Figure 1The contents of the 3D memory array 150 are shown in FIG. 2D 2101, 2D 2102, and 2D 2103.

[0237] The search operation is similar to Fig.19 and Fig. 20 However, instead of looking for one or two layers, Fig.21 All layers of the 3D memory array 150 are shown being searched.

[0238] The search depth of the search condition indicates all layers. Therefore, there is no Vass Fig.19 and Fig. 20 Alternatively, WL+WL' 2170 encodes the search word from Search In 2110 according to a specific encoding and provides the encoding result to drive word line WL1_1, word line WL1_1' to word line WL256_1 and word line WL256_1' and WL1_256, word line WL1_256' to word line WL256_256 and word line WL256_256', thereby enabling searching of all layers of the 3D memory array 150. The encoding result provided at each layer is the same, as conceptually copied from Search In 2110 to WL+WL' 2170.

[0239] The search range indicates the whole chip, so WL+WL' 2170 enables activating the entire 2D memory array by activating all string selection lines SSL (eg, string selection lines SSL_1 to SSL_512 ).

[0240] As in Fig.19 and Fig. 20 middle, Fig.21 A plurality of 2D memory arrays having a plurality of 2D memory arrays coupled to Figure 1 The plurality of bit lines of the page buffer 130 are detected to determine whether zero or more stored data values ​​match the search value as compared with the search value according to the search depth, the search starting point and the search range.

[0241] Likewise as Fig.19 and Fig. 20 In Fig.21 In multiple implementations, the stored data and stored values ​​are based on two-level values, eight-level values, p-level values ​​and analog values.

[0242] Other use cases enable any number of layers to be enabled, so the search depth can vary from one to however many layers are present. Further, the search start point can vary from one to however many layers are present to indicate starting from the first to the last layer in any of the layers. In some implementations, multiple search depths and / or search start point indicators enable searching multiple non-contiguous layers of the 3D memory array 150.

[0243] 3D Memory Search Operation

[0244] Fig. 22 A method for searching a memory for 3D (eg Figure 1 An example operation flow chart of a 3D search memory 100) is shown as operation flow 2200.

[0245] The flow begins at select a particular encoding technique step 2201. A particular encoding technique is used for programming data and searching.

[0246] The process then proceeds to step 2202 of programming data according to the selected encoding technique. Figure 1 The data encoder 160 receives the data 110, encodes it according to a specific encoding technique, and provides the encoded data 111 to the 3D memory array 150 for programming, such as storage data to be used for search and comparison.

[0247] The flow proceeds to encoding the search according to the selected encoding technique step 2203. Continuing with the example, the search encoder 170 receives the search 120, encodes its search value according to the specific encoding technique, and provides the word line 172 (word line WL, word line WL') to the 3D memory array 150 for searching. The search 120 optionally includes one or more of a search depth, a search start point, and a search range. If provided, the search encoder 170 uses the search start point to determine the search value of one layer with reference to the word line 172 (word line WL, word line WL'). If provided, the search encoder 170 uses the search depth and / or search start point to ignore the threshold voltage and enable the current through the voltage in the memory string to "override" all or any portion of the word line 172 (word line WL, word line WL'). If provided, the search encoder 170 uses the search range to determine one of the activations of the string select lines SSL, such as provided on the string select line 171 to the 3D memory array 150.

[0248] The process then proceeds to drive string select lines and word lines step 2204. Continuing with the example, circuits in the search encoder 170 and / or the 3D memory array 150 drive the information provided via the string select lines 171 and word lines 172 (word lines WL, word lines WL') to the string select lines and word lines of the 2D memory array of the 3D memory array 150, respectively.

[0249] The flow then proceeds to sense bit lines step 2205. Continuing with the example, circuitry (e.g., one or more sense amplifiers and / or comparators) in the 3D memory array 150 and / or the page buffer 130 senses the bit lines in response to driving the string select lines and word lines, and the subsequent currents affected by the memory devices on the bit lines.

[0250] The flow then proceeds to the priority encode sensing result step 2206. Continuing with the example, one or more priority encoders in the page buffer 130 determine from the bit line sensing result that zero or more stored data values ​​match as compared to the search value according to the search depth, search start point and search range.

[0251] Flow then proceeds to Provide Results Step 2207. The results are provided, for example, to a host agent. Flow then optionally loops back to the previous steps to encode the next search (Encode Search Step 2203 according to the selected encoding technique).

[0252] 3D Memory Search Additional Information

[0253] Example memory technologies applicable to memory arrays of non-volatile 3D memory search architectures as described herein include floating gate, split gate, SONOS, floating dot memory, DRAM, DRAM-like (e.g., 2TOC), FeFET, and any memory technology compatible with searching through word lines and bit lines. Example SONOS memory technology (sometimes referred to as charge capture memory) uses an insulating layer (e.g., silicon nitride) with traps to capture and retain charge ejected from a channel. Example floating point memory technology conceptually replaces the floating gate with floating silicon nanodots, or embedded floating silicon nanodots, in a polysilicon gate. Example 2TOC memory technology uses parasitic capacitance of a read transistor to store charge, rather than using an explicit storage capacitor. Example FeFET memory technology uses permanent electric field polarization of a ferroelectric material embedded between a gate and a source-gate conduction region to store information. Example memory structures applicable to memory arrays of non-volatile 3D memory search architectures include two-dimensional structures (e.g., 2D flash memory structures) and three-dimensional structures (e.g., 3D flash memory structures). Example array architectures of memory arrays that may be used in the non-volatile 3D memory search architecture include NOR / OR type array architectures and AND / NAND type array architectures.

[0254] It is to be understood that although the present invention has been disclosed above in terms of implementations, variations, embodiments and examples, they are not intended to limit the present invention. A person skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached claims.

Claims

1. A computing system, comprising: a bit line and a source line; a paired memory string, comprising a first memory string and a second memory string connected in parallel between the bit line and the source line, wherein the first memory string comprises at least one selection device responsive to a selection input, and the at least one selection device is connected in series to a plurality of programmable devices connected in series, each of the programmable devices being responsive to a corresponding programmed state and a corresponding control input, and wherein the second memory string is identical to the first memory string; a sense amplifier connected to the bit line and enabled to provide an indication of one of a plurality of match indications; a data encoding circuit, responsive to at least one data input and according to a selection code, enabled to provide programming data to the programmable devices of the first memory string and the second memory string; as well as searching the data encoding circuit, enabled to (i) drive the select inputs of the first memory string and the second memory string in response to a search range of a search condition, and enabled to (ii) drive the control input in response to a search value of the search condition according to the select code, wherein the paired memory string is enabled to couple to the bit line and the source line through a corresponding one of a plurality of string pair currents in response to the selection input, the control input and the programmed state of the first memory string and the second memory string, The string pair currents include a precise matching current and an unmatched current, and The match indications include an exact match indicated in response to the exact match current and a no match indicated in response to the no match current. 2 . The computing system of claim 1 , wherein the string pair currents further include at least a portion of a matching current, and the matching indications include at least a portion of a matching indicated in response to the at least a portion of the matching current.

3. An operating system according to claim 1, wherein these programmable devices connected in series are configured in multiple layers, and the data encoding circuit is further enabled to drive the selection input of the first memory string and the second memory string in response to a search depth of the search condition, and the search depth indicates the number of these layers to be searched.

4. The operating system according to claim 3, wherein the data encoding circuit is further enabled to drive the selection inputs of the first memory string and the second memory string in response to a search starting point of the search condition, and the search starting point indicates starting the search from one of the layers.

5. The operating system of claim 1, further comprising a page buffer comprising a plurality of sense amplifiers, one of the sense amplifiers being the sense amplifier, and wherein the page buffer further comprises a priority encoder enabled to preferentially encode a plurality of matching results of the sense amplifiers. The computing system as claimed in claim 1 , wherein the precise matching current is greater than the unmatched current. 7 . The computing system as claimed in claim 1 , wherein the precise matching current is smaller than the unmatched current.

8. The computing system of claim 1 , wherein each of the programmable devices connected in series is programmed by adjusting a corresponding threshold voltage to one of at least two threshold levels, the selection code respectively indicating how to encode a binary logic 0 and a binary logic 1 to corresponding two of the at least two threshold levels, and the at least two threshold levels are distinguishable from each other.

9. The computing system of claim 1 , wherein each of the programmable devices connected in series is programmed by adjusting a corresponding threshold voltage to one of at least eight threshold levels, the selection code respectively indicating how to encode an octal logic 0, an octal logic 1, an octal logic 2, an octal logic 3, an octal logic 4, an octal logic 5, an octal logic 6, and an octal logic 7 to corresponding eight of the at least eight threshold levels, and the at least eight threshold levels are distinguishable from each other.

10. The operating system of claim 1, wherein each of the programmable devices connected in series is programmed by adjusting a corresponding threshold voltage to one of a plurality of analog threshold levels, the selection code respectively indicating how to encode a corresponding plurality of analog data values ​​to corresponding ones of the analog threshold levels, and the analog threshold levels are distinguishable from each other.

11. The computing system according to claim 1 , further comprising a plurality of memory string pairs, identical to the paired memory strings, and connected in parallel between the bit line and the source line, and wherein, In response to the at least one data input and based on the selection code, the data encoding circuit is further enabled to provide additional programming data (1) to the programmable devices of the first memory string of the memory string pairs, and (2) to the programmable devices of the second memory string of the memory string pairs. 12 . The computing system of claim 11 , further comprising a plurality of 2D memory arrays, a first one of the 2D memory arrays comprising the memory string pairs and the paired memory strings.

13. The operating system according to claim 12, further comprising a plurality of sense amplifiers having the sense amplifier, wherein: Each of the bit lines of the 2D memory arrays is connected to a corresponding one of the sense amplifiers. 14 . The operating system of claim 13 , further comprising a page buffer, the page buffer comprising a priority encoder enabled to preferentially encode the matching results of the sense amplifiers.

15. A computing method of a computing system, comprising: receiving at least one data input; Receiving search conditions including a search range and a search value; Providing programming data to a plurality of programmable devices of a first memory string and a second memory string in response to the at least one data input according to a selection code; driving a plurality of select inputs of the first memory string and the second memory string in response to the search range; driving a plurality of control inputs of the first memory string and the second memory string according to the selection code and in response to the search value; sensing a bit line to provide an indication of one of a plurality of match indications, and wherein the first memory string and the second memory string are connected in parallel between the bit line and a source line; providing the indication as an output, wherein a paired memory string comprises the first memory string and the second memory string, the first memory string comprises at least one selection device and is responsive to a corresponding one of the selection inputs, and is serially connected to a plurality of programmable devices connected in series, each of the programmable devices being responsive to a corresponding programmed state and a corresponding one of the control inputs, and the second memory string is identical to the first memory string, wherein the paired memory string is enabled to couple to the bit line and the source line through a corresponding one of a plurality of string pair currents in response to the selection inputs, the control inputs and the programmed states of the first memory string and the second memory string, The string pair currents include a precise matching current and an unmatched current, and The match indications include an exact match indicated in response to the exact match current and a no match indicated in response to the no match current. 16 . The operation method of the operation system according to claim 15 , wherein the string pair currents further include at least a portion of matching currents, and the matching indications include at least a portion of matching indicated in response to the at least a portion of matching currents.

17. An operating method of an operating system according to claim 15, wherein these programmable devices connected in series are configured in multiple layers, the search condition further includes a search depth, driving these control inputs further responds to the search depth, and the search depth indicates the number of these layers to be searched.

18. A search memory, comprising: multiple sense amplifiers; Multiple 2D memory arrays, each comprising: A corresponding bit line is connected to a corresponding one of these sense amplifiers, A corresponding source line, and a plurality of corresponding memory strings, each of the memory strings being coupled to (a) the corresponding bit line and (b) the corresponding source line, and each of the memory strings comprising (1) a plurality of corresponding floating gate transistors connected in series, each of the floating gate transistors having and responding to (c) a corresponding set state and (d) a corresponding control input, and each of the memory strings further comprising (2) a corresponding selection device connected in series between the corresponding floating gate transistors connected in series and the corresponding bit line, and each of the selection devices having and responding to a corresponding selection line; a plurality of word lines, each of the word lines being coupled to a corresponding one of the control inputs corresponding to each of the floating gate transistors connected in series; A data encoder is enabled for programming data to the floating gate transistors connected in series, and is responsive to at least one data input and based on a selection code; a search encoder enabled to receive a search and drive the word lines according to the search and the select code, and further enabled to drive the select lines according to the search; as well as wherein (e) corresponding to each of the memory strings, each of the memory strings is driven to be coupled to the corresponding bit line and the source line via a match finding current, in response to the set states of the memory string being precisely matched to the corresponding control inputs of the series-connected floating gate transistors of the memory string, and (f) each of the sense amplifiers is enabled to generate a corresponding indication of whether the bit line coupled to each of the sense amplifiers is coupled to the source line via the match finding current; and wherein (g) each memory string is further enabled to couple corresponding each of the memory strings to the corresponding bit line and the source line through a no-match finding current in response to the set states of the memory string not precisely matching the corresponding control inputs of the series-connected floating gate transistors of the memory string, and (h) each sense amplifier is further enabled to generate a corresponding indication of whether the bit line coupled to each sense amplifier is coupled to the source line through the no-match finding current.

19. The search memory according to claim 18, wherein: The corresponding memory strings are further enabled to couple the corresponding memory strings to the corresponding bit lines and the source lines through a portion of the match finding current, in response to the set states of the memory strings partially matching the corresponding control inputs of the series-connected floating gate transistors of the memory strings, and the sense amplifiers are further enabled to generate a corresponding one indicating whether the bit line coupled to the sense amplifier is coupled to the source line through the portion of the match finding current.

20. The search memory of claim 18, wherein the floating gate transistors connected in series are arranged in a plurality of layers, the search encoder is enabled to drive the selection lines in response to a search depth, and the search depth indicates how many layers are searched.

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