Power supply circuit, related system and method

Abstract

The invention relates to a power supply circuit, a related system and a method. The power supply circuit includes a plurality of current supply circuits, each configured to provide an output current in accordance with a respective digital control signal, and a measurement current proportional to the respective output current. The control circuit selects one of the measurement currents associated with the current supply circuit and one of the digital control signals. A comparison circuit generates a threshold current and generates a comparison signal by comparing the selected measurement current with the threshold current. The control circuit sets the threshold current to a first value during a first phase that is less than an expected value of the selected measurement current as indicated by the selected digital control signal, and sets the threshold current to a second value during a second phase that is greater than the expected value. The control circuit verifies whether the comparison signal is de-asserted during the first phase and asserted during the second phase.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102023000018681, filed on September 12, 2023, entitled “Power supply circuit, related system and method”, which is hereby incorporated by reference into this application to the maximum extent permitted by law. Technical Field

[0003] Embodiments of the present description relate to power supply circuits and methods, such as power supply circuits configured to power lighting modules, and associated methods. Background Art

[0004] FIG1 shows a typical lighting system. The lighting system includes a power supply circuit 1 and one or more lighting modules 20, such as a lighting module 20. 1 Up to 20 k For example, the lighting module 20 may form an LED or OLED panel 2 .

[0005] In the example considered, each lighting module 20 comprises one or more lighting sources. For example, in the example considered, each lighting module 20 comprises at least one LED (light emitting diode) or OLED (organic light emitting diode) L. For example, typically each lighting module 20 comprises an LED string, i.e., a plurality of LEDs connected in series, as schematically shown via two LEDs L1 and L2 connected in series.

[0006] Those skilled in the art will recognize that LEDs (or LED chains) are usually not powered by a constant voltage, but rather by a current. Therefore, in order to individually control the light intensity of each lighting module 20, the power supply circuit 1 usually includes a corresponding output terminal or channel OUT for each lighting module 20, such as an output terminal OUT 1 To OUT k , and the power supply circuit 1 is configured to provide a corresponding current to each output terminal OUT, such as the current i 1 to i k .

[0007] Such power supply circuits 1 are well known in the art. For example, the applicant of the present patent application sells an LED driver integrated circuit such as the L99LDLH32 with 32 channels. For example, the operation of the L99LDLH32 is described in the data sheet DS12879 "L99LDLH32-32-channel LED driver with automotive CAN FD Light interface", for example, revision 5 of 2021.

[0008] In many applications, the power supply circuit 1 should be able to monitor the current i 1 to i k For example, such monitoring may help to verify whether each current provided by the power supply circuit 1 corresponds to an expected value or more generally is within an expected tolerance range, which, for example, allows to determine whether the intensity of the light emitted by the lighting module 20 corresponds to an expected value and / or whether the lighting module indicates a malfunction, for example due to a short-circuit or open-circuit load condition. Summary of the invention

[0009] In view of the above circumstances, an object of various embodiments of the present disclosure is to provide a solution for verifying the current supply status of a power circuit.

[0010] According to one or more embodiments, the above objects are achieved by a power supply circuit having unique elements as specifically set forth in the following claims.In addition, embodiments relate to related systems and methods.

[0011] The claims form an integral part of the technical teaching of the description provided herein.

[0012] As mentioned above, various embodiments of the present disclosure relate to a power supply circuit. In various embodiments, the power supply circuit includes a plurality of output terminals, such as pads or pins of a corresponding integrated circuit including the power supply circuit, and for each output terminal, a corresponding current supply circuit. Specifically, each current supply circuit is configured to provide an output current to the corresponding output terminal according to a corresponding first digital control signal.

[0013] For example, in various embodiments, each current supply circuit includes a current digital-to-analog converter configured to receive a first reference current and a corresponding first digital control signal, wherein the first digital control signal indicates a first multiplier, and the current digital-to-analog converter is configured to generate the first current by multiplying the first reference current by the first multiplier. In addition, each current supply circuit includes a scaling circuit configured to generate an output current by generating an amplified version of the first current according to a first scaling factor.

[0014] For example, in various embodiments, each current supply circuit includes a first resistor connected between the regulated voltage and the output of the current digital-to-analog converter, a second resistor connected to the current path of the first FET between the regulated voltage and the corresponding output terminal, and an operational amplifier configured to drive the gate-source voltage of the first FET so that the voltage drop at the second resistor corresponds to the voltage drop at the first resistor. Therefore, in this case, the ratio between the resistance value of the second resistor and the resistance value of the first resistor defines the first scaling factor.

[0015] In various embodiments, each current supply circuit further comprises a current sensor configured to provide a measurement current proportional to the corresponding output current. For example, in various embodiments, the current sensor comprises a third resistor connected in series with a current path from a second FET to a regulated voltage, wherein a gate terminal of the second FET is connected to a gate terminal of the first FET. Thus, the resistance value of the third resistor and the scaling of the second FET relative to the first FET define a second scaling factor. Preferably, the ratio between the first scaling factor and the second scaling factor is one.

[0016] Thus, in various embodiments, the current supply circuit includes a first FET connected between a regulated voltage and a corresponding output terminal, and the current sensor includes a second FET configured to provide a measurement current, wherein the current supply circuit is configured such that a gate-source voltage of the second FET corresponds to a gate-source voltage of the first FET.

[0017] In various embodiments, the power supply circuit includes a first multiplexer circuit, a second multiplexer circuit, a comparison circuit, and a control circuit. Specifically, the first multiplexer circuit is configured to provide a selected measurement current by selecting one of the measurement currents according to a selection signal indicating the selected current supply circuit. Conversely, the second multiplexer circuit is configured to provide a selected digital control signal by selecting one of the first digital control signals according to the selection signal indicating the selected current supply circuit.

[0018] In various embodiments, the comparison circuit is configured to generate the threshold current according to one or more digital threshold control signals. For example, in various embodiments, the one or more digital threshold control signals include a second digital control signal, the comparison circuit includes an additional current digital-to-analog converter, the additional current digital-to-analog converter is configured to receive a second reference current and a second digital control signal, wherein the second digital control signal indicates a second multiplier, and the additional current digital-to-analog converter is configured to generate the threshold current by multiplying the second reference current by the second multiplier.

[0019] Furthermore, in various embodiments, the comparison circuit is configured to compare the selected measured current with a threshold current. Specifically, in response to determining that the selected measured current is greater than the threshold current, the comparison circuit de-asserts the comparison signal, and in response to determining that the selected measured current is less than the threshold current, the comparison circuit asserts the comparison signal.

[0020] For example, for this purpose, the comparison circuit may include a summing node and a current comparator, the summing node being configured to provide a current corresponding to the difference between the selected measurement current and the threshold current, the current comparator being configured to assert the comparison signal when the current is greater than zero, and to assert the comparison signal when the current is less than zero. Alternatively, the comparison circuit may include a first measurement resistor configured to be traversed by the threshold current, and a second measurement resistor configured to be traversed by the selected measurement current. In this case, the comparison circuit may include a voltage comparator configured to assert the comparison signal when the voltage drop at the first measurement resistor is greater than the voltage drop at the second measurement resistor, and to assert the comparison signal when the voltage drop at the first measurement resistor is less than the voltage drop at the second measurement resistor.

[0021] In various embodiments, the control circuit is configured to periodically repeat various operations. Specifically, the control circuit generates a selection signal to select a measurement current and a first digital control signal associated with a given current supply circuit. For example, the control circuit can sequentially select all current supply circuits or a subset of current supply circuits. Next, the control circuit generates the one or more digital threshold control signals according to the selected digital control signal to set the threshold current during the first stage to a first value, wherein the first value is less than the expected value of the selected measurement current as indicated by the selected digital control signal. In addition, the control circuit sets the threshold current during the second stage to a second value, wherein the second value is greater than the expected value of the selected measurement current as indicated by the selected digital control signal.

[0022] Therefore, in various embodiments, the first value and the second value can be used to define a tolerance range for the expected value of the selected measured current. For example, in various embodiments, the control circuit is configured to set the second digital control signal to a first value that is less than the selected digital control signal by a given first percentage during the first stage, and to set the second digital control signal to a second value that is greater than the selected digital control signal by a given second percentage during the second stage. Alternatively, the one or more digital threshold control signals may also include a reference current selection signal, and the control circuit may set the second digital control signal to the value of the selected digital control signal during the first stage, and select a current that is less than the first reference current by a given first percentage as the second reference current via the reference current selection signal, and set the second digital control signal to the value of the selected digital control signal during the second stage, and select a current that is greater than the first reference current by a given second tolerance percentage as the second reference current via the reference current selection signal.

[0023] In various embodiments, the control circuit then verifies whether the comparison signal is de-asserted during the first phase and asserted during the second phase. Specifically, when the comparison signal is de-asserted during the first phase and asserted during the second phase, the control circuit asserts the status signal, and when the comparison signal is asserted during the first phase or de-asserted during the second phase, the control circuit de-asserts the status signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, provided by way of non-limiting example only, in which:

[0025] FIG1 shows an example of a lighting system;

[0026] Figure 2 An embodiment of a power supply circuit is shown;

[0027] Figure 3 Shows Figure 2 An embodiment of a current supply circuit of a power supply circuit;

[0028] Figure 4 Shows Figure 3 An embodiment of a current source of a current supply circuit;

[0029] Figure 5 Shows Figure 3 An embodiment of a current sensor for a current supply circuit;

[0030] Figure 6 Shows Figure 2 An embodiment of a current monitoring circuit for a power supply circuit;

[0031] Fig. 7A , Figure 7B , Figure 7C and Fig.7D Shows Figure 6 An embodiment of the operation of the current monitoring circuit;

[0032] Figure 8 , Fig. 9 and Fig.10 Shows Figure 6 An embodiment of a comparison circuit of a current monitoring circuit; and

[0033] Fig.11 Shows Figure 6

[0026] Further embodiments of the operation of the current monitoring circuit are described below. DETAILED DESCRIPTION

[0034] In the following description, many specific details are given to provide a thorough understanding of the embodiments. The embodiments may be implemented without one or more of the specific details, or using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0035] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0036] The references used herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0037] In the following Figures 2 to 11 1, parts, elements or components that have been described with reference to FIG. 1 are indicated by the same reference numerals previously used in that figure; in order not to overburden this detailed description, the description of these previously described elements will not be repeated below.

[0038] Figure 2 An embodiment of a power supply circuit 1a according to the present disclosure is shown. In various embodiments, the power supply circuit 1a may be implemented within an integrated circuit (IC).

[0039] Specifically, in the embodiment under consideration, the power supply circuit 1a includes a plurality of output terminals OUT (eg, pads of a die of an IC of the power supply circuit 1a or pins of a packaged IC of the power supply circuit 1a), such as k output terminals OUT 1 To OUT kIn various embodiments, the power supply circuit 1a may be used in a lighting system, wherein one or more lighting modules 20 (such as k lighting modules 20) 1 Up to 20 k ) is connected to the output terminal OUT. In general, the number of lighting modules 20 connected to the power supply circuit 1a may correspond to the number k of the output terminals OUT, or may be less than the number k of the output terminals OUT. For example, the number of output terminals (i.e., channels) may be greater than 4, for example, between 8 and 256. In various embodiments, each lighting module 20 includes one or more lighting sources (such as LEDs or OLEDs), or other solid-state lighting sources (such as laser diodes). In general, the power supply circuit 1a may also be used to power other types of loads.

[0040] As mentioned above, in various embodiments, the power supply circuit 1a is configured to provide a corresponding current, such as a current i 1 to i k Specifically, in the embodiment considered, the power supply circuit 1a comprises, for each output terminal OUT, a respective current supply circuit 12, such as a current supply circuit 12 1 to 12 k , wherein each current supply circuit 12 is configured to provide a corresponding current.

[0041] In the embodiment considered, the current supply circuit 12 is connected via a common DC voltage V applied between the two nodes 102a and 102b. REG 102a and 102b, respectively. In various embodiments, each current supply circuit 12 may be powered by a corresponding voltage V REG Power supply, or current supply circuit 12 subset can be by the corresponding voltage V REG For example, the voltage V REG It may be in the range between 5V and 24V, for example, between 9V and 14V. However, the voltage V REG It may also be greater than 24V, for example in the range between 50V and 100V.

[0042] In various embodiments, the voltage(s) V REG The power supply circuit 1a may be received via input terminals, such as two input terminals 100a and 100b (eg, pads or pins of a corresponding IC). Alternatively, Figure 2 As shown in FIG. 1 , the power supply circuit 1 a may include a voltage generator circuit 10 configured to generate (one or more) voltages VREG In this case, the power supply circuit 1a may be configured to receive an input voltage V via input terminals 100a and 100b. IN , the voltage generator circuit 10 may be configured to generate (one or more) voltages V REG , for example, based on the voltage V IN A regulated voltage V is generated at nodes 102a and 102b. REG Generally speaking, the input voltage V IN It can be an AC or DC voltage. For example, in various embodiments, terminals 100a and 100b can be connected to mains, an external electronic converter that generates a DC voltage, or a battery. Therefore, in various embodiments, the voltage generator circuit 10 can include a linear regulator, or an AC / DC or DC / DC electronic converter (switch mode power supply). For example, in various embodiments, the voltage generator circuit 10 is implemented with a DC / DC electronic converter, such as a buck or multi-phase buck converter, a boost converter, a SEPIC converter, or other types of electronic converters. In this case, the reactive components (inductors, such as inductors and / or transformers, and / or capacitors) of such an electronic converter can be external to the IC relative to the power supply circuit 1a.

[0043] In the embodiment under consideration, each current supply circuit 12 is configured to control the current supply circuit 12 according to one or more corresponding control signals CTR, such as 1 The control signal(s) CTR 1 and the current supply circuit 12 k The control signal(s) CTR k To generate a corresponding current. In various embodiments, the power supply circuit 1a may include a terminal for receiving a control signal CTR, for example, from an external microprocessor. Conversely, in other embodiments, such as Figure 2 As shown in FIG. 1 , the power supply circuit 1 a includes a control circuit 14 configured to generate a control signal CTR.

[0044] For example, in various embodiments, the power supply circuit 1a includes a communication interface 16, such as a serial communication interface, for example, a universal asynchronous receiver / transmitter (UART), a serial peripheral interface bus (SPI), an inter-integrated circuit (I2C), a controller area network (CAN) bus and / or an Ethernet interface, which is connected to one or more terminals IF of the power supply circuit 1a. Therefore, in the embodiment under consideration, the control circuit 14 can be configured to receive data indicating a requested value of the current to be provided by the current supply circuit 12 via the communication interface 16, and the control circuit 14 can generate a control signal CTR accordingly. In various embodiments, the control circuit 14 can also be connected to one or more sensors to generate the control signal CTR, such as a sensor configured to monitor the current and / or voltage V generated via the current supply circuit 12. REG and / or one or more current sensors for the temperature of the power supply circuit 1a.

[0045] Figure 3 An embodiment of the current supply circuit 12 is shown. In the embodiment considered, the current supply circuit 12 comprises a REG (or the corresponding voltage V REG ) and a variable current source 120 between the corresponding output terminal OUT, wherein the variable current source 120 is configured to provide a current to the output terminal OUT, the current being Figure 3 Specifically, in various embodiments, the variable current source 120 is configured to set the value / amplitude of the current i according to the control signal CTR.

[0046] As mentioned above, various embodiments of the present disclosure relate to a method for monitoring a current i provided by a power supply circuit 1a. 1 to i k For example, in the embodiment under consideration, the power supply circuit 1a includes a current monitoring circuit 18, and each current supply circuit 12 includes a current sensor 122 configured to provide a current i to the current monitoring circuit 18. MON , where the current i MON is proportional to the current i provided by the corresponding current supply circuit 12. For example, as will be described in more detail below, the current monitoring circuit 18 can determine the current i, or more specifically, the monitored current i MON Whether it is between the lower threshold and the upper threshold.

[0047] In general, as is well known to those skilled in the art, the intensity of the light emitted by an LED can be changed by changing the average current flowing through the LED. In this regard, the average current flowing through the lighting module 20 can be changed by changing the amplitude of the current i (commonly referred to as constant current or CC dimming) and / or by pulse width modulation (PWM) of the current (commonly referred to as PWM dimming). Therefore, although not shown in the figure, the power supply circuit 1a can also be configured to modulate each current i via corresponding PWM modulation. 1 to i k , and / or modulate all currents i via a common PWM modulation 1 to i k For example, in the former case, the variable current source 120 of each current supply circuit 12 can be turned on and off via a corresponding additional control signal CTR corresponding to the PWM signal, thereby achieving individual PWM modulation of the current i provided to the corresponding lighting module 20. In contrast, in the latter case, the power supply circuit 1a may include an electronic switch configured to selectively connect the current supply circuit 12 and the lighting source 20 to the voltage V REG For example, in various embodiments, the lighting modules 20 may be connected to the ground GND via a common electronic switch, and the electronic switch may be closed and opened via an additional control signal CTR corresponding to the PWM signal, thereby achieving common PWM dimming of all lighting modules 20, whereby the relative light intensity of the lighting modules may be controlled by individual CC dimming of the current generator 120 (i.e., the current i during the on period of the PWM modulation). 1 to i k The amplitude of the current i is set by the optional additional individual PWM dimming. In general, the following will not specifically consider the current i 1 to i k This PWM dimming is possible because the current monitoring circuit 18 is configured to monitor each current i when the corresponding channel is enabled (ie, during the on-period of the optional (one or more) PWM modulations). 1 to i k is enough.

[0048] Figure 4 A possible implementation of the variable current source 120 is shown. Specifically, in the embodiment considered, the variable current source 120 comprises a current digital-to-analog converter (IDAC) 1200. Figure 4 As schematically shown in FIG. 1 , in the embodiment considered, IDAC 1200 is configured to receive a reference current i REF and a digital signal Curr_Set_CH indicating the multiplier c, the reference current i REFFor example, it is provided via a reference current source 1202, which is powered, for example, via a DC supply voltage VDD (such as a voltage in the range between 3 and 5 V), where the multiplier c is an integer. In addition, the IDAC 1200 is configured to generate a reference current i according to the multiplier c set via the signal Curr_Set_CH. REF The current i corresponding to the multiple of SET , i.e. i SET =c·i REF For example, in various embodiments, the signal Curr_Set_CH has 8 bits, which allows the current i SET Set between 0 and 255. REF However, the signal Curr_Set_CH may also have fewer bits or more bits. For example, as is well known in the art, such an IDAC may be implemented with a plurality of current mirrors having different mirror ratios, and wherein the current mirrors are selectively enabled according to the bits of the signal Curr_Set_CH.

[0049] In various embodiments, the current source 120 includes a circuit 1204 for converting the current i SET The scaled version of is applied to the corresponding output terminal OUT, that is, i = m·i SET , where m represents a scaling factor. For example, in various embodiments, circuit 1204 is implemented via a current mirror.

[0050] On the contrary, Figure 4 In the embodiment shown in FIG. 1 , the circuit 1204 includes a circuit connected to a voltage V REG and the output of IDAC 1200. Therefore, in the embodiment considered, the current i SET flows through the resistor 1206 and generates a current i SET A voltage drop is proportional to the resistance value of resistor 1206.

[0051] Furthermore, in the embodiment under consideration, the circuit 1204 includes a circuit at a voltage V REG A second resistor 1208 is provided between the output terminal OUT and the output terminal OUT, which is connected to a field effect transistor (FET) 1212 (such as a MOSFET) (current path). Therefore, in the embodiment considered, the current i flows through the resistor 1208 and generates a voltage drop proportional to the current i and the resistance value of the resistor 1208.

[0052] Finally, in the embodiment considered, the circuit 1204 includes an operational amplifier (OpAmp) 1210 configured to drive the gate terminal of the FET 1212 such that the voltage drop at the resistor 1208 corresponds to the voltage drop at the resistor 1206. Thus, in the embodiment considered, the FET 1212 essentially acts as a variable current source.

[0053] For example, in various embodiments, the FET is a p-channel FET. In this case, the first terminal of the resistor 1208 is connected to the voltage V REG , the source terminal of the p-channel FET 1212 is connected to the second terminal of the resistor 1208, and the drain terminal of the p-channel FET 1212 is connected to the output terminal OUT. In addition, when a p-channel FET is used, the positive / non-inverting input of the OpAmp 1210 is connected to the middle node between the resistor 1206 and the IDAC 1200, and the negative / inverting input of the OpAmp 1210 is connected to the middle node between the resistor 1208 and the FET 1212 (the source terminal of the FET 1212), wherein the output terminal of the OpAmp 1210 is connected to the gate terminal of the p-channel FET 1212.

[0054] Therefore, under steady state conditions, the voltage drop across resistor 1208 corresponds to the voltage drop across resistor 1206. Therefore, to obtain the scaled current i=m·i SET , the resistor 1206 has a resistance value corresponding to the resistance value of the resistor 1208 multiplied by m. For example, when the resistance value of the resistor 1208 is indicated as Rs, the resistor 1206 has a resistance value of m·Rs. For example, the scaling factor m can be selected between 5 and 100, such as between 10 and 30, such as m=20. In various embodiments, the resistors 1206 and 1208 are matched resistors, which ensures that the resistors 1206 and 1208 experience the same process, voltage and temperature (PVT) changes. For example, in various embodiments, the resistors 1206 and 1208 are arranged in close proximity within the IC of the power supply circuit 1a.

[0055] Figure 5 In this regard it is shown that when using Figure 4The variable current source 120 described is a possible implementation of the current sensor 122. In particular, as described above, the current i also flows through the FET 1212. Therefore, in order to implement the current sensor 122, it is sufficient that the current supply circuit 12 comprises a further branch comprising a further resistor 1220 and a further FET 1222 of the same type (n-channel or p-channel) as the FET 1212, wherein the gate terminal of the FET 1222 is connected to the gate terminal of the FET 1212. For example, in the embodiment considered, the FET 1222 is a p-channel FET, wherein the source terminal of the FET 1222 is connected via the resistor 1220 to the voltage V REG , the gate terminal of FET 1222 is connected to the gate terminal of FET 1212, and the drain terminal of FET 1222 provides the measurement current i MON .

[0056] Therefore, in the embodiment considered, in order to obtain the scaled current i MON =i / p, the resistor 1220 has a resistance value corresponding to the resistance value of the resistor 1208 multiplied by p, that is, the resistor 1220 has a resistance value of p·Rs. Preferably, the FET 1222 also corresponds to a scaled version of the FET 1212, for example, the FET 1222 has a ratio W / L corresponding to the width to length ratio (W / L) of the FET 1212 divided by the scaling factor p. In various embodiments, the resistors 1220 and 1208 are matched resistors, which ensures that the resistors 1220 and 1208 experience the same process, voltage and temperature (PVT) changes. For example, in various embodiments, the resistors 1206, 1208 and 1220 are arranged in close proximity within the IC of the power supply circuit 1a. As will be described in more detail below, in various embodiments, the scaling factor p corresponds to the scaling factor m, that is, p=m.

[0057] Similarly, when current mirror 1204 is used, current mirror 1204 may include providing a measurement current i MON For example, such a current mirror 1204 can be implemented with three p-channel FETs whose source terminals are connected to a voltage V REG , wherein the drain terminal of the first FET is connected to the output of IDAC 1200, the drain terminal of the second FET provides a current i to the output OUT, and the drain terminal of the third FET provides a measurement current i MON, and the gate terminals of the three FETs are connected to the drain terminal of the first FET (the output of the IDAC 1200). Specifically, in this case, the scaling factor m corresponds to the scaling between the second FET and the first FET, and the scaling factor p corresponds to the scaling between the third FET and the second FET, wherein also in this case, the scaling factors preferably correspond, i.e., p=m.

[0058] Figure 6 1 shows an embodiment of the current monitoring circuit 18. Specifically, as mentioned above, in various embodiments, the current monitoring circuit 18 is configured to determine the current i 1 to i k Is it within a given expected threshold, where the current i 1 to i k The value of is set via a corresponding signal Curr_Set_CH provided to each current supply circuit 12, which signals are indicated as signals Curr_Set_CH1 to Curr_Set_CHk in the following, for example, 1 The current i is set based on the signal Curr_Set_CH1 1 .

[0059] For example, in the embodiment considered, the control circuit 14 of the power supply circuit 1 a comprises a plurality of registers 142 for storing the values ​​of the signals Curr_Set_CH1 to Curr_Set_CHk.

[0060] As mentioned above, in various embodiments, the values ​​of the signals Curr_Set_CH1 to Curr_Set_CHk can be programmed by the control circuit 14. For example, Figure 6 1 shows a processing circuit 140 of the control circuit 14, which is configured to program / write the contents of the register 142. For example, as mentioned above, in various embodiments, the control circuit 14, e.g., the processing circuit 140, may receive the values ​​of the signals Curr_Set_CH1 to Curr_Set_CHk via the communication interface 16. In general, any suitable communication protocol may be used to receive programming commands via the communication interface 16, such as:

[0061] - comprising the value of one of the signals Curr_Set_CH1 to Curr_Set_CHk, for example a programming command comprising the address of the register 142 associated with the respective signal Curr_Set_CH1 to Curr_Set_CHk and the respective value of the signal Curr_Set_CH1 to Curr_Set_CHk; and / or

[0062] - a programming command including the values ​​of all signals Curr_Set_CH1 to Curr_Set_CHk, for example including a data packet including the values ​​of signals Curr_Set_CH1 to Curr_Set_CHk in sequence; and / or

[0063] - A program command comprising a subset of the values ​​of the signals Curr_Set_CH1 to Curr_Set_CHk.

[0064] Additionally or alternatively, the processing circuit 140 may generate a voltage signal based on data provided by one or more sensors of the power supply circuit 1a (such as an indication voltage V REG The values ​​of the signals Curr_Set_CH1 to Curr_Set_CHk are changed based on data indicating the value of the current supply circuit 12 and / or data indicating the temperature of one or more components of the power supply system 1a (such as the temperature of the current supply circuit 12).

[0065] In the embodiment considered, the current monitoring circuit 18 comprises a multiplexer 184 configured to select the current i according to a selection signal SEL generated by a (digital) control circuit 182 of the current monitoring circuit 18. MON1 to i MONk One of the MONi For example, in the embodiment considered, the multiplexer 184 comprises k electronic switches SW 1 To SW k , where each electronic switch SW 1 To SW k is connected between the corresponding current supply circuit and the node A. Therefore, in this case, each electronic switch SW 1 To SW k is configured as an electronic switch SW 1 To SW k When closed, the corresponding current i is provided to node A MON1 to i MONk , node A provides the corresponding electronic switch SW 1 To SW k The corresponding current i when closed MON1 to i MONk The sum of the currents i MONi Thus, in the embodiment considered, the multiplexer 184 may include a decoder 1840 configured to close the electronic switch SW according to the selection signal SEL. 1 To SW k One of the nodes, whereby node A provides a current i MON1 to i MONk One of the corresponding currents i MONiThus, in the embodiment considered, the selection signal SEL can be used to select one of the channels of the power supply circuit.

[0066] Therefore, in various embodiments, the control circuit 182 is configured to generate a selection signal SEL to sequentially select the signal i MON1 to i MONk (in any suitable order), the current monitoring circuit 18 is configured to verify that the selected current i MONi Is it within the expected value range, where the expected value range depends on the selected current i MON1 to i MONk The associated corresponding values ​​Curr_Set_CH1 to Curr_Set_CHk are determined.

[0067] Generally speaking, the current monitoring circuit 18 may include an analog-to-digital converter (ADC). The current monitoring circuit 18 may be configured to obtain the selected current i MONi and verifying whether the digital sample is within the expected value range determined based on the corresponding values ​​Curr_Set_CH1 to Curr_Set_CHk. However, as mentioned above, a significant amount of current i MON1 to i MONk Therefore, in many application scenarios where rapid detection of abnormal conditions is required, performing AD conversion may not be feasible. Therefore, in order to increase the speed of the verification operation, the current monitoring circuit 18 may include multiple ADCs to sample multiple currents i in parallel. MON1 to i MONk However, this ADC is complex and will increase the size and cost of the power supply circuit.

[0068] Therefore, a solution will be described below in which the current monitoring circuit 18 is configured to verify the selected current i in an analog manner. MONi The value of .

[0069] Specifically, in various embodiments, the selected current i MONi is provided to the current comparison circuit 180. The current comparison circuit 180 also receives one or more indications of the comparison threshold value i TH The threshold control signal TH is configured to pass the selected current i MONi Compare with threshold i TH For example, in various embodiments, the comparison circuit 180 is configured to generate a comparison signal COMP when the current i MONi Less than comparison threshold i TH , that is, i MONi TH , the comparison signal COMP is asserted (eg, set high), and when the current i​MONi Greater than comparison threshold i TH , that is, i MONi >i TH , de-assert the comparison signal COMP (eg, set it low).

[0070] In this regard, as previously described, in various embodiments, the current i provided by the current supply circuit corresponds to i=m·i SET , where i SET =c·i REF ,Right now:

[0071] i = m · c · i REF (1)

[0072] Wherein m is the constant scaling factor (or in general, the proportional factor) of the variable current source 120 , and the multiplier c is set via the signal Curr_Set_CH.

[0073] In addition, the measured current corresponds to i MON =i / p, which can be restated according to equation (1) as:

[0074] i MON = m / p · c · i REF (2)

[0075] Where p is a constant scaling factor (or, in general, a proportional factor) of the current sensor 122, i.e., the ratio m / p is fixed. In this regard, by selecting a scaling factor p corresponding to the scaling factor m, i.e., p=m, equation (2) can be simplified as follows:

[0076] i MON = c · i REF (3)

[0077] Therefore, equation (2) or (3) indicates that for a given signal Curr_Set_CH, the current i MON The expected value of MON,exp Therefore, equation (2) or (3) also applies to the selected current i MONi The expected value of MONi,exp , where the expected value i MONi,exp can be calculated based on the corresponding signal Curr_Set_CHi. Figure 6 As shown in FIG. 1 , the current monitoring circuit 18 may include a multiplexer 186 configured to select a selected channel / selected current i MONi The associated signals Curr_Set_CH1 to Curr_Set_CHk are used to generate the signal Curr_Set_CHi.

[0078] In this regard, Fig. 7A As shown in , in various embodiments, the control circuit 182 receives the signal Curr_Set_CHi and generates the one or more signals TH to:

[0079] - In the first phase PH1, the threshold i is compared TH Set to the first value i TH1 , the first value is greater than the expected value i MONi,exp (as indicated by the signal Curr_Set_CHi) by a given first amount, for example, i TH1 =i MON,exp -(x·i MON,exp ), where x indicates the expected value i MON,exp and may be selected, for example, within a range between 0.05 and 0.3, preferably within a range between 0.1 and 0.25, for example, x=0.20; and

[0080] - In the second phase PH2, the threshold i is compared TH Set to the second value i TH2 , the second value is greater than the expected value i MONi,exp (as indicated by the signal Curr_Set_CHi) by a given second amount, for example, i TH2 =i MON,exp +(x·i MON,exp ).

[0081] In general, the order of the phases may also be reversed. In addition, the first and second quantities may be fixed or predetermined, rather than using a tolerance range, for example, the first and second quantities may be programmed via the communication interface 16. Similarly, in various embodiments, the tolerance value x may be programmed via the communication interface 16.

[0082] Therefore, if Figure 7B As shown in FIG. , in various embodiments, when the monitored current i MONi has an (approximate) expected value i MONi,exp , the comparison circuit 180 de-asserts the comparison signal COMP during phase PH1 because the current i MONi Greater than comparison threshold i TH , that is, i MONi >i TH1 , and asserts the comparison signal COMP during phase PH2 because the current i MONi Less than comparison threshold i TH , that is, i MONi TH2 .

[0083] On the contrary, Figure 7C ​As shown in FIG. , in various embodiments, when the monitored current i MONi (significantly) less than the expected value i MONi,exp , the comparison circuit 180 asserts the comparison signal COMP during both phase PH1 and phase PH2, because the current i MONi Less than comparison threshold i TH , that is, i MONi TH1 And i MONi TH2 .

[0084] On the contrary, Fig.7D As shown in FIG. , in various embodiments, when the monitored current i MONi (significantly) greater than expected value i MONi,exp , the comparison circuit 180 de-asserts the comparison signal COMP during both phase PH1 and phase PH2, because the current i MONi Greater than comparison threshold i TH , that is, i MONi >i TH1 And i MONi >i TH2 .

[0085] Therefore, in various embodiments, the control circuit 182 generates the one or more threshold control signals TH to change the threshold current i as described above. TH , and verify whether the comparison signal COMP is de-asserted in phase PH1 and asserted in phase PH2. In this regard, in various embodiments, the control circuit 182 is configured to:

[0086] - in response to determining that the comparison signal COMP is de-asserted in phase PH1 and asserted in phase PH2 , asserting the state signal STATUSi (eg, setting it high); and

[0087] - In response to determining that the comparison signal COMP is asserted in phase PH1 or de-asserted in phase PH2 , de-asserting the status signal STATUSi (eg, setting it low).

[0088] In various embodiments, the same operation may be achieved by performing comparisons in parallel via two comparison circuits 180, wherein the first comparison circuit 180 is configured to compare the current i MONi With threshold i TH1 The second comparison circuit 180 is configured to compare the current i MONi With threshold i TH2 However, in this case, the control circuit 182 generates two threshold signals TH in parallel, namely, for setting the current i TH1 The first threshold signal TH is used to set the current i​​TH2 In this regard, Figure 6 The solution shown in requires only one comparison circuit 180 and thus has reduced complexity and cost.

[0089] In various embodiments, the control circuit 14 of the power supply circuit 1a may include a register 144, and the value of the state signal STATUSi may be stored in a corresponding bit position associated with the channel selected via the selection signal SEL. Figure 6 144, where the selection signal SEL is used to select the bit position in the register 144 to store the value of the status signal STATUSi. Therefore, in the embodiment considered, the control circuit 182 can (for example, periodically) scan all channels, whereby the register 144 provides an indication of the status of all channels OUT 1 To OUT k The status signal STATUS indicates the status of the device.

[0090] In this regard, in various embodiments, the control circuit 182 may sequentially select (via the select signal SEL) only a subset of the channels, rather than scanning all channels.

[0091] For example, in various embodiments, the control circuit 182 may select only channels whose values ​​of the signals Curr_Set_CH1 to Curr_Set_CHk are different from zero.

[0092] Alternatively, in various embodiments, the control circuit 14 may further include a register for storing a channel enable flag, which indicates for each current supply circuit 12 whether the corresponding current source 120 should be enabled. Therefore, in this case, the control circuit 182 may only select the channel whose corresponding channel enable flag indicates that the corresponding current source 120 is enabled. For example, such a channel enable flag may be stored to the register 142 and may be used to generate an additional control signal CTR for each current supply circuit 12, which indicates whether the corresponding current source 120 should be enabled. In various embodiments, the channel enable flag may be programmed via the communication interface 16.

[0093] Alternatively, in various embodiments, the control circuit 14 may further include a register for storing a channel monitoring flag, the channel monitoring flag indicating for each channel whether the corresponding channel should be monitored. Therefore, in this case, the control circuit 182 may only select the channel for which the corresponding channel monitoring flag indicates that the corresponding channel should be monitored. For example, such a channel monitoring flag may be stored in the register 144. In various embodiments, the channel monitoring flag may be programmed via the communication interface 16.

[0094] The following describes possible embodiments of the comparison circuit 180 and the one or more threshold control signals TH generated by the control circuit 182. As mentioned above, in various embodiments, the current comparison circuit 180 receives the selected current i MONi and indicates the comparison threshold i TH one or more threshold control signals TH, and is configured to pass the selected current i MONi Compare with threshold i TH Therefore, in various embodiments, the comparison circuit 180 is configured to generate a comparison threshold value i according to the one or more threshold control signals TH. TH .

[0095] Figure 8 A first embodiment of a comparison circuit 180 is shown, which is indicated as comparison circuit 180a, where comparison circuit 180a includes IDAC 1800. Figure 8 As schematically shown in FIG. 1 , in the embodiment considered, IDAC 1800 is configured to receive a reference current i REF ', the reference current i REF 'For example, provided via a reference current source 1802, which is powered, for example, via a DC power supply voltage VDD, and receives a digital signal Curr_Set_TH indicating a multiplier q, wherein the multiplier q is an integer. In addition, the IDAC 1800 is configured to generate a reference current i according to the multiplier q set via the signal Curr_Set_TH. REF The current i corresponding to the multiple of ' DAC , that is, i DAC =q·i REF '. For example, in various embodiments, the signal Curr_Set_TH has 8 bits, which allows the current i DAC Set between 0 and 255. REF ' in the range between.

[0096] Specifically, as described with respect to equation (2), the monitored current corresponds to i MON =m / p·c·i REF Therefore, in various embodiments, the reference current i REF 'Selected as:

[0097] i REF ' = m / p · i REF (4)

[0098] For example, in various embodiments, the scaling factors m and p are designed such that m / p=1, that is, the reference current i REF ' corresponds to the reference current i REF , that is, iREF '=i REF .

[0099] Thus, in various embodiments, IDAC 1800 provides the following currents:

[0100] i DAC = q · m / p · i REF (5)

[0101] In fact, in this way, when the signal Curr_Set_TH corresponds to the signal Curr_Set_CHi of the currently selected channel, that is, when q=c, the IDAC 1800 is configured to provide the expected current i MONi,exp The corresponding current i DAC , that is, i DAC =i MONi,exp .

[0102] In the embodiment considered, the current i MONi is provided to node B, and IDAC 1800 is configured to sink current i from node B DAC , that is, node B provides current i M =i MONi -i DAC In addition, node B is connected to the current comparator 1804, that is, the current comparator 1804 receives the current i M In addition, the current comparator 1804 is configured as:

[0103] -When the current i M When it is less than zero, the comparison signal COMP is asserted (e.g., set to high);

[0104] -When the current i M When greater than zero, the compare signal COMP is de-asserted (eg, set low).

[0105] Thus, in the embodiment considered, the operation of the comparator 1804 is inverted relative to a conventional current comparator, which is schematically illustrated via the inverting “dot” at the output of the comparator 1804 .

[0106] Therefore, in the embodiment considered, in order to generate information about Figure 6 and the current i described in Figure 7 TH =i TH1 and i TH =i TH2 , the control circuit 182 can be configured as:

[0107] - In a first phase PH1, the value of the signal Curr_Set_TH is set to a first value Curr_Set_TH1 which is greater than Curr_Set_CHi (which indicates the expected value i MONi,exp ) is less than a given first amount, for example, Curr_Set_TH1=Curr_Set_CHi−(x·Curr_Set_CHi), where x indicates the expected value i described previously. MON,exp Tolerance range;

[0108] - In a second phase PH2, the value of the signal Curr_Set_TH is set to a second value Curr_Set_TH2 which is greater than the value Curr_Set_CHi by a given second amount, for example Curr_Set_TH2 = Curr_Set_CHi + (x·Curr_Set_CHi).

[0109] Fig. 9 A second embodiment of the comparison circuit 180 is shown, which is indicated as comparison circuit 180b. Specifically, in the embodiment considered, the control circuit 182 is configured to set the value of the signal Curr_Set_TH to the value Curr_Set_CHi both during the first phase PH1 and during the second phase. Conversely, in order to generate the current i TH =i TH1 and i TH =i TH2 , the control circuit 182 can be configured as:

[0110] - In the first phase PH1, the reference current i REF 'The value is set to the first value i REFA , the first value is greater than the reference current i REF Small given first quantity, for example, i REFA =i REF -(x·i REF ), where x indicates the expected value i described previously MON,exp tolerance range; and

[0111] - In the second phase PH2, the reference current i REF 'The value is set to the second value i REFB , the second value is greater than the reference current i REF A given second quantity, for example, i REFB =i REF +(x·i REF ).

[0112] As described with respect to equation (4), when the factor m does not correspond to the factor p, the current i REF You can actually use m / p·i REF replace.

[0113] For example, to change the reference current i REF ', the current comparison circuit 180b may include two circuits that are actually configured to generate a current i REFA and i REFB The two reference current sources 1802a and 1802b are configured to convert the current i REFA or current i REB Provided to IDAC 1800 as reference current i REF 'Switching circuit SERF. Therefore, in the embodiment considered, the control circuit 182 is configured to also generate a control signal CTH to:

[0114] - In the first phase PH1, a reference current i is provided to the IDAC 1800 REFA , for example by setting signal CTH low; and

[0115] - In the second phase PH2, a reference current i is provided to the IDAC 1800 REFB , for example by setting the signal CTH high.

[0116] Therefore, in Fig. 9 In the embodiment shown in , the signals Curr_Set_TH and CTH represent the threshold control signal TH generated by the control circuit 182 .

[0117] Fig.10 A third embodiment of a comparison circuit 180 is shown, which is indicated as comparison circuit 180c. Specifically, in the embodiment considered, the comparison circuit 180c comprises a voltage comparator 1806 configured to compare a first voltage with a second voltage, without using a current comparator 1804.

[0118] Specifically, in the embodiment under consideration, the control circuit 182 and the IDAC 1800 are again configured to generate a current i during the first phase PH1. DAC =i TH1 , and generates a current i during the second phase PH2 DAC =i TH2 For example, in Fig.10 Used in Fig. 9 The solution described (digital input Curr_Set_TH remains unchanged, while the reference current i REF ' is changed), but you can also use Figure 8 Solution (reference current i REF ' remains unchanged, while the digital input Curr_Set_TH is changed).

[0119] In the embodiment considered, the current monitoring circuit 180c also includes two resistors Rmon1 and Rmon2, such as resistors, wherein the current i DAC flows through the resistor Rmon1, thereby generating a first voltage, and the current i MONi Flows through resistor Rmon2, thereby generating a second voltage. In the embodiment under consideration, resistors Rmon1 and Rmon2 have the same resistance value and are preferably matched resistors. Therefore, in the embodiment under consideration, the voltage comparator 1806 can receive the voltage (drop) at the resistor Rmon1 at the positive input terminal and the voltage (drop) at the resistor Rmon2 at the negative input terminal, whereby the comparator 1806:

[0120] -When the current i DAC Greater than voltage i MONi When PH2 is reached (which is typically the case during the second phase PH2), the comparison signal COMP is asserted (eg, set high).

[0121] -When the current i DAC Less than voltage i MONi When (which is typically the case during the first phase PH1), the comparison signal COMP is de-asserted (eg, set to low).

[0122] As mentioned above, the measurement circuit 18 may also include two comparison circuits 180 that operate in parallel using corresponding threshold values. Figure 8 , Fig. 9 and Fig.10 The comparison circuit 180 shown in FIG. 1 includes the IDAC 1800 , so the complexity of the measurement circuit 18 will be significantly increased.

[0123] Fig.11 shows the current i generated by IDAC 1800 DAC Specifically, in the above-mentioned embodiment, the control circuit 182 receives the signal Curr_Set_CHi (indicating that the current i MONi ) and setting the one or more signals TH, such as the signal Curr_Set_TH and the optional signal CTH, to set the first current i during the first phase PH1 TH1 and setting a second current i during the second phase PH2 TH2 For example, in various embodiments, the control circuit 182 includes a timer circuit configured to generate one or more signals indicating the first phase PH1 and the second phase PH2, such as a first signal TA_EN indicating the start of a new first phase PH1 and a second signal TB_EN indicating the start of a new second phase PH2. For example, in various embodiments, the control circuit 182 is configured to:

[0124] - in response to detecting that the signal TA_EN is asserted, setting the one or more signals TH according to the value Curr_Set_Chi to generate the same signal as the value i TH1 The corresponding current i DAC ;as well as

[0125] - in response to detecting that the signal TB_EN is asserted, setting the one or more signals TH according to the value Curr_Set_Chi to generate the same signal as the value i TH2 The corresponding current i DAC .

[0126] Furthermore, in various embodiments, the control circuit changes the selection signal SEL at the beginning of each measurement period MPH (comprising phases PH1 and PH2 ), for example in response to detecting the beginning of the first phase PH1 or the end of the second phase PH2 .

[0127] However, if Fig.11 As shown in FIG. 1 , based on the implementation of IDAC 1080, once the reference current i REF ' or the digital input Curr_Set_TH is changed, the output i DAC may not stabilize immediately, but may take a given time, such as several microseconds (μs), until the output i DAC reaches the requested value, that is, the current i TH1 or TH2 . Therefore, in various embodiments, the control circuit 182 is configured not to sample the comparison signal COMP immediately, but only after a given predetermined time (e.g., signaled via a sampling request signal generated by a timer circuit of the control circuit 182). Alternatively, the control circuit 182 may sample the signal COMP at the end of the corresponding phase. Therefore, in various embodiments, the control circuit 182 may be configured to sample the comparison signal COMP after a sampling time, which is, for example, greater than 1 μs, for example, in a range between 2 μs and 200 μs, for example, in a range between 5 μs and 50 μs, for example, selected in a range between 10 μs and 30 μs. Therefore, in various embodiments, the period of each phase may have a duration that is the same as or longer than the sampling time. For example, in various embodiments, the control circuit 182 is configured to:

[0128] - in response to detecting the moment when the signal TB_EN becomes asserted, sampling the signal COMP (which should be de-asserted) of the first phase PH1; and

[0129] - in response to detecting the moment when the signal TA_EN becomes asserted, sampling the signal COMP (which should be asserted) of the second phase PH2;

[0130] Of course, without prejudice to the principle of the invention, the construction details and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the invention as defined by the appended claims.

Claims

1. A power supply circuit, comprising: Multiple output terminals; a respective current supply circuit for each output terminal, wherein each current supply circuit is configured to provide an output current to the respective output terminal in accordance with a respective first digital control signal, and wherein each current supply circuit includes a current sensor configured to provide a measurement current proportional to the respective output current; a first multiplexer circuit configured to provide a selected measurement current by selecting one of the measurement currents according to a selection signal indicating a selected current supply circuit; a second multiplexer circuit configured to provide a selected digital control signal by selecting one of the first digital control signals according to a selection signal indicating a selected current supply circuit; The comparison circuit is configured as: generating a threshold current in accordance with one or more digital threshold control signals; comparing the selected measured current to a threshold current; responsive to determining that the selected measured current is greater than the threshold current, deasserting the comparison signal; as well as In response to determining that the selected measured current is less than the threshold current, asserting the comparison signal; and controlling the circuit, configured to periodically repeat: generating a selection signal to select a measurement current and a first digital control signal associated with a corresponding current supply circuit; generating the one or more digital threshold control signals according to the selected digital control signal to: During a first phase, setting the threshold current via the comparison circuit to a first value that is less than an expected value of the selected measurement current as indicated by the selected digital control signal; as well as During a second phase, setting the threshold current via the comparison circuit to a second value that is greater than an expected value of the selected measurement current as indicated by the selected digital control signal; verifying whether a comparison signal is de-asserted during the first phase and asserted during the second phase; asserting a status signal in response to determining that the comparison signal is de-asserted during the first phase and asserted during the second phase; as well as In response to determining that the comparison signal is asserted during the first phase or de-asserted during the second phase, the status signal is de-asserted.

2. The power supply circuit according to claim 1, wherein each current supply circuit comprises: a current digital-to-analog converter configured to receive a first reference current and a corresponding first digital control signal, wherein the first digital control signal indicates a first multiplier, and the current digital-to-analog converter is configured to generate a first current by multiplying the first reference current by the first multiplier; as well as The scaling circuit is configured to generate an output current by generating an amplified version of the first current according to a first scaling factor.

3. The power supply circuit according to claim 2, wherein the scaling circuit of each current supply circuit includes a first field effect transistor (FET) connected between the regulated voltage and the corresponding output terminal; and The current sensor of each current supply circuit includes a second FET configured to provide a measurement current of the corresponding current supply circuit, wherein the second FET is a scaled version of the first FET according to a second scaling factor, and the corresponding current supply circuit is configured so that the gate-source voltage of the second FET corresponds to the gate-source voltage of the first FET. The power supply circuit of claim 3 , wherein a ratio between the first scaling factor and the second scaling factor is 1. 5 .

5. The power supply circuit according to claim 3, wherein each current supply circuit comprises: A first resistor connected between the regulated voltage and the output of the current digital-to-analog converter; a second resistor connected to the current path of the first FET between the regulated voltage and the corresponding output terminal; an operational amplifier configured to drive a gate-source voltage of the first FET such that a voltage drop across the second resistor corresponds to a voltage drop across the first resistor; as well as A third resistor is connected in series with a current path of a second FET to the regulated voltage, wherein a gate terminal of the second FET is connected to a gate terminal of the first FET.

6. The power supply circuit of claim 2, wherein the one or more digital threshold control signals include a second digital control signal, wherein the comparison circuit comprises: The further current digital-to-analog converter is configured to receive a second reference current and a second digital control signal, wherein the second digital control signal indicates a second multiplier, and the further current digital-to-analog converter is configured to generate a threshold current by multiplying the second reference current by the second multiplier.

7. The power supply circuit according to claim 6, wherein the control circuit is configured to: During the first phase, setting the second digital control signal to a third value that is a first percentage less than the selected digital control signal; and During the second phase, the second digital control signal is set to a fourth value that is a second percentage greater than the selected digital control signal.

8. The power supply circuit of claim 6, wherein the one or more digital threshold control signals include a reference current selection signal, and wherein the control circuit is configured to: During a first phase, setting the second digital control signal to the value of the selected digital control signal, and selecting a first current value that is a first percentage less than the first reference current as the second reference current via a reference current selection signal; and During the second phase, the second digital control signal is set to the value of the selected digital control signal, and a second current value greater than the first reference current by a second tolerance percentage is selected as the second reference current via the reference current selection signal.

9. The power supply circuit according to claim 1, wherein the comparison circuit comprises: a summing node configured to provide a current corresponding to a selected difference between the measured current and the threshold current; as well as Current comparator, configured as: responsive to determining that the current is greater than zero, deasserting a comparison signal; as well as In response to determining that the current is less than zero, a comparison signal is asserted.

10. The power supply circuit according to claim 1, wherein the comparison circuit comprises: a first measuring resistor configured to be traversed by a threshold current; a second measurement resistor configured to be traversed by the selected measurement current; as well as Voltage comparators, configured as: asserting a comparison signal in response to determining that the voltage drop at the first measurement resistor is greater than the voltage drop at the second measurement resistor; as well as In response to determining that the voltage drop at the first measurement resistor is less than the voltage drop at the second measurement resistor, the comparison signal is de-asserted.

11. A system comprising: Power supply circuit, including: Multiple output terminals; a respective current supply circuit for each output terminal, wherein each current supply circuit is configured to provide an output current to the respective output terminal in accordance with a respective first digital control signal, and wherein each current supply circuit includes a current sensor configured to provide a measurement current proportional to the respective output current; a first multiplexer circuit configured to provide a selected measurement current by selecting one of the measurement currents according to a selection signal indicating a selected current supply circuit; a second multiplexer circuit configured to provide a selected digital control signal by selecting one of the first digital control signals according to a selection signal indicating a selected current supply circuit; The comparison circuit is configured as: generating a threshold current in accordance with one or more digital threshold control signals; comparing the selected measured current to a threshold current; In response to determining that the selected measured current is greater than the threshold current, deasserting the comparison signal; and responsive to determining that the selected measured current is less than a threshold current, asserting a comparison signal; The control circuit is configured to periodically repeat: generating a selection signal to select a measurement current and a first digital control signal associated with a corresponding current supply circuit; generating the one or more digital threshold control signals according to the selected digital control signal to: During a first phase, setting the threshold current via the comparison circuit to a first value that is less than an expected value of the selected measurement current as indicated by the selected digital control signal; and During a second phase, setting the threshold current via the comparison circuit to a second value that is greater than an expected value of the selected measurement current as indicated by the selected digital control signal; verifying whether a comparison signal is de-asserted during the first phase and asserted during the second phase; responsive to determining that the comparison signal is de-asserted during the first phase and asserted during the second phase, asserting the status signal; and In response to determining that the comparison signal is asserted during the first phase or de-asserted during the second phase, de-asserting the status signal; and At least one load is connected to the output terminal of the power circuit.

12. The system of claim 11, wherein the at least one load is at least one lighting module.

13. The system of claim 1 , wherein each current supply circuit comprises: a current digital-to-analog converter configured to receive a first reference current and a corresponding first digital control signal, wherein the first digital control signal indicates a first multiplier, and the current digital-to-analog converter is configured to generate a first current by multiplying the first reference current by the first multiplier; as well as The scaling circuit is configured to generate an output current by generating an amplified version of the first current according to a first scaling factor.

14. A method of operating a power circuit, the method comprising: generating a first digital control signal; According to the first digital control signal, the current supply circuit provides an output current; generating, by the control circuit, a selection signal to select the measurement current via the first multiplexer circuit and to select one of the first digital control signals associated with the corresponding current supply circuit via the second multiplexer circuit; The control circuit generates one or more digital threshold control signals according to the selected digital control signal to: During a first phase, the threshold current is set by the control circuit via the comparison circuit to a first value that is less than an expected value of the selected measurement current as indicated by the selected digital control signal; as well as During a second phase, the threshold current is set by the control circuit via the comparison circuit to a second value, the second value being greater than an expected value of the selected measurement current as indicated by the selected digital control signal; receiving a comparison signal from a comparison circuit and verifying whether the comparison signal is de-asserted during the first phase and asserted during the second phase; asserting a status signal in response to determining that the comparison signal is de-asserted during the first phase and asserted during the second phase; as well as In response to determining that the comparison signal is asserted during the first phase or de-asserted during the second phase, the status signal is de-asserted.

15. The method according to claim 14, further comprising: receiving, by a current digital-to-analog converter of each current supply circuit, a first reference current and a corresponding first digital control signal, the corresponding first digital control signal indicating a first multiplier; generating, by a current digital-to-analog converter, a first current by multiplying a first reference current by a first multiplier; as well as The output current is generated by the scaling circuit of each current supply circuit by generating an amplified version of the first current according to a first scaling factor.

16. The method of claim 15, wherein the one or more digital threshold control signals include a second digital control signal indicating a second multiplier, and the method further comprises: receiving a second reference current and a second digital control signal by a further current digital-to-analog converter of the comparison circuit; as well as The threshold current is generated by the further current digital-to-analog converter by multiplying the second reference current by a second multiplier.

17. The method according to claim 16, further comprising: During the first phase, the second digital control signal is set by the control circuit to a third value that is a first percentage less than the selected digital control signal; as well as During the second phase, the second digital control signal is set by the control circuit to a fourth value that is a second percentage greater than the selected digital control signal.

18. The method of claim 16, wherein the one or more digital threshold control signals include a reference current selection signal, and the method further comprises: During the first phase, the control circuit sets the second digital control signal to the value of the selected digital control signal, and the control circuit selects a first current value that is a first percentage smaller than the first reference current as the second reference current via the reference current selection signal; as well as During the second phase, the control circuit sets the second digital control signal to the value of the selected digital control signal, and the control circuit selects a second current value greater than the first reference current by a second tolerance percentage as the second reference current via the reference current selection signal.

19. The method of claim 14, wherein the comparison circuit comprises: providing, from a summing node of the comparison circuit, a current corresponding to a difference between the selected measurement current and the threshold current; In response to determining that the current is greater than zero, asserting a comparison signal by the current comparator; and In response to determining that the current is less than zero, a comparison signal is asserted by the current comparator.

20. The method according to claim 14, wherein the method further comprises: passing a threshold current across a first measuring resistor of the comparison circuit; passing the selected measuring current across a second measuring resistor of the comparator circuit; asserting a comparison signal by a voltage comparator of the comparison circuit in response to determining that the voltage drop at the first measurement resistor is greater than the voltage drop at the second measurement resistor; as well as In response to determining that the voltage drop across the first measuring resistor is less than the voltage drop across the second measuring resistor, a comparison signal is asserted by a voltage comparator of the comparison circuit.

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