Multi-channel sampling synchronization precision correction method based on RFSOC

Abstract

The invention belongs to the technical field of electromagnetic signal analysis, and particularly relates to a multichannel sampling synchronization precision correction method based on an RFSOC (Radio Frequency System On Chip), a plurality of RFSOC chips synchronously sample in parallel, an ADC (Analog to Digital Converter) high-speed data conversion module is integrated in each RFSOC chip, data acquisition is carried out through the ADC high-speed data conversion module, the acquired data is stored in an FIFO (First In First Out) in real time, and the accuracy of the FIFO is improved. And adjusting the output sequence of the FIFO storage according to the rising edge of the pulse signal. The ADC module of the RFSOC is used in the multi-channel high-speed sampling synchronization process, multiple chips are synchronized through pulse signals, multi-channel synchronous correction among the multiple chips is achieved, the number of needed peripheral circuits is small, collection channels are convenient to expand, additional ADC chips are not needed, and hardware resources can be saved; meanwhile, the signal transmission path is shortened, so that the synchronization precision of signal sampling can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of electromagnetic signal analysis, and in particular relates to a multi-channel sampling synchronization accuracy correction method based on RFSOC. Background Art

[0002] As the electromagnetic environment becomes more and more complex, the requirements for data acquisition are getting higher and higher, and the requirements for AD sampling accuracy, sampling rate and sampling channels are also getting higher and higher. As well as the demand for miniaturization, higher requirements are put forward for multi-channel high-speed sampling synchronization.

[0003] The existing solution mainly adopts ADC+FPGA+high-speed interface to design a high-speed synchronous sampling system, which mainly uses multiple ADC synchronization signals SYNC or FPGA internal IO delay to achieve multi-channel data synchronization. The SYNC synchronization signal is used to achieve the initial synchronization of multiple ADC acquisition signals, and the IO delay of data acquisition can be adjusted inside the FPGA to perform synchronous processing of each channel. The existing technology mainly realizes the acquisition and processing of multiple channels with a single chip, with many peripheral circuits, complex structure, and a limited number of expandable channels. Summary of the invention

[0004] In view of the various deficiencies in the prior art, the inventors have designed a multi-channel sampling synchronization accuracy correction method based on RFSOC in long-term practice. First, the design is miniaturized, and second, multiple chips are provided to collect multiple channels respectively to achieve synchronous correction among all channels.

[0005] The present invention provides a multi-channel sampling synchronization accuracy correction method based on RFSOC. Multiple RFSOC chips perform synchronous sampling in parallel. Each RFSOC chip integrates an ADC high-speed data conversion module. Data is collected through the ADC high-speed data conversion module. The collected data is stored in FIFO in real time. According to the rising edge of the pulse signal, the output order of the FIFO storage is adjusted. The method specifically includes the following steps:

[0006] Step 1: Add the same clock input to each RFSOC chip, and use the same clock source chip to generate ADC data sampling clock and synchronization clock;

[0007] Step 2: The synchronization clock is connected to the SYSREF synchronization pin of each RFSOC chip in a differential manner to perform the first internal chip synchronization to achieve data acquisition synchronization of each data channel inside the chip;

[0008] Step 3: Perform inter-chip synchronization processing; use a signal source to generate a pulse signal, connect it to the data acquisition pins of each RFSOC chip through a power divider, and store the sampled data in each chip;

[0009] Step 4: 1us before the signal source generates a pulse signal, start data acquisition, and each channel continuously collects 2us data and saves it in FIFO;

[0010] Step 5: Compare the sampling data of each channel of each chip with the timing of the pulse signal; when the pulse signal is collected, the high level is identified as 1, the low level is identified as 0, and a rising edge is generated when the level changes from low to high, and the sampling accuracy of each chip is synchronized by capturing the rising edge; when multiple channels of multiple chips are not completely synchronized, the channel with the largest rising edge count is used as the reference, and the corresponding count difference of the corresponding delay of other channels is used to determine the data sampling delay between each chip, and the subsequent data is stored according to the data sampling delay timing during data collection;

[0011] Step 6: When the data is finally collected, it is output according to the data sampling delay sequence to achieve synchronous correction of each channel between each chip.

[0012] Furthermore, in step one, four or eight of the ADC high-speed data conversion modules are integrated inside the RFSOC chip.

[0013] Furthermore, the clock source chip provides the clock in the form of a combination of LMX2594 chip + HMC987 chip.

[0014] Furthermore, in step two, the internal SYSREF programmable delay for setup / hold is automatically adjusted, which is done automatically within each module, using multiple periodic SYSREF pulses to determine the optimal delay value.

[0015] Furthermore, in step 2, all modules in the RFSOC chip capture SYSREF, and subsequent SYSREF edges are used to synchronize the phases of all frequency dividers to measure the delay of each FIFO.

[0016] Furthermore, in step 2, the measurement delay value of the FIFO and ADC Tile configuration is determined by running the chip's own XRFdc_MultiConverter_Sync function and setting the target to -1.

[0017] Furthermore, in step three, the collected data is stored in the FIFO inside each chip.

[0018] The beneficial effects of the present invention are:

[0019] In the multi-channel high-speed sampling synchronization process, the ADC module that comes with RFSOC is used to synchronize multiple chips through pulse signals, and a secondary synchronization operation is performed on the data to achieve multi-channel synchronization correction between multiple chips. In addition, fewer peripheral circuits are required and the acquisition channels can be easily expanded. Since no additional ADC chip is required, hardware resources can be saved. At the same time, since the signal transmission path is shortened, the synchronization accuracy of signal sampling can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a principle block diagram of the multi-channel sampling synchronization precision correction of the present invention;

[0021] Figure 2 It is a schematic diagram of the multi-channel data delay processing principle of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and implementation examples. These implementation examples are described in sufficient detail so that those skilled in the art can understand and practice the present invention. Without departing from the spirit and scope of the present invention, logical, achievable and other changes may be made to the implementation. Therefore, the following detailed description should not be construed as limiting, and the scope of the present invention is limited only by the claims.

[0023] See also Figure 1 The multi-channel sampling synchronization accuracy correction method based on RFSOC of the present invention is different from the previous external high-speed ADC chip, which requires a large number of peripheral hardware circuits. The present invention adopts the ADC high-speed data conversion module that comes with the RFSOC chip. According to the different models of the RFSOC chip, the number of ADC high-speed data conversion modules integrated in each RFSOC chip is also different. Some chips integrate 4 conversion modules, and some chips integrate 8 conversion modules.

[0024] The present invention can realize parallel synchronous sampling of multiple RFSOCs of the same model. The internal design of the RFSOC chip is as follows: Figure 1 As shown, each RFSOC chip collects data through the ADC high-speed data conversion module, and the collected data is stored in FIFO in real time. According to the rising edge of the pulse signal, the output order of the FIFO storage is adjusted. Since the hardware conditions do not change, the output order of the subsequent data sampling can be consistent with the pulse signal, and there is no need to recalibrate each time the acquisition is collected. The design scheme of the present invention does not require an additional ADC chip, which can save hardware resources. At the same time, since the signal transmission path is shortened, the synchronization accuracy of the signal sampling can be improved.

[0025] The present invention provides multiple chips to synchronously collect multiple channels to achieve synchronous correction among all channels. The specific steps are as follows:

[0026] Step 1: Add the same clock input to each RFSOC chip, use the same clock source chip to generate ADC data sampling clock and synchronization clock, and ensure that the clock sources of each chip are synchronized.

[0027] The present invention adopts the combination of LMX2594 chip + HMC987 chip to provide clock, and the LMX2594 chip generates sampling clock and synchronization clock, which are input into HMC987 chip. After passing through HMC987 chip, the clock is divided into 8 channels, which can be used by 8 ADCs. If more channels ADC sampling is required, the number of HMC chips can be increased accordingly to realize sampling channel clock expansion. Since the source of all clocks is the same clock chip (i.e. LMX2594 chip), the clock source synchronization of each sampling channel can be guaranteed.

[0028] Step 2: The synchronization clock is connected to the SYSREF synchronization pin of each RFSOC chip in a differential manner to perform the first internal chip synchronization to ensure that the data collected by each data channel inside the chip is synchronized.

[0029] The synchronous clock of the present invention is connected to the SYSREF synchronous pin of each RFSOC chip in a differential manner, and the internal SYSREF programmable delay for establishment / holding is automatically adjusted to ensure the safe capture of SYSREF. This is done automatically inside each module, and multiple periodic SYSREF pulses are required to determine the optimal delay value.

[0030] When all modules in the chip have safely captured SYSREF, the subsequent SYSREF edge is used to synchronize the phases of all dividers for measuring the latency of each FIFO. The delays can be adjusted to match the latency using the measurements of all channel acquisition modules.

[0031] The measured delay value of the FIFO and ADC Tile configuration is determined by running the chip's own XRFdc_MultiConverter_Sync function and setting the target to -1. This process is completed internally by the RFSOC, which can achieve the first synchronization between the channels in the chip.

[0032] Step 3: Perform inter-chip synchronization processing.

[0033] At this time, a signal source is used to generate a pulse signal, which is connected to the data acquisition pins of each RFSOC chip through a power divider, and the sampled data is stored in each chip. The pulse width of the pulse signal in this embodiment can be set by yourself, and is set to 1us in this system.

[0034] The collected data is stored in the FIFO inside each chip. Due to reasons such as path and timing, the data between channels may have different delays.

[0035] Step 4: Start data acquisition 1us before the signal source generates a pulse signal. At this time, each channel continuously collects 2us data and saves it in FIFO to ensure that the pulse signal is collected. By comparing the sampling data of each channel of each chip, it is found that the rising edge of the pulse signal is delayed in the storage position in the FIFO, so a second synchronization correction is required.

[0036] Step 5: Compare the timing of stored data and pulse signal.

[0037] When collecting pulse signals, a high level is recognized as 1 and a low level is recognized as 0. When the level changes from low to high, a rising edge will be generated. The sampling accuracy of each chip can be synchronized by capturing the rising edge.

[0038] like Figure 2 As shown in the figure, the gray "1" part in each FIFO indicates that the rising edge of the pulse signal has been collected. When collecting and storing data, the storage position of the rising edge in the FIFO can be determined by counting. If the count is 1000 when channel 1 collects the rising edge, and the count is 998 when channel 2 collects the rising edge, the data between the two channels is not completely synchronized. By delaying the starting position of the data in the FIFO, it is ensured that the rising edge of the pulse signal is stored in the same position in each FIFO. If the data between channel 1 and channel 2 is not completely synchronized as mentioned above, when outputting data, the channel 2 data can be delayed by 2 clocks so that the rising edge is output when the count is 1000, which is consistent with channel 1.

[0039] Similarly, when multiple channels of multiple chips are not completely synchronized, the channel with the largest rising edge count is used as the benchmark, and the corresponding count differences of the corresponding delays of other channels are used to determine the data sampling delay between each chip. Subsequent data collection is stored according to the determined delay sequence.

[0040] Step 6: When the data is finally collected, it is output according to the determined delay timing, thereby ensuring the synchronous correction of each channel between each chip.

[0041] The above description includes examples of one or more embodiments. Of course, it is impossible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but it should be recognized by those skilled in the art that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to cover all such changes, modifications and variations that fall within the scope of protection of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, the word is covered in a manner similar to the term "including", just as "including," is explained as a transitional word in the claims. In addition, any term "or" used in the specification of the claims is intended to mean "non-exclusive or".

Claims

1. A multi-channel sampling synchronization accuracy correction method based on RFSOC, characterized in that: Multiple RFSOC chips are sampled synchronously in parallel. Each RFSOC chip integrates an ADC high-speed data conversion module. Data is collected through the ADC high-speed data conversion module. The collected data is stored in FIFO in real time. According to the rising edge of the pulse signal, the output order of the FIFO storage is adjusted. Specifically, the following steps are included: Step 1: Add the same clock input to each RFSOC chip, and use the same clock source chip to generate ADC data sampling clock and synchronization clock; Step 2: The synchronization clock is connected to the SYSREF synchronization pin of each RFSOC chip in a differential manner to perform the first internal chip synchronization to achieve data acquisition synchronization of each data channel inside the chip; Step 3: Perform inter-chip synchronization processing; use a signal source to generate a pulse signal, connect it to the data acquisition pins of each RFSOC chip through a power divider, and store the sampled data in each chip; Step 4: 1us before the signal source generates a pulse signal, start data acquisition, and each channel continuously collects 2us data and saves it in FIFO; Step 5: Compare the sampling data of each channel of each chip with the timing of the pulse signal; when the pulse signal is collected, the high level is identified as 1, the low level is identified as 0, and a rising edge is generated when the level changes from low to high, and the sampling accuracy of each chip is synchronized by capturing the rising edge; when multiple channels of multiple chips are not completely synchronized, the channel with the largest rising edge count is used as the reference, and the corresponding count difference of the corresponding delay of other channels is used to determine the data sampling delay between each chip, and the subsequent data is stored according to the data sampling delay timing during data collection; Step 6: When the data is finally collected, it is output according to the data sampling delay sequence to achieve synchronous correction of each channel between each chip.

2. The multi-channel sampling synchronization accuracy correction method based on RFSOC according to claim 1 is characterized in that: In step 1, 4 or 8 ADC high-speed data conversion modules are integrated inside the RFSOC chip.

3. The multi-channel sampling synchronization accuracy correction method based on RFSOC according to claim 1 is characterized in that: The clock source chip provides the clock in the form of a combination of LMX2594 chip + HMC987 chip.

4. The multi-channel sampling synchronization accuracy correction method based on RFSOC according to claim 1 is characterized in that: In step two, this is done automatically within each module by automatically adjusting the internal SYSREF programmable delay for setup / hold, using multiple periodic SYSREF pulses to determine the optimal delay value.

5. The multi-channel sampling synchronization accuracy correction method based on RFSOC according to claim 4 is characterized in that: In step 2, all modules in the RFSOC chip capture SYSREF, and the subsequent SYSREF edge is used to synchronize the phases of all dividers to measure the delay of each FIFO.

6. The multi-channel sampling synchronization accuracy correction method based on RFSOC according to claim 5 is characterized in that: In step 2, the measurement delay value of the FIFO and ADC Tile configuration is determined by running the chip's built-in XRFdc_MultiConverter_Sync function with the target set to -1.

7. The multi-channel sampling synchronization accuracy correction method based on RFSOC according to claim 1 is characterized in that: In step three, the collected data is stored in the FIFO inside each chip.

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