Multi-cycle accumulated dual granularity co-quantizer circuit

Abstract

The application discloses a kind of double granularity cooperative quantizer circuit of multi-cycle accumulation, belongs to integrated circuit field, for high energy efficiency quantization circuit design.The circuit is composed of four parts of accumulation voltage temporary storage circuit, coarse granularity quantization circuit, fine granularity quantization circuit and post-processing unit circuit, analog calculation result is input into accumulation voltage temporary storage circuit, coarse granularity quantization is carried out by coarse granularity quantization circuit in multiple cycles, and the remaining accumulation voltage is quantized by fine granularity quantization circuit after multiple cycle calculation is completed, and the final quantization result is obtained by adding coarse and fine granularity results in proportion in post-processing circuit.Compared with traditional single-cycle quantizer, the circuit uses multi-cycle quantization design, avoids the problem of single-cycle quantization truncation error accumulation, improves quantization accuracy, and significantly reduces quantization circuit power consumption while ensuring accuracy, improves circuit energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a dual-granularity cooperative quantizer circuit for multi-cycle accumulation. Background Technology

[0002] The massive data processing resulting from the rapid development of artificial intelligence (AI) has led to the traditional von Neumann architecture facing the problems of "power wall" and "memory wall." The high power consumption and bandwidth limitations caused by frequent data movement between the processor and storage urgently necessitate a new computing volume architecture, giving rise to Computing-in-Memory (CIM) technology. In addition to the basic storage and read / write access functions of memory, CIM places multiply-accumulate (MAC) operations within the storage array, effectively reducing the repeated data movement between the processor and storage, saving significant energy, and greatly improving computing energy efficiency. CIM can be categorized into analog domain, digital domain, mixed domain, and time domain computing based on its computational method.

[0003] In both mixed-domain and analog-domain CIM (Computational In-Memory), multiplication-accumulation operations need to be converted into analog calculations. Input and stored data are represented by analog quantities such as voltage, current, or charge. Finally, the calculated analog results are quantized into digital quantities for subsequent digital processing. With the increasing demands for high precision in in-memory computation, and the further reduction in signal margin of analog signals due to circuit operating voltage limitations, the precision requirements for analog-to-digital converters (ADCs) are further increased. However, high-precision ADCs typically consume more power and introduce greater latency, which becomes a significant limitation in low-power scenarios.

[0004] Traditional analog quantization schemes convert analog results into digital values ​​using an ADC in each cycle, and then accumulate the results of each cycle using digital circuitry. This method is unsuitable for cycles with low computational complexity, as it increases the number of quantizations, leading to higher power consumption and additional storage overhead for the Partial Power Sum Accumulator (PSUM). Furthermore, due to the inherent conversion error introduced by the ADC, the numerous quantizations cause the PSUM error to accumulate, resulting in a shift in the final result. To achieve energy-efficient in-memory analog quantization, novel ADC designs are needed to address the single-cycle analog quantization problem. Summary of the Invention

[0005] This invention provides a dual-granularity cooperative quantizer (DGCQ) circuit for multi-cycle accumulation, which realizes multi-cycle accumulation quantization of analog quantities. By reducing the number of analog quantization cycles, the inherent conversion error accumulation of the ADC is reduced, and the power consumption of the quantization circuit is reduced while ensuring the calculation accuracy of analog quantization, thereby improving the overall energy efficiency.

[0006] This invention provides a multi-cycle accumulation dual-granularity cooperative quantizer circuit, including: an accumulation voltage temporary storage circuit, a coarse-grained quantizer and a fine-grained quantizer, and a post-processing unit circuit.

[0007] The accumulated voltage storage circuit consists of a control logic unit, four identical capacitors and four sets of corresponding switches, used to accumulate voltages of different periods, and output the accumulated voltage to the coarse-grained quantizer and the fine-grained quantizer according to the control logic.

[0008] The coarse-grained quantizer consists of a comparator circuit, a 4-bit counter circuit, and a voltage subtraction circuit. It is used to perform coarse-grained quantization based on the accumulated voltage of the accumulated voltage temporary storage circuit to obtain the coarse-grained quantization result.

[0009] The fine-grained quantizer is an 8-bit successive approximation register type analog-to-digital converter, used to perform fine-grained quantization based on the remaining accumulated voltage of the accumulated voltage temporary storage circuit to obtain the fine-grained quantization result.

[0010] The post-processing unit circuit is used to receive the coarse-grained quantization result of the coarse-grained quantizer and the fine-grained quantization result of the fine-grained quantizer, and quantize the coarse-grained quantization result and the fine-grained quantization result to obtain the analog quantization result.

[0011] Optionally, in one embodiment of the present invention, when the accumulated voltage storage circuit is working, the control logic unit accumulates the voltages of different cycles into four capacitors C1 of the same capacitance size in the accumulated voltage storage circuit. The four capacitors are composed of four branches connected in parallel. Each branch consists of a capacitor and a MOS transistor for capacitor discharge. Four sets of switches SW0 and SW1 control the voltage input and voltage output of the capacitors in the corresponding branches, respectively. Only one voltage input can be received from each of the four branches at the same time. The voltage input comes from the calculated voltages of different cycles. When the voltage Vs of the new cycle is ready, it will be transferred to the accumulated voltage storage circuit and share charge with the old accumulated voltage Vacc. The voltage Vs of the new cycle is stored in the capacitors C1 of the same capacitance size. The voltage output is output to the subsequent circuit for quantization output according to the control logic.

[0012] Optionally, in one embodiment of the present invention, when the coarse-grained quantifier is working, the switch SW2 in the voltage subtraction circuit is turned on to input the new accumulated voltage Vacc into the voltage subtraction circuit. At the same time, the new accumulated voltage Vacc is compared with Vcm through a comparator circuit to determine the behavior of the counter and the voltage subtraction circuit. Vcm is 1 / 4 of the power supply voltage Vdd. If the new accumulated voltage Vacc is not greater than Vcm, the voltage subtraction circuit realizes the output voltage Vota = 2 × Vacc, and Vacc is updated to Vota. If Vacc is greater than Vcm, the counter clock gets a rising edge, realizing the counter value incremented by one. At the same time, the voltage subtraction circuit realizes Vota = 2 × Vacc - Vref, where Vref = 1 / 2 Vdd, and Vacc is updated to Vota. This process is repeated multiple times in multiple cycles until it is determined that the multi-cycle calculation is complete.

[0013] Optionally, in one embodiment of the present invention, the fine-grained quantization circuit is started once after the coarse-grained quantization stage is completed. There is still a residual charge value in the capacitor of the voltage temporary storage circuit, denoted by Vacc. After the multi-cycle calculation is completed, the fine-grained quantization stage is entered. The remaining Vacc is sent to an 8-bit successive approximation register-type analog-to-digital converter to realize the fine-grained quantization of the remaining charge.

[0014] Optionally, in one embodiment of the present invention, after both coarse-grained quantization and fine-grained quantization are completed, the results of coarse-grained and fine-grained quantization are passed to the post-processing unit. The post-processing unit adds the coarse-grained quantization result Qcg[3:0] and the fine-grained quantization result Qfg[7:0] generated by the counter in proportion to obtain the final analog quantization result.

[0015] The multi-cycle accumulation dual-granularity cooperative quantizer circuit of this invention realizes the quantization of multi-cycle accumulation results of analog quantities in the analog or mixed domain, reducing the number of ADC activations and the accumulation of inherent ADC conversion errors. Simultaneously, by utilizing the dual-granularity cooperation of coarse-grained and fine-grained quantization, the power consumption of the quantization circuit is significantly reduced while ensuring accuracy requirements, thus improving circuit energy efficiency.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 A schematic diagram of a dual-granularity cooperative quantizer circuit for multi-cycle accumulation according to an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the working process and waveforms of the multi-cycle accumulation analog storage quantizer circuit according to an embodiment of the present invention. Detailed Implementation

[0020] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0021] Figure 1 This is a schematic diagram of a dual-granularity cooperative quantizer circuit for multi-cycle accumulation according to an embodiment of the present invention.

[0022] like Figure 1 As shown, the multi-cycle cumulative dual-granularity cooperative quantizer circuit includes four parts: an accumulation voltage (Vacc) temporary storage circuit, a coarse-grained quantizer (CGQ), a fine-grained quantizer (FGQ), and a post-processing unit (PPU).

[0023] The accumulated voltage storage circuit consists of a control logic unit, four identical capacitors, and four sets of corresponding switches. It is used to accumulate voltages of different periods and output the accumulated voltage to the coarse-grained quantizer and the fine-grained quantizer according to the control logic.

[0024] The coarse-grained quantizer consists of a comparator circuit, a 4-bit counter circuit, and a voltage subtraction circuit (VSC). It is used to perform coarse-grained quantization based on the accumulated voltage of the accumulated voltage storage circuit to obtain the coarse-grained quantization result.

[0025] The fine-grained quantizer is an 8-bit successive approximation register analog-to-digital converter (SAR ADC) used to perform fine-grained quantization based on the remaining accumulated voltage of the accumulated voltage buffer circuit to obtain the fine-grained quantization result.

[0026] The post-processing unit circuit is used to receive the coarse-grained quantization results from the coarse-grained quantizer and the fine-grained quantization results from the fine-grained quantizer, and to quantize the coarse-grained quantization results to obtain the analog quantization results.

[0027] The output of the accumulating voltage temporary storage circuit is connected to the non-inverting input of the amplifier in the voltage subtraction circuit, while the inverting input is connected to the reference voltage V through a resistor. ref The circuit is connected to the operational amplifier's output via a resistor, forming a feedback loop. Simultaneously, the output of the accumulating voltage buffer circuit is also connected to the non-inverting input of the amplifier in the comparator, while the inverting input is connected to the comparison voltage V. cm The output terminal controls the reference voltage input and is connected to the clock terminal of the first D flip-flop in the counter to realize the counting operation; the output terminal of the accumulating voltage temporary storage circuit is also connected to the successive approximation register type analog-to-digital converter for fine-grained quantization.

[0028] In one embodiment of the present invention, when the voltage accumulation temporary storage circuit is working, the control logic unit accumulates the voltage of different cycles into four capacitors C1 of the same capacitance size in the circuit. The four capacitors are composed of four branches connected in parallel. Each branch consists of a capacitor and a MOSFET for capacitor discharge. Four sets of switches SW0 and SW1 control the voltage input and voltage output of the capacitors in the corresponding branches, respectively. Only one voltage can be input at a time. The voltage input comes from the calculated voltage of different cycles. When the voltage Vs of the new cycle is ready, it is transferred to the voltage temporary storage circuit and shares charge with the old accumulated voltage Vacc. The voltage Vs of the new cycle is stored in C1 of the same capacitance size. The voltage output is output to the subsequent circuit for quantization output according to the control logic.

[0029] like Figure 2 As shown, the workflow of the dual-granularity collaborative quantizer circuit DGCQ is mainly divided into two parts: coarse-grained quantization stage and fine-grained quantization stage.

[0030] In one embodiment of the present invention, when the coarse-grained quantizer is operating, SW2 is turned on to input a new Vacc into the voltage subtraction circuit. Simultaneously, the new Vacc is compared with Vcm (1 / 4 of the power supply voltage Vdd) via a comparator circuit to determine the behavior of the counter and the voltage subtraction circuit. If Vacc is not greater than Vcm, the voltage subtraction circuit outputs a voltage Vota = 2 × Vacc, and Vacc is updated to Vota. If Vacc is greater than Vcm, the counter clock receives a rising edge, incrementing the counter value by one. Simultaneously, the voltage subtraction circuit outputs Vota = 2 × Vacc - Vref, where Vref = 1 / 2 Vdd, and Vacc is updated to Vota. This process is repeated multiple times over several cycles until the multi-cycle calculation is determined to be complete.

[0031] In one embodiment of the present invention, the fine-grained quantization circuit is activated once after the coarse-grained quantization stage is completed. There is still a remaining charge value, denoted by Vacc, in the capacitor of the accumulated voltage temporary storage circuit. After multi-cycle calculations are completed, the fine-grained quantization stage begins, and the remaining Vacc is fed into an 8-bit successive approximation register-type analog-to-digital converter to achieve fine-grained quantization of the remaining charge.

[0032] In one embodiment of the present invention, after both coarse-grained and fine-grained metricization are completed, the results of both coarse-grained and fine-grained metricization are passed to the post-processing unit. The post-processing unit then processes the coarse-grained metricization result Q generated by the counter. cg [3:0] and fine-grained quantization results Q fg [7:0] The final simulated quantization result is obtained by adding them in proportion (224:1).

[0033] The dual-granularity cooperative quantizer circuit for multi-cycle accumulation proposed in this invention reduces the number of ADC activations and the inherent conversion error accumulation of the ADC by quantizing the multi-cycle accumulation result of analog quantities in the analog or mixed domain. Simultaneously, a novel coarse-grained quantization circuit is proposed, utilizing the dual-granularity cooperation of coarse-grained and fine-grained quantization to significantly reduce the power consumption of the quantization circuit while ensuring accuracy requirements, thereby improving circuit energy efficiency.

[0034] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

Claims

1. A dual-granularity cooperative quantizer circuit for multi-cycle accumulation, characterized in that, include: Accumulated voltage storage circuit, coarse-grained quantizer and fine-grained quantizer and post-processing unit circuit; The accumulated voltage storage circuit consists of a control logic unit, four identical capacitors and four sets of corresponding switches, used to accumulate voltages of different periods, and output the accumulated voltage to the coarse-grained quantizer and the fine-grained quantizer according to the control logic. The coarse-grained quantizer consists of a comparator circuit, a 4-bit counter circuit, and a voltage subtraction circuit. It is used to perform coarse-grained quantization based on the accumulated voltage of the accumulated voltage temporary storage circuit to obtain the coarse-grained quantization result. The fine-grained quantizer is an 8-bit successive approximation register type analog-to-digital converter, used to perform fine-grained quantization based on the remaining accumulated voltage of the accumulated voltage temporary storage circuit to obtain the fine-grained quantization result. The post-processing unit circuit is used to receive the coarse-grained quantization result of the coarse-grained quantizer and the fine-grained quantization result of the fine-grained quantizer, and to quantize the coarse-grained quantization result and the fine-grained quantization result to obtain the analog quantization result; When the accumulated voltage storage circuit is working, the control logic unit accumulates the voltage of different cycles into four capacitors C1 of the same size in the accumulated voltage storage circuit. The four capacitors are composed of four branches connected in parallel. Each branch consists of a capacitor and a MOSFET for capacitor discharge. Four sets of switches SW0 and SW1 control the voltage input and voltage output of the capacitor in the corresponding branch, respectively. Only one voltage can be input at a time. The voltage input comes from the calculated voltage of different cycles. When the voltage Vs of the new cycle is ready, it will be transferred to the accumulated voltage storage circuit and share charge with the old accumulated voltage. The voltage Vs of the new cycle is stored in the capacitors C1 of the same size. The voltage output is output to the subsequent circuit for quantization output according to the control logic. The fine-grained quantizer is activated once after the coarse-grained quantization stage is completed. There is still a residual charge value voltage in the capacitor in the voltage temporary storage circuit. After multiple cycles of calculation are completed, the fine-grained quantization stage is entered. The remaining charge value voltage is sent to an 8-bit successive approximation register-type analog-to-digital converter to realize the fine-grained quantization of the remaining charge.

2. The multi-cycle cumulative dual-granularity cooperative quantizer circuit according to claim 1, characterized in that, When the coarse-grained quantizer is working, switch SW2 in the voltage subtraction circuit is turned on, inputting a new accumulated voltage Vacc into the voltage subtraction circuit. Simultaneously, the new accumulated voltage Vacc is compared with Vcm via a comparator circuit to determine the behavior of the counter and the voltage subtraction circuit. Vcm is 1 / 4 of the power supply voltage Vdd. If the new accumulated voltage Vacc is not greater than Vcm, the voltage subtraction circuit achieves an output voltage Vota = 2 × Vacc, and Vacc is updated to Vota. If Vacc is greater than Vcm, the counter clock receives a rising edge, incrementing the counter value by one. Simultaneously, the voltage subtraction circuit achieves Vota = 2 × Vacc - Vref, where Vref = 1 / 2 Vdd, and Vacc is updated to Vota. This process is repeated multiple times over multiple cycles until the multi-cycle calculation is considered complete.

3. The dual-granularity cooperative quantizer circuit with multi-cycle accumulation according to claim 1, characterized in that, After both coarse-grained quantization and fine-grained quantization are completed, the results of coarse-grained and fine-grained quantization are passed to the post-processing unit. The post-processing unit adds the coarse-grained quantization result Qcg[3:0] and the fine-grained quantization result Qfg[7:0] generated by the counter in proportion to obtain the final analog quantization result.

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