Satellite communication MIMO system high-speed data synchronous acquisition and transmission system

Abstract

The application relates to a high-speed data synchronous acquisition and transmission system suitable for a satellite communication MIMO system, the system comprising two acquisition and transmission subcards and a clock management unit; the acquisition and transmission subcard comprises a multichannel ADC acquisition unit and a multichannel DAC refreshing unit; the multichannel ADC acquisition unit of the acquisition and transmission subcard sends the acquired data to an FPGA for processing through a JESD204B interface, and then forwards the data through an optical module; the multichannel DAC refreshing unit of the acquisition and transmission subcard sends the data received by the optical module to the FPGA for processing, and then sends the data to a DAC through the JESD204B interface for interpolation filtering and IQ conversion and then refreshes and outputs to a radio frequency front end; the clock management unit utilizes the trigger signal of a clock chip to realign the phases of the device clock and the reference clock in each power-on process, so that the inter-board synchronization is realized. The system can improve the synchronization performance and reduce the power consumption.

Description

Technical Field

[0001] This application relates to the field of satellite communication technology, and in particular to a high-speed data synchronous acquisition and transmission system suitable for satellite communication MIMO systems. Background Technology

[0002] With the rapid development of science and technology, carrier signals in fields such as radar receivers, phased arrays, satellite communications, and aerospace are gradually evolving from high frequencies to radio frequencies, becoming increasingly complex. This complexity is mainly manifested in higher signal frequency limits, wider signal bandwidths, and faster signal transients. Furthermore, radio frequency signals possess advantages such as strong anti-interference capabilities, concentrated energy, long propagation distances, and high reliability, making them highly suitable for applications in low-Earth orbit (LEO) satellite communications. In the future, LEO satellite communications will also develop towards multiple-input multiple-output (MIMO) systems, using multiple transmit and receive antennas to achieve signal transmission and reception. Based on this, multi-channel synchronization technology has become one of the key technical indicators for system implementation. However, in practice, differences between transmit and receive channels can easily lead to aperture effects, causing beam gain reduction and beam deviation from the pre-controlled direction. To solve these problems, a solution is needed to eliminate inconsistencies between channels and control the signals of each transmit and receive channel within the expected phase difference. In multi-channel synchronization, especially in inter-board synchronization systems, the increasing complexity of multi-level clock trees exacerbates the problem of occasional phase ambiguity or phase shift caused by the phase detectors and frequency dividers within the clock chip. This becomes a key technical challenge for synchronous sampling of multiple ADCs and synchronous refresh of multiple DACs. While a single clock chip can meet the design requirements for intra-board multi-chip synchronization, phase synchronization between clock chips at each level of the clock tree is crucial when clocks are cascaded to achieve phase synchronization of multiple boards and channels.

[0003] In the field of low-Earth orbit satellite communication, multi-input multi-output systems often use separate boards to achieve multi-channel synchronization due to limitations in structural size and power consumption. However, due to the differences in connector delay and power-on cycles of various boards, achieving synchronization of acquisition and transmission of multiple channels has defects such as low synchronization accuracy and poor stability. At the same time, the increasingly complex multi-level clock tree architecture has made the clock skew and phase ambiguity problems of different channels caused by clocks increasingly prominent. Summary of the Invention

[0004] Therefore, it is necessary to provide a high-speed data synchronization acquisition and transmission system suitable for satellite communication MIMO systems that can improve synchronization performance and reduce power consumption, in order to address the above-mentioned technical problems.

[0005] A high-speed data synchronous acquisition and transmission system suitable for satellite communication MIMO systems is disclosed. The system includes two acquisition and transmission sub-cards and a clock management unit. The acquisition and transmission sub-cards include a multi-channel ADC acquisition unit and a multi-channel DAC refresh unit.

[0006] The multi-channel ADC acquisition unit of the acquisition and transmission sub-card sends the acquired data to the FPGA for processing through the JESD204B interface, and then forwards the data through the optical module;

[0007] The multi-channel DAC refresh unit of the acquisition and transmission sub-card sends the data received by the optical module to the FPGA for processing, and then sends it to the DAC through the JESD204B interface for interpolation filtering and IQ conversion before refreshing and outputting it to the RF front end;

[0008] The clock management unit uses the trigger signal of the clock chip to realign the phase of the device clock and the reference clock during each power-on process, thereby achieving inter-board synchronization.

[0009] The above applies to high-speed data synchronization acquisition and transmission systems for satellite communication MIMO systems. This application utilizes the elastic buffer built into the JESD204B interface to resolve the time delay difference between cross-board synchronization channels. Simultaneously, it uses the SYNC trigger signal of the clock chip to re-align the phases of the device clock and the reference clock during each power-up process, successfully solving the problem of non-synchronization between board receiving or transmitting channels caused by clock phase offset or phase ambiguity during different power-up processes. Furthermore, the parameters and technical specifications of the selected 4-channel ADC and DAC chips are studied and analyzed. By reducing the sampling rate of the ADC and the refresh rate of the DAC, the power consumption of the entire system is further optimized, ultimately achieving a power consumption of less than 0.6W for a single transceiver channel. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a high-speed data synchronous acquisition and transmission system applicable to a satellite communication MIMO system in one embodiment;

[0011] Figure 2 This is a schematic diagram of the ADC clock tree management unit architecture in one embodiment;

[0012] Figure 3 This is a schematic diagram of the DAC clock tree management unit architecture in one embodiment;

[0013] Figure 4 This is a flowchart illustrating a method for implementing a high-speed data synchronous acquisition and transmission system applicable to a satellite communication MIMO system, as shown in one embodiment. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0015] In one embodiment, such as Figure 1As shown, a high-speed data synchronous acquisition and transmission system suitable for satellite communication MIMO systems is provided, including two acquisition and transmission sub-cards and a clock management unit; the acquisition and transmission sub-cards include a multi-channel ADC acquisition unit and a multi-channel DAC refresh unit;

[0016] The multi-channel ADC acquisition unit of the acquisition and transmission sub-card sends the acquired data to the FPGA for processing through the JESD204B interface, and then forwards the data through the optical module;

[0017] The multi-channel DAC refresh unit of the acquisition and transmission sub-card sends the data received by the optical module to the FPGA for processing, and then sends it to the DAC through the JESD204B interface for interpolation filtering and IQ conversion before refreshing and outputting it to the RF front end;

[0018] The clock management unit uses the trigger signal of the clock chip to realign the phase of the device clock and the reference clock during each power-on process, thereby achieving inter-board synchronization.

[0019] The above describes a high-speed data synchronous acquisition and transmission system applicable to satellite communication MIMO systems. The system comprises two acquisition and transmission daughter cards and one clock management unit. The two daughter cards have identical hardware design and structural envelope. They interlock via the clock management unit board as a backplane, sending the intermediate frequency (IF) signal converted by the frequency converter module to multiple ADCs for parallel data acquisition. The data is processed by the FPGA and then forwarded by an optical module. Simultaneously, the optical module receives parallel data, processes it through the FPGA, refreshes it using multiple DACs, and outputs it to the RF front-end. Each daughter card has four ADC chips forming 16 parallel IF signal acquisition channels and four DAC chips forming 16 parallel IF signal transmission channels. Each daughter card also has a 4-transmit, 4-receive optical transceiver module with a single-channel transmission rate of up to 10Gbps, used to forward the data to be sampled by the ADCs and receive the data to be refreshed by the DACs. The multi-channel ADC acquisition unit of the daughter card sends the acquired data to the FPGA for processing via the JESD204B interface, and then forwards the data through the optical module. The multi-channel DAC refresh unit of the acquisition and transmission daughter card sends the data received by the optical module to the FPGA for processing, and then sends it to the DAC for interpolation filtering, IQ conversion, and refresh output via the JESD204B interface. The JESD204B interface is used, which has a built-in elastic buffer. During data transmission, the elastic buffer can buffer the signal and adjust the delay. When a delay difference occurs between cross-board synchronization channels, the elastic buffer can absorb or compensate for these delays, enabling better synchronization when data is transmitted between different boards. Both the ADC-encoded data and the DAC-decoded data from the acquisition and transmission daughter card are transmitted through the JESD204B interface. During this process, the elastic buffers in the link are active, ensuring that data transmission between different boards is not excessively affected by delay differences, thereby improving synchronization accuracy. This solves the problem of low synchronization accuracy caused by delay differences between cross-board synchronization channels and improves the system's synchronization performance. The clock management unit includes a control FPGA processor, an ADC clock tree management unit, and a DAC clock tree management unit. The clock management unit utilizes the SYNC trigger signal from the clock chip to re-align the phases of the device clock and the reference clock during each power-up process. During power-up, this trigger signal adjusts the clock phase, similar to a calibration mechanism, ensuring that the clocks of each board return to the correct phase relationship upon each power-up. The clocks of the two acquisition and transmission daughter cards and the clock management unit can all be calibrated using this trigger signal during power-up, avoiding asynchrony issues caused by inconsistent clock phases during initial power-up and significantly improving inter-board synchronization performance. This successfully overcomes the problem of poor inter-board synchronization performance. Simultaneously, the chip's power consumption is reduced by lowering the ADC sampling rate and DAC refresh rate.Ultimately, the power consumption of a single transceiver channel was reduced to less than 0.6W, meeting the system's low power requirements, and is especially suitable for satellite communication MIMO systems limited by factors such as structural size and power consumption.

[0020] In a specific embodiment, each acquisition and transmission daughter card includes four 4-channel ADC chips with a sampling rate of 122.88Mbps and a resolution of 16bit, and four 4-channel DAC chips with a refresh rate of 737.28MSPS and a resolution of 16bit. The ADC can sample quadrature modulation signals, and the DAC chip has an internal quadrature modulation output IQ signal.

[0021] Each ADC chip samples four channels of analog signals, then encodes, scrambles, and serializes the data before sending it to the FPGA chip for processing. The second-level clock chip of the ADC clock tree management unit fans out one 122.88MHz device clock for each ADC chip as the sampling clock and one accompanying clock as the reference clock SYSREF. It also fans out two channels to the FPGA chip for the core clock and reference clock of the JESD204B IP core, and four channels for the data transceiver clock to the GT Bank.

[0022] The FPGA simultaneously receives data from the optical module, processes the digital signal, and sends it to each DAC chip for interpolation filtering, quadrature modulation, and refresh before outputting. The second-level clock chip of the DAC clock tree management unit fans out one 737.28MHz device clock for each DAC chip as the refresh data clock and one accompanying clock as the reference clock SYSREF. It also fans out two paths to the FPGA chip for the core clock and reference clock of the JESD204B IP core, and four paths to the GT Bank for data transmission and reception.

[0023] In one embodiment, the clock management unit includes an FPGA processor management unit, an ADC clock tree management unit, and a DAC clock tree management unit.

[0024] In a specific embodiment, both the ADC clock tree management unit and the DAC clock tree management unit belong to a two-level clock tree architecture. The first-level clock tree uses a clock chip with an internally integrated dual phase-locked loop (PLL) architecture. The VCO multiplies the clock to the required frequency before distributing it to the second-level clock chip for clock allocation. The advantage of the two-level PLL is that the PLL1 loop bandwidth within the clock chip is relatively narrow, generally in the tens of Hz range, to suppress high-frequency phase noise of the input reference clock and eliminate clock jitter. The PLL2 operating loop is wider, used to fan out a high-frequency clock and improve the phase noise at the far end. At the same time, the RFSYNC pin of the first-level clock is connected to the clock pin of the FPGA control system to trigger the first-level output clock for phase synchronization after power-on stabilization.

[0025] In one embodiment, such as Figure 2 As shown, the ADC clock tree management unit is a two-level clock tree architecture, including a first-level clock chip and a second-level clock chip. The first-level clock chip outputs four clocks: two master clocks and two reference clocks, which are respectively given to the two clock chips in the second level. The reference clocks are used to trigger the RFSYNC pin to solve the phase ambiguity problem caused by the output of the second-level clock chip during power-up. The master clocks enter the CLKIN pin and are fanned out to each channel for frequency division before being sent to the ADC chip and the FPGA processor.

[0026] In one embodiment, the first-stage clock chip is a clock chip with an internally integrated dual-loop PLL architecture. The PLL1 loop inside the clock chip is narrower to suppress high-frequency phase noise of the input reference clock and eliminate clock jitter. The PLL2 loop inside the clock chip is wider to fan out a high-frequency clock and improve the phase noise at the far end.

[0027] In one embodiment, the RFSYNCIN pin of the first-stage clock chip is connected to the clock management unit to control the FPGA clock pin, and is used to trigger the first-stage output clock for phase synchronization after power-on stabilization.

[0028] In one embodiment, the first-stage clock chip is also used to receive one of the differential clocks after it is split into two, which enters PLL1 through the CLKIN0 differential port as the system master clock of the ADC unit, and the other is used as the system master clock of the DAC unit. The single-ended output of the voltage-controlled temperature-compensated crystal oscillator is selected and connected to the positive terminal of the OSCIN differential port of the first-stage clock chip as the input of PLL2. At the same time, the voltage control pin VC of the voltage-controlled temperature-compensated crystal oscillator is connected to the CPOUT1 pin of PLL1 to adjust the voltage control voltage, thereby adjusting the frequency deviation of the output clock of the temperature-compensated crystal oscillator across the entire temperature range and improving the phase noise capability.

[0029] In a specific embodiment, the ADC clock tree management unit is implemented as follows: one of the two paths of the 122.88MHz system differential clock is sent to the CLKIN0 differential port of the first-stage clock chip and enters PLL1 as the system master clock for the ADC unit. A 128.88MHz voltage-controlled temperature-compensated crystal oscillator (VC-TCXO) single-ended output is connected to the positive terminal of the OSCIN differential port as the input of the second-stage PLL. At the same time, the VC pin of the VC-TCXO is connected to the CPOUT1 pin of PLL1 to adjust the voltage control voltage, thereby adjusting the frequency offset of the output clock of the temperature-compensated crystal oscillator across the entire temperature range and improving phase noise capability.

[0030] like Figure 3 As shown, the architecture design of the DAC clock tree management unit is basically the same as that of the ADC clock tree management unit, with the only difference being the configuration of the clock chip, which will not be elaborated here.

[0031] In one embodiment, the second-stage clock chip simultaneously provides device clock and reference clock signals to both the ADC chip transmitter and the FPGA receiver. After allocation processing, the device clock is divided into frame clock and multi-frame clock. The multi-frame clock is aligned with the edge of the captured reference clock signal to ensure that the transmission delay of data from the ADC chip transmitter to the FPGA receiver is fixed and used to calculate the deterministic delay. The reference clock signal and the device clock meet the timing requirements. The leading edge alignment of the frame and multi-frame clocks is completed by capturing the edge of the reference clock signal through the falling or rising edge of the device clock, and the data in the elastic buffer is released with the aligned multi-frame clock edge as a reference.

[0032] In a specific embodiment, the ADC clock synchronization process is as follows: The second-level clock tree of the ADC simultaneously provides the device clock DCLK and the accompanying reference clock SYSREF signal to both the ADC transmitter and the FPGA receiver. After allocation processing, the device clock DCLK yields the frame clock and the multi-frame clock LMFC, where the LMFC is aligned with the edge of the captured SYSREF signal. The deterministic delay is closely related to the edge of the captured LMFC; the edges of the LMFC at the transmitter and receiver must be strictly aligned to ensure a fixed transmission delay between the transmitter and receiver for calculating the deterministic delay. The SYSREF signal and the device clock must meet timing requirements. The leading edge alignment of the frame and LMFC is completed by capturing the edge of SYSREF using the falling or rising edge of the device clock, and the data in the elastic buffer is released with the aligned LMFC edge as a reference. If the timing of the SYSREF signal and the device clock does not meet the setup and hold time requirements, the channel delay can be adjusted individually using the clock chip, with a minimum adjustment step accuracy of 25ps and a maximum adjustable range of 670ps.

[0033] In one embodiment, the multi-channel ADC acquisition unit includes multiple ADC chips; the FPGA performs an AND operation on the trigger signals of the clock chips of the multiple ADC chips and pulls them low simultaneously. After the device clock of each ADC chip detects the trigger signal of the clock chip being pulled low, it starts sending the K28.5 character after a delay at the next multi-frame clock edge; the FPGA receiver uses clock recovery technology to parse four consecutive K28.5 characters from the aligned data stream and then pulls the trigger signal of the clock chip high, indicating that the code group synchronization is complete; after the device clock of the ADC chip transmitter detects the trigger signal of the clock chip being pulled high, it stops sending the K28.5 character at the rising edge of the multi-frame clock. The FPGA uses the first non-K28.5 character detected as the starting frame of the next frame to complete the frame synchronization operation.

[0034] In a specific embodiment, the ADC unit code group synchronization (CGS) process is as follows: After clock synchronization, the FPGA performs an AND operation on the SYNC signals of multiple ADC chips and pulls them low simultaneously. Each ADC chip's device clock, upon detecting the SYNC signal going low, starts transmitting the K28.5 character after a delay on the next LMFC edge. The FPGA receiver uses clock recovery technology to parse four consecutive K28.5 characters from the aligned data stream and then pulls the SYNC signal high, indicating that CGS synchronization is complete. The ADC chip transmitter's device clock, upon detecting the SYNC signal going high, stops transmitting the K28.5 character on the rising edge of the LMFC edge. The FPGA uses the first detected non-K28.5 character as the starting frame for the next frame to complete the frame synchronization operation.

[0035] In one embodiment, after the code group synchronization is complete, the ILAS sequence is sent starting at the next multi-frame clock edge. The ILAS sequence length is generally composed of four or more multi-frame lengths. The last character of each multi-frame is the multi-frame alignment character / A / . The first, third, and fourth multi-frames begin with the character / R / and end with the character / A / . The second multi-frame contains the characters / R / and / Q / . The data after the character / Q / is the ADC link configuration parameters. The FPGA receiver compares the link configuration parameters in the second multi-frame sent by the ADC chip transmitter with those parameters. If they match, then... If the link parameters are verified to be correct, the JESD204B link establishment will fail if there is an error. After the last character / A / of the last ILAS multiframe is sent, the transmitter will start sending user data. After the FPGA receiver detects the / R / character, it stores the data after the / R / character in the ILAS sequence into the elastic buffer to ensure that the data of different channels arrives before the clock edge of the next multiframe. The data of all channels is aligned and data output begins. The elastic buffer is used to absorb variable delays in the link. The buffer depth ranges from 1 to K frames. K frames is the length of a multiframe.

[0036] In a specific embodiment, the ADC unit initial channel synchronization (ILAS) process is as follows: after CGS synchronization, the next initial channel synchronization process is performed. The main function of ILAS is to align all channels on the link, verify the link configuration parameters, and determine the position of the data stream in the receiver at frame and multi-frame boundaries. After CGS synchronization, the ILAS sequence is transmitted starting at the next LMFC edge. The ILAS sequence length is generally composed of four multi-frames (32 bytes) or more multi-frame lengths (F*K bytes). The last character of each multi-frame is the multi-frame alignment character / A / . The first, third, and fourth multi-frames begin with the character / R / and end with the character / A / . The second multi-frame contains the characters / R / and / Q / . The data after the character / Q / is the ADC link configuration parameters. The FPGA receiver compares the link configuration parameters in the second multi-frame transmitted by the ADC transmitter with those in the second multi-frame. If they match, it means the link parameters are verified correctly; otherwise, the JESD204B link establishment fails. After the last character / A / of the last ILAS multi-frame is transmitted, the transmitter will begin transmitting user data.

[0037] ADC Unit Link Channel Alignment Process: The transmission and reception of the ILAS sequence have specific timing requirements. First, all channels at the transmitting end begin outputting multi-frame ILAS data at the LMFC edge. Due to factors such as PCB trace delays and power cycle variations in each analog channel, the arrival times of data from different channels at the receiving end differ. After the receiving end detects the / R / character, it stores the subsequent data in the elastic buffer (BRD). As long as the last arrival time of data from different channels is before the next LMFC clock edge, the data from all channels can complete the alignment operation and begin data output. The deterministic delay cannot exceed one LMFC clock cycle. Otherwise, the phase relationship between the device clock and SYSREF needs to be readjusted so that the SYSREF edge is within the effective clock window. The receive buffer delay (BRD) directly determines the buffer depth, ranging from 1 to K frames (one multi-frame length), used to absorb variable delays in the link. The more multi-frames, the greater the allowed variable delay.

[0038] The link establishment process of the multi-channel synchronous JESD204B DAC unit is similar to that of the ADC, and will not be described in detail here.

[0039] In one embodiment, the multi-channel DAC refresh unit is composed of multiple DAC chips, and the JESD204B link synchronization process is similar to that of the multi-channel ADC acquisition unit. The clock tree architecture of the DAC clock tree management unit is the same as that of the ADC clock tree management unit. The difference is that the frequency of the first-stage clock chip VCO is 737.28MHz, and the configuration of the clock chips is different.

[0040] Finally, the phase consistency measurement between the ADC channels is performed by selecting one channel as the reference and comparing the phase of the remaining 31 channels with the reference channel to calculate the phase difference. The ADC is excited by an RF source outputting a sine wave of known frequency, which is then input to each analog channel through two cascaded power dividers and equal-length RF cables. The control FPGA controls the ADC's link establishment and data sampling process through the data interface with the FPGAs on each acquisition and transmission daughter card, and exports a portion of the user data sampled by the ADC, cached in the FPGA buffer, to the host computer. The host computer tool performs FFT calculations on the acquired waveforms to extract the phase information of each channel, thereby calculating the phase difference between the channel under test and the reference channel. In the initial testing, when significant phase differences were found between some channels, the timing relationship between the device clock and the SYSREF signal of the corresponding ADC chip clock channel could be adjusted to meet the phase difference with the reference channel, with a minimum adjustable step of 25 ps. Then, the relevant registers of the clock chip were reconfigured, and the system was repeatedly powered on and off to perform stress tests on the above process. The phase difference between the channel under test and the reference channel was observed to remain constant during different power-on processes, thus determining whether the multiple channels of the ADC unit met the synchronization requirements. In this implementation case, the phase difference of the 32 receiving channels was always within 1° during different power-on processes, as measured by the host computer, demonstrating excellent synchronization performance.

[0041] The phase consistency measurement of each channel in the DAC unit is similar to that of the ADC. After interpolation, filtering, and refreshing the received data, the DAC outputs an analog sine wave signal. Phase difference calculation can be performed by selecting one I-channel and one Q-channel as a reference, and comparing the phase of the remaining 15 I-channels and Q-channels with the reference channel to calculate the phase difference between the tested I-channel and the reference I-channel, as well as the phase difference between the tested Q-channel and the reference Q-channel. Testing methods for observing phase consistency include using a multi-channel high-speed oscilloscope or LabVIEW. However, conventional testing equipment cannot complete multi-channel testing at once; due to the limitation of the number of measurement channels, it is necessary to continuously change the tested channel until all channels have been polled and tested. This invention uses 32 stably synchronized ADC receiving channels for loop-through testing, but the accuracy of the measured phase difference is limited by the synchronization consistency index of the ADC receiving channels. In this embodiment, the phase difference of the 32 transmitting channels measured by loop-through testing using 32 stably synchronized receiving channels is within 3°, demonstrating excellent synchronization performance.

[0042] In one embodiment, such as Figure 4The diagram shows a flowchart of a high-speed data synchronization acquisition and transmission system applicable to satellite communication MIMO systems. The main steps include: After system power-on and initialization, the management FPGA configures the first-stage clock chip of the ADC and DAC clock tree, opens the main clock channel, and simultaneously synchronizes the second-stage output clock phase with the SCLK output pulse synchronization signal of the accompanying clock channel. The second-stage clock tree of the ADC and DAC is configured, each clock channel is opened, and the output device clock and SYSREF signal are configured. After the clock tree stabilizes, the management FPGA triggers the RFSYNC pin of the first-stage clock chip again to resynchronize the output reference clock to trigger the RFSYNC pin of the second-stage clock tree to align the SYSREF signals of each channel. After synchronization, the trigger signal and the SCLK synchronization pulse signal output by the first-stage accompanying clock are turned off. On the acquisition and transmission sub-card, the FPGA configures the registers of each ADC and DAC chip, and simultaneously receives the device clock DCLK and reference clock SYSREF signals from the second-stage clock chip. The device clocks of the ADC and DAC capture the edge-aligned SYSREF signal to complete frame clock and multi-frame clock alignment operations. The FPGA processor on the acquisition transmitter daughterboard resets the JESD204B IP cores used by the ADC and DAC. The FPGA processor on the acquisition transmitter daughterboard establishes a JESD204B link with multiple ADCs and DACs by controlling the SYNC signal. First, the waveform to be measured is input to the ADC. After sampling, a segment of data is extracted from the FPGA buffer and exported to the host computer for phase analysis and calculation of the waveforms acquired by the multiple ADCs. After determining the synchronization of the multiple ADC channels, the output waveforms of the multiple DACs are looped back in, sampled using the ADC, and the data is exported to the host computer for analysis and calculation of the phase difference between each I / Q channel of the DAC. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0043] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A high-speed data synchronous acquisition and transmission system suitable for satellite communication MIMO systems, characterized in that, The system includes two acquisition and transmission sub-cards and a clock management unit; the acquisition and transmission sub-cards include a multi-channel ADC acquisition unit and a multi-channel DAC refresh unit. The multi-channel ADC acquisition unit of the acquisition and transmission sub-card sends the acquired data to the FPGA for processing through the JESD204B interface, and then forwards the data through the optical module; The multi-channel DAC refresh unit of the acquisition and transmission sub-card sends the data received by the optical module to the FPGA for processing, and then sends it to the DAC through the JESD204B interface for interpolation filtering and IQ conversion before refreshing and outputting it to the RF front end. The clock management unit uses the trigger signal of the clock chip to realign the phases of the device clock and the reference clock during each power-on process, thereby achieving inter-board synchronization. The clock management unit includes an FPGA processor control unit, an ADC clock tree management unit, and a DAC clock tree management unit; The ADC clock tree management unit is a two-level clock tree architecture, including a first-level clock chip and a second-level clock chip. The first-level clock chip outputs four clocks, two main clocks and two reference clocks, which are respectively given to the two clock chips in the second level. The reference clocks are used to trigger the RFSYNC pin to solve the phase ambiguity problem caused by the output of the second-level clock chip during power-up. The main clocks enter the CLKIN pin and are fanned out to each channel for frequency division before being sent to the ADC chip and FPGA processor. The multi-channel ADC acquisition unit includes multiple ADC chips; the FPGA performs an AND operation on the trigger signals of the clock chips of the multiple ADC chips and pulls them low simultaneously. After the device clock of each ADC chip captures the trigger signal of the clock chip being pulled low, it starts sending the K28.5 character after a certain delay at the next multi-frame clock edge; the FPGA receiving end uses clock recovery technology to parse four consecutive K28.5 characters from the aligned data stream and then pulls the trigger signal of the clock chip high, indicating that the code group synchronization is complete; After the device clock of the ADC chip's transmitting end captures the trigger signal of the clock chip and pulls it high, it stops sending the K28.5 character on the rising edge of the multi-frame clock. The FPGA end will use the first non-K28.5 character detected as the starting frame of the next frame to complete the frame synchronization operation. After the code group is synchronized, the ILAS sequence is sent starting from the next multi-frame clock edge. The ILAS sequence length is generally composed of four or more multi-frame lengths. The last character of each multi-frame is the multi-frame alignment character / A / . The first, third, and fourth multi-frames begin with the character / R / and end with the character / A / . The second multi-frame contains the characters / R / and / Q / . The data after the character / Q / is the ADC link configuration parameter. The FPGA receiver compares the link configuration parameter in the second multi-frame sent by the ADC chip transmitter with the FPGA receiver. If they match, it indicates that the link parameters are correct. If the verification is successful, the JESD204B link establishment will fail if an error occurs. After the last character / A / of the last ILAS multiframe is sent, the transmitter will start sending user data. After the FPGA receiver detects the / R / character, it stores the data following the / R / character in the ILAS sequence into a flexible buffer to ensure that the data from different channels arrives before the clock edge of the next multiframe. All channels complete the data alignment operation and begin data output. The flexible buffer is used to absorb variable delays in the link. The buffer depth ranges from 1 to K frames, where K frames is the length of a multiframe.

2. The system according to claim 1, characterized in that, The first-stage clock chip is a clock chip with an internally integrated dual-loop PLL architecture. The PLL1 loop inside the clock chip is used to suppress high-frequency phase noise of the input reference clock and eliminate clock jitter. The PLL2 working loop inside the clock chip is wider and is used to fan out a high-frequency clock and improve the phase noise at the far end.

3. The system according to claim 1, characterized in that, The RFSYNCIN pin of the first-stage clock chip is connected to the clock management unit to control the FPGA clock pin. After power-on and stabilization, it is used to trigger the first-stage output clock for phase synchronization.

4. The system according to claim 2, characterized in that, The first-stage clock chip is also used to receive one of the differential clocks after it is split into two, which enters PLL1 through the CLKIN0 differential port as the system master clock of the ADC unit. The other one is used as the system master clock of the DAC unit. The single-ended output of the voltage-controlled temperature-compensated crystal oscillator is selected and connected to the positive terminal of the OSCIN differential port of the first-stage clock chip as the input of PLL2. At the same time, the voltage control pin VC of the voltage-controlled temperature-compensated crystal oscillator is connected to the CPOUT1 pin of PLL1 to adjust the voltage control voltage, thereby adjusting the frequency deviation of the output clock of the temperature-compensated crystal oscillator in the entire temperature range and improving the phase noise capability.

5. The system according to claim 1, characterized in that, The second-stage clock chip simultaneously provides device clock and reference clock signals to both the ADC chip transmitter and the FPGA receiver. After allocation processing, the device clock is divided into frame clock and multi-frame clock. The multi-frame clock is aligned with the edge of the captured reference clock signal to ensure that the transmission delay between the data transmitter and the FPGA receiver is fixed and used to calculate the deterministic delay. The reference clock signal and the device clock meet the timing requirements. The leading edge alignment of the frame and multi-frame clocks is completed by capturing the edge of the reference clock signal through the falling or rising edge of the device clock, and the data in the elastic buffer is released with the aligned multi-frame clock edge as a reference.

6. The system according to claim 1, characterized in that, The multi-channel DAC refresh unit is composed of multiple DAC chips, and the JESD204B link synchronization process is similar to that of the multi-channel ADC acquisition unit. The clock tree architecture of the DAC clock tree management unit is the same as that of the ADC clock tree management unit. The difference is that the frequency of the first-stage clock chip VCO is 737.28MHz, and the configuration of the clock chips is different.

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