Bit level mode retimer

Abstract

The invention relates to a bit level mode retimer. Some examples of retimer circuitry, systems, and methods are disclosed. In some embodiments, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to receive the phase control signal, generate an output clock signal based on the phase control signal, and provide the output clock signal to the transmitter to track a data packet of the data component.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of June 15, 2022, an invention name of “Bit-level mode retimer”, and an application number of 202210677397.2. Technical Field

[0003] The present application relates to a bit-level mode retimer. Background Art

[0004] A retimer (also called a retimer) generally refers to a circuit with a clock data recovery circuit that retimes the signal. Retimers can be used to extend the physical length of a system by creating separate clock domains on either side of the retimer. With the advent of carrier systems in telecommunications (especially T1 and E1), retimers began to gain importance. For example, some conventional carrier systems carry multi-channel voice circuits on shielded twisted pair cables, with a retimer installed every several thousand feet.

[0005] Without a retimer or redriver, the integrity of the signal transmitted in the system degrades as the frequency or data rate of the signal and / or the length of the transmission line increases. By using repeaters between connected devices, the signal degradation problem on the interface can be solved. Repeaters can be implemented as retimers or redrivers. Retimers and redrivers can restore or enhance the signal integrity of data as it is transmitted between connected devices. Summary of the invention

[0006] According to some implementations, a retimer circuit system includes a clock data recovery circuit system coupled between a receiver and a transmitter. The clock data recovery circuit system is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Also included in the retimer circuit system is a phase interpolator circuit system coupled to the clock data recovery circuit system. The phase interpolator circuit system includes a phase interpolator, which is configured to: receive the phase control signal, generate an output clock signal based on the phase control signal, and provide the output clock signal to the transmitter to track data packets of the data component.

[0007] In some embodiments, the retimer circuit system further includes an analog / digital converter coupled between the receiver and the clock data recovery circuit system. In some embodiments, the retimer circuit system further includes another phase interpolator of the phase interpolator circuit system. The other phase interpolator is configured to: receive the phase control signal, generate another output clock signal based on the phase control signal, and provide the other output clock signal to the analog / digital converter. The analog / digital converter is configured to generate the input data signal based on the other output clock signal. In some embodiments, one or more electrical characteristics of the other phase interpolator match one or more electrical characteristics of the phase interpolator. In some embodiments, the phase interpolator and the other phase interpolator are configured to control the phase of the basic clock signal by processing the control code of the phase control signal, and generate a corresponding output clock signal based on the phase control signal.

[0008] In some implementations, the retimer circuitry further includes a digital filter coupled between the clock data recovery circuitry and the phase interpolator. The digital filter is configured to perform digital filtering of the phase control signal to remove or reduce one or more frequency components associated with jitter noise. In some implementations, the digital filter includes one or more low pass filters. In some implementations, the low pass filter may include one or more moving average filters. For example, two or more moving average filters may be coupled in series and have the same or different configurations.

[0009] In some embodiments, the moving average filter may be configured according to: OUT(m,next)=OUT(m,previous)+1 / m(X(n+1)-X(n-m+1)), where OUT(m) is the smoothed output of the moving average filter, X(n) is the control code sequence of the phase control signal, and m is the division factor. In some other embodiments, the moving average filter is configured according to: OUT(n)=OUT(n-1)+1 / N(P(n)-P(nN)), where OUT(n) is the smoothed output of the moving average filter, P(n) is the control code sequence of the phase control signal, N=2^m, and m is the division factor. In some embodiments, the moving average filter includes two or more m-bit shift circuits, two or more delay units, and two or more adders.

[0010] In some implementations, a retimer system includes: a first device, a second device, and a data interface connecting the first and second devices. The data interface includes a repeater. The repeater includes clock data recovery circuitry coupled between a receiver communicating with the first device and a transmitter communicating with the second device. The repeater further includes phase interpolator circuitry coupled to the clock data recovery circuitry.

[0011] In some implementations, a retiming method includes extracting a data component from an input data signal associated with a receiver, providing the data component to a transmitter, generating a phase control signal, generating an output clock signal based on the phase control signal, and providing the output clock signal to the transmitter to track data packets of the data component.

[0012] In some implementations, the retiming method further includes performing digital filtering on the phase control signal to remove or reduce one or more frequency components associated with jitter noise. For example, the digital filtering may include low-pass filtering.

[0013] A further understanding of the nature and advantages of the various embodiments may be obtained by reference to the remainder of the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A is a block diagram depicting an example of a data transmission system in the form of a serial interface communication system 100 .

[0015] Figure 1B is a block diagram depicting examples of some implementations of the system 100 in which the bus includes one or more repeaters 108 .

[0016] Figure 2 is a block diagram depicting an example of a retimer 200 according to some embodiments.

[0017] Figure 3 is a block diagram depicting an example of a moving average filter 300 according to some implementations of the digital filter.

[0018] Figure 4 is a block diagram depicting an example of a low pass filter 400 including at least two moving average filters 404a and 404b according to some implementations of the digital filter.

[0019] Figure 5 is a flow chart depicting an example of a retiming method 500 performed according to some embodiments. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to specific embodiments. Examples of these embodiments are illustrated in the accompanying drawings. It should be noted that these examples are described for illustrative purposes and are not intended to limit the scope of the present disclosure. Specifically, alternatives, modifications and equivalents of the described embodiments are included within the scope of the present disclosure as defined by the appended claims. In addition, in order to facilitate a thorough understanding of the described embodiments, specific details may be provided. Some embodiments within the scope of the present disclosure may be practiced without some or all of these details. Further, for the sake of clarity, well-known features may not be described in detail.

[0021] Some disclosed embodiments relate to retimers that are primarily implemented in the digital domain to actively retransmit new copies of data packets of an input data signal using a clean clock. Some examples of the disclosed retimers can be implemented in applications to provide enhanced reach. Examples of such applications include, but are not limited to: reaching corners of large printed circuit boards (PCBs), using additional connectors, supporting daughter cards, reaching expansion racks, compensating for the use of inferior PCB materials, and enhancing device operation.

[0022] Some embodiments of the present disclosure relate to a retimer circuit system and technique for phase control by generating a phase control code from a clock data recovery circuit (CDR) and sending the phase control code to a phase interpolator (PI) in communication with a transmitter (Tx) via a digital filter. The phase control code controls the PI, and the output clock signal of the PI is passed to the Tx to track parallel data streams or other portions of data components extracted by the CDR from an input data signal and provided by the CDR to the Tx.

[0023] In some implementations, a digital filter coupled between the CDR and the PI is configured to improve the signal quality of the phase control signal carrying the phase control code by digital signal conditioning. For example, the digital filter may perform high-frequency filtering in the digital domain on the phase control signal to reduce jitter noise. In some implementations, the digital filter includes one or more low-pass finite impulse response (FIR) filters. For example, the low-pass FIR filter may be implemented to include one or more moving average (MA) filters. Such MA filters are configured to smooth the discrete time data of the phase control signal, that is, to remove the undesirable high-frequency components of the phase control signal, because the high-frequency components of the signal typically represent jitter noise. In addition or alternatively, other types of low-pass FIR filters may be incorporated into the digital filter, and low-pass infinite impulse response (IIR) filters may also be incorporated into the digital filter.

[0024] Some implementations of the retimer circuitry and techniques disclosed herein may be practiced using various transmission protocols, such as those used to transmit serial data between connected devices. Examples of such protocols include the DisplayPort standard, the High Definition Multimedia Interface (HDMI) standard, the Serial ATA standard, the Peripheral Component Interconnect Express (PCI-E) standard, the Universal Serial Bus (USB) standard, the HyperTransport protocol, the Infiniband protocol, the XAUI protocol, and the Ethernet protocol. Over time, each of these protocols has evolved to include multiple generations, and at least for some protocols, each generation has multiple versions. The serial interface may be implemented according to any of these standards using either single-ended or differential signaling.

[0025] It should be noted that the circuits and techniques implemented by the present disclosure are more generally applicable. For example, any serial or parallel interface or protocol can benefit from the techniques described herein. Therefore, the scope of the present disclosure should not be limited by such embodiments.

[0026] Figure 1A is a block diagram depicting an example of a data transmission system in the form of a serial interface communication system 100. The system 100 may be implemented according to any of the various transmission protocols mentioned above, including, for example, the DisplayPort standard, the HDMI standard, the Serial ATA standard, the PCI-E standard, the USB standard, the HyperTransport protocol, the Infiniband protocol, the XAUI protocol, the Ethernet protocol, or any generation and / or version of each.

[0027] System 100 includes an upstream device 102, a downstream device 104, and a serial bus 106. It should be appreciated that system 100 may be a two-way communication system where upstream device 102 is capable of transmitting and receiving, and downstream device 104 is capable of transmitting and receiving.

[0028] It should also be appreciated that bidirectional implementations of system 100 may include full-duplex implementations and half-duplex implementations with switching interfaces for Tx and receiver (Rx) ports. It should further be appreciated that system 100 may be a unidirectional communication system in which upstream device 102 is capable of transmitting and downstream device 104 is capable of receiving.

[0029] Figure 1Bis a block diagram depicting examples of some implementations of system 100, wherein a bus includes one or more repeaters 108, which are examples of intermediate high-speed signal conditioning transceivers. Repeaters may be coupled in series, wherein the number of such devices depends on the trace or cable length of the bus. Repeater 108 may be used as a serial link driver interface for serial bus 106, or multiple repeaters 108 may be used to provide a serial link driver interface for serial bus 106. Further, it should be appreciated that serial bus 106 includes traces or cables formed in or using a transmission medium, such as a conductive material or other means for propagating electrical signals. It should be further appreciated that implementations of serial bus communication system 100 including one or more repeaters may be full-duplex bidirectional, half-duplex bidirectional, or unidirectional, such as for Figure 1A as described.

[0030] exist Figure 1A and 1B In the embodiment of the present invention, the upstream device 102 may be implemented in a larger device or system, such as any of a variety of integrated circuits or devices, including, but not limited to, input / output (I / O) hubs, root complexes, servers and laptop docking stations, etc. In addition, it should be appreciated that the downstream device 104 may be implemented in a larger device or system, such as any of a variety of peripheral devices, including, but not limited to, hard drives, graphics cards and daughter cards, etc. It should be appreciated that references to upstream devices and downstream devices are for purposes of example, and the examples of upstream devices 102 and downstream devices 104 listed above may correspond to terminal communication devices of a serial standard that does not utilize a hierarchical topology.

[0031] Communication via the serial bus 106 may use a differential or single-ended signaling protocol. For example, the upstream device 102 may include a differential output driver (not shown) for providing differential signals. The repeater 108 (when present) processes output transmissions from the upstream device 102 to provide such processed output transmissions to another repeater or directly to the downstream device 104. The downstream device 104 may include a differential input driver (not shown). There are many known differential digital signaling protocols that can be used with the serial bus communication system 100, such as, for example, differential stub series terminated logic (SSTL), differential high-speed transceiver logic (HSTL), low voltage differential signaling (LVDS), differential low voltage positive emitter coupled logic (LVPECL), and reduced swing differential signaling (RSDS), as well as other differential digital signaling protocols. Furthermore, implementations using single-ended serial interface protocols are contemplated, such as, for example, low voltage transistor-transistor logic (LVTTL) (such as used for PCI) and low voltage complementary metal oxide semiconductor (LVCMOS), as well as other single-ended serial interface protocols. Conventionally, PCI uses LVTTL input buffers and push-pull output buffers.

[0032] Figure 2 2 is a block diagram depicting an example of a retimer 200 that can be used as a repeater in some implementations. The retimer 200 is implemented primarily in the digital domain using a combination of circuit components described herein. The retimer 200 includes a Tx port 204 and an Rx port 208 for connecting to an upstream device or a downstream device. In the depicted example, the ports 204 and 208 of the retimer 200 employ differential signaling; however, single-ended implementations are also possible.

[0033] exist Figure 2 , retimer 200 includes Tx 212 at Tx port 204 and Rx 216 at Rx port 208. Tx 212 may be any circuit system or device capable of transmitting a signal, including a signal carrying data. By way of illustration, Tx may include a light emitting diode (LED) or a laser diode. Rx 216 may be any circuit system or device capable of receiving a signal.

[0034] exist Figure 2, coupled to Rx 216 is a continuous time linear equalizer (CTLE) 220, which may be incorporated to process the signal received from Rx 216 and equalize frequency-dependent losses in the signal, such as those experienced in a communication channel. The output of CTLE 220 is coupled to the input of an analog-to-digital converter (ADC) 224, which converts the equalized signal from CTLE 220 into a digital data signal. For example, ADC 224 may be implemented as a 5-bit time-interleaved ADC. ADC 224 has an output that is coupled to deliver the digital data signal to the input of CDR 228, which in this example optionally includes an integrated decision feedback equalizer (DFE) 232. DFE 232 may be used as a nonlinear equalizer to suppress inter-symbol interference (ISI) due to channel imperfections such as high-frequency losses and notches. The data output 236 of the CDR 228 is coupled to a first-in, first-out circuit (FIFO) 240, which processes the data components extracted by the CDR 228 and outputs them to the Tx 212, as illustrated. In particular, the FIFO 240 is coupled between the CDR 228 and the Tx 212 and is configured as a buffer for transferring data packets of data components from the CDR 228 to the Tx 212. In some implementations, the FIFO 240 transfers the data packets as multi-bit parallel data signals, while in some other implementations, the FIFO 240 operates in a serial manner to transfer the data packets sequentially.

[0035] exist Figure 2 , the CDR 228 of the retimer 200 is of a digital type, particularly a phase interpolator based CDR, which is configured to communicate with a PI, as opposed to a conventional analog type CDR that typically communicates with an analog circuit system such as a phase locked loop (PLL). The retimer 200 further includes: a first PI 244 coupled between a PI control output 246 of the CDR 228 and the ADC 224, and a second PI 248 coupled between the PI control output 246 and the Tx 212. The first PI 244 is associated with the Rx 216, while the second PI 248 is associated with the Tx 212. A digital filter 252 is coupled between the PI control output 246 and the second PI 248. In this example, the first PI 244 can be implemented using four different phase clock inputs and an adjustable current source to update the phase output of the sampling clock provided as an output clock signal to the ADC 224.

[0036] exist Figure 2In the embodiment of the present invention, for example, when implemented on the same chip, the electrical characteristics of the first PI 244 are replicated or closely matched by the second PI 248. Configuring the second PI 248 in this manner is beneficial because PIs are generally available circuits in chip design and manufacturing. The same phase control of the first PI 244 and the second PI 248 is provided by passing the same phase control signal from the PI control output 246 of the CDR 228 to the first PI 244 and the second PI 248. The clock output 260 of the second PI 248 can pass the output clock signal to the Tx to accordingly track the parallel data streams of the data components provided from the FIFO 240 to the Tx 212.

[0037] exist Figure 2 In some embodiments, the system PLL (SysPLL) 256 may be located outside the retimer 200, but in this example it is illustrated as part of the retimer 200 for ease of understanding. By way of illustration, the SysPLL 256 may be implemented as an all-digital PLL (ADPLL). The SysPLL 256 outputs a base clock signal to both the first PI 244 and the second PI 248. The phase control signal passed from the CDR 228 to the first and second PIs 244 and 248 controls the PIs 244 and 248 to change the phase of the base clock signal. Each PI generates a corresponding output clock signal accordingly. The first PI 244 provides the output clock signal to the ADC 224, and the second PI 248 can set the output clock signal at the clock output 260, where this output clock signal is aligned with the data stream provided at the Tx 212.

[0038] In operation, the CDR 228 tracks the incoming bit stream of the digital data signal mentioned above and extracts the embedded clock signal and data components from the bit stream. In this example, the CDR 228 does this by checking the phase information of the data sampled by the ADC 224 and continuously updating the phase control signal to the first PI 244. If the CDR 228 finds that the sampled data is ahead of the output clock signal provided from the first PI 244 to the ADC 224, then the CDR 228 updates the phase control signal to increase the clock frequency accordingly, and vice versa. The goal is to align the basic clock signal generated by the SysPLL 256 with the embedded clock signal and sample the data at the optimal timing.

[0039] In this example, CDR 228 collects sampled data over a specific period of time and uses statistical methods to determine whether and when to update the phase control signal. In some implementations, CDR 228 may also filter out some undesirable data patterns in the bit stream to prevent the generation of erroneous phase control signals.

[0040] In one example, the phase control signal passed to the first and second PIs 244 and 248 is 34 bits and can be classified into two parts: a 2-bit quadrant part and a 32-bit code part. For example, the phase control signal can be updated up to 2 bits at a time (1 bit in the quadrant part and 1 bit in the code part) to avoid coupling in the physical circuit system. In such a case, the phase control signal updates 1 bit most of the time and only updates 2 bits when the quadrant changes.

[0041] exist Figure 2 244. In this example, by way of illustration, ADC 224 may be implemented as a flash 5-bit ADC with 2-bit interpolation. For example, ADC 224 may include four time-interleaved ADCs with an input bandwidth greater than 10 GHz. For example, the sampling clock of ADC 224 may run at 5 GHz with an effective number of bits (ENOB) greater than 4.5 bits. In such an implementation, DFE 232 may receive the output data of the four time-interleaved ADCs and process / optimize the DFE coefficients accordingly. CDR 228 may apply an algorithm to adjust early / late sampling based on the output clock signal from PI 244.

[0042] exist Figure 2 In the embodiment of the present invention, the digital filter 252 is coupled between the CDR 228 and the second PI 248 and is configured to perform high frequency filtering on the phase control signal in the digital domain to mitigate switching of the phase control signal of the PI control output 246 from the CDR 228. The digital filter 252 can be implemented using a customized transfer function to filter the phase control code of the phase control signal before the phase control code is input to the second PI 248.

[0043] Internal digital logic, state machines, and / or microcontrollers may be used to control and otherwise manage components of the retimer 200, including the CTLE 220, ADC 224, CDR 228, FIFO 240, digital filter 252, and first and second PIs 244 and 248. The internal digital logic, state machines, and / or microcontrollers may also manage automatic adaptation of the CTLE 220 and DFE 232, and implement protocol link training and status updates.

[0044] In some embodiments, a digital filter (e.g. Figure 2 The digital filter 252) includes one or more low-pass FIR or IIR filters. For example, the low-pass FIR filter can be implemented to include one or more cascaded MA filters to smooth the discrete time data of the phase control signal. In some embodiments, the MA filter can be configured to have a sliding window structure, where the size of the window is a division factor. For example, the MA filter can operate according to the following formula:

[0045] OUT(m, next) = OUT(m, previous) + 1 / m(X(n + 1) - X(n - m + 1)), where:

[0046] OUT(m) is the output data;

[0047] X(n) is the sampled input data, for example, the phase control code sequence of the phase control signal output from the CDR to control the PI;

[0048] n = 0, 1, 2, …; and

[0049] m is a division factor such as 8, 16, 32, 64, 128, 256, etc.

[0050] In the above formula, when calculating the next MA value, the logic of the MA filter adds the new sampled data (X(n + l)) and subtracts the old sampled data (X(n - m + l)). Such an implementation of the MA filter is desirable when compared with some conventional low - pass FIR filters because the disclosed MA filter can be implemented using adders and subtractors, i.e., no multipliers are required.

[0051] Figure 3 is a block diagram depicting an example of an MA filter 300 according to some embodiments of a digital filter (such as Figure 2 digital filter 252). In this example, the MA filter 300 is implemented using two m - bit shift circuits 304 and 308 instead of the multipliers of a conventional low - pass FIR filter. In Figure 3 the MA filter 300 operates according to the following formula:

[0052] OUT(n) = OUT(n - 1) + 1 / N(P(n) - P(n - N)), where:

[0053] OUT(n) is the output data;

[0054] P(n) is the sampled input data, for example, the phase control code sequence of the phase control signal output from the CDR to control the PI;

[0055] n = 0, 1, 2, …; and

[0056] N = 2^m, where m is a division factor such as 8, 16, 32, 64, 128, 256, etc.

[0057] In Figure 3, the MA filter 300 includes N delay units 312a, 312b, 312c ... 312N, which are coupled in series to receive P(n) at the input and generate P(nN). P(n) is also provided as an input to the shift circuit 304, and P(nN) is provided as an input to the shift circuit 308. In this example, at the first adder 316, the output of the shift circuit 308 is subtracted from the output of the shift circuit 304. The second adder 320 receives the output of the first adder 316 and interacts with another delay unit 324 to generate OUT(n) based on OUT(n-1) and l / N(P(n)-P(nN)) according to the above formula.

[0058] Figure 4 4 is a block diagram depicting an example of a low pass filter 400 including at least two cascaded MA filters 404a and 404b according to some implementations of a digital filter. In this example, the phase control signal output from the CDR 408 is first smoothed by the MA filter 404a and then by the MA filter 404b. In this example, the output of the MA filter 404b is provided to a binary-to-thermometer 412 for binary-to-thermometer decoding and then delivered to another component, such as a PI. In this example, both MA filters operate according to the previous formula, namely:

[0059] OUT(n)=OUT(n-1)+1 / N(P(n)-P(nN)), where

[0060] OUT(n) is the output data;

[0061] P(n) is the sampled input data, e.g., a phase control code sequence of a phase control signal output from a CDR to control the PI; and

[0062] n=0,1,2,…。

[0063] However, in Figure 4 In the example of , by way of illustration, MA filter 404a supports N = 8, 16, 32, and 64, while MA filter 404b supports N = 4. In other examples, N may be 2, 4, 8, 16, 32, 64, 128, 256, or 512 for either or both of MA filters 404a and 404b.

[0064] Figure 5 is a flow chart depicting an example of a retiming method 500 performed according to some embodiments. Figure 5In the embodiment of the present invention, the retiming method 500 includes: at 504, the CDR extracts the data component from the input data signal associated with the receiver, as described above. At 508, the data component is provided from the CDR to the transmitter, such as through the FIFO, as described above. At 512, the CDR generates a phase control signal, such as described above. In some implementations, at 516, a digital filter is incorporated to receive and perform digital filtering of the phase control signal to remove or reduce one or more frequency components associated with jitter noise. At 520, a phase interpolator receives the phase control signal from the digital filter and generates an output clock signal based on the phase control signal. At 524, the phase interpolator provides the output clock signal to the transmitter to track the data packets of the data component.

[0065] Those skilled in the art will appreciate that the form and details of the embodiments described herein may be changed without departing from the scope of the present disclosure. In addition, although various advantages, aspects, and objects have been described with reference to various embodiments, the scope of the present disclosure should not be limited by such advantages, aspects, and objects. Specifically, the scope of the present disclosure should be determined with reference to the appended claims.

Claims

1. A phase interpolator circuit system, comprising: A first phase interpolator is configured to: Receives a phase control signal from a clock and data recovery circuit, generating an output clock signal based on the phase control signal, and providing the output clock signal to an analog-to-digital converter; A second phase interpolator is configured to: receiving the phase control signal, generating another output clock signal based on the phase control signal, and providing the another output clock signal to a transmitter to track a plurality of data packets; and a digital filter coupled between the first phase interpolator and the second phase interpolator and between the clock data recovery circuit system and the second phase interpolator, the digital filter being configured to perform digital filtering on the phase control signal to the second phase interpolator to remove or reduce one or more frequency components associated with jitter noise.

2. The phase interpolator circuit system of claim 1, wherein the analog-to-digital converter is configured to generate an output data signal to the clock data recovery circuit based on the output clock signal.

3. The phase interpolator circuit system of claim 1, wherein one or more electrical characteristics of the second phase interpolator match one or more electrical characteristics of the first phase interpolator.

4. A phase interpolator circuit system according to claim 1, wherein the first phase interpolator is configured to generate the output clock signal, and the second phase interpolator is configured to control the phase of the basic clock signal by processing a control code of the phase control signal, and generate the other output clock signal based on the phase control signal.

5. The phase interpolator circuitry of claim 1, wherein the digital filter comprises one or more moving average filters.

6. The phase interpolator circuit system of claim 5, wherein each of the one or more moving average filters is configured according to: OUT(m,next)=OUT(m,previous)+1 / m(X(n+1)-X(n-m+1)), Where OUT(m) is the smoothed output of the moving average filter, X(n) is the control code sequence of the phase control signal, and m is the division factor.

7. The phase interpolator circuit system of claim 5, wherein each of the one or more moving average filters is configured according to: OUT(n)=OUT(n-1)+1 / N(P(n)-P(nN)), Wherein OUT(n) is the smoothed output of the moving average filter, P(n) is the control code sequence of the phase control signal, N=2^m, and m is the division factor.

8. The phase interpolator circuitry of claim 7, wherein each of the one or more moving average filters comprises two or more m-bit shift circuits, two or more delay units, and two or more adders.

9. The phase interpolator circuit system of claim 1, wherein the digital filter comprises two or more moving average filters coupled in series and having different configurations.

10. The phase interpolator circuitry of claim 1, wherein the first phase interpolator and the second phase interpolator are implemented on the same chip.

Images