Light detection device

Abstract

The present invention relates to a light detection device comprising: a first capacitive element; a second capacitive element connected in parallel with the first capacitive element; an upstream circuit that sequentially generates a reset level and a signal level corresponding to the exposure amount, and causes each of the first and second capacitive elements to maintain the reset level and the signal level; a selection circuit that sequentially performs control to connect one of the first and second capacitive elements to the first node, control to disconnect both of the first and second capacitive elements from the first node, and control to connect the other of the first and second capacitive elements to the first node; and a downstream circuit that sequentially reads out a reset level and a signal level from the first and second capacitive elements via a first node and outputs the read-out reset level and signal level, the selection circuit including first and second selection transistors, the first selection transistor being connected between the first capacitive element and the first node, and the second selection transistor being connected between the second capacitive element and the second node. The second selection transistor is connected between the second capacitive element and the first node.

Description

[0001] This application is a divisional application of a patent application with application number 202180028744.2, whose application date is February 24, 2021 and whose invention name is “Solid-state imaging element”. Technical Field

[0002] The present technology relates to a solid-state imaging element. Specifically, the present technology relates to a control method of a solid-state imaging element that performs analog-to-digital (AD) conversion for each column. Background Art

[0003] Generally, in order to miniaturize pixels, the following column analog-to-digital converter (ADC) system has been used in solid-state imaging elements: in this column ADC system, an ADC is configured for each column outside the pixel array unit, and the pixel signals are read out row by row. In such a column ADC system, when exposure is performed by a rolling shutter method in which exposure is started row by row, rolling shutter distortion may occur. Therefore, such a solid-state imaging element has been proposed (for example, see non-patent document 1): in order to realize a global shutter method in which exposure is started simultaneously in all pixels, a pair of capacitors is provided for each pixel to maintain the reset level and the signal level in these capacitors. The pair of capacitors is connected in series with a source follower circuit via a node, and the reset level and the signal level are read out sequentially using the source follower circuit.

[0004] Citation list

[0005] Non-patent literature

[0006] Non-patent document 1: Jae-kyu Lee, et al., A 2.1e-Temporal Noise and-105dBParasitic Light Sensitivity Backside-Illuminated 2.3μm-Pixel Voltage-DomainGlobal Shutter CMOS Image Sensor Using High-Capacity DRAM CapacitorTechnology, ISSCC 2020. Summary of the invention

[0007] Problems to be solved by the present invention

[0008] In the above conventional technology, the global shutter method in the column ADC system is implemented by holding the reset level and the signal level in a pair of capacitors provided for each pixel. However, when the transistor in the source follower circuit initializes the node connected to the capacitor, there is a possibility that kTC noise (in other words, reset noise) of a level corresponding to the capacitor is generated, thereby causing the image quality of the image data to be degraded due to the noise.

[0009] The present technology has been made in view of the above-mentioned situation, and an object of the present technology is to improve the image quality of a solid-state imaging element that exposes all pixels simultaneously.

[0010] Technical solutions to the problem

[0011] The present technology is made to solve the above-mentioned problems, and the first aspect of the present technology relates to a solid-state imaging element and a control method thereof. The solid-state imaging element includes: a first capacitor and a second capacitor; an upstream circuit, which sequentially generates a predetermined reset level and a signal level corresponding to the exposure amount, and causes each of the first capacitor and the second capacitor to maintain the reset level and the signal level; a selection circuit, which sequentially performs control of connecting one of the first capacitor and the second capacitor to a predetermined downstream node, control of disconnecting both the first capacitor and the second capacitor from the downstream node, and control of connecting the other of the first capacitor and the second capacitor to the downstream node; a downstream reset transistor, when both the first capacitor and the second capacitor are disconnected from the downstream node, the downstream reset transistor initializes the level of the downstream node; and a downstream circuit, which sequentially reads out the reset level and the signal level from the first capacitor and the second capacitor via the downstream node, and outputs the reset level and the signal level read out. This brings about the effect of reducing kTC noise.

[0012] In addition, in the first aspect, it can be further provided with: an upstream selection transistor, which is used to open and close the path between the upstream circuit and a predetermined upstream node; and an upstream reset transistor, which is used to initialize the level of the upstream node. In addition, the first capacitor and the second capacitor each have a first end connected to the upstream node and each have a second end connected to the selection circuit. This brings about the effect of blocking noise from the upstream circuit.

[0013] Furthermore, in the first aspect, during the period when the upstream circuit causes each of the first capacitor and the second capacitor to maintain the reset level and the signal level, the upstream selection transistor can be changed to a closed state, and during the period when the downstream circuit sequentially reads out the reset level and the signal level from the first capacitor and the second capacitor, the upstream reset transistor can initialize the level of the upstream node. This brings about the effect of fixing the potential of the upstream node at the time of reading.

[0014] In addition, in the first aspect, the upstream circuit may include: a photoelectric conversion element; an upstream transfer transistor that transfers charge from the photoelectric conversion element to a floating diffusion layer; a first reset transistor that initializes the floating diffusion layer; and an upstream amplifier transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node. In addition, the first capacitor and the second capacitor may each have a first end commonly connected to the upstream node and each have a second end connected to the selection circuit. This brings about the effect of providing a signal corresponding to the potential of the floating diffusion layer to the upstream node.

[0015] In addition, in the first aspect, a switching unit may be provided for adjusting a source voltage to be provided to the source of the upstream amplifier transistor. The upstream circuit may also include a current source transistor connected to the drain of the upstream amplifier transistor. In addition, after the exposure period ends, the current source transistor may be changed from an ON state to an OFF state. This brings about the effect of putting the upstream source follower in an OFF state during readout.

[0016] Furthermore, in the first aspect, during the exposure period, the switching section can provide a predetermined power supply voltage as the source voltage, and after the exposure period ends, the switching section can provide a generated voltage different from the power supply voltage as the source voltage. This brings about the effect of adjusting the source voltage of the upstream source follower.

[0017] Furthermore, in the first aspect, the difference between the power supply voltage and the generated voltage may be substantially equal to the sum of the variation caused by the reset feedthrough of the first reset transistor and the gate-source voltage of the upstream amplifying transistor. This brings about the effect that the potential of the upstream node is equal during exposure and during readout.

[0018] Furthermore, in the first aspect, at a predetermined exposure start time, the upstream transfer transistor can transfer the charge to the floating diffusion layer, and the first reset transistor can initialize the photoelectric conversion element together with the floating diffusion layer. Furthermore, at a predetermined exposure end time, the upstream transfer transistor can transfer the charge to the floating diffusion layer. This brings about the effect of generating a pixel signal corresponding to the exposure amount.

[0019] Furthermore, in the first aspect, the upstream circuit may further include: a discharge transistor for discharging the charge from the photoelectric conversion element. This brings about an effect that the photoelectric conversion element is initialized.

[0020] Furthermore, in the first aspect, before a predetermined exposure start time, the first reset transistor can initialize the floating diffusion layer, and the discharge transistor can discharge the charge from the photoelectric conversion element. Furthermore, at a predetermined exposure end time, the upstream transfer transistor can transfer the charge to the floating diffusion layer. This brings about the effect of achieving a very short exposure time.

[0021] In addition, in the first aspect, a control circuit for controlling a reset power supply voltage of the upstream circuit is further provided. The first reset transistor can initialize the voltage of the floating diffusion layer to the reset power supply voltage. In addition, during a readout period for reading out the reset level and the signal level, the control circuit can set the reset power supply voltage to a voltage different from the voltage during exposure. This brings about an effect of improving the non-uniformity of light sensitivity.

[0022] Furthermore, in the first aspect, the difference between the reset power supply voltage during the readout period and the reset power supply voltage during the exposure period may be substantially consistent with the variation caused by reset feedthrough of the first reset transistor. This brings about an effect of improving light sensitivity non-uniformity.

[0023] Furthermore, in the first aspect, the first reset signal may be input to the gate of the first reset transistor, and the amplitude of the first reset signal may be a value obtained by adding a predetermined margin to a value corresponding to the dynamic range. This brings about an effect of suppressing the black dot phenomenon.

[0024] In addition, in the first aspect, a digital signal processing unit for adding a pair of continuous frames may be further provided. The upstream circuit may cause one of the first capacitor and the second capacitor to maintain the reset level during the exposure period of one of the pair of frames, and then cause the other of the first capacitor and the second capacitor to maintain the signal level. In addition, the upstream circuit may cause the other of the first capacitor and the second capacitor to maintain the reset level during the exposure period of the other of the pair of frames, and then cause the one of the first capacitor and the second capacitor to maintain the signal level. This brings about the effect of improving the unevenness of light sensitivity.

[0025] Furthermore, in the first aspect, an analog-to-digital converter may be provided to convert the reset level of the output and the signal level of the output into digital signals in sequence, which results in the effect of generating digital image data.

[0026] Furthermore, in the first aspect, the analog-to-digital converter may include: a comparator that compares the level of a vertical signal line for transmitting the reset level and the signal level with a predetermined ramp signal and outputs a comparison result; and a counter that counts a count value during a period until the comparison result is inverted and outputs the digital signal representing the count value. This brings about an effect of realizing analog-to-digital conversion with a simple structure.

[0027] Furthermore, in the first aspect, the comparator may include: a comparison section that compares the levels of each of a pair of input terminals and outputs a comparison result; and an input side selector that selects any one of the vertical signal line and a node having a predetermined reference voltage and connects the selected vertical signal line or the node to one of the pair of input terminals. Furthermore, the ramp signal may be input to one of the pair of input terminals. This brings about an effect of suppressing the black spot phenomenon.

[0028] In addition, in the first aspect, there may be provided: a control unit that determines whether the illuminance is higher than a predetermined value based on the comparison result and outputs the determination result; a correlated double sampling (CDS) processing unit that performs correlated double sampling processing on the digital signal; and an output side selector that outputs the digital signal subjected to the correlated double sampling processing or a digital signal having a predetermined value based on the determination result. This brings about the effect of suppressing the black spot phenomenon.

[0029] In addition, in the first aspect, a vertical scanning circuit may be further provided, and for a plurality of rows in which a predetermined number of pixels are arranged in each row, the vertical scanning circuit performs control for controlling the plurality of rows to start exposure at the same time. In addition, the first capacitor element, the second capacitor element, the upstream circuit, the selection circuit, the downstream reset transistor, and the downstream circuit may be arranged in each of the pixels. This brings about an effect that it is easy to miniaturize pixels.

[0030] In addition, in the first aspect, the vertical scanning circuit may further perform control for controlling the plurality of rows to start exposure in sequence. This brings about an effect that it is easy to miniaturize pixels.

[0031] Furthermore, in the first aspect, the upstream circuit may be provided on a first chip, and the first capacitor, the second capacitor, the selection circuit, the downstream reset transistor, and the downstream circuit may be provided on a second chip. This brings about an effect that it is easy to miniaturize pixels.

[0032] In addition, in the first aspect, an analog-to-digital converter may be provided to convert the reset level of the output and the signal level of the output into digital signals in sequence, and the analog-to-digital converter may be provided on the second chip. This brings about the effect of facilitating pixel miniaturization.

[0033] In addition, in the first aspect, an analog-to-digital converter may be provided to convert the reset level of the output and the signal level of the output into digital signals in sequence, and the analog-to-digital converter may be provided on the third chip. This brings about the effect of facilitating pixel miniaturization.

[0034] In addition, the second aspect of the present technology relates to a solid-state imaging element, which includes: a photoelectric conversion unit that converts incident light into electric charge; a first amplifier transistor that converts the electric charge into a voltage; a signal line that outputs a pixel signal; a first capacitor element whose first end is connected to a first node as an output destination of the first amplifier transistor; a second capacitor element that is provided in parallel with the first capacitor element between the first amplifier transistor and the signal line, and the first end of the second capacitor element is connected to the first node; a first selection transistor that is connected to the first capacitor element at the second end of the first capacitor element; a second selection transistor that is connected to the second capacitor element at the second end of the second capacitor element; a reset transistor whose source or drain is connected to a second node, and the first selection transistor and the second selection transistor are connected at the second node; and a second amplifier transistor whose gate is connected to the second node, and the second amplifier transistor outputs the pixel signal. This brings about the effect of generating image data with reduced kTC noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a block diagram showing a configuration example of an imaging device in the first embodiment of the present technology.

[0036] Figure 2 : is a block diagram showing a configuration example of a solid-state imaging element in the first embodiment of the present technology.

[0037] Figure 3 : is a circuit diagram showing a configuration example of a pixel in the first embodiment of the present technology.

[0038] Figure 4 : is a block diagram showing a configuration example of a column signal processing circuit and a load MOS circuit block in the first embodiment of the present technology.

[0039] Figure 5 : is a timing chart showing an example of the global shutter operation in the first embodiment of the present technology.

[0040] Figure 6 is a timing chart showing an example of a readout operation in the first embodiment of the present technology.

[0041] Figure 7 is a timing chart showing another example of the readout operation in the first embodiment of the present technology.

[0042] Figure 8 is a circuit diagram showing a configuration example of a pixel in a comparative example.

[0043] Fig. 9 : is a diagram showing an example of the state of the pixel when the reset level is read out and when the downstream node is initialized in the first embodiment of the present technology.

[0044] Fig.10 : is a diagram showing an example of a state of a pixel when a signal level is read out in the first embodiment of the present technology.

[0045] Fig.11 : is a flowchart showing an operation example of the solid-state image pickup element in the first embodiment of the present technology.

[0046] Fig.12 : is a circuit diagram showing a configuration example of a pixel in a first modification example of the first embodiment of the present technology.

[0047] Fig.13 : is a timing chart showing an example of the global shutter operation in the first modification example of the first embodiment of the present technology.

[0048] Fig.14 is a timing chart showing an example of a readout operation in the first modification example of the first embodiment of the present technology.

[0049] Fig.15 : is a diagram showing an example of a stacked structure of a solid-state imaging element in a second modification example of the first embodiment of the present technology.

[0050] Fig.16 : is a circuit diagram showing a configuration example of a pixel in the second modification example of the first embodiment of the present technology.

[0051] Fig.17 : is a diagram showing an example of a stacked structure of a solid-state imaging element in a third modification example of the first embodiment of the present technology.

[0052] Fig.18 : is a circuit diagram showing a configuration example of a pixel in a second embodiment of the present technology.

[0053] Fig.19 : is a timing chart showing an example of the global shutter operation in the second embodiment of the present technology.

[0054] Fig. 20 : is a circuit diagram showing a configuration example of a pixel in a third embodiment of the present technology.

[0055] Fig.21 It is a diagram for explaining reset feedthrough in the third embodiment of the present technology.

[0056] Fig. 22 It is a diagram for explaining level change caused by reset feedthrough in the third embodiment of the present technology.

[0057] Fig.23 : is a timing chart showing an example of voltage control in the third embodiment of the present technology.

[0058] Fig.24 : is a timing chart showing an example of the global shutter operation of odd-numbered frames in the fourth embodiment of the present technology.

[0059] Fig.25 is a timing chart showing an example of the readout operation of an odd-numbered frame in the fourth embodiment of the present technology.

[0060] Fig.26 : is a timing chart showing an example of the global shutter operation of the even-numbered frames in the fourth embodiment of the present technology.

[0061] Fig. 27 is a timing chart showing an example of the readout operation of an even-numbered frame in the fourth embodiment of the present technology.

[0062] Fig.28 : is a circuit diagram showing a configuration example of a column signal processing circuit in a fifth embodiment of the present technology.

[0063] Fig.29 : is a timing chart showing an example of the global shutter operation in the fifth embodiment of the present technology.

[0064] Fig.30 is a timing chart showing an example of a readout operation in the fifth embodiment of the present technology.

[0065] Fig.31 : is a timing chart showing an example of a rolling shutter operation in the sixth embodiment of the present technology.

[0066] Fig.32 : is a block diagram showing a configuration example of a solid-state imaging element in a seventh embodiment of the present technology.

[0067] Fig.33 : is a circuit diagram showing a configuration example of a dummy pixel, a regulator, and a switching unit in a seventh embodiment of the present technology.

[0068] Fig.34 : is a timing chart showing an operation example of a dummy pixel and an adjuster in the seventh embodiment of the present technology.

[0069] Fig.35 : is a circuit diagram showing a configuration example of an effective pixel in a seventh embodiment of the present technology.

[0070] Fig.36 : is a timing chart showing an example of the global shutter operation in the seventh embodiment of the present technology.

[0071] Fig.37 is a timing chart showing an example of a readout operation in the seventh embodiment of the present technology.

[0072] Fig.38It is a diagram for explaining the effects in the seventh embodiment of the present technology.

[0073] Fig.39 : is a block diagram showing a schematic configuration example of a vehicle control system.

[0074] Fig.40 1 is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0075] Hereinafter, a mode for implementing the present technology (hereinafter, referred to as an embodiment) will be described. The description will be given in the following order.

[0076] 1. First Embodiment (Example in which Pixel Signals are Retained in First and Second Capacitive Elements)

[0077] 2. Second Embodiment (Example in which a discharge transistor is added and a pixel signal is held in first and second capacitive elements)

[0078] 3. Third Embodiment (Example in which pixel signals are held in first and second capacitance elements, and reset power supply voltage is controlled)

[0079] 4. Fourth Embodiment (Example in which pixel signals are held in first and second capacitive elements, and the levels to be held are switched for each frame)

[0080] 5. Fifth Embodiment (Example in which pixel signals are held in first and second capacitive elements and a black dot phenomenon is suppressed)

[0081] 6. Sixth Embodiment (Example in which pixel signals are held in first and second capacitive elements, and rolling shutter operation is performed)

[0082] 7. Application examples for mobile objects

[0083] <1. First Implementation Method>

[0084] [Configuration Example of Imaging Device]

[0085] Figure 1 1 is a block diagram showing a configuration example of an image pickup device 100 in the first embodiment of the present technology. The image pickup device 100 is a device that picks up image data, and includes an image pickup lens 110, a solid-state image pickup element 200, a recording section 120, and an image pickup control section 130. As the image pickup device 100, a digital camera or an electronic device having an image pickup function (a smartphone, a personal computer, etc.) is assumed.

[0086] The solid-state imaging element 200 captures image data under the control of the imaging control section 130. The solid-state imaging element 200 supplies the image data to the recording section 120 via the signal line 209.

[0087] The imaging lens 110 condenses light and guides the light to the solid-state imaging element 200. The imaging control section 130 controls the solid-state imaging element 200 to capture image data. The imaging control section 130 supplies an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element 200, for example, via a signal line 139. The recording section 120 records image data.

[0088] Here, the vertical synchronization signal VSYNC is a signal indicating an imaging timing, and a periodic signal of a constant frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0089] Incidentally, the camera 100 records image data, which can be transmitted to the outside of the camera 100. In this case, an external interface configured to transmit image data is also provided. Alternatively, the camera 100 can also display image data. In this case, a display unit is also provided.

[0090] [Configuration Example of Solid-State Image Sensor]

[0091] Figure 2 1 is a block diagram showing a configuration example of a solid-state imaging element 200 in the first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array section 220, a plurality of pixels 300 are arranged in a two-dimensional lattice pattern. In addition, each circuit in the solid-state imaging element 200 is provided on, for example, a single semiconductor chip.

[0092] Hereinafter, a set of pixels 300 arranged in a horizontal direction is referred to as a “row”, and a set of pixels 300 arranged in a direction perpendicular to the row is referred to as a “column”.

[0093] The timing control circuit 212 controls the operation timing of each of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control section 130 .

[0094] The DAC 213 generates a ramp signal in a sawtooth wave shape through digital-to-analog (DA) conversion and supplies the generated ramp signal to the column signal processing circuit 260 .

[0095] The vertical scanning circuit 211 sequentially selects and drives rows and outputs analog pixel signals. The pixel 300 photoelectrically converts incident light to generate analog pixel signals. The pixel 300 supplies the pixel signals to the column signal processing circuit 260 via the load MOS circuit block 250 .

[0096] In the load MOS circuit block 250 , a MOS transistor that supplies a constant current is provided for each column.

[0097] The column signal processing circuit 260 performs signal processing such as AD conversion processing and CDS processing on the pixel signal of each column. The column signal processing circuit 260 supplies image data including the processed signal to the recording section 120. Incidentally, the column signal processing circuit 260 is an example of a signal processing circuit described in the claims.

[0098] [Pixel Configuration Example]

[0099] Figure 3 3 is a circuit diagram showing a configuration example of a pixel 300 in the first embodiment of the present technology. The pixel 300 includes an upstream circuit 310 , capacitors 321 and 322 , a selection circuit 330 , a downstream reset transistor 341 , and a downstream circuit 350 .

[0100] The upstream circuit 310 includes a photoelectric conversion element 311 , a transfer transistor 312 , an FD reset transistor 313 , an FD (floating diffusion) 314 , an upstream amplifier transistor 315 , and a current source transistor 316 .

[0101] The photoelectric conversion element 311 generates electric charge by photoelectric conversion. The transfer transistor 312 transfers the electric charge from the photoelectric conversion element 311 to the FD 314 according to the transfer signal trg from the vertical scanning circuit 211.

[0102] The FD reset transistor 313 extracts charge from the FD 314 according to the FD reset signal rst from the vertical scanning circuit 211 and initializes. The FD 314 accumulates charge and generates a voltage corresponding to the amount of charge. The upstream amplifier transistor 315 amplifies the voltage level of the FD 314 and outputs the amplified voltage to the upstream node 320. Incidentally, the FD reset transistor 313 is an example of the first reset transistor described in the claims. In addition, the upstream amplifier transistor 315 is an example of the first amplifier transistor described in the claims.

[0103] Furthermore, the source of the FD reset transistor 313 and the source of the upstream amplifying transistor 315 are connected to the power supply voltage VDD. The current source transistor 316 is connected to the drain of the upstream amplifying transistor 315. The current source transistor 316 supplies the current id1 under the control of the vertical scanning circuit 211.

[0104] One end of each of the capacitance elements 321 and 322 is commonly connected to the upstream node 320, and the other end of each of them is connected to the selection circuit 330. Incidentally, the capacitance elements 321 and 322 are examples of the first and second capacitance elements described in the claims.

[0105] The selection circuit 330 includes a selection transistor 331 and a selection transistor 332. The selection transistor 331 opens and closes the path between the capacitance element 321 and the downstream node 340 according to the selection signal Φr from the vertical scanning circuit 211. The selection transistor 332 opens and closes the path between the capacitance element 322 and the downstream node 340 according to the selection signal Φs from the vertical scanning circuit 211.

[0106] The downstream reset transistor 341 initializes the level of the downstream node 340 to a predetermined potential Vreg according to a downstream reset signal rstb from the vertical scanning circuit 211. A potential different from the power supply potential VDD (eg, a potential lower than VDD) is set as the potential Vreg.

[0107] The downstream circuit 350 includes a downstream amplifier transistor 351 and a downstream selection transistor 352. The downstream amplifier transistor 351 amplifies the level of the downstream node 340. The downstream selection transistor 352 outputs the signal of the level amplified by the downstream amplifier transistor 351 as a pixel signal to the vertical signal line 309 according to the downstream selection signal selb from the vertical scanning circuit 211. Incidentally, the downstream amplifier transistor is an example of the second amplifier transistor described in the claims.

[0108] Incidentally, as various transistors (transfer transistor 312 and the like) in the pixel 300, for example, n-channel Metal Oxide Semiconductor (nMOS) transistors are used.

[0109] At the start of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and a transfer signal trg to all pixels. Thus, the photoelectric conversion element 311 is initialized. Hereinafter, this control is referred to as "PD reset".

[0110] Then, just before the end of exposure, the vertical scanning circuit 211 provides a high-level FD reset signal rst within the pulse period while setting the downstream reset signal rstb and the selection signal Φr to a high level for all pixels. Therefore, FD314 is initialized, and a level corresponding to the level of FD 314 at this time is held in the capacitor element 321. This control is hereinafter referred to as "FD reset".

[0111] The level of the FD 314 at the time of FD reset and the level corresponding to the level (the level held in the capacitance element 321 and the level of the vertical signal line 309) are hereinafter collectively referred to as "P phase" or "reset level".

[0112] When the exposure is finished, the vertical scanning circuit 211 sets the downstream reset signal rstb and the selection signal Φs to high level for all pixels and provides a high-level transfer signal trg in the pulse period. Therefore, the signal charge corresponding to the exposure amount is transferred to the FD 314, and the level corresponding to the level of the FD 314 at this time is held in the capacitor 322.

[0113] The level of the FD 314 when transferring signal charges and the level corresponding to the level (the level held in the capacitance element 322 and the level of the vertical signal line 309) are hereinafter collectively referred to as "D phase" or "signal level".

[0114] This exposure control for all pixels to start and end exposure at the same time is called a global shutter method. Through this exposure control, the upstream circuit 310 of all pixels generates a reset level and a signal level in sequence. The reset level is maintained in the capacitor element 321, and the signal level is maintained in the capacitor element 322.

[0115] After the exposure is completed, the vertical scanning circuit 211 sequentially selects a row and sequentially outputs the reset level and signal level of the row. When the reset level is to be output, the vertical scanning circuit 211 sets the FD reset signal rst and the downstream selection signal selb of the selected row to a high level and provides a high-level selection signal Φr for a predetermined period. Therefore, the capacitive element 321 is connected to the downstream node 340, thereby reading the reset level.

[0116] After reading the reset level, the vertical scanning circuit 211 provides a high-level downstream reset signal rstb during the pulse period while keeping the FD reset signal rst and the downstream selection signal selb of the selected row at a high level. Therefore, the level of the downstream node 340 is initialized. At this time, both the selection transistor 331 and the selection transistor 332 are in an open state, and the capacitor elements 321 and 322 are disconnected from the downstream node 340.

[0117] After the downstream node 340 is initialized, the vertical scanning circuit 211 supplies a high-level selection signal Φs for a predetermined period while keeping the FD reset signal rst and the downstream selection signal selb of the selected row at high levels. Thus, the capacitance element 322 is connected to the downstream node 340, thereby reading the signal level.

[0118] Through the above-described readout control, the selection circuit 330 of the selected row sequentially performs control of connecting the capacitor element 321 to the downstream node 340, control of disconnecting the capacitor elements 321 and 322 from the downstream node 340, and control of connecting the capacitor element 322 to the downstream node 340. In addition, when the capacitor elements 321 and 322 are disconnected from the downstream node 340, the downstream reset transistor 341 of the selected row initializes the level of the downstream node 340. In addition, the downstream circuit 350 of the selected row sequentially reads out the reset level and the signal level from the capacitor elements 321 and 322 via the downstream node 340, and outputs the readout reset level and signal level to the vertical signal line 309.

[0119] [Configuration Example of Column Signal Processing Circuit]

[0120] Figure 4 : is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 in the first embodiment of the present technology.

[0121] In the load MOS circuit block 250 , a vertical signal line 309 is arranged for each column. When the number of columns is I (I is an integer), I vertical signal lines 309 are arranged. In addition, a load MOS transistor 251 for supplying a constant current id2 is connected to each vertical signal line 309 .

[0122] In the column signal processing circuit 260, a plurality of ADCs 261 and a digital signal processing unit 262 are provided. The ADC 261 is provided for each column. When the number of columns is one, one ADC 261 is provided.

[0123] The ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing section 262. As the ADC 261, for example, a single slope ADC including a comparator and a counter is configured.

[0124] The digital signal processing section 262 performs predetermined signal processing such as CDS processing on the digital signal of each column, and supplies image data including the processed digital signal to the recording section 120 .

[0125] [Operation example of solid-state imaging element]

[0126] Figure 51 is a timing diagram showing an example of the global shutter operation in the first embodiment of the present technology. The vertical scanning circuit 211 provides a high-level FD reset signal rst and a transfer signal trg to all rows (in other words, all pixels) from the time T0 immediately before the start of exposure to the time T1 after the pulse period has passed. Therefore, all pixels undergo PD reset, and exposure starts simultaneously in all rows.

[0127] Here, rst_[n] and trg_[n] in the figure represent signals about pixels in the nth row among N rows. N is an integer representing the total number of rows, and n is an integer from 1 to N.

[0128] Then, at time T2 just before the end of the exposure period, the vertical scanning circuit 211 provides a high-level FD reset signal rst within the pulse period while setting the downstream reset signal rstb and the selection signal Φr to a high level for all pixels. Therefore, all pixels undergo FD reset, and the reset level is sampled and held. Here, rstb_[n] and Φr_[n] in the figure represent signals about the n-th row of pixels.

[0129] At time T3 after time T2, the vertical scanning circuit 211 returns the selection signal Φr to the low level.

[0130] At the end of exposure time T4, the vertical scanning circuit 211 sets the downstream reset signal rstb and the selection signal Φs to a high level in all pixels, and provides a high-level transmission signal trg within the pulse period. Therefore, the signal level is sampled and held. In addition, the level of the upstream node 320 is reduced from the reset level (VDD-Vsig) to the signal level (VDD-Vgs-Vsig). Here, VDD represents the power supply voltage, and Vsig represents the net signal level obtained by CDS processing. Vgs represents the gate-source voltage of the upstream amplifier transistor 315. In addition, Φs_[n] in the figure represents the signal about the nth row of pixels.

[0131] At time T5 after time T4, the vertical scanning circuit 211 returns the selection signal Φs to the low level.

[0132] In addition, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to provide current id1. Here, id1_[n] in the figure represents the current of the nth row pixel. When the current id is large, the IR drop becomes large, and therefore, the current id1 needs to be in the order of a few nanoamperes (nA) to tens of nanoamperes (nA). On the other hand, the load MOS transistors 251 of all columns are in the off state, and the current id2 is not provided to the vertical signal line 309.

[0133] Figure 61 is a timing diagram showing an example of the readout operation in the first embodiment of the present technology. During the readout of the nth row from time T10 to time T17, the vertical scanning circuit 211 sets the FD reset signal rst and the downstream selection signal selb of the nth row to a high level. In addition, during the readout, the downstream reset signal rstb of all rows is controlled to a low level. Here, selb_[n] in the figure represents a signal about the nth row of pixels.

[0134] During the period from time T11 to time T13 immediately after time T10, the vertical scanning circuit 211 supplies the high-level selection signal Φr to the n-th row. The potential of the downstream node 340 becomes the reset level Vrst.

[0135] During the period from time T12 to time T13 after time T11, the DAC 213 gradually increases the ramp signal Rmp. The ADC 261 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309 and counts the count value until the comparison result is inverted. Thus, the P-phase level (reset level) is read out.

[0136] In the pulse period from time T14 immediately after time T13, the vertical scanning circuit 211 supplies the downstream reset signal rstb of high level to the nth row. Therefore, when parasitic capacitance exists in the downstream node 340, the history of the last signal held in the parasitic capacitance can be erased.

[0137] During the period from time T15 to time T17 immediately after the downstream node 340 is initialized, the vertical scanning circuit 211 provides the high-level selection signal Φs to the n-th row. The potential of the downstream node 340 becomes the signal level Vsig. Although the signal level is lower than the reset level at the time of exposure, the signal level is higher than the reset level at the time of reading because the downstream node 340 is used as a reference. The difference between the reset level Vrst and the signal level Vsig is equivalent to the net signal level from which the reset noise and offset noise of the FD have been removed.

[0138] During the period from time T16 to time T17 after time T15, the DAC 213 gradually increases the ramp signal Rmp. The ADC 261 compares the ramp signal Rmp with the level Vrst' of the vertical signal line 309 and counts the count value until the comparison result is inverted. Thus, the D-phase level (signal level) is read out.

[0139] Furthermore, the vertical scanning circuit 211 controls the current source transistor 316 of the nth row to be read out during the period from time T10 to time T17 to provide current id1. Furthermore, the timing control circuit 212 controls the load MOS transistors 251 of all columns during the readout period of all rows to provide current id2.

[0140] Incidentally, the solid-state imaging element 200 reads out the signal level after resetting the level, but is not limited to this order. Figure 7 As shown, the solid-state imaging element 200 can also read out the reset level after the signal level. In this case, as shown in the figure, the vertical scanning circuit 211 provides a high-level selection signal Φr after the high-level selection signal Φs. In addition, in this case, it is necessary to reverse the slope of the ramp signal.

[0141] Figure 8 3 is a circuit diagram showing a configuration example of a pixel in a comparative example. In this comparative example, a selection circuit 330 is not provided, and a transfer transistor is inserted between an upstream node 320 and an upstream circuit. In addition, capacitors C1 and C2 are inserted to replace capacitive elements 321 and 322. Capacitor C1 is inserted between the upstream node 320 and the ground terminal, and capacitor C2 is inserted between the upstream node 320 and the downstream node 340.

[0142] For example, in Non-Patent Document 1 Figure 5 .5.2 describes the exposure control and readout control of the pixel in this comparative example. In this comparative example, assuming that the capacitance value of each of capacitors C1 and C2 is C, the level Vn of the kTC noise during exposure and readout is expressed by the following equation.

[0143] Vn = (3 * kT / C) 1 / 2 ...Formula 1

[0144] In the above formula, k is the Boltzmann constant, and the unit is, for example, joule / Kelvin (J / K). T is the absolute temperature, and the unit is, for example, Kelvin (K). In addition, the unit of Vn is, for example, volt (V), and the unit of C is, for example, farad (F).

[0145] Fig. 9 : is a diagram showing an example of the state of a pixel when a reset level is read out and when a downstream node is initialized in the first embodiment of the present technology. Fig. 9 a in denoted the state of the pixel 300 when the reset level is read out. Fig. 9 b in φ represents the state of the pixel 300 when the downstream node 340 is initialized. In addition, in the figure, for convenience of explanation, the selection transistor 331, the selection transistor 332, and the downstream reset transistor 341 are represented by graphical symbols of switches.

[0146] like Fig. 9 As shown in a in FIG. 2 , the vertical scanning circuit 211 sets the selection transistor 331 to a closed state and sets the selection transistor 332 and the downstream reset transistor 341 to an open state. Therefore, the reset level is read out via the downstream circuit 350 .

[0147] like Fig. 9 As shown in b, after reading the reset level, the vertical scanning circuit 211 sets the selection transistors 331 and 332 to an open state and sets the downstream reset transistor 341 to a closed state. Therefore, both the capacitors 321 and 322 are disconnected from the downstream node 340, and the level of the downstream node 340 is initialized.

[0148] In this way, the capacitance value of the parasitic capacitance Cp of the downstream node 340 in a state of being disconnected from the capacitance elements 321 and 322 is set to be very small compared with the capacitance values ​​of the capacitance elements 321 and 322. For example, assuming that the parasitic capacitance Cp is several femtofarads (fF), the capacitance elements 321 and 322 are in the order of tens of femtofarads.

[0149] Fig.10 is a diagram showing an example of the state of the pixel 300 when the signal level is read out in the first embodiment of the present technology.

[0150] After initialization of the downstream node 340 , the vertical scanning circuit 211 sets the selection transistor 332 to a closed state and sets the selection transistor 331 and the downstream reset transistor 341 to an open state. Thus, the signal level is read out via the downstream circuit 350 .

[0151] Here, consider the kTC noise of the pixel 300 during exposure. During exposure, kTC noise occurs in each of the sampling of the reset level and the sampling of the signal level immediately before the end of exposure. Assuming that the capacitance value of each of the capacitor elements 321 and 322 is C, the level Vn of the kTC noise during exposure is expressed by the following formula.

[0152] Vn = (2 * kT / C) 1 / 2 ...Formula 2

[0153] In addition, if Fig. 9 and Fig.10 As shown, since the downstream reset transistor 341 is driven during readout, kTC noise will appear at this time. However, when the downstream reset transistor 341 is driven, the capacitor elements 321 and 322 are disconnected, and the parasitic capacitance Cp is small at this time. Therefore, compared with the kTC noise during exposure, the kTC noise during readout can be ignored. Therefore, the kTC noise during exposure and readout is expressed by Formula 2.

[0154] According to Formula 1 and Formula 2, the kTC noise in the pixel 300 in which the capacitor is disconnected at the time of readout is smaller than the kTC noise in the comparative example in which the capacitor is not disconnected at the time of readout. Therefore, the image quality of the image data can be improved.

[0155] Fig.11 1 is a flowchart showing an operation example of the solid-state image pickup element 200 in the first embodiment of the present technology. For example, when a predetermined application for image data pickup is executed, the operation is started.

[0156] The vertical scanning circuit 211 performs exposure for all pixels (step S901). Then, the vertical scanning circuit 211 selects a row to be read out (step S902). The column signal processing circuit 260 reads out the reset level of the row (step S903), and then reads out the signal level (step S904).

[0157] The solid-state imaging element 200 determines whether the readout of all rows has been completed (step S905). In the case where the readout of all rows has not been completed (step S905: No), the solid-state imaging element 200 repeats step S902 and subsequent steps. On the other hand, in the case where the readout of all rows has been completed (step S905: Yes), the solid-state imaging element 200 performs CDS processing and the like, and ends the operation for imaging. In the case of continuously imaging a plurality of pieces of image data, steps S901 to S905 are repeatedly performed in synchronization with the vertical synchronization signal.

[0158] In this way, in the first embodiment of the present technology, when the selection circuit 330 disconnects the capacitor elements 321 and 322 from the downstream node 340, the downstream reset transistor 341 initializes the downstream node 340. Since the capacitor elements 321 and 322 are disconnected, the level of the reset noise caused by the driving thereof becomes a level corresponding to the parasitic capacitance smaller than the capacitance thereof. By reducing this noise, the image quality of the image data can be improved.

[0159] [First Modification]

[0160] Although in the first embodiment described above, the upstream circuit 310 reads out a signal while being connected to the upstream node 320, in this configuration, it is difficult to block noise from the upstream node 320 during readout. The pixel 300 of the first modification of the first embodiment is different from the pixel of the first embodiment in that a transistor is inserted between the upstream circuit 310 and the upstream node 320.

[0161] Fig.121 is a circuit diagram showing a configuration example of a pixel 300 in a first modification of the first embodiment of the present technology. The pixel 300 of the first modification of the first embodiment is different from the pixel of the first embodiment in that it further includes an upstream reset transistor 323 and an upstream selection transistor 324. In addition, the power supply voltage of the upstream circuit 310 and the downstream circuit 350 of the first modification of the first embodiment is set to VDD1.

[0162] The upstream reset transistor 323 initializes the level of the upstream node 320 with the power supply voltage VDD2. The power supply voltage VDD2 is preferably set to a value that satisfies the following formula.

[0163] VDD2 = VDD1 - Vgs...Equation 3

[0164] In the above formula, Vgs represents the gate-source voltage of the upstream amplifier transistor 315 .

[0165] By setting the value to satisfy Formula 3, the potential variation between the upstream node 320 and the downstream node 340 in the dark can be reduced. Therefore, the photo response non-uniformity (PRNU) can be improved.

[0166] The upstream selection transistor 324 opens and closes a path between the upstream circuit 310 and the upstream node 320 according to an upstream selection signal sel from the vertical scanning circuit 211 .

[0167] Fig.13 1 is a timing diagram showing an example of global shutter operation in the first variant of the first embodiment of the present technology. The timing diagram of the first variant of the first embodiment is different from the timing diagram of the first embodiment in that the vertical scanning circuit 211 also provides an upstream reset signal rsta and an upstream selection signal sel. In this figure, rsta_[n] and sel_[n] represent signals about the nth row of pixels.

[0168] The vertical scanning circuit 211 supplies the upstream selection signal sel of high level to all pixels from time T2 immediately before the end of exposure to time T5. The upstream reset signal rsta is controlled to be low level.

[0169] Fig.14 3 is a timing diagram showing an example of a readout operation in a first variation of the first embodiment of the present technology. When reading out each row, the upstream selection signal sel is controlled to a low level. This control causes the upstream selection transistor 324 to be turned into an open state, and the upstream node 320 is disconnected from the upstream circuit 310. Therefore, noise from the upstream node 320 can be blocked when reading out.

[0170] Furthermore, during the readout period of the n-th row from the time T10 to the time T17 , the vertical scanning circuit 211 supplies the upstream reset signal rsta of the high level to the n-th row.

[0171] Furthermore, at the time of readout, the vertical scanning circuit 211 controls the current source transistors 316 of all pixels to stop supplying the current id1. The current id2 is supplied similarly to the first embodiment. In this way, the control of the current id1 is simplified compared to the first embodiment.

[0172] In this way, in the first modification according to the first embodiment of the present technology, the upstream selection transistor 324 is turned to the open state at the time of reading, and the upstream circuit 310 is disconnected from the upstream node 320, so that noise from the upstream circuit 310 can be blocked.

[0173] [Second Modification]

[0174] Although the circuits in the solid-state imaging element 200 are arranged on a single semiconductor chip in the above-mentioned first embodiment, in this configuration, when the pixel 300 is miniaturized, there is a possibility that the semiconductor chip cannot accommodate the components. The solid-state imaging element 200 of the second modified example of the first embodiment is different from the solid-state imaging element of the first embodiment in that the circuits in the solid-state imaging element 200 are dispersedly arranged on two semiconductor chips.

[0175] Fig.15 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in a second variant of the first embodiment of the present technology. The solid-state imaging element 200 in the second variant of the first embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. The two chips are electrically connected by, for example, Cu-Cu bonding. By the way, in addition to using Cu-Cu bonding, connection can be made via a vertical interconnection path (via) or a bump.

[0176] The upper pixel array section 221 is configured on the upper pixel chip 201. The lower pixel array section 222 and the column signal processing circuit 260 are configured on the lower pixel chip 202. For each pixel in the pixel array section 220, a part thereof is configured in the upper pixel array section 221, and the remaining part is configured in the lower pixel array section 222.

[0177] Furthermore, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are also arranged on the lower pixel chip 202. These circuits are not shown in the figure.

[0178] In addition, the upper pixel chip 201 is manufactured, for example, by a pixel-specific process, and the lower pixel chip 202 is manufactured, for example, by a complementary MOS (CMOS) process. Incidentally, the upper pixel chip 201 is an example of a first chip described in the claims, and the lower pixel chip 202 is an example of a second chip described in the claims.

[0179] Fig.16 is a circuit diagram showing an example of the configuration of a pixel 300 in a second variant of the first embodiment of the present technology. In the pixel 300, the upstream circuit 310 is configured on the upper pixel chip 201, and other circuits and elements (such as capacitor elements 321 and 322, etc.) are configured on the lower pixel chip 202. Incidentally, the current source transistor 316 can be further configured on the lower pixel chip 202. As shown in the figure, since the elements in the pixel 300 are dispersedly configured on the stacked upper pixel chip 201 and the lower pixel chip 202, the area of ​​the pixel can be reduced, and the miniaturization of the pixel can be facilitated.

[0180] In this way, since the circuits and elements in the pixel 300 are dispersedly arranged on two semiconductor chips in the second modification example according to the first embodiment of the present technology, it is possible to facilitate miniaturization of the pixel.

[0181] [Third Modification]

[0182] In the second variant of the first embodiment described above, a portion of the pixel 300 and peripheral circuits (such as the column signal processing circuit 260, etc.) are arranged on the lower pixel chip 202 on the lower side. However, in this configuration, due to the area occupied by the peripheral circuits, the arrangement area of ​​the circuits and components on the lower pixel chip 202 side is larger than the arrangement area of ​​the upper pixel chip 201, and a useless space that does not contain circuits or components may be generated in the upper pixel chip 201. The solid-state imaging element 200 of the third variant of the first embodiment is different from the solid-state imaging element of the second variant of the first embodiment in that the circuits in the solid-state imaging element 200 are dispersedly arranged on three semiconductor chips.

[0183] Fig.17 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in a third variant of the first embodiment of the present technology. The solid-state imaging element 200 of the third variant of the first embodiment includes an upper pixel chip 203, a lower pixel chip 204, and a circuit chip 202. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. By the way, in addition to using Cu-Cu bonding, connection can be made by vertical interconnection paths or bumps.

[0184] The upper pixel array section 221 is arranged on the upper pixel chip 203. The lower pixel array section 222 is arranged on the lower pixel chip 204. For each pixel in the pixel array section 220, a part thereof is arranged in the upper pixel array section 221, and the remaining part is arranged in the lower pixel array section 222.

[0185] Furthermore, a column signal processing circuit 260, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are arranged on the circuit chip 202. Circuits other than the column signal processing circuit 260 are not shown in the figure.

[0186] Incidentally, the upper pixel chip 203 is an example of a first chip described in the claims, and the lower pixel chip 204 is an example of a second chip described in the claims. The circuit chip 202 is an example of a third chip described in the claims.

[0187] As shown in the figure, since a three-layer structure is adopted, it is possible to reduce useless space and further miniaturize pixels compared to a two-layer structure. In addition, the lower pixel chip 204 in the second layer can be manufactured by a dedicated process for capacitors or switches.

[0188] In this way, since the circuits in the solid-state imaging element 200 are dispersedly configured on three semiconductor chips in the third variant of the first embodiment of the present technology, the pixels can be further miniaturized compared to the case where the circuits are dispersedly configured on two semiconductor chips.

[0189] <2. Second Implementation Method>

[0190] Although the reset level is sampled and held during the exposure period in the above-mentioned first embodiment, it is difficult to set the exposure period to be shorter than the sampling and holding period of the reset level in this configuration. The solid-state imaging element 200 of the second embodiment is different from the solid-state imaging element of the first embodiment in that the exposure period is further shortened by adding a transistor for discharging charge from the photoelectric conversion element.

[0191] Fig.18 2 is a circuit diagram showing a configuration example of a pixel 300 in a second embodiment of the present technology. The pixel 300 of the second embodiment is different from the pixel of the first embodiment in that a discharge transistor 317 is further provided in the upstream circuit 310 .

[0192] The discharge transistor 317 functions as an overflow drain that discharges electric charge from the photoelectric conversion element 311 in accordance with a discharge signal ofg from the vertical scanning circuit 211. As the discharge transistor 317, for example, an nMOS transistor is used.

[0193] In a configuration in which the discharge transistor 317 is not provided as in the first embodiment, blooming may occur when charges are transferred from the photoelectric conversion element 311 to the FD 314 for all pixels. Then, at the time of FD reset, the potential of the FD 314 and the upstream node 320 decreases. As the potential decreases, current that charges and discharges the capacitor elements 321 and 322 continues to be generated, and the IR drop of the power supply or the ground changes from a steady state without blooming.

[0194] On the other hand, when the signal levels of all pixels are sampled and held, after the signal charge is transferred, the photoelectric conversion element 311 becomes a state without charge, so that no halo occurs, and the IR drop of the power supply or ground becomes a constant state without halo. Since the IR drop at the sample-hold reset level is different from the IR drop at the sample-hold signal level, streaking noise occurs.

[0195] In contrast, in the second embodiment in which the discharge transistor 317 is provided, the charge of the photoelectric conversion element 311 is discharged to the overflow drain side. Therefore, approximately the same IR drop occurs when sampling and holding the reset level and when sampling and holding the signal level, and band noise can be suppressed.

[0196] Fig.19 1 is a timing diagram showing an example of global shutter operation in the second embodiment of the present technology. At time T0 before the exposure start time, the vertical scanning circuit 211 sets the discharge signal ofg of all pixels to a high level and provides a high-level FD reset signal rst to all pixels during the pulse period. Therefore, PD reset and FD reset are performed on all pixels. In addition, the reset level is sampled and held. Here, ofg_[n] in the figure represents a signal about the nth row of pixels among N rows.

[0197] Then, at the exposure start time T1, the vertical scanning circuit 211 returns the discharge signal ofg of all pixels to a low level. Then, during the period from the time T2 immediately before the end of exposure to the exposure end time T3, the vertical scanning circuit 211 provides a high-level transfer signal trg to all pixels. Thus, the signal level is sampled and held.

[0198] In the configuration in which the discharge transistor 317 is not provided as in the first embodiment, both the transfer transistor 312 and the FD reset transistor 313 must be turned on at the start of exposure (i.e., at the time of PD reset). In this control, the FD 314 must also be reset at the same time when the PD is reset. Therefore, it is necessary to perform FD reset again during the exposure period and sample and hold the reset level, and it is difficult to set the exposure period to be shorter than the sampling and holding period of the reset level. When the reset level of all pixels is sampled and held, a certain waiting time is required before the voltage or current reaches stability, and, for example, a sampling and holding period of several microseconds (μs) to several tens of microseconds (μs) is required.

[0199] On the other hand, in the second embodiment provided with the discharge transistor 317, the PD reset and the FD reset can be performed separately. Therefore, as shown in the figure, the reset level can be sampled and held by performing the FD reset before the release of the PD reset (exposure start). Therefore, the exposure period can be set to be shorter than the sampling and holding period of the reset level.

[0200] Incidentally, the first to third modified examples of the first embodiment can also be applied to the second embodiment.

[0201] In this way, since the discharge transistor 317 for discharging the charge from the photoelectric conversion element 311 is provided according to the second embodiment of the present technology, the reset level can be sampled and held by performing FD reset before the start of exposure. Therefore, the exposure period can be set to be shorter than the sampling and holding period of the reset level.

[0202] <3. Third Implementation Plan>

[0203] Although the FD 314 is initialized by the power supply voltage VDD in the above-described first embodiment, in this configuration, there is a possibility that the light sensitivity non-uniformity (PRNU) deteriorates due to the difference or parasitic capacitance of the capacitor elements 321 and 322. The solid-state imaging element 200 of the third embodiment is different from that of the first embodiment in that the PRNU is improved by lowering the power supply voltage of the FD reset transistor 313 at the time of readout.

[0204] Fig. 20 3 is a circuit diagram showing a configuration example of a pixel 300 in a third embodiment of the present technology. The pixel 300 of the third embodiment is different from the pixel of the first embodiment in that the source of the FD reset transistor 313 is disconnected from the power supply voltage VDD of the pixel 300.

[0205] The drain of the FD reset transistor 313 of the third embodiment is connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by, for example, the timing control circuit 212. Incidentally, the timing control circuit 212 is an example of a control circuit described in the claims.

[0206] Here, we will refer to Fig.21 and Fig. 22 Let us consider the degradation of PRNU in the pixel 300 of the first embodiment. In the first embodiment, Fig.21 As shown, at time T0 immediately before exposure starts, the potential of the FD 314 decreases due to reset feedthrough of the FD reset transistor 313. This variation is Vft.

[0207] In the first embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 changes from VDD to VDD-Vft at time T0. In addition, the potential of the upstream node 320 during exposure is VDD-Vft-Vsig.

[0208] Furthermore, in the first embodiment, if Fig. 22 As shown, the FD reset transistor 313 is turned on at the time of reading, and the FD 314 is fixed to the power supply voltage VDD. The variation amount Vft of the FD 314 causes the potentials of the upstream node 320 and the downstream node 340 to be higher by about Vft at the time of reading. However, due to the difference in the capacitance value of the capacitor elements 321 and 322 or due to the parasitic capacitance, the amount of voltage to be shifted varies in each pixel, which causes the degradation of PRNU.

[0209] When the downstream node 340 is offset by Vft, the offset amount of the upstream node 320 is expressed by the following equation, for example.

[0210] {(Cs+δCs) / (Cs+δCs+Cp)}*Vft...Formula 4

[0211] In the above formula, Cs is the capacitance value of the capacitance element 322 on the signal level side, δCs is the difference in Cs, and Cp is the capacitance value of the parasitic capacitance of the downstream node 340 .

[0212] Formula 4 can be approximated as follows.

[0213] {1-(δCs / Cs)*(Cp / Cs)}*Vft...Formula 5

[0214] According to Formula 5, the variation in the downstream node 340 can be expressed as follows.

[0215] {(δCs / Cs)*(Cp / Cs)}*Vft...Formula 6

[0216] Assume (δCs / Cs) is 10 -2 , (Cp / Cs) is 10 -1 , and Vft is 400 millivolts (mV), then according to Formula 6, PRNU is 400μVrms, which is a relatively large value.

[0217] In particular, if it is desired to reduce the kTC noise when the capacitance subjected to input scaling is sampled and held, it is necessary to increase the charge-voltage conversion efficiency of the FD 314. Although it is necessary to reduce the capacitance of the FD 314 in order to increase the charge-voltage conversion efficiency, the variation Vft increases as the capacitance of the FD 314 decreases and may become several hundred millivolts (mV). In this case, according to Formula 6, the influence of the PRNU may be at a level that cannot be ignored.

[0218] Fig.23 : is a timing chart showing an example of voltage control in the third embodiment of the present technology.

[0219] During the period in which readout is performed row by row after time T9 , the timing control circuit 212 controls the reset power supply voltage VRST to a value different from the value during the exposure period.

[0220] For example, during exposure, the timing control circuit 212 sets the reset power supply voltage VRST to the same value as the power supply voltage VDD. On the other hand, during readout, the timing control circuit 212 reduces the reset power supply voltage VRST to VDD-Vft. That is, during readout, the timing control circuit 212 reduces the reset power supply voltage VRST by an amount substantially consistent with the variation amount Vft caused by reset feedthrough. This control can make the reset level of the FD 314 equal during exposure and during readout.

[0221] As shown in the figure, the control of the reset power supply voltage VRST can reduce the voltage variation between the FD 314 and the upstream node 320. Therefore, it is possible to suppress the degradation of the PRNU due to the difference between the capacitance elements 321 and 322 or due to the parasitic capacitance.

[0222] Incidentally, the first to third modifications of the first embodiment and the second embodiment can also be applied to the third embodiment.

[0223] In this way, according to the third embodiment of the present technology, since the timing control circuit 212 reduces the reset power supply voltage VRST by the variation amount Vft caused by the reset feedthrough at the time of reading, the reset level at the time of exposure and at the time of reading can be made equal. Therefore, the degradation of the photosensitivity non-uniformity (PRNU) can be suppressed.

[0224] <4. Fourth Implementation Plan>

[0225] In the first embodiment described above, the signal level is read out after the reset level for each frame, but in this configuration, there is a possibility that the light sensitivity non-uniformity (PRNU) deteriorates due to the difference between the capacitor elements 321 and 322 or due to parasitic capacitance. The solid-state imaging element 200 of the fourth embodiment is different from the solid-state imaging element of the first embodiment in that the PRNU is improved by switching the level held in the capacitor element 321 and the level held in the capacitor element 322 for each frame.

[0226] The solid-state imaging element 200 of the fourth embodiment continuously captures a plurality of frames in synchronization with a vertical synchronization signal. An odd-numbered frame is referred to as an "odd-numbered frame", and an even-numbered frame is referred to as an "even-numbered frame". Incidentally, an odd-numbered frame and an even-numbered frame are examples of a pair of frames described in the claims.

[0227] Fig.24 1 is a timing diagram showing an example of global shutter operation for odd-numbered frames in the fourth embodiment. During exposure of odd-numbered frames, the upstream circuit 310 in the solid-state imaging element 200 sets the selection signal Φs to a high level after the selection signal Φr, thereby maintaining the capacitor 321 at a reset level, and then maintaining the capacitor 322 at a signal level.

[0228] Fig.25 1 is a timing chart showing an example of the readout operation of the odd-numbered frame in the fourth embodiment of the present technology. During the readout of the odd-numbered frame, the downstream circuit 350 in the solid-state imaging element 200 sets the selection signal Φs to a high level after the selection signal Φr to read out the signal level after the reset level.

[0229] Fig.26 1 is a timing diagram showing an example of global shutter operation for even frames in the fourth embodiment. During exposure of even frames, the upstream circuit 310 in the solid-state imaging element 200 sets the selection signal Φr to a high level after the selection signal Φs, thereby maintaining the capacitor element 322 at a reset level, and then maintaining the capacitor element 321 at a signal level.

[0230] Fig. 27 1 is a timing chart showing an example of the readout operation of the even-numbered frame in the fourth embodiment of the present technology. During the readout of the even-numbered frame, the downstream circuit 350 in the solid-state imaging element 200 sets the selection signal Φr to a high level after the selection signal Φs to read out the signal level after the reset level.

[0231] like Fig.24 and Fig.26As shown in FIG. 1 , the levels to be held in the capacitor elements 321 and 322 are reversed in the even frame and the odd frame. Therefore, the polarity of the PRNU is also reversed in the even frame and the odd frame. The downstream column signal processing circuit 260 calculates the average value by adding the odd frame and the even frame. Therefore, the PRNUs with opposite polarities can be canceled out.

[0232] This control is an effective control implemented by capturing a moving image and adding frames. In addition, there is no need to add an element to the pixel 300, and this control can be implemented only by changing the driving method.

[0233] Incidentally, the first to third modified examples of the first embodiment and the second and third embodiments can also be applied to the fourth embodiment.

[0234] In this way, in the fourth embodiment of the present technology, since the level held in the capacitor element 321 and the level held in the capacitor element 322 are reversed in the odd frame and the even frame, the polarity of the PRNU can be reversed in the odd frame and the even frame. Since the column signal processing circuit 260 adds the odd frame and the even frame, the degradation of the PRNU can be suppressed.

[0235] <5. Fifth Implementation Plan>

[0236] In the first embodiment described above, the column signal processing circuit 260 obtains the difference between the reset level and the signal level for each column. However, in this configuration, when light with very high illuminance is incident on a pixel, there is a possibility that a black dot phenomenon occurs in which the brightness decreases and becomes dark due to charge overflow from the photoelectric conversion element 311. The solid-state imaging element 200 of the fifth embodiment is different from the solid-state imaging element of the first embodiment in that whether the black dot phenomenon occurs is determined for each pixel.

[0237] Fig.28 : is a circuit diagram showing a configuration example of a column signal processing circuit 260 in a fifth embodiment of the present technology. In the column signal processing circuit 260 of the fifth embodiment, a plurality of ADCs 270 are configured and a digital signal processing section 290 is configured. In addition, a plurality of CDS processing sections 291 and a plurality of selectors 292 are configured in the digital signal processing section 290. The ADC 270, the CDS processing section 291, and the selector 292 are provided for each column.

[0238] In addition, the ADC 270 includes a comparator 280 and a counter 271. The comparator 280 compares the level of the vertical signal line 309 with the ramp signal Rmp from the DAC 213, and outputs a comparison result VCO. The comparison result VCO is provided to the counter 271 and the timing control circuit 212. The comparator 280 includes a selector 281, capacitance elements 282 and 283, auto-zero switches 284 and 286, and a comparison section 285.

[0239] The selector 281 connects any one of the vertical signal line 309 of the corresponding column and the node having a predetermined reference voltage VREF to the non-inverting input terminal (+) of the comparison section 285 via the capacitor element 282 according to the input side selection signal selin. The input side selection signal selin is provided from the timing control circuit 212. Incidentally, the selector 281 is an example of an input side selector described in the claims.

[0240] The comparison unit 285 compares the levels of the non-inverting input terminal (+) and the inverting input terminal (−), and outputs the comparison result VCO to the counter 271. The ramp signal Rmp is input to the inverting input terminal (−) via the capacitor 283.

[0241] The auto-zero switch 284 short-circuits the non-inverting input terminal (+) and the output terminal of the comparison result VCO according to the auto-zero signal Az from the timing control circuit 212. The auto-zero switch 286 short-circuits the inverting input terminal (-) and the output terminal of the comparison result VCO according to the auto-zero signal Az.

[0242] The counter 271 counts the count value until the comparison result VCO is inverted, and outputs a digital signal CNT_out indicating the count value to the CDS processing unit 291 .

[0243] The CDS processing unit 291 performs CDS processing on the digital signal CNT_out. The CDS processing unit 291 calculates a difference between the digital signal CNT_out corresponding to the reset level and the digital signal CNT_out corresponding to the signal level, and outputs the difference to the selector 292 as CDS_out.

[0244] The selector 292 outputs the CDS-processed digital signal CDS_out or the full-code digital signal FULL as pixel data of the corresponding column according to the output-side selection signal selout from the timing control circuit 212. Incidentally, the selector 292 is an example of an output-side selector described in the claims.

[0245] Fig.291 is a timing chart showing an example of the global shutter operation in the fifth embodiment of the present technology. The control method of the transistor at the time of the global shutter operation of the fifth embodiment is similar to the control method of the first embodiment.

[0246] Here, it is assumed that light with very high illuminance is incident on the pixel 300. In this case, the charge of the photoelectric conversion element 311 becomes full, the charge overflows from the photoelectric conversion element 311 to the FD 314, and the potential of the FD 314 after the FD is reset decreases. The dashed line in the figure represents the potential change of the FD 314 when weak sunlight that causes a relatively small amount of overflowing charge is incident. The dotted line in the figure represents the potential change of the FD 314 when strong sunlight that causes a relatively large amount of overflowing charge is incident.

[0247] When weak sunlight is incident, the reset level decreases at time T3 when the FD reset is completed, but the level is not completely reduced at this time.

[0248] On the other hand, when strong sunlight is incident, the reset level is completely lowered at time T3. In this case, the signal level becomes the same as the reset level, and the potential difference between them is "0", so that the digital signal after CDS processing becomes black as in the case of a dark state. In this way, the phenomenon in which a pixel becomes black even if light with very high illuminance such as sunlight is incident is called a black dot phenomenon or halo.

[0249] In addition, when the level of FD 314 of a pixel in which a black dot phenomenon has occurred is too low, it is difficult to ensure the operating point of the upstream circuit 310, and the current id1 of the current source transistor 316 changes. Since the current source transistors 316 of each pixel are connected to a common power supply or ground, when the current in a certain pixel changes, the change in the IR voltage drop of the pixel affects the sampling level of other pixels. The pixel in which the black dot phenomenon has occurred becomes an interference source, and the pixel in which the sampling level has changed due to the pixel becomes an interfered source. Therefore, stripe noise is generated.

[0250] Incidentally, in the case where the discharge transistor 317 is provided as in the second embodiment, in the pixel having black dots (halos), the overflowing charge is discarded to the discharge transistor 317 side, so that the black dot phenomenon is unlikely to occur. However, even if the discharge transistor 317 is provided, part of the charge may flow to the FD 314, and there is a possibility that the black dot phenomenon is not completely solved. In addition, due to the addition of the discharge transistor 317, there is also a disadvantage that the ratio of the effective area / charge amount per pixel is reduced. Therefore, it is desirable to suppress the black dot phenomenon without using the discharge transistor 317.

[0251] As a method of suppressing the black dot phenomenon without using the discharge transistor 317, two methods can be thought of. The first method is to adjust the clip level of the FD 314. The second method is to determine whether the black dot phenomenon will occur at the time of reading and replace the output with a full code when the black dot phenomenon occurs.

[0252] In the first method, the high level of the FD reset signal rst in the figure (in other words, the gate of the FD reset transistor 313) is equivalent to the power supply voltage VDD, and the low level thereof is equivalent to the clipping level of the FD 314. In the first embodiment, the difference between the high level and the low level (i.e., the amplitude) is set to a value corresponding to the dynamic range. In contrast, in the fifth embodiment, it is adjusted to a value obtained by further adding a margin to this value. Here, the value corresponding to the dynamic range is equivalent to the difference between the power supply voltage VDD and the potential of the FD 314 when the digital signal becomes a full code.

[0253] By lowering the gate voltage of the FD reset transistor 313 in the off state (the low level of the FD reset signal rst), it is possible to prevent the FD 314 from being excessively lowered due to blooming to thereby deteriorate the operating point of the upstream amplification transistor 315 .

[0254] By the way, the dynamic range changes according to the analog gain of the ADC. When the analog gain is low, a larger dynamic range is required, whereas when the analog gain is high, a smaller dynamic range is sufficient. Therefore, the gate voltage of the FD reset transistor 313 in the off state can also change according to the analog gain.

[0255] Fig.30 3 is a timing chart showing an example of a readout operation in the fifth embodiment of the present technology. When the selection signal Φr becomes high level at time T11 immediately after the readout start time T10, the potential of the vertical signal line 309 changes in the pixel with incident sunlight. The dotted line in the figure indicates the potential change of the vertical signal line 309 when weak sunlight is incident. The dotted line in the figure indicates the potential change of the vertical signal line 309 when strong sunlight is incident.

[0256] During the auto-zero period from time T10 to time T12, the timing control circuit 212 supplies the input side selection signal selin of, for example, "0", and connects the comparison section 285 to the vertical signal line 309. During this auto-zero period, the timing control circuit 212 performs auto-zero by the auto-zero signal Az.

[0257] For the second method, during the determination period from time T12 to time T13, the timing control circuit 212 provides an input side selection signal selin of, for example, "1". According to the input side selection signal selin, the comparison unit 285 is disconnected from the vertical signal line 309 and connected to a node having a reference voltage VREF. The reference voltage VREF is set to an expected value of the level of the vertical signal line 309 when no halo occurs. For example, when the gate-source voltage of the downstream amplifying transistor 351 is Vgs2, Vrst is equivalent to Vreg-Vgs2. In addition, the DAC 213 reduces the level of the ramp signal Rmp from Vrmp_az to Vrmp_sun during the determination period.

[0258] Furthermore, during the determination period, in the case where halation does not occur, the reset level Vrst of the vertical signal line 309 is substantially the same as the reference voltage VREF, and the potential of the inverting input terminal (+) of the comparison section 285 does not change much from the potential at the time of automatic zeroing. On the other hand, since the non-inverting input terminal (-) has been lowered from Vrmp_az to Vrmp_sun, and therefore, the comparison result VCO becomes a high level.

[0259] On the contrary, when haloing occurs, the reset level Vrst becomes sufficiently higher than the reference voltage VREF, and when the following expression is satisfied, the comparison result VCO becomes a low level.

[0260] Vrst - VREF > Vrmp_az - Vrmp_sun ... Formula 7

[0261] That is, the timing control circuit 212 can determine whether halation occurs based on whether the VCO becomes a low level as a result of the comparison during the determination period.

[0262] Incidentally, in order to avoid erroneous determination due to differences in threshold voltage of the downstream amplifier transistor 351, IR drop differences of Vregs within the plane, etc., a larger margin for solar determination (the right side of Formula 7) must be ensured to a certain extent.

[0263] After the time T13 after the determination period has passed, the timing control circuit 212 connects the comparison unit 285 to the vertical signal line 309. Furthermore, when the P-phase stable period from the time T13 to the time T14 has passed, the P-phase is read out during the period from the time T14 to the time T15. When the D-phase stable period from the time T15 to the time T19 has passed, the D-phase is read out during the period from the time T19 to the time T20.

[0264] When it is determined that halation does not occur within the determination period, the timing control circuit 212 controls the selector 292 through the output side selection signal selout to directly output the digital signal CDS_out after the CDS processing as it is.

[0265] On the other hand, if it is determined that halation occurs during the determination period, the timing control circuit 212 controls the selector 292 through the output side selection signal selout to output the full code FULL instead of the digital signal CDS_out after CDS processing. Therefore, the black dot phenomenon can be suppressed.

[0266] Incidentally, the first to third modified examples of the first embodiment and the second to fourth embodiments can also be applied to the fifth embodiment.

[0267] In this way, according to the fifth embodiment of the present technology, since the timing control circuit 212 determines whether the black dot phenomenon has occurred based on the comparison result VCO and outputs a full code when the black dot phenomenon occurs, the black dot phenomenon can be suppressed.

[0268] <6. Sixth Implementation Plan>

[0269] In the first embodiment described above, the vertical scanning circuit 211 performs control for simultaneously exposing all rows (all pixels) (i.e., global shutter operation). However, when the simultaneity of exposure is not required and low noise is required when performing a test, performing an analysis, etc., it is desirable to perform a rolling shutter operation. The solid-state imaging element 200 of the sixth embodiment is different from the solid-state imaging element of the first embodiment in that a rolling shutter operation is performed when performing a test, etc.

[0270] Fig.31 2 is a timing chart showing an example of a rolling shutter operation in the sixth embodiment of the present technology. The vertical scanning circuit 211 performs control for sequentially selecting a plurality of rows and starting exposure. This figure shows exposure control for the n-th row.

[0271] During the period from time T0 to time T2, the vertical scanning circuit 211 provides a high-level downstream selection signal selb, a selection signal Φr, and a selection signal Φs to the nth row. In addition, at the exposure start time T0, the vertical scanning circuit 211 provides a high-level FD reset signal rst and a downstream reset signal rstb to the nth row during the pulse period. At the exposure end time T1, the vertical scanning circuit 211 provides a transfer signal trg to the nth row. Through the rolling shutter operation in the figure, the solid-state imaging element 200 can generate image data with low noise.

[0272] Incidentally, during normal image pickup, the solid-state image pickup element 200 of the sixth embodiment performs a global shutter operation similarly to the first embodiment.

[0273] Furthermore, the first to third modified examples of the first embodiment and the second to fifth embodiments can also be applied to the sixth embodiment.

[0274] In this way, according to the sixth embodiment of the present technology, since the vertical scanning circuit 211 performs control for sequentially selecting a plurality of rows and starting exposure (ie, rolling shutter operation), image data with low noise can be generated.

[0275] <7. Seventh Implementation Plan>

[0276] In the first embodiment described above, the source of the upstream source follower (upstream amplifier transistor 315 and current source transistor 316) is connected to the power supply voltage VDD, and readout is performed row by row in a state where the source follower is turned on. However, in this driving method, there is a possibility that the circuit noise of the upstream source follower is propagated to the downstream during row-by-row readout, thereby increasing random noise. The solid-state imaging element 200 of the seventh embodiment is different from the solid-state imaging element of the first embodiment in that noise is reduced by turning off the upstream source follower during readout.

[0277] Fig.32 1 is a block diagram showing a configuration example of a solid-state imaging element 200 in a seventh embodiment of the present technology. The solid-state imaging element 200 of the seventh embodiment is different from the solid-state imaging element of the first embodiment in that it further includes a regulator 420 and a switching section 440. In addition, a plurality of effective pixels 301 and a predetermined number of dummy pixels 430 are arranged in the pixel array section 220 of the seventh embodiment. The dummy pixels 430 are arranged around the area where the effective pixels 301 are arranged.

[0278] In addition, a power supply voltage VDD is supplied to each dummy pixel 430, and the power supply voltage VDD and the source voltage Vs are supplied to each effective pixel 301. The figure omits a signal line for supplying the power supply voltage VDD to the effective pixel 301. In addition, the power supply voltage VDD is supplied from a pad 410 outside the solid-state imaging element 200.

[0279] The regulator 420 generates a constant generated voltage V based on the input potential Vi from the dummy pixel 430. gen , and provides the generated voltage to the switching section 440. The switching section 440 selects the power supply voltage VDD from the pad 410 or the generated voltage V gen , and supplies the selected voltage as the source voltage Vs to each column of the effective pixel 301.

[0280] Fig.33: is a circuit diagram showing a configuration example of the dummy pixel 430 , the regulator 420 , and the switch 440 in the seventh embodiment of the present technology. Fig.33 a in FIG. 4 is a circuit diagram of the pseudo pixel 430 and the regulator 420, and Fig.33 Ref. b in FIG. 4 is a circuit diagram of the switching unit 440 .

[0281] like Fig.33 As shown in a in FIG. 1 , the pseudo pixel 430 includes a reset transistor 431, an FD 432, an amplifier transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to the reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charge and generates a voltage corresponding to the amount of charge. The amplifier transistor 433 amplifies the voltage level of the FD 432 and provides the amplified voltage as the input voltage Vi to the regulator 420.

[0282] Furthermore, sources of the reset transistor 431 and the amplifier transistor 433 are connected to the power supply voltage VDD. A current source transistor 434 is connected to a drain of the amplifier transistor 433. The current source transistor 434 supplies a current id1 under the control of the vertical scanning circuit 211.

[0283] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor 423. The low-pass filter 421 allows a component of a low-frequency band lower than a predetermined frequency in a signal of an input voltage Vi to pass as an output voltage Vj.

[0284] The output voltage Vj is input to the non-inverting input terminal (+) of the buffer amplifier 422. The inverting input terminal (-) of the buffer amplifier 422 is connected to its output terminal. The capacitor 423 keeps the voltage of the output terminal of the buffer amplifier 422 at V gen . The V gen is provided to the switching unit 440 .

[0285] like Fig.33 As shown in a in FIG. 8 , the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442 . The switching circuit 442 is arranged for each column of the effective pixels 301 .

[0286] The inverter 441 inverts the switching signal SW from the timing control circuit 212. The inverter 441 provides the inverted signal to each of the switching circuits 442.

[0287] The switching circuit 442 selects the power supply voltage VDD and the generated voltage V genThe switching circuit 442 includes switches 443 and 444. The switch 443 opens and closes the path between the node with the power supply voltage VDD and the corresponding column according to the switching signal SW. The switch 444 opens and closes the path between the node with the generated voltage VDD and the corresponding column according to the inverted signal of the switching signal SW. gen The path between the nodes and the corresponding columns.

[0288] Fig.34 : is a timing chart showing an operation example of the dummy pixel 430 and the regulator 420 in the seventh embodiment of the present technology. At time T10 just before a certain row is read out, the vertical scanning circuit 211 supplies a reset signal RST of a high level (here, the power supply voltage VDD) to each dummy pixel 430. The potential Vfd of the FD 432 in the dummy pixel 430 is initialized to the power supply voltage VDD. Then, when the reset signal RST becomes a low level, the reset feedthrough causes a change in VDD-Vft.

[0289] In addition, the input voltage Vi is reduced to VDD-Vgs-Vsig after reset. After passing through the low-pass filter 421, Vj and V gen The voltage becomes approximately constant.

[0290] After time T20 immediately before the next row is read out, similar control is performed for each row, and a constant generated voltage V gen .

[0291] Fig.35 301 in the seventh embodiment of the present technology. The circuit configuration of the effective pixel 301 is similar to that of the pixel 300 in the first embodiment, except that the source voltage Vs from the switching section 440 is supplied to the source of the upstream amplifying transistor 315.

[0292] Fig.36 is a timing diagram showing an example of global shutter operation in the seventh embodiment of the present technology. In the seventh embodiment, when exposure is performed simultaneously in all pixels, the switching section 440 selects the power supply voltage VDD and provides the power supply voltage as the source voltage Vs. In addition, the voltage of the upstream node decreases from VDD-Vgs-Vth to VDD-Vgs-Vsig at time T4. Here, Vth is the threshold voltage of the transfer transistor 312.

[0293] Fig.37 1 is a timing chart showing an example of a readout operation in the seventh embodiment of the present technology. In the seventh embodiment, the switching section 440 selects the generated voltage V gen The generated voltage is provided as the source voltage Vs.gen is adjusted to VDD-Vgs-Vft. Furthermore, in the seventh embodiment, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to stop supplying the current id1.

[0294] Fig.38 3 is a diagram for explaining the effect in the seventh embodiment of the present technology. In the first embodiment, when the readout is performed row by row, the source coupler (upstream amplification transistor 315 and current source transistor 316) of the pixel 300 to be read out is turned on. However, in this driving method, there is a possibility that the circuit noise of the upstream source coupler is propagated to the downstream (capacitive element, downstream source coupler or ADC), thereby increasing the readout noise.

[0295] For example, in the first embodiment, as shown in the figure, the kTC noise generated in the pixel during the global shutter operation is 450 μVrms. In addition, the noise generated in the upstream source follower (upstream amplifier transistor 315 and current source transistor 316) when reading out each row is 380 μVrms. The noise generated after the downstream source follower is 160 μVrms. Therefore, the total noise is 610 μVrms. In this way, in the first embodiment, the proportion of the noise of the upstream source follower in the total noise value becomes relatively large.

[0296] In order to reduce the noise of the upstream source coupler follower, as described above, in the seventh embodiment, a voltage (Vs) that can be adjusted is provided to the source of the upstream source coupler follower. During the global shutter (exposure) operation, the switching section 440 selects the power supply voltage VDD and provides the power supply voltage as the source voltage Vs. Then, after the exposure is completed, the switching section 440 switches the source voltage Vs to VDD-Vgs-Vft. In addition, during the global shutter (exposure) operation, the timing control circuit 212 turns on the upstream current source transistor 316, and turns off the current source transistor 316 after the exposure is completed.

[0297] like Fig.36 and Fig.37 As shown in FIG. 1 , the above control can make the potential of the upstream node equal when performing the global shutter operation and when performing the readout for each row, and can improve the PRNU. In addition, since the upstream source coupler is in the disconnected state when reading out for each row, Fig.38 As shown, the circuit noise of the source follower is not generated and becomes zero (μVrms). Incidentally, the upstream amplifying transistor 315 in the upstream source follower is in the on state.

[0298] In this way, since the upstream source follower is in an OFF state at the time of reading according to the seventh embodiment of the present technology, noise generated in the source follower can be reduced.

[0299] <8. Application examples of mobile objects>

[0300] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobility vehicle, an airplane, a drone, a ship, and a robot.

[0301] Fig.39 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0302] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig.39 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: interface) 12053 are shown.

[0303] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for various devices such as: a drive force generating device such as an internal combustion engine or a drive motor for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a braking force for the vehicle.

[0304] The body system control unit 12020 controls the operation of various devices mounted in the body according to various programs. For example, the body system control unit 12020 functions as a control device for various devices such as the following: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, radio waves emitted from a portable device that replaces the key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the door lock device, power window device, lights, etc. of the vehicle.

[0305] The vehicle exterior information detection unit 12030 detects information related to the exterior of the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform detection processing of objects such as people, vehicles, obstacles, signs, text on the road surface, etc., or detection processing of the distance thereto.

[0306] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information related to distance measurement. In addition, the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.

[0307] The in-vehicle information detection unit 12040 detects information related to the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the state of the driver. For example, the driver state detection unit 12041 includes a camera that takes a picture of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, and can determine whether the driver is dozing off.

[0308] Based on the information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device, and output a control instruction to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of an advanced driver assistance system (ADAS), the functions of which include collision avoidance or impact mitigation of the vehicle, following driving based on vehicle-to-vehicle distance, vehicle constant speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0309] In addition, based on the information related to the interior or exterior of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control such as automatic driving to enable the vehicle to drive autonomously without the need for driver operation by controlling the driving force generating device, steering mechanism, braking device, etc.

[0310] In addition, based on the information related to the exterior of the vehicle obtained by the exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12020. For example, based on the position of the preceding vehicle or oncoming vehicle detected by the exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control for preventing glare, such as switching the headlights from high beam to low beam.

[0311] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle passengers or the outside of the vehicle of information. Fig.39 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0312] Fig.40 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0313] exist Fig.40 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104, and 12105.

[0314] Camera units 12101, 12102, 12103, 12104, 12105 are arranged, for example, at the front nose, side mirrors, rear bumper, and trunk door of the vehicle 12100, and at the upper part of the windshield in the vehicle compartment. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment mainly acquire images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the side mirrors mainly acquire images on the sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or trunk door mainly acquires images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0315] By the way, Fig.40An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above is obtained.

[0316] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging devices, or may be an imaging device having pixels for phase difference detection.

[0317] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can obtain the distance to each solid object within the camera ranges 12111 to 12114 and the change in the distance over time (relative speed relative to the vehicle 12100), and thereby extract the following solid object as the leading vehicle: it is particularly the closest solid object existing on the driving path of the vehicle 12100 and the solid object traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can set the inter-vehicle distance that should be ensured in advance relative to the front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control for automatic driving, such as enabling the vehicle to travel autonomously without the need for driver operation, etc.

[0318] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into the three-dimensional object data of a two-wheeled vehicle, an ordinary car, a large vehicle, a pedestrian, a telephone pole or other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted results to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes the obstacles around the vehicle 12100 into obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually identify. Then, the microcomputer 12051 determines the degree of danger representing the risk of collision with each obstacle. In the case where the collision risk is equal to or greater than the set value and a collision is likely to occur, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thus provide assisted driving for avoiding collisions.

[0319] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the image captured by the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by the following process: a process of extracting feature points from the image captured by the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether the object is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the image captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a superimposed manner on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian is displayed at a desired position.

[0320] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. The technology of the present disclosure can be applied to the camera unit 12031 in the above-mentioned configuration. Specifically, for example, Figure 1 The camera device 100 in the embodiment can be applied to the camera unit 12031. When the technology according to the present disclosure is applied to the camera unit 12031, kTC noise can be reduced, and a camera image that is easier to view can be obtained, thereby reducing the fatigue of the driver.

[0321] Incidentally, the above-mentioned embodiments illustrate examples for embodying the present technology, and the matters in the embodiments respectively have a corresponding relationship with the matters specifying the present invention in the claims. Similarly, the matters specifying the present invention in the claims respectively have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be implemented by making various modifications to the embodiments within the scope of protection that does not depart from its main purpose.

[0322] Incidentally, the effects described in this specification are merely examples and not limitative, and there may be additional effects.

[0323] Incidentally, the present technology may also have the following configurations.

[0324] (1) A solid-state imaging device comprising:

[0325] a first capacitive element and a second capacitive element;

[0326] an upstream circuit that sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes each of the first capacitance element and the second capacitance element to maintain the reset level and the signal level;

[0327] a selection circuit that sequentially performs control of connecting one of the first capacitance element and the second capacitance element to a predetermined downstream node, control of disconnecting both of the first capacitance element and the second capacitance element from the downstream node, and control of connecting the other of the first capacitance element and the second capacitance element to the downstream node;

[0328] a downstream reset transistor that initializes a level of the downstream node when both the first capacitance element and the second capacitance element are disconnected from the downstream node; and

[0329] A downstream circuit sequentially reads out the reset level and the signal level from the first capacitance element and the second capacitance element via the downstream node, and outputs the readout reset level and the signal level.

[0330] (2) The solid-state imaging device according to (1) above, further comprising:

[0331] an upstream selection transistor that opens and closes a path between the upstream circuit and a predetermined upstream node; and

[0332] an upstream reset transistor which initializes the level of the upstream node,

[0333] The first capacitive element and the second capacitive element each have a first end commonly connected to the upstream node and each have a second end connected to the selection circuit.

[0334] (3) The solid-state imaging device according to (2) above, wherein:

[0335] During a period in which the upstream circuit causes each of the first capacitance element and the second capacitance element to maintain the reset level and the signal level, the upstream selection transistor is turned into a closed state, and

[0336] The upstream reset transistor initializes the level of the upstream node during a period in which the downstream circuit sequentially reads the reset level and the signal level from the first capacitor and the second capacitor.

[0337] (4) The solid-state imaging device according to any one of (1) to (3) above, wherein:

[0338] The upstream circuit comprises:

[0339] Photoelectric conversion element;

[0340] an upstream transfer transistor that transfers charge from the photoelectric conversion element to a floating diffusion layer;

[0341] a first reset transistor that initializes the floating diffusion layer; and

[0342] an upstream amplifying transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined upstream node, and

[0343] The first capacitive element and the second capacitive element each have a first end commonly connected to the upstream node and each have a second end connected to the selection circuit.

[0344] (5) The solid-state imaging device according to (4) above, further comprising:

[0345] a switching section that adjusts a source voltage to be supplied to a source of the upstream amplifying transistor,

[0346] Wherein, the upstream circuit further includes a current source transistor connected to the drain of the upstream amplifying transistor, and

[0347] After the exposure period ends, the current source transistor changes from the on state to the off state.

[0348] (6) The solid-state imaging device according to (5) above, wherein:

[0349] During an exposure period, the switching section provides a predetermined power supply voltage as the source voltage, and

[0350] After an exposure period ends, the switching section supplies a generated voltage different from the power supply voltage as the source voltage.

[0351] (7) The solid-state imaging device according to (6) above, wherein:

[0352] The difference between the power supply voltage and the generated voltage is substantially consistent with the sum of the variation caused by reset feedthrough of the first reset transistor and the gate-source voltage of the upstream amplifying transistor.

[0353] (8) The solid-state imaging device according to any one of (4) to (7) above, wherein:

[0354] At a predetermined exposure start timing, the upstream transfer transistor transfers the charge to the floating diffusion layer, and the first reset transistor initializes the photoelectric conversion element together with the floating diffusion layer, and

[0355] At a predetermined exposure end time, the upstream transfer transistor transfers the charge to the floating diffusion layer.

[0356] (9) The solid-state imaging device according to any one of (4) to (7) above, wherein:

[0357] The upstream circuit further includes a discharge transistor for discharging the charge from the photoelectric conversion element.

[0358] (10) The solid-state imaging device according to (9) above, wherein:

[0359] Before a predetermined exposure start time, the first reset transistor initializes the floating diffusion layer, and the discharge transistor discharges the charge from the photoelectric conversion element, and

[0360] At a predetermined exposure end time, the upstream transfer transistor transfers the charge to the floating diffusion layer.

[0361] (11) The solid-state imaging device according to any one of (4) to (10) above, further comprising:

[0362] a control circuit that controls a reset power supply voltage of the upstream circuit,

[0363] wherein the first reset transistor initializes the voltage of the floating diffusion layer to the reset power supply voltage, and

[0364] The control circuit sets the reset power supply voltage to a voltage different from a voltage during an exposure period during a readout period for reading the reset level and the signal level.

[0365] (12) The solid-state imaging device according to (11) above, wherein:

[0366] A difference between the reset power supply voltage during the readout period and the reset power supply voltage during the exposure period substantially coincides with an amount of variation caused by reset feedthrough of the first reset transistor.

[0367] (13) The solid-state imaging device according to any one of (4) to (12) above, wherein:

[0368] A first reset signal is input to the gate of the first reset transistor, and

[0369] The amplitude of the first reset signal is a value obtained by adding a predetermined margin to a value corresponding to the dynamic range.

[0370] (14) The solid-state imaging device according to any one of (1) to (13) above, further comprising:

[0371] a digital signal processing unit that adds a pair of consecutive frames together,

[0372] wherein the upstream circuit causes one of the first capacitive element and the second capacitive element to maintain the reset level during an exposure period of one of the pair of frames, and then causes the other of the first capacitive element and the second capacitive element to maintain the signal level, and

[0373] The upstream circuit causes the other of the first and second capacitive elements to maintain the reset level during an exposure period of the other of the pair of frames, and then causes the one of the first and second capacitive elements to maintain the signal level.

[0374] (15) The solid-state imaging device according to any one of (1) to (14) above, further comprising:

[0375] An analog-to-digital converter converts the reset level of the output and the signal level of the output into digital signals in sequence.

[0376] (16) The solid-state imaging device according to (15) above, wherein:

[0377] The analog-to-digital converter comprises:

[0378] a comparator that compares the level of a vertical signal line for transmitting the reset level and the signal level with a predetermined ramp signal and outputs a comparison result; and

[0379] A counter counts a count value during a period until the comparison result is inverted, and outputs the digital signal indicating the count value.

[0380] (17) The solid-state imaging device according to (16) above, wherein:

[0381] The comparator comprises:

[0382] a comparison unit that compares the levels of the pair of input terminals and outputs a comparison result;

[0383] and

[0384] an input-side selector that selects any one of the vertical signal line and a node having a predetermined reference voltage and connects the selected vertical signal line or the node to one of the pair of input terminals, and

[0385] The ramp signal is input to one of the pair of input terminals.

[0386] (18) The solid-state imaging device according to (17) above, further comprising:

[0387] a control unit that determines whether the illuminance is higher than a predetermined value based on the comparison result and outputs a determination result;

[0388] a correlated double sampling (CDS) processing section that performs a correlated double sampling process on the digital signal; and

[0389] An output-side selector outputs the digital signal subjected to the correlated double sampling process or a digital signal having a predetermined value based on the determination result.

[0390] (19) The solid-state imaging device according to any one of (1) to (18) above, further comprising:

[0391] a vertical scanning circuit for performing control for controlling a plurality of rows in each of which a predetermined number of pixels are arranged so as to start exposure of the plurality of rows at the same time,

[0392] The first capacitor, the second capacitor, the upstream circuit, the selection circuit, the downstream reset transistor, and the downstream circuit are arranged in each of the pixels.

[0393] (20) The solid-state imaging device according to (19) above, wherein:

[0394] The vertical scanning circuit also performs control for controlling the plurality of rows to sequentially start exposure.

[0395] (21) The solid-state imaging device according to any one of (1) to (20) above, wherein:

[0396] The upstream circuit is provided on a first chip, and

[0397] The first capacitive element, the second capacitive element, the selection circuit, the downstream reset transistor, and the downstream circuit are provided on a second chip.

[0398] (22) The solid-state imaging device according to (21) above, further comprising:

[0399] an analog-to-digital converter, which converts the reset level of the output and the signal level of the output into digital signals in sequence,

[0400] Wherein, the analog-to-digital converter is arranged on the second chip.

[0401] (23) The solid-state imaging device according to (21) above, further comprising:

[0402] an analog-to-digital converter, which converts the reset level of the output and the signal level of the output into digital signals in sequence,

[0403] Wherein, the analog-to-digital converter is arranged on a third chip.

[0404] (24) A solid-state imaging device comprising:

[0405] a photoelectric conversion unit that converts incident light into electric charges;

[0406] a first amplifying transistor that converts the charge into a voltage;

[0407] A signal line that outputs a pixel signal;

[0408] a first capacitance element having a first end connected to a first node which is an output destination of the first amplifying transistor;

[0409] a second capacitance element provided between the first amplifying transistor and the signal line in parallel with the first capacitance element, wherein a first end of the second capacitance element is connected to the first node;

[0410] a first selection transistor connected to the first capacitive element at a second end of the first capacitive element;

[0411] a second selection transistor connected to the second capacitive element at a second end of the second capacitive element;

[0412] a reset transistor having a source or a drain connected to a second node to which the first selection transistor and the second selection transistor are connected; and

[0413] A second amplifying transistor has a gate connected to the second node, and the second amplifying transistor outputs the pixel signal.

[0414] [reference numerals list]

[0415] 100: Camera device

[0416] 110: Camera lens

[0417] 120: Records Department

[0418] 130: Camera control unit

[0419] 200: Solid-state imaging device

[0420] 201: Upper pixel chip

[0421] 202: Lower pixel chip

[0422] 203: Circuit Chip

[0423] 211: Vertical scanning circuit

[0424] 212: Timing control circuit

[0425] 213: DAC

[0426] 220: Pixel array unit

[0427] 221: Upper pixel array portion

[0428] 222: Lower pixel array portion

[0429] 250: Load MOS circuit block

[0430] 251: Load MOS transistor

[0431] 260: Column signal processing circuit

[0432] 261, 270: ADC

[0433] 262, 290: Digital Signal Processing Department

[0434] 271: Counter

[0435] 280: Comparator

[0436] 281, 292: Selector

[0437] 282, 283, 321, 322: Capacitor elements

[0438] 284, 286: Automatic zeroing switch

[0439] 285: Comparative Department

[0440] 291: CDS Processing Department

[0441] 300: Pixels

[0442] 301: Effective pixels

[0443] 310: Upstream circuit

[0444] 311: Photoelectric conversion element

[0445] 312: Pass transistor

[0446] 313: FD reset transistor

[0447] 314: FD

[0448] 315: Upstream amplifier transistor

[0449] 316: Current Source Transistor

[0450] 317: discharge transistor

[0451] 323: Upstream reset transistor

[0452] 324: Upstream selection transistor

[0453] 330: Select Circuit

[0454] 331, 332: Select transistor

[0455] 341: Downstream reset transistor

[0456] 350: Downstream circuit

[0457] 351: Downstream amplifier transistor

[0458] 352: Downstream selection transistor

[0459] 420: Regulator

[0460] 421: Low pass filter

[0461] 422: Buffer Amplifier

[0462] 423: Capacitor element

[0463] 430: Pseudo-pixel

[0464] 431: Reset transistor

[0465] 432: FD

[0466] 433: Amplifying transistor

[0467] 434: Current Source Transistor

[0468] 440: Switching Department

[0469] 441: Inverter

[0470] 442: Switching Circuit

[0471] 443, 444: switch

[0472] 12031: Camera Department

Claims

1. A light detection device, comprising: a first capacitive element; a second capacitive element connected in parallel with the first capacitive element; an upstream circuit that sequentially generates a reset level and a signal level corresponding to an exposure amount, and causes each of the first capacitance element and the second capacitance element to maintain the reset level and the signal level; a selection circuit that sequentially performs control of connecting one of the first capacitance element and the second capacitance element to a first node, control of disconnecting both of the first capacitance element and the second capacitance element from the first node, and control of connecting the other of the first capacitance element and the second capacitance element to the first node; as well as a downstream circuit that sequentially reads the reset level and the signal level from the first capacitance element and the second capacitance element via the first node and outputs the read reset level and the signal level, The selection circuit includes a first selection transistor and a second selection transistor, the first selection transistor is connected between the first capacitance element and the first node, and the second selection transistor is connected between the second capacitance element and the first node.

2. The light detection device according to claim 1, further comprising: A downstream reset transistor has a source or a drain connected to the first node and resets the first node.

3. The light detection device according to claim 1, wherein: The downstream circuit includes an amplifying transistor having a gate connected to the first node, and the amplifying transistor outputs the signal level.

4. The light detection device according to claim 1, further comprising: An upstream selection transistor for opening and closing a path between the upstream circuit and the first capacitance element and the second capacitance element.

5. The light detection device according to claim 1, wherein: The upstream circuit is provided on a first chip, and The first capacitive element, the second capacitive element, the selection circuit, and the downstream circuit are provided on a second chip.

6. The light detection device according to claim 1, wherein: The upstream circuit comprises: Photoelectric conversion element; an upstream transfer transistor that transfers charges from the photoelectric conversion element to a floating diffusion layer; an upstream reset transistor that initializes the floating diffusion layer; and An upstream amplifying transistor amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to the first capacitance element and the second capacitance element.

7. The light detection device according to claim 6, further comprising: a switching circuit that adjusts a source voltage to be supplied to a source of the upstream amplifying transistor, Wherein, the upstream circuit further includes a current source transistor connected to the drain of the upstream amplifying transistor, and After the exposure period ends, the current source transistor changes from the on state to the off state.

8. The light detection device according to claim 7, wherein: During the exposure period, the switching circuit provides a predetermined power supply voltage as the source voltage, and After an exposure period ends, the switching circuit provides a generated voltage different from the power supply voltage as the source voltage.

9. The light detection device according to claim 7, wherein: The upstream circuit further includes a discharge transistor for discharging the charge from the photoelectric conversion element.

10. The light detection device according to claim 7, further comprising: a control circuit that controls a reset power supply voltage of the upstream circuit, wherein the upstream reset transistor initializes the voltage of the floating diffusion layer to the reset power supply voltage, and The control circuit sets the reset power supply voltage to a voltage different from a voltage during an exposure period during a readout period for reading the reset level and the signal level.

11. The light detection device according to claim 7, wherein: A first reset signal is input to the gate of the upstream reset transistor, and The amplitude of the first reset signal is a value obtained by adding a predetermined margin to a value corresponding to the dynamic range.

12. A light detection device comprising: a photoelectric conversion element that converts incident light into electric charge; a first amplifying transistor that converts the charge into a voltage; A signal line that outputs a pixel signal; a first capacitive element; a second capacitance element provided in parallel with the first capacitance element between the output of the first amplifying transistor and the signal line; a first selection transistor, a first terminal of the first selection transistor being connected to the first capacitive element and a second terminal of the first selection transistor being connected to a first node; a second selection transistor, a first terminal of the second selection transistor being connected to the second capacitive element and a second terminal of the second selection transistor being connected to the first node; as well as A second amplifying transistor, a gate of the second amplifying transistor is connected to the first node, and the second amplifying transistor outputs the pixel signal.

13. The light detection device according to claim 12, further comprising: A reset transistor has a source or a drain connected to the first node and resets a charge level at the first node.

14. The light detection device according to claim 12, further comprising: an upstream transfer transistor that transfers charges from the photoelectric conversion element to a floating diffusion layer; as well as An upstream reset transistor initializes the floating diffusion layer.

15. The light detection device according to claim 12, wherein: The photoelectric conversion element and the first amplifying transistor are provided on a first chip, and The first capacitive element, the second capacitive element, the first selection transistor, the second selection transistor, and the second amplification transistor are provided on a second chip.

16. The light detection device according to claim 15, wherein: The first chip and the second chip are stacked.

17. A light detection device comprising: a photoelectric conversion element that converts incident light into electric charge; a first amplifying transistor that converts the charge into a voltage; A signal line that outputs a pixel signal; a first capacitive element; a second capacitive element; a first selection transistor, a first terminal of the first selection transistor being connected to the first capacitive element and a second terminal of the first selection transistor being connected to a first node; a second selection transistor, a first terminal of the second selection transistor being connected to the second capacitive element and a second terminal of the second selection transistor being connected to the first node; a second amplifying transistor, a gate of the second amplifying transistor being connected to an output of the first selection transistor or the second selection transistor, and the second amplifying transistor outputting the pixel signal; as well as A downstream reset transistor has a source or a drain connected to the first node and resets the charge level at the first node.

18. The light detection device according to claim 17, further comprising: an upstream transfer transistor that transfers charges from the photoelectric conversion element to a floating diffusion layer; as well as An upstream reset transistor initializes the floating diffusion layer.

19. The light detection device according to claim 17, wherein: The photoelectric conversion element and the first amplifying transistor are provided on a first chip, and The first capacitance element, the second capacitance element, the first selection transistor, the second selection transistor, the second amplification transistor, and the downstream reset transistor are provided on a second chip.

20. The light detection device according to claim 19, wherein The first chip and the second chip are stacked.

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