Semiconductor structure and method of fabricating the same

Abstract

The application relates to a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; at least one memory cell, the memory cell being arranged on the substrate, the memory cell comprising a transistor and a capacitor, the transistor comprising a first source / drain electrode, a gate electrode, a second source / drain electrode and a semiconductor layer arranged in sequence along a first direction, the first source / drain electrode and the second source / drain electrode being connected through the semiconductor layer and the gate electrode, the capacitor being arranged on one side of the second source / drain electrode and covering part of the side surface of the semiconductor layer; and at least one bit line, the bit line being arranged on one side of the first source / drain electrode and covering part of the side surface of the semiconductor layer, the contact area of the bit line and the semiconductor layer being smaller than the contact area of the capacitor and the semiconductor layer, the contact area of the bit line and the transistor is reduced, the opposite area of the bit line and the gate electrode of the transistor is reduced, the parasitic capacitance between the bit line and the gate electrode of the transistor is reduced, and the reading capability of the transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Semiconductor memories are generally of planar structure. At present, the size of the semiconductor memories of planar structure has been reduced to the limit, and it is difficult to continue to miniaturize to continue the effectiveness of Moore's law. The semiconductor memories begin to develop in the direction of three-dimensional structure.

[0003] The storage unit of the planar type ring-gate transistor of three-dimensional structure is one of the main directions of development of the semiconductor memories of three-dimensional structure. However, the distance between the gate of the transistor and the bit line is very close, and the parasitic capacitance between the gate of the transistor and the bit line is large. This not only produces signal crosstalk during the read and write operation of the device, but also increases the capacitive load on the word line, increasing the difficulty of signal reading. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor structure and a manufacturing method thereof aiming at the problem of large parasitic capacitance between the gate and the drain of the transistor in the prior art.

[0005] In order to achieve the above-mentioned purpose, in a first aspect, the present application provides a semiconductor structure, comprising:

[0006] a substrate;

[0007] at least one storage unit, the storage unit is arranged on the substrate, each of the storage units comprises a transistor and a capacitor, the transistor comprises a first source / drain, a gate, a second source / drain arranged in sequence along a first direction, and a semiconductor layer surrounding the sidewall covering the gate, the first source / drain and the second source / drain are connected through the semiconductor layer and the gate, the first direction is parallel to the top surface of the substrate, the capacitor is arranged on one side of the second source / drain, and the lower electrode of the capacitor covers part of the side surface of the semiconductor layer;

[0008] at least one bit line, the bit line is arranged on one side of the first source / drain, the bit line covers part of the side surface of the semiconductor layer, and the contact area between the bit line and the semiconductor layer is smaller than the contact area between the capacitor and the semiconductor layer.

[0009] In one of the embodiments, in a second direction perpendicular to the first direction and parallel to the substrate, the semiconductor layer has a first maximum length, and the contact surface between the bit line and the semiconductor layer has a second maximum length, the second maximum length being less than one half of the first maximum length.

[0010] In one of the embodiments, the bit line comprises a first conductive layer covering part of the sidewall of the semiconductor layer away from the capacitor, and the first source / drain is disposed in the first conductive layer.

[0011] In one of the embodiments, the first conductive layer comprises a first extension extending along the second direction, and at least one second extension disposed in the first extension along the second direction and corresponding to the transistor, each of the second extensions covering part of the sidewall of the semiconductor layer away from the capacitor, and the first source / drain is disposed in the second extension.

[0012] In one of the embodiments, the semiconductor structure further comprises:

[0013] a second conductive layer extending along the first direction on one side of the second source / drain, the second conductive layer covering part of the sidewall of the semiconductor layer, and the second source / drain is disposed in the second conductive layer;

[0014] the capacitor takes the second conductive layer as the lower electrode.

[0015] In one of the embodiments, the transistor further comprises:

[0016] a gate dielectric layer surrounding the sidewall of the gate, and disposed between the gate and the semiconductor layer.

[0017] In one of the embodiments, at least one of the memory cells is arranged in an array on the substrate along the first direction, and / or, the second direction, and / or, the third direction, the first direction, the second direction, and the third direction being perpendicular to each other; and the semiconductor structure further comprises:

[0018] at least one word line disposed on the substrate along the third direction, each of the word lines being connected to the gate of a column of the transistors arranged along the third direction.

[0019] In a second aspect, the present application provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0020] providing a substrate, forming a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive material layers alternately stacked on the substrate, and the stack structure defining an isolation region;

[0021] removing the stack structure of the isolation region to form an isolation trench in the isolation region, and the conductive material layers remaining in each layer forming an initial conductive layer;

[0022] filling a second dielectric layer in the isolation trench;

[0023] forming a channel trench through the stack structure by etching away part of the second dielectric layer and part of the stack structure, the channel trench dividing the initial conductive layer into a first conductive layer and a second conductive layer arranged independently, the first conductive layer and the second conductive layer being arranged oppositely along a first direction on two sides of the channel trench, an area of the first conductive layer exposed by the channel trench being smaller than an area of the second conductive layer exposed by the channel trench, wherein the first conductive layer is a bit line;

[0024] forming a semiconductor layer covering a wall of the channel trench, a contact area of the first conductive layer and the semiconductor layer being smaller than a contact area of the second conductive layer and the semiconductor layer;

[0025] forming a gate covering the semiconductor layer and filling the channel trench.

[0026] In one embodiment, along a second direction perpendicular to the first direction, the semiconductor layer has a first maximum length, and a contact surface of the first conductive layer and the semiconductor layer has a second maximum length, the second maximum length being less than one half of the first maximum length.

[0027] In one embodiment, the initial conductive layer includes a first initial conductive layer and a second initial conductive layer, the second initial conductive layer extending along the first direction, the first initial conductive layer being arranged on one side of the second initial conductive layer, the first initial conductive layer extending along the second direction, and the first initial conductive layer and the second initial conductive layer being arranged apart along the first direction.

[0028] forming the channel trench by etching away part of the first initial conductive layer, part of the second initial conductive layer, part of the first dielectric layer, and the second dielectric layer between the first initial conductive layer and the second initial conductive layer, and etching the remaining first initial conductive layer to form the first conductive layer and etching the remaining second initial conductive layer to form the second conductive layer;

[0029] An area in which a projection of the channel trench formed on the substrate and a projection of the first initial conductive layer formed on the substrate coincide is smaller than an area in which a projection of the channel trench formed on the substrate and a projection of the second initial conductive layer formed on the substrate coincide.

[0030] In one of the embodiments, the initial conductive layer comprises a first portion extending along the first direction, a second portion disposed on one side of the first portion, and a third portion connecting the first portion and the second portion, the second portion extending along the second direction, the third portion being disposed between the first portion and the second portion, and the size of the third portion being smaller than the size of the first portion along the second direction; forming a channel groove through the stack structure comprises:

[0031] etching and removing part of the first portion, part of the third portion, part of the first dielectric layer, and part of the second dielectric layer to form the channel groove, and etching and retaining the first portion to form the first conductive layer, and etching and retaining the second portion and the third portion to form the second conductive layer.

[0032] In one of the embodiments, before forming the gate, the method further comprises:

[0033] forming a gate dielectric layer covering the semiconductor layer, the gate and the semiconductor layer being separated by the gate dielectric layer.

[0034] In one of the embodiments, the method for manufacturing the semiconductor structure further comprises:

[0035] forming a capacitor on one side of the second conductive layer with the second conductive layer as a lower electrode.

[0036] In one of the embodiments, forming the capacitor on one side of the second conductive layer comprises:

[0037] removing part of the dielectric layer to expose the sidewall of the second conductive layer;

[0038] forming a high-K dielectric layer covering the sidewall of the second conductive layer;

[0039] forming an upper electrode covering the high-K dielectric layer, the second conductive layer, the high-K dielectric layer, and the upper electrode forming the capacitor.

[0040] The semiconductor structure and the method for manufacturing the same have the following beneficial effects:

[0041] The semiconductor structure has a smaller contact area between the bit line and the semiconductor layer than a contact area between the capacitor and the semiconductor layer, which reduces the contact area between the bit line and the transistor, reduces the facing area between the bit line and the gate of the transistor, and thus reduces the parasitic capacitance between the bit line and the gate of the transistor, and improves the reading ability of the transistor.

[0042] The method for manufacturing the semiconductor structure of the present application, when forming the channel groove, the middle line of the channel groove is deviated to the second conductive layer, so that the area of the first conductive layer exposed by the channel groove is less than the area of the second conductive layer exposed by the channel groove, after forming the transistor, the contact area between the first conductive layer (i.e. the bit line) and the semiconductor layer of the transistor is less than the contact area between the second conductive layer and the semiconductor layer, the opposite area between the bit line and the gate of the transistor is reduced, the parasitic capacitance between the bit line and the gate is reduced, and the reading ability of the transistor is improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0044] Figure 1 A projection view of the semiconductor structure formed on the substrate is provided in an exemplary embodiment.

[0045] Figure 2 A projection view of the semiconductor structure formed on the substrate is provided in an exemplary embodiment.

[0046] Figure 3 A projection view of the semiconductor structure formed on the substrate is provided in an exemplary embodiment.

[0047] Figure 4 A structural schematic diagram of the semiconductor structure is provided in an exemplary embodiment.

[0048] Figure 5 A sectional view of the A-A section of the semiconductor structure is provided in an exemplary embodiment.

[0049] Figure 6 A structural schematic diagram of the semiconductor structure is provided in an exemplary embodiment.

[0050] Figure 7 A flow chart of the manufacturing method of the semiconductor structure is provided in an exemplary embodiment.

[0051] Figure 8 A structural schematic diagram of the semiconductor structure after forming the laminated structure on the substrate is provided in an exemplary embodiment.

[0052] Figure 9 A projection view of the initial conductive layer formed on the substrate is provided in an exemplary embodiment.

[0053] Figure 10A projection view of the substrate formed after forming the second dielectric layer and the initial conductive layer in an exemplary embodiment.

[0054] Figure 11 A projection view of the substrate formed after forming the channel trench in an exemplary embodiment.

[0055] Figure 12 A projection view of the substrate formed after forming the transistor in an exemplary embodiment.

[0056] Figure 13 A projection view of the substrate formed after forming the first trench in an exemplary embodiment.

[0057] Figure 14 A projection view of the substrate formed after forming the initial conductive layer in an exemplary embodiment.

[0058] Figure 15 A projection view of the substrate formed after forming the second dielectric layer and the initial conductive layer in an exemplary embodiment.

[0059] Figure 16 A projection view of the substrate formed after forming the channel trench in an exemplary embodiment.

[0060] Figure 17 A projection view of the substrate formed after forming the transistor in an exemplary embodiment.

[0061] BRIEF DESCRIPTION OF DRAWINGS

[0062] 10, substrate; 100, transistor; 110, first source / drain; 120, second source / drain; 130, gate; 140, semiconductor layer; 150, gate dielectric layer; 200, capacitor; 20, memory cell; 210, lower electrode; 220, high-K dielectric layer; 230, upper electrode; 30, bit line; 310, first conductive layer; 311, first extension; 312, second extension; 320, second conductive layer; 40, word line; 50, stack structure; 51, first dielectric layer; 52, conductive material layer; 53, second dielectric layer; 54, first trench; 70, initial conductive layer; 71, first initial conductive layer; 72, second initial conductive layer; 701, first portion; 702, second portion; 703, third portion; 80, channel trench; 90, isolation trench;

[0063] D1, first direction; D2, second direction; D3, third direction; L1, first maximum length; L2, second maximum length. DETAILED DESCRIPTION

[0064] For the purposes of the present application, the following terms are intended to have the meanings set forth below. The following terms are intended to have the following meanings throughout the specification and claims:

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0066] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when a term is used herein to refer to a process, operation, etc., that includes two or more steps, the term can be used to refer to those two or more steps individually or collectively. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type. It will be understood that the terms "comprises" and / or "comprising," or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0067] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0068] As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. As used herein, the term "comprises" and / or "comprising" and / or "includes" and / or "including" when used in this specification and in the following claims is taken to specify the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0069] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, an implanted region formed by implantation can result in some implantation in a region between the implanted region and a surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic and are not intended to limit the scope of the application.

[0070] Embodiments of the present application provide a semiconductor structure and a method for fabricating the same, by reducing the contact area of the bit line and the transistor, reducing the opposite area of the gate of the bit line and the transistor, thereby reducing the parasitic capacitance between the bit line and the gate of the transistor, and improving the reading ability of the transistor.

[0071] According to an exemplary embodiment, the present embodiment provides a semiconductor structure, with reference to Figure 1 , Figure 2 , Figure 3 , Figure 4 ,Figure 5 As shown, the semiconductor structure includes a substrate 10, at least one memory cell 20, and at least one bit line 30. At least one memory cell 20 is disposed on the substrate 10. Each memory cell 20 includes a transistor 100 and a capacitor 200. The transistor 100 includes a first source / drain 110, a gate 130, and a second source / drain 120 sequentially disposed along a first direction D1, and a semiconductor layer 140 surrounding the sidewalls covering the gate 130. The first source / drain 110 and the second source / drain 120 are connected through the semiconductor layer 140 and the gate 130. The first direction D1 is parallel to the top surface of the substrate 10. The capacitor 200 is disposed on one side of the second source / drain 120, and its lower electrode 210 covers a portion of the side surface of the semiconductor layer 140. At least one bit line 30 is disposed on one side of the first source / drain 110, and the bit line 30 covers a portion of the side surface of the semiconductor layer 140. The contact area between the bit line 30 and the semiconductor layer 140 is smaller than the contact area between the capacitor 200 and the semiconductor layer 140.

[0072] Reference Figure 1 , Figure 2 , Figure 3 As shown in the diagram, in this embodiment, one side of the first source / drain 110 is the right side of the gate 130, and the other side of the second source / drain 120 is the left side of the gate 130.

[0073] This embodiment does not limit the shape of the gate 130. For example, the projection of the gate 130 on the substrate 10 can be circular, near-circular, elliptical, elongated, or rounded rectangle.

[0074] Reference Figure 5 In this embodiment, the gate 130 is disposed above the substrate 10. The gate 130 includes a top surface and a bottom surface parallel to the substrate 10, and a circumferential sidewall perpendicular to the substrate 10. The semiconductor layer 140 continuously surrounds and covers the circumferential sidewall of the gate 130.

[0075] In some embodiments, refer to Figure 1 , Figure 2 , Figure 3 As shown, transistor 100 further includes a gate dielectric layer 150, which surrounds the sidewall of gate 130 and is disposed between gate 130 and semiconductor layer 140. That is, the circumferential sidewall of gate 130 is successively covered by gate dielectric layer 150 and semiconductor layer 140.

[0076] Reference Figure 1 , Figure 2 , Figure 3The capacitor 200 is disposed on one side of the second source / drain 120 of the transistor 100, and the second source / drain 120 of the transistor 100 is connected to the lower electrode 210 of the capacitor 200. The bit line 30 is disposed on one side of the first source / drain 110 of the transistor 100, and the first source / drain 110 of the transistor 100 is connected to the bit line 30, and the bit line 30 is separated from the gate 130 by the semiconductor layer 140 and the gate dielectric layer 150.

[0077] According to the capacitance formula C = εS / d, where C is the capacitance, ε is the dielectric constant, S is the coupling area, and d is the coupling distance. It can be seen that the size of the parasitic capacitance and the coupling area (i.e., the facing area of the two conductive devices) are positively correlated. The semiconductor structure of the embodiment reduces the contact area of the bit line and the transistor, which is equivalent to reducing the facing area of the bit line and the gate of the transistor, thereby reducing the parasitic capacitance between the bit line and the gate of the transistor, reducing the adverse effects of the parasitic capacitance on the semiconductor structure, and facilitating the improvement of the response speed of the transistor and the ability of the transistor to read data.

[0078] In some embodiments, with reference to Figure 1 , Figure 2 , Figure 3 In a second direction D2 perpendicular to the first direction D1 and parallel to the substrate 10, the semiconductor layer 140 has a first maximum length L1, and the contact surface of the bit line and the semiconductor layer 140 has a second maximum length L2, which is less than one-half of the first maximum length L1. For example, the second maximum length L2 can be one-third, one-fourth, or one-fifth of the first maximum length L1, etc. It can be understood that the projection of the contact surface of the bit line 30 and the semiconductor layer 140 on the gate 130, i.e., the facing area of the bit line 30 and the gate 130. The embodiment reduces the facing area of the bit line 30 and the gate 130 by reducing the second maximum length L2 of the contact surface of the bit line 30 and the semiconductor layer 140 in the second direction D2, thereby achieving the effect of reducing the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100.

[0079] In some examples, with reference to Figure 1 , Figure 2As shown, the projection of the gate 130 of the transistor 100 formed on the substrate 10 is circular, the projection of the semiconductor layer 140 formed on the substrate 10 is circular ring type, the first maximum length L1 of the semiconductor layer 140 in the second direction D2 is the diameter of the semiconductor layer 140, the contact surface of the bit line 30 and the semiconductor layer 140 of the transistor 100 is arc surface, the second maximum length L2 of the contact surface of the bit line 30 and the semiconductor layer 140 in the second direction D2 is the chord length of the contact surface, that is, the chord length of the contact surface of the bit line 30 and the semiconductor layer 140 is less than one half of the diameter of the semiconductor layer 140. The contact surface of the bit line 30 and the semiconductor layer 140 in the example is arc surface, the contact area of the bit line 30 and the semiconductor layer 140 is maximum and the contact resistance is minimum, which reduces the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100, and at the same time, can ensure that the bit line 30 and the semiconductor layer 140 of the transistor 100 have good electrical conduction capability, and further improve the electrical performance of the semiconductor structure.

[0080] In some examples, referring to Figure 3 As shown, the projection of the gate 130 of the transistor 100 formed on the substrate 10 is long strip or rounded rectangle, the projection of the semiconductor layer 140 formed on the substrate 10 is long strip or rounded rectangle surrounding the projection of the gate 130, and the contact surface of the bit line 30 and the semiconductor layer 140 of the transistor 100 is plane. The second maximum length L2 of the contact surface of the bit line 30 and the semiconductor layer 140 of the transistor 100 in the second direction D2 is less than one half of the first maximum length L1 of the semiconductor layer 140 in the second direction D2.

[0081] In some embodiments, referring to Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, and referring to Figure 12 , the bit line 30 includes a first conductive layer 310, the first conductive layer 310 covers part of the side wall of the side of the semiconductor layer 140 away from the capacitor 200, and the first source / drain 110 of the transistor 100 is arranged in the first conductive layer 310.

[0082] In some embodiments, referring to Figure 2 , Figure 4 As shown, and referring to Figure 17 , the first conductive layer 310 includes a first extension 311 and at least one second extension 312, the first extension 311 extends along the second direction D2, each second extension 312 is arranged in the first extension 311 close to the side of the transistor 100 in the second direction D2, each second extension 312 and the transistor 100 are arranged one by one, and covers part of the side wall of the side of the semiconductor layer 140 away from the capacitor 200, and the first source / drain 110 of the transistor 100 is arranged in the second extension 312.

[0083] The bit line 30 is connected by the second extension 312 and the semiconductor layer 140 of the transistor 100. The second maximum length L2 of the contact surface between the bit line 30 and the semiconductor layer 140, i.e. the length of the second extension 312 in the second direction D2, is thus precisely controllable, reducing the parasitic capacitance between the bit line 30 and the gate 130. At the same time, the second extension 312 increases the distance between the first extension 311 and the transistor 100, which can increase the thickness of the insulating material arranged between the first extension 311 and the transistor 100 (it can be understood that the first extension 311 and the transistor 100, the transistors 100, and the capacitors 200 are all filled with insulating material to avoid short-circuiting between adjacent conductive devices, as shown in Figure 4

[0084] In some embodiments, as shown in Figure 1 、 Figure 2 、 Figure 3 The semiconductor structure further includes a second conductive layer 320 extending along the first direction D1 on one side of the second source / drain 120. The second conductive layer 320 covers part of the sidewall of the semiconductor layer 140. The second source / drain 120 of the transistor 100 is arranged in the second conductive layer 320. The capacitor 200 takes the second conductive layer 320 as the lower electrode 210. Thus, the lower electrode 210 of the capacitor 200 and the semiconductor layer 140 have a larger contact area, which can ensure that the capacitor 200 has good charge storage capability.

[0085] As shown in Figure 1 、 Figure 2 、 Figure 3 The capacitor 200 further includes a high-K dielectric layer 220 and an upper electrode 230. The high-K dielectric layer 220 covers the sidewall of the second conductive layer 320 away from the semiconductor layer 140. The upper electrode 230 covers the high-K dielectric layer 220.

[0086] In some embodiments, as shown in Figure 4 The semiconductor structure further includes a word line 40 arranged on the substrate 10 along a third direction D3 perpendicular to the top surface of the substrate 10. The word line 40 is connected to the gate 130 of the transistor 100.

[0087] According to an exemplary embodiment, the present embodiment provides a semiconductor structure, as shown in Figure 6 ​As shown, the semiconductor structure includes at least one memory cell 20. The structure of the memory cell 20 is the same as that of the memory cell 20 in the above embodiment. At least one memory cell 20 is arranged in an array along a first direction D1, and / or a second direction D2, and / or a third direction D3.

[0088] The semiconductor structure also includes at least one bit line 30 and at least one word line 40, the bit line 30 being along the second direction D2 on the substrate 10 (refer to...). Figure 5 Extending from the substrate 10, bit lines 30 are arrayed along a first direction D1 and / or a third direction D3; word lines 40 are disposed on the substrate 10 along a third direction D3, and arrayed along a first direction D1 and / or a second direction D2. Transistors 100 of multiple memory cells 20 are disposed at the intersection nodes of multiple word lines 40 and multiple bit lines 30. Each word line 40 is connected to the gate 130 of a column of transistors 100 arranged along the third direction D3, and each bit line 30 is connected to the first source / drain 110 of a column of transistors 100 arranged along the second direction D2. Bit lines 30 cover a portion of the surface of the semiconductor layer 140 of the transistors 100 to which they are connected, and the contact area between the bit lines 30 and the semiconductor layer 140 is smaller than the contact area between the capacitor 200 and the semiconductor layer 140.

[0089] The semiconductor structure in this embodiment is a planar ring-channel transistor three-dimensional stacked memory. By reducing the contact area between the bit line and the transistor, the parasitic capacitance between the bit line and the gate of the transistor is reduced, overcoming the problem of large parasitic capacitance of planar ring-channel transistors and bit lines. This reduces the adverse effects of parasitic capacitance on the semiconductor structure, which is beneficial to improving the response speed of the transistor and enhancing the transistor's ability to read data.

[0090] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 7 As shown, Figure 7 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 8-17 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 8-17 And refer to Figure 1 The method for fabricating the semiconductor structure in this embodiment will be described.

[0091] The semiconductor structure is not limited in the embodiment, and the semiconductor structure is taken as a dynamic random access memory (DRAM) as an example for description below, but the embodiment is not limited thereto, and the semiconductor structure in the embodiment can also be other types of memories, such as a static random access memory (SRAM), a flash memory (flash EPROM), a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), a phase change random access memory (PRAM), and the like.

[0092] As shown in FIG. 1, Figure 7 The embodiment provides a semiconductor structure manufacturing method, which comprises the following steps:

[0093] S110: providing a substrate, and forming a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive material layers alternately stacked on the substrate, and the stack structure defining an isolation region.

[0094] As shown in FIG. 1, Figure 8 The substrate 10 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 10 (see Figure 5 ) can be a single-layer structure or a multi-layer structure. For example, the substrate 10 (see Figure 5 ) can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 (see Figure 5 ) can be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium on insulator.

[0095] In the embodiment, the stack structure 50 is formed on the substrate 10, and the following implementation can be adopted:

[0096] As shown in FIG. 1, Figure 8As shown, the first dielectric layer 51 can be formed on the top surface of the substrate 10 by any one of a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a sputtering process.

[0097] Then, the conductive material layer 52 is formed by any one of the above deposition processes, and covers the top surface of the first dielectric layer 51. The steps of forming the first dielectric layer 51 and the conductive material layer 52 are repeated to form the stack structure 50 on the substrate 10, which includes the first dielectric layer 51 and the conductive material layer 52 alternately stacked. In this embodiment, the top layer structure and the bottom layer structure of the stack structure 50 are both the first dielectric layer 51.

[0098] The first dielectric layer 51 and the conductive material layer 52 of the stack structure 50 can be alternately stacked in 2 to 1024 layers or more. For example, the first dielectric layer 51 and the conductive material layer 52 can be alternately stacked in 48 layers, 64 layers, 128 layers, 256 layers, 512 layers, or the like.

[0099] The material of the first dielectric layer 51 can include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the first dielectric layer 51 is silicon oxide.

[0100] The material of the conductive material layer 52 can be selected from metal materials such as cobalt (Co), titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride (TiN), tantalum titanium (TaTi), tungsten nitride (WN), or the like. In this embodiment, the material of the conductive material layer 52 includes titanium nitride.

[0101] The stack structure 50 is removed in the isolation region (not labeled in the figure, refer to the isolation region in FIG. 2B) to form the isolation trench 90 in the subsequent steps (which will be described in detail in the subsequent steps). Figure 8 、 Figure 9 , Figure 9 The stack structure 50 is removed in the isolation region (not labeled in the figure, refer to the isolation region in FIG. 2B) to form the isolation trench 90 in the subsequent steps (which will be described in detail in the subsequent steps).

[0102] Step S120: removing the stack structure in the isolation region to form the isolation trench in the isolation region, and the remaining conductive material layer of each layer forms the initial conductive layer.

[0103] A mask layer is formed on the top surface of the stack structure 50, and the mask layer exposes the top surface of the stack structure 50 in the isolation region. The stack structure 50 is etched layer by layer according to the mask layer until the top surface of the substrate 10 is exposed to stop etching, the stack structure 50 in the isolation region is removed, and the isolation trench 90 is formed in the isolation region. In this embodiment, the stack structure 50 can be etched by a dry etching process or a wet etching process.

[0104] Referring to Figure 9 As shown in the figure, after the isolation trench 90 is formed, the part of each conductive material layer 52 that is etched and remains forms an initial conductive layer 70.

[0105] In this embodiment, the initial conductive layer 70 includes a first initial conductive layer 71 and a second initial conductive layer 72. Referring to Figure 9 As shown in the figure, the second initial conductive layer 72 extends along the first direction D1, the first initial conductive layer 71 is arranged on one side of the second initial conductive layer 72, the first initial conductive layer 71 extends along the second direction D2, and the first initial conductive layer 71 and the second initial conductive layer 72 are arranged apart along the first direction D1.

[0106] Step S130: filling the second dielectric layer in the isolation trench.

[0107] Referring to Figure 10 As shown in the figure, the second dielectric layer 53 can be deposited by any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process to fill the isolation trench 90, and the top surface of the second dielectric layer 53 is flush with the stack structure 50 to facilitate subsequent processing of the stack structure 50. The material of the second dielectric layer 53 can include at least one of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the second dielectric layer 53 includes silicon oxide.

[0108] Step S140: etching and removing part of the second dielectric layer and part of the stack structure to form a channel trench that penetrates the stack structure, the channel trench divides the initial conductive layer into an independently arranged first conductive layer and a second conductive layer, the first conductive layer and the second conductive layer are arranged opposite to each other along the first direction on two sides of the channel trench, the area of the first conductive layer exposed by the channel trench is smaller than the area of the second conductive layer exposed by the channel trench, and the first conductive layer is a bit line.

[0109] Referring to Figure 10 , Figure 11 The part of the first initial conductive layer 71, the part of the second initial conductive layer 72, and the part of the first dielectric layer 51 are etched and removed (see Figure 8) and a second dielectric layer 52 between the first initial conductive layer 71 and the second initial conductive layer 72, forming a channel trench 80, etching the reserved first initial conductive layer 71 to form a first conductive layer 310, and etching the reserved second initial conductive layer 72 to form a second conductive layer 320.

[0110] The projection of the channel trench 80 formed on the substrate 10 can be circular, quasi-circular, elliptical, long strip-shaped, or circular rectangular, etc., and the two ends of the channel trench 80 extend into the first initial conductive layer 71 and the second initial conductive layer 72 along the first direction D1, respectively. The area of the projection of the channel trench 80 formed on the substrate 10 and the projection of the first initial conductive layer 71 formed on the substrate 10 is less than the area of the projection of the channel trench 80 formed on the substrate 10 and the projection of the second initial conductive layer 72 formed on the substrate 10. In the first direction D1, the distance between the center line of the channel trench 80 and the first conductive layer 310 is less than the distance between the center line of the channel trench 80 and the second conductive layer 320, that is, the center line of the channel trench 80 is biased to one side of the first conductive layer 310, and the area of the first conductive layer 310 exposed by the channel trench 80 is less than the area of the second conductive layer 320 exposed by the channel trench 80.

[0111] Referring to Figure 11 , the first conductive layer 310 formed in this step extends above the substrate 10, and the first conductive layer 310 serves as a bit line 30 of the semiconductor structure. The area of the first conductive layer 310 exposed by the channel trench 80 is less than the area of the second conductive layer 320 exposed by the channel trench 80, that is, the contact area between the semiconductor layer 140 (to be described in detail in subsequent steps) and the bit line 30 formed in the channel trench 80 later is less than the contact area between the semiconductor layer 140 and the second conductive layer 320.

[0112] Step S150: Forming a semiconductor layer, the semiconductor layer covers the channel trench wall, and the contact area between the first conductive layer and the semiconductor layer is less than the contact area between the second conductive layer and the semiconductor layer.

[0113] Referring to Figure 12 , any one of chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process (ALD) or sputtering deposition process can be selected to deposit the semiconductor layer 140, and the semiconductor layer 140 covers the channel trench 80 (referring to Figure 11 ) wall.

[0114] The material of the semiconductor layer 140 is a metal oxide semiconductor material, and the metal oxide material can be indium gallium zinc oxide (IGZO). When the metal oxide material is indium gallium zinc oxide, the leakage current of the channel of the transistor 100 formed thereby can be reduced, the control of the channel of the transistor 100 can be improved, and the refresh frequency of the transistor 100 in the semiconductor structure can be ensured. For example, the material of the semiconductor layer 140 can include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), tungsten-doped indium oxide (IWO), zinc oxide (ZnOx), indium oxide (InOx, In2O3), tin oxide (SnO2), titanium oxide (TiOx), indium zinc tin oxide (InSnOx), zinc oxynitride (ZnxOyNz), magnesium zinc oxide (MgxZnyOz), indium zinc oxide (InxZnyOz), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa), hafnium indium zinc oxide (HfxInyZnzOa), tin indium zinc oxide (SnxInyZnzOa), aluminum tin indium zinc oxide (AlxSnyInzZnaOd), silicon indium zinc oxide (SixInyZnzOa), zinc tin oxide (ZnxSnyOz), aluminum zinc tin oxide (AlxZnySnzOa), gallium zinc tin oxide (GaxZnySnzOa), zirconium zinc tin oxide (ZrxZnySnzOa), indium gallium silicon oxide (InGaSiO).

[0115] Step S160: forming a gate electrode, the gate electrode covering the semiconductor layer and filling the channel groove.

[0116] In one embodiment, before forming the gate electrode, the following step is further performed:

[0117] Step S161: forming a gate dielectric layer, the gate dielectric layer covering the semiconductor layer, and the gate electrode and the semiconductor layer being separated by the gate dielectric layer.

[0118] Referring to Figure 12 The gate dielectric layer 150 can be deposited by any one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process, and the material of the gate dielectric layer 150 can include at least one of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum oxynitride (AlON), hafnium oxide (HfO2).

[0119] The gate electrode 130 can be formed by the following implementation: the gate electrode 130 is deposited by any one of the above deposition processes, and the gate electrode 130 covers the gate dielectric layer 150 and fills the channel groove 80 (refer to Figure 11)unfilled area. The material of the gate 130 can include metal tungsten or a compound of tungsten, metal titanium or a compound of titanium. In this embodiment, the material of the gate 130 includes metal tungsten. The portion of the first conductive layer 310 connected with the semiconductor layer 140 serves as the first source / drain 110, and the portion of the second conductive layer 320 connected with the semiconductor layer 140 serves as the second source / drain 120. The gate 150, the semiconductor layer 140, the first source / drain 110 and the second source / drain 120 together form the transistor 100.

[0120] The manufacturing method of the semiconductor structure in this embodiment, when forming the channel groove, deviates the center line of the channel groove towards the second conductive layer, so that the area of the first conductive layer exposed by the channel groove is smaller than the area of the second conductive layer exposed by the channel groove. After forming the transistor, the contact area between the first conductive layer (i.e. the bit line) and the semiconductor layer of the transistor is smaller than the contact area between the second conductive layer and the semiconductor layer of the transistor. The opposite area between the bit line and the gate of the transistor is reduced, and the parasitic capacitance between the bit line and the gate of the transistor is reduced, thereby improving the reading ability of the transistor.

[0121] In some embodiments, with reference to Figure 12 , along a second direction D2 perpendicular to the first direction D1, the semiconductor layer 140 has a first maximum length L1, and the contact surface between the first conductive layer 310 and the semiconductor layer 140 has a second maximum length L2, which is less than one half of the first maximum length L1. For example, the second maximum length L2 can be one third, one fourth or one fifth of the first maximum length L1, etc.

[0122] It can be understood that the opposite area between the bit line 30 and the gate 130 is the projection of the contact surface between the first conductive layer 310 and the semiconductor layer 140 on the gate 130. In this embodiment, by reducing the second maximum length L2 of the contact surface between the first conductive layer 310 and the semiconductor layer 140 in the second direction D2, the opposite area between the bit line 30 and the gate 130 is reduced, and the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100 is further reduced.

[0123] According to an exemplary embodiment, the manufacturing method in this embodiment includes all the steps of the above-mentioned embodiments. After step S150, the following steps are further performed:

[0124] Step S170: forming a capacitor on one side of the second conductive layer with the second conductive layer as the lower electrode.

[0125] In this embodiment, the capacitor is formed on one side of the second conductive layer, and the following implementation is adopted:

[0126] Step S171: removing part of the first dielectric layer and part of the second dielectric layer to expose the surface of the second conductive layer.

[0127] A capacitor region (not numbered) is defined according to the layout of the first conductive layer 310 and the second conductive layer 320. A mask layer defining a capacitor pattern is formed on the top surface of the structure (not shown). The mask layer defining the capacitor pattern exposes the top surface of the second dielectric layer 53 in the capacitor region. The second dielectric layer 53 is etched according to the mask layer defining the capacitor pattern. A first trench 54 is formed in the capacitor region. The first trench 54 exposes the top surface of the substrate 10. The first trench 54 also exposes part of the sidewall of the second conductive layer 320 and part of the sidewall of the first dielectric layer 51 between adjacent second conductive layers 320.

[0128] The exposed first dielectric layer 51 is etched according to the first trench 54. The second conductive layer 320 between adjacent first dielectric layers 51 is etched away. A gap is formed between adjacent second conductive layers 320. Part of the top surface and part of the bottom surface of the second conductive layer 320 are exposed.

[0129] Step S162: Form a high-K dielectric layer. The high-K dielectric layer covers the sidewall of the second conductive layer.

[0130] Referring to FIGS. 1A-1C, Figure 1 , Figure 4 , Figure 5 , Figure 13 The high-K dielectric layer 220 can be formed by any of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process. The high-K dielectric layer 220 covers the exposed sidewall, the bottom surface, and the top surface of the second conductive layer 320. The material of the high-K dielectric layer 220 can include at least one of strontium titanate (SrTiO3), aluminum oxide (Al2O3), zirconium oxide (ZrO), or hafnium oxide (HfO2).

[0131] Step S163: Form an upper electrode. The upper electrode covers the high-K dielectric layer. The second conductive layer, the high-K dielectric layer, and the upper electrode form a capacitor 200.

[0132] Referring to FIGS. 1A-1C, Figure 1 , Figure 4 , Figure 5 , Figure 13 The upper electrode 230 can be formed by any of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process. The upper electrode 230 covers the surface of the high-K dielectric layer 220. The material of the upper electrode 230 can include at least one of a high-melting-point metal, such as cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W), and / or molybdenum (Mo). Alternatively, the material of the upper electrode 230 can also include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and / or tungsten nitride.

[0133] The second conductive layer 320 serves as the lower electrode 210 of the capacitor 200, and together with the high-K dielectric layer 220 and the upper electrode 230, forms the capacitor 200, the contact area between the lower electrode 210 of the capacitor 200 and the semiconductor layer 140 of the transistor 100 is greater than the contact area between the bit line 30 and the semiconductor layer 140, thereby reducing the parasitic capacitance between the bit line 30 and the gate 130 of the transistor 100, while ensuring that the capacitor 200 has good charge storage capability.

[0134] In some embodiments, referring to Figure 8 , Figure 14 It is shown that the formed initial conductive layer 70 of the etching stack structure 50 includes a first part 701 extending along the first direction D1, a second part 702 disposed on one side of the first part 701, and a third part 703 connecting the first part 701 and the second part 702, the second part 702 extends along the second direction D2, the third part 703 is disposed between the first part 701 and the second part 702, and along the second direction D2, the size of the third part 703 is smaller than the size of the first part 701.

[0135] In this embodiment, a channel groove is formed through the stack structure, and the following implementation is adopted;

[0136] Referring to Figure 15 , first, a second dielectric layer 53 is formed to fill the removed part of the stack structure 50.

[0137] Referring to Figure 16 , Figure 17 Then, the first part 701, the third part 703, the first dielectric layer 51, and the second dielectric layer are etched to form a channel groove 80, the etched first part 701 forms a first conductive layer 310, and the second part 702 and the etched third part 703 together form a second conductive layer 320.

[0138] In some embodiments, referring to Figure 3 , Figure 16 It is shown that the projection of the channel groove 80 formed on the substrate 10 is a long strip, and the projection of the gate 130 of the transistor 100 formed on the substrate 10 is a long strip.

[0139] The manufacturing method of the semiconductor structure of the present embodiment, the length of the contact surface between the bit line and the semiconductor layer of the transistor in the second direction, i.e. the length of the third part in the second direction, in the present embodiment, by limiting the size of the third part, the area of the contact surface between the bit line and the semiconductor layer of the transistor can be accurately controlled, the parasitic capacitance between the bit line and the gate of the transistor is reduced, the process is simple and controllable, and the formed semiconductor structure is more in line with the expectation.

[0140] Any combination of the technical features of the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, it is to be understood that the scope of protection includes all possible combinations of the technical features.

[0141] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; at least one memory cell disposed on the substrate, each memory cell comprising a transistor and a capacitor, the transistor comprising a first source / drain, a gate, a second source / drain disposed in sequence along a first direction, and a semiconductor layer surrounding a sidewall covering the gate, the first source / drain and the second source / drain being connected through the semiconductor layer and the gate, the first direction being parallel to a top surface of the substrate, the capacitor being disposed on a side of the second source / drain, a lower electrode of the capacitor covering a part of a sidewall of the semiconductor layer; at least one bit line disposed on a side of the first source / drain, the bit line covering a part of the sidewall of the semiconductor layer, a contact area of the bit line and the semiconductor layer being smaller than a contact area of the capacitor and the semiconductor layer.

2. The semiconductor structure of claim 1, wherein, In a second direction perpendicular to the first direction and parallel to the substrate, the semiconductor layer has a first maximum length, and a contact surface of the bit line and the semiconductor layer has a second maximum length, the second maximum length being less than one half of the first maximum length.

3. The semiconductor structure of claim 2, wherein, The bit line comprises a first conductive layer covering a part of a sidewall of the semiconductor layer away from the capacitor, and the first source / drain is disposed in the first conductive layer.

4. The semiconductor structure of claim 3, wherein, The first conductive layer comprises a first extension extending along the second direction, and at least one second extension disposed in the first extension away from the transistor along the second direction, each second extension corresponding to one transistor and covering a part of a sidewall of the semiconductor layer away from the capacitor, and the first source / drain is disposed in the second extension.

5. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a second conductive layer extending along the first direction on a side of the second source / drain, the second conductive layer covering a part of a sidewall of the semiconductor layer, and the second source / drain is disposed in the second conductive layer; the capacitor has the second conductive layer as the lower electrode.

6. The semiconductor structure of claim 1, wherein, The transistor further comprises: a gate dielectric layer surrounding a sidewall of the gate, the gate dielectric layer being disposed between the gate and the semiconductor layer.

7. The semiconductor structure of claim 1, wherein, The at least one memory cell is arranged in an array on the substrate along the first direction, and / or, a second direction, and / or, a third direction, the first direction, the second direction, and the third direction being perpendicular to each other; and the semiconductor structure further comprises: at least one word line disposed on the substrate along the third direction perpendicularly, each word line being connected to the gate of one transistor arranged along the third direction.

8. A method of fabricating a semiconductor structure, the method comprising: The semiconductor structure is manufactured by the following steps: providing a substrate, forming a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive material layers alternately stacked on the substrate, the stack structure defining an isolation region; removing the stack structure of the isolation region to form an isolation trench in the isolation region, and the conductive material layers of each layer remaining to form an initial conductive layer; filling a second dielectric layer in the isolation trench; etching to remove part of the second dielectric layer and part of the stack structure, to form a channel trench penetrating the stack structure, the channel trench dividing the initial conductive layer into a first conductive layer and a second conductive layer arranged independently, the first conductive layer and the second conductive layer being arranged oppositely along a first direction on two sides of the channel trench, an area of the first conductive layer exposed by the channel trench being smaller than an area of the second conductive layer exposed by the channel trench, wherein the first conductive layer is a bit line; forming a semiconductor layer covering a wall of the channel trench, a contact area of the first conductive layer and the semiconductor layer being smaller than a contact area of the second conductive layer and the semiconductor layer; forming a gate covering the semiconductor layer and filling the channel trench.

9. The method of fabricating a semiconductor structure of claim 8, wherein, In a second direction perpendicular to the first direction, the semiconductor layer has a first maximum length, and a contact surface of the first conductive layer and the semiconductor layer has a second maximum length, the second maximum length being smaller than one half of the first maximum length.

10. The method of fabricating a semiconductor structure of claim 9, wherein, The initial conductive layer includes a first initial conductive layer and a second initial conductive layer, the second initial conductive layer extending along the first direction, and the first initial conductive layer being arranged on one side of the second initial conductive layer, the first initial conductive layer extending along the second direction, and the first initial conductive layer and the second initial conductive layer being arranged apart along the first direction; forming the channel trench penetrating the stack structure includes: etching to remove part of the first initial conductive layer, part of the second initial conductive layer, part of the first dielectric layer, and the second dielectric layer between the first initial conductive layer and the second initial conductive layer, to form the channel trench, and etching the remaining first initial conductive layer to form the first conductive layer, and etching the remaining second initial conductive layer to form the second conductive layer; An area in which a projection of the channel trench formed on the substrate and a projection of the first initial conductive layer formed on the substrate coincide is smaller than an area in which a projection of the channel trench formed on the substrate and a projection of the second initial conductive layer formed on the substrate coincide.

11. The method of fabricating a semiconductor structure of claim 9, wherein, The initial conductive layer includes a first portion extending along the first direction, a second portion arranged on one side of the first portion, and a third portion connecting the first portion and the second portion, the second portion extending along the second direction, and the third portion being arranged between the first portion and the second portion, and along the second direction, a size of the third portion being smaller than a size of the first portion; forming the channel trench penetrating the stack structure includes: etching to remove part of the first portion, part of the third portion, part of the first dielectric layer, and part of the second dielectric layer, to form the channel trench, etching the remaining first portion to form the first conductive layer, and etching the second portion and the remaining third portion to form the second conductive layer.

12. The method of fabricating a semiconductor structure of claim 8, wherein, Before forming the gate, the method further includes: A gate dielectric layer is formed, covering the semiconductor layer, and the gate electrode and the semiconductor layer are separated by the gate dielectric layer.

13. The method of fabricating a semiconductor structure of claim 8, wherein, The method for manufacturing the semiconductor structure further comprises: A capacitor is formed on one side of the second conductive layer with the second conductive layer as a lower electrode.

14. The method of fabricating a semiconductor structure of claim 13, wherein, The capacitor is formed on one side of the second conductive layer, comprising: Part of the dielectric layer is removed to expose the sidewall of the second conductive layer; A high-K dielectric layer is formed, covering the sidewall of the second conductive layer; An upper electrode is formed, covering the high-K dielectric layer, and the second conductive layer and the high-K dielectric layer, the upper electrode form the capacitor.

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