Semiconductor bonding structure and manufacturing method thereof

Abstract

The invention provides a semiconductor bonding structure and a manufacturing method thereof. The semiconductor bonding structure comprises a first semiconductor chip, at least one second semiconductor chip, a stress adjusting structure and a conductive layer. The at least one second semiconductor chip is disposed on the first semiconductor chip and electrically connected to the first semiconductor chip. The stress adjusting structure is disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip. The conductive layer is disposed on the at least one second semiconductor chip, and the conductive layer is electrically connected to the at least one second semiconductor chip. The invention also provides a manufacturing method of the semiconductor bonding structure. The semiconductor bonding structure can be applied to manufacturing of a high-performance and high-capacity 3D NAND flash memory.

Description

Technical Field

[0001] This disclosure relates to a semiconductor bonding structure and a method for manufacturing the same, and more particularly to a semiconductor bonding structure having a stress adjustment structure and a method for manufacturing the same. Background Technology

[0002] As memory capacity increases, the number of component layers required for memory fabrication continues to rise. Taking current 3D NAND flash memory as an example, as the silicon oxide-silicon nitride-silicon oxide (ONO) stack used for data storage increases, significant warpage begins to occur in the semiconductor wafers used to manufacture 3D NAND flash memory. This warpage is detrimental to the stacking, alignment, and bonding of semiconductor wafers, thus reducing the bonding yield. Therefore, reducing semiconductor wafer warpage to increase bonding yield is a crucial issue that those in the field urgently need to address. Furthermore, heat dissipation is also a concern when 3D NAND flash memory operates at high frequencies. Therefore, improving the heat dissipation performance and component performance of 3D NAND flash memory is another important issue that those in the field urgently need to address. Summary of the Invention

[0003] This disclosure provides a semiconductor bonding structure with stress adjustment structure and a method for manufacturing the same.

[0004] One embodiment of this disclosure provides a semiconductor bonding structure including a first semiconductor chip, at least one second semiconductor chip, a stress-adjusting structure, and a conductive layer. The at least one second semiconductor chip is disposed on and electrically connected to the first semiconductor chip. The stress-adjusting structure is disposed within at least one of the first semiconductor chip and the at least one second semiconductor chip. The conductive layer is disposed on and electrically connected to the at least one second semiconductor chip.

[0005] Another embodiment of this disclosure provides a method for manufacturing a semiconductor bonding structure, comprising the following steps: Providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first semiconductor substrate and a first interconnect structure disposed on the first semiconductor substrate. Patterning the first interconnect structure of the first semiconductor wafer to form a first stress-adjusting opening along a first dicing track of the first semiconductor wafer. Providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second semiconductor substrate and a second interconnect structure disposed on the second semiconductor substrate. Patterning the second interconnect structure of the second semiconductor wafer to form a second stress-adjusting opening along a second dicing track of the second semiconductor wafer. Bonding the first interconnect structure and the second interconnect structure. After bonding the first interconnect structure and the second interconnect structure, forming a conductive layer on the second semiconductor substrate. Dividing the first semiconductor wafer, the second semiconductor wafer, and the conductive layer along the first dicing track and the second dicing track to form a plurality of monomeric semiconductor bonding structures, wherein each of the plurality of monomeric semiconductor bonding structures has a stress-adjustable groove on its sidewall.

[0006] Another embodiment of this disclosure provides a method for manufacturing a semiconductor chip bonding structure, comprising the following steps: Providing a first semiconductor wafer, the first semiconductor wafer including a first semiconductor substrate and a first interconnect structure disposed on the first semiconductor substrate. Providing a second semiconductor wafer, the second semiconductor wafer including a second semiconductor substrate, a plurality of stress-adjusting structures embedded within the second semiconductor substrate, and a second interconnect structure disposed on the second semiconductor substrate and the plurality of stress-adjusting structures. Bonding the first semiconductor wafer and the second semiconductor wafer. After bonding the first semiconductor wafer and the second semiconductor wafer, forming a conductive layer on the second semiconductor substrate and the plurality of stress-adjusting structures. Dividing the first semiconductor wafer, the second semiconductor wafer, and the conductive layer to form a plurality of monomeric semiconductor bonding structures. Attached Figure Description

[0007] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings.

[0008] Figure 1 , Figure 2 , Figure 3A , Figure 4A , Figure 5A as well as Figure 6A This schematically illustrates a manufacturing process diagram of a semiconductor bonding structure according to a first embodiment of the present disclosure;

[0009] Figure 1 , Figure 2 , Figure 3B , Figure 4B , Figure 5B as well as Figure 6BA schematic diagram illustrating the manufacturing process of the semiconductor bonding structure according to a second embodiment of the present disclosure is shown.

[0010] Figure 7 A schematic cross-sectional view of a semiconductor bonding structure according to a third embodiment of the present disclosure is shown.

[0011] Figure 8 A schematic cross-sectional view of a semiconductor bonding structure according to a fourth embodiment of the present disclosure is shown.

[0012] Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A as well as Figure 15A A schematic diagram illustrating the manufacturing process of the semiconductor bonding structure according to the fifth embodiment of this disclosure is shown.

[0013] Figure 9 , Figure 10 , Figure 11B , Figure 12B , Figure 13B , Figure 14B as well as Figure 15B A schematic diagram illustrating the manufacturing process of the semiconductor bonding structure according to the sixth embodiment of this disclosure is shown.

[0014] Figure 16 A schematic cross-sectional view of a semiconductor bonding structure according to a seventh embodiment of the present disclosure is shown.

[0015] Figure 17 A schematic cross-sectional view of a semiconductor bonding structure according to an eighth embodiment of the present disclosure is shown.

[0016] Figure 18 , Figure 19 , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A as well as Figure 25A A schematic diagram illustrating the manufacturing process of the semiconductor bonding structure according to the ninth embodiment of this disclosure is shown.

[0017] Figure 18 , Figure 19 , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B as well as Figure 25B A schematic diagram illustrating the manufacturing process of the semiconductor bonding structure according to the tenth embodiment of this disclosure is shown.

[0018] Figures 26 to 28 A schematic diagram illustrating the manufacturing process of the semiconductor bonding structure according to the eleventh embodiment of this disclosure is shown.

[0019] Figures 29 to 33 A schematic diagram illustrating the manufacturing process of a semiconductor bonding structure according to the twelfth embodiment of this disclosure is shown.

[0020] Explanation of reference numerals in the attached figures:

[0021] 100: First Semiconductor Wafer

[0022] 110: First semiconductor substrate

[0023] 112: Semiconductor components

[0024] 120: First interconnect structure

[0025] 122, 222, 222a, 222b, 222c: Dielectric layers

[0026] 124a: Interconnecting wire

[0027] 124b, 224, 224a, 224b, 224c: Conductive vias

[0028] 126, 126': First stress adjustment opening

[0029] 135, 135', 235, 235', 235a, 235b: Functional material layers

[0030] 140, 140': First stress adjustment structure

[0031] 200: Second semiconductor wafer

[0032] 210, 210a, 210b, 210c: Second semiconductor substrate

[0033] 212: Groove

[0034] 214: Stress Adjustment Zone

[0035] 220, 220a, 220b, 220c: Second interconnection structure

[0036] 225, 225a, 225b, 225c: Memory element layer

[0037] 226, 226', 226a, 226b: Second stress adjustment openings

[0038] 226R: Adjustable stress groove

[0039] 240, 240', 240a, 240b: Second stress adjustment structure

[0040] 250: Conductive layer

[0041] 260: Conductive Through-hole

[0042] 310: First Semiconductor Chip

[0043] 320, 320a, 320b, 320c: Second semiconductor chip

[0044] 330, 330', 330'': Stress adjustment structure

[0045] 330a: First stress adjustment zone

[0046] 330b: Second stress adjustment zone

[0047] 330c: Third stress adjustment zone

[0048] 330d: Fourth stress adjustment region

[0049] S1, S2, S3: Cutting track

[0050] SS1~SS10: Semiconductor bonding structure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0052] The following description provides detailed embodiments in conjunction with the accompanying drawings, but these embodiments are not intended to limit the scope of this disclosure. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, the same elements will be labeled with the same symbols in the following description. Additionally, the terms "comprising," "including," "having," etc., used herein are open-ended terms, meaning "including but not limited to." Moreover, directional terms such as "upper" and "lower" are used only for reference to the direction of the drawings and are not intended to limit this disclosure. Furthermore, the quantities and shapes mentioned in the specification are used only to specifically illustrate this disclosure to facilitate understanding of its content and are not intended to limit this disclosure.

[0053] First Embodiment

[0054] Figure 1 , Figure 2 , Figure 3A , Figure 4A , Figure 5A as well as Figure 6A This is a schematic diagram of the manufacturing process of the semiconductor bonding structure SS1 according to the first embodiment of this disclosure.

[0055] Please refer to Figure 1 The lower half of the structure provides a first semiconductor wafer 100. In this embodiment, the first semiconductor wafer 100 includes a first semiconductor substrate 110 and a first interconnect structure 120, wherein the first interconnect structure 120 is disposed on the first semiconductor substrate 110 and is electrically connected to semiconductor elements 112 in the first semiconductor substrate 110. In some embodiments, the first semiconductor substrate 110 in the first semiconductor wafer 100 includes a group IV semiconductor substrate (e.g., a silicon substrate), a group III-V semiconductor substrate, or a substrate of other materials. The semiconductor elements 112 in the first semiconductor substrate 110 include active elements such as transistors (e.g., complementary metal-oxide-semiconductor field-effect transistors) formed in the first semiconductor substrate 110 and / or passive elements such as resistors, capacitors, and inductors. The first interconnect structure 120 includes multiple dielectric layers 122 stacked on the first semiconductor substrate 110, multiple interconnect wires 124a embedded in the dielectric layers 122, and a plurality of conductive vias 124b connecting different layers of interconnect wires 124a. The semiconductor element 112 in the first semiconductor substrate 110 is fabricated by front-end of line (FEOL) process, while the dielectric layer 122, interconnect wire 124a and conductive via 124b in the first interconnect structure 120 are fabricated by back-end of line (BEOL) process.

[0056] like Figure 1 As shown in the lower half, interconnecting wires 124a and conductive vias 124b are embedded in the dielectric layer 122. Interconnecting wires 124a in different layers are electrically connected to each other through conductive vias 124b, and the interconnecting wires 124a are electrically connected to the active element 112 in the first semiconductor substrate 110 through the conductive vias 124b. For example, the dielectric layer 122 in the first interconnect structure 120 may be made of SiO2, SiON, SiN, SiC, SiCN, polymer materials, or other insulating materials. The interconnecting wires 124a may be made of polysilicon, copper, gold, silver, cobalt, or other metals, and the conductive vias 124b may be made of polysilicon, copper, gold, silver, cobalt, or other metals. Furthermore, the aforementioned interconnecting wires 124a may be a single metal layer or multiple metal layers.

[0057] Please refer to Figure 1As shown in the upper half, a second semiconductor wafer 200 is provided. In this embodiment, the second semiconductor wafer 200 includes a second semiconductor substrate 210 and a second interconnect structure 220, wherein the second semiconductor substrate 210 may or may not have semiconductor elements, and the second interconnect structure 220 is disposed on the second semiconductor substrate 210. In some embodiments, the second semiconductor substrate 210 in the second semiconductor wafer 200 includes a group IV semiconductor substrate (e.g., a silicon substrate), a group III-V semiconductor substrate, or a substrate of other materials. The second interconnect structure 220 includes multiple dielectric layers 222 stacked on the second semiconductor substrate 210, a plurality of memory element layers 225, and multiple conductive vias 224 embedded in the dielectric layers 222, wherein the memory element layers 225 are stacked on the second semiconductor substrate 210, and the plurality of memory element layers 225 are embedded in the dielectric layers 222. In this embodiment, the dielectric layers 222 and the conductive vias 224 in the second interconnect structure 220 are fabricated by back-end processing (BEOL). For example, the dielectric layer 222 in the second interconnect structure 220 may be made of SiO2, SiON, SiN, SiC, SiCN, polymer materials, or other insulating materials, while the conductive vias 224 may be made of polysilicon, copper, gold, silver, cobalt, or other metals. In some embodiments, each memory element layer 225 is electrically connected to the bottom end of at least one of the conductive vias 224, while the top end of the conductive vias 224 is exposed on the upper surface of the second interconnect structure 220.

[0058] In some embodiments, the memory element layer 225 includes a multilayer 3D NAND memory element layer, and the memory element layer 225 may include at least 300 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stacks formed from silicon oxide-silicon tungsten-silicon oxide (OWO) stacks. In other feasible embodiments, the memory element layer 225 includes a multilayer 3D NAND memory element layer, and the memory element layer 225 may include at least 1000 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stacks formed from silicon oxide-silicon tungsten-silicon oxide (OWO) stacks.

[0059] Please refer to Figure 2 and Figure 3ATo alleviate stress on the first semiconductor wafer 100 and / or the second semiconductor wafer 200, thereby reducing the warpage of the first semiconductor wafer 100 and / or the second semiconductor wafer 200, a patterning process (e.g., etching process) can be performed on at least one of the first semiconductor wafer 100 and the second semiconductor wafer 200, and a stress-adjusting structure can be formed in at least one of the first semiconductor wafer 100 and the second semiconductor wafer 200. In this embodiment, the first semiconductor wafer 100 can be patterned first, and then a first stress-adjusting structure 140 can be formed in the first semiconductor wafer 100; and the second semiconductor wafer 200 can be patterned, and then a second stress-adjusting structure 240 can be formed in the second semiconductor wafer 200. It is worth noting that this disclosure does not limit the formation order of the first stress-adjusting structure 140 and the second stress-adjusting structure 240.

[0060] like Figure 2 As shown, a patterning process is performed on the first interconnect structure 120 of the first semiconductor wafer 100 to form first stress-adjusting openings 126 distributed in the first interconnect structure 120 along the first dicing path S1 of the first semiconductor wafer 100. Furthermore, a patterning process is performed on the second interconnect structure 220 of the second semiconductor wafer 200 to form second stress-adjusting openings 226 distributed in the second interconnect structure 220 along the second dicing path S2 of the second semiconductor wafer 200. The aforementioned first stress-adjusting opening 126 and second stress-adjusting opening 226 can have various cross-sectional shapes, such as semi-circular, rectangular, trapezoidal, hexagonal, stepped, etc., and the widths of the first stress-adjusting opening 126 and second stress-adjusting opening 226 are between several micrometers and hundreds of micrometers. In this embodiment, the height of the first stress-adjusting opening 126 is substantially equal to the thickness of the first interconnect structure 120, and the height of the second stress-adjusting opening 226 is substantially equal to the thickness of the second interconnect structure 220. Furthermore, a portion of the first semiconductor substrate 110 is exposed by the first stress-adjusting opening 126, and a portion of the second semiconductor substrate 210 is exposed by the second stress-adjusting opening 226. After the formation of the first stress-adjusting opening 126 and the second stress-adjusting opening 226, the stress of the first semiconductor wafer 100 and the second semiconductor wafer 200 is released by the first stress-adjusting opening 126 and the second stress-adjusting opening 226, thus the warpage of the first semiconductor wafer 100 and the second semiconductor wafer 200 can be improved to a certain extent.

[0061] like Figure 2 and Figure 3AAs shown, stress-adjusting materials are filled into the first stress-adjusting opening 126 and the second stress-adjusting opening 226 to form a first stress-adjusting structure 140 and a second stress-adjusting structure 240, respectively. In this embodiment, the first stress-adjusting structure 140 can be formed by forming stress-adjusting materials on the first interconnect structure 120 and in the first stress-adjusting opening 126, and then removing the stress-adjusting materials outside the first stress-adjusting opening 126 by a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or a combination of the aforementioned processes). Similarly, the second stress-adjusting structure 240 can be formed by forming stress-adjusting materials on the second interconnect structure 220 and in the second stress-adjusting opening 226, and then removing the stress-adjusting materials outside the second stress-adjusting opening 226 by a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or a combination of the aforementioned processes). In this embodiment, the height of the first stress-adjusting structure 140 is substantially equal to the thickness of the first interconnect structure 120, and the height of the second stress-adjusting structure 240 is substantially equal to the thickness of the second interconnect structure 220. In some other embodiments, the height of the first stress-adjusting structure 140 is greater than or less than the thickness of the first interconnect structure 120, and the height of the second stress-adjusting structure 240 is greater than or less than the thickness of the second interconnect structure 220. For example, when the coefficient of thermal expansion of the first stress-adjusting structure 140 is higher than the coefficient of thermal expansion of the dielectric layer 122 in the first interconnect structure 120, the height of the first stress-adjusting structure 140 may be slightly smaller than (e.g., a few nanometers) the thickness of the first interconnect structure 120. The material of the first stress-adjusting structure 140 may be or may include a metal, a specific polymer, or graphene. When the coefficient of thermal expansion of the first stress-adjusting structure 140 is higher than that of silicon dioxide (between 0.7 and 1.4 W / m·K), the first stress-adjusting structure 140 can provide good heat dissipation performance. When the material of the first stress-adjusting structure 140 may be or may include a polymer material with water-absorbing properties, the first stress-adjusting structure 140 can retain moisture in the film to avoid degradation of the subsequently formed bonding interface. Conversely, when the coefficient of thermal expansion of the first stress-adjusting structure 140 is lower than that of the dielectric layer 122 in the first interconnect structure 120, the height of the first stress-adjusting structure 140 may be equal to or slightly greater than (e.g., several nanometers) the thickness of the first interconnect structure 120. Similarly, when the coefficient of thermal expansion of the second stress-adjusting structure 240 is higher than that of the dielectric layer 222 in the second interconnect structure 220, the height of the second stress-adjusting structure 240 may be slightly less than (e.g., several nanometers) the thickness of the second interconnect structure 220. The material of the second stress-adjusting structure 240 may be or may include a metal, a specific polymer, or graphene.When the coefficient of thermal expansion of the second stress-adjusting structure 240 is higher than that of silicon dioxide (between 0.7-1.4 W / m·K), the second stress-adjusting structure 240 can provide good heat dissipation performance. When the material of the second stress-adjusting structure 240 can be or may include a polymer material with water-absorbing properties, the second stress-adjusting structure 240 can retain moisture in the film to avoid degradation of the subsequently formed bonding interface. Conversely, when the coefficient of thermal expansion of the second stress-adjusting structure 240 is lower than that of the dielectric layer 222 in the second interconnect structure 220, the height of the second stress-adjusting structure 240 can be equal to or slightly greater than (e.g., several nanometers) the thickness of the second interconnect structure 220.

[0062] In some embodiments, the materials of the first stress-adjusting structure 140 and the second stress-adjusting structure 240 include polymeric materials, such as polyimide (PI), epoxy resin, benzocyclobutene (BCB), SU-8, or other suitable stress-absorbing materials. The material of the first stress-adjusting structure 140 may be the same as or different from the material of the second stress-adjusting structure 240. In other embodiments, the materials of the first stress-adjusting structure 140 and the second stress-adjusting structure 240 include inorganic materials, such as carbon, silicon, SiCN, silicon carbide (SiC), silicon oxide (SiOx), borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), inorganic two-dimensional materials (2D materials), etc. In other feasible embodiments, the materials of the first stress-adjusting structure 140 and the second stress-adjusting structure 240 include metallic materials, such as tungsten (W), copper (Cu), aluminum (Al), silver (Ag), gold (Au), metallic two-dimensional materials, etc.

[0063] As mentioned above, in addition to the stress adjustment function, the first stress adjustment structure 140 and the second stress adjustment structure 240 may also have good heat dissipation characteristics, water absorption characteristics, or other functions.

[0064] Please refer to Figure 4AThe second semiconductor wafer 200 is flipped and aligned with the first semiconductor wafer 100. After alignment, the second stress adjustment structure 240 in the second interconnect structure 220 is aligned with the first stress adjustment structure 140 in the first interconnect structure 120, and the conductive via 224 in the second interconnect structure 220 is aligned with the interconnect wire 124a in the first interconnect structure 120. After alignment, a bonding process, such as a hybrid bonding process or a micro-bump bonding process, is performed to bond the patterned first interconnect structure 120 to the patterned second interconnect structure 220. In some embodiments, while the first interconnect structure 120 and the second interconnect structure 220 are bonded to each other, the second stress-adjusting structure 240 is well bonded to the first stress-adjusting structure 140. The first stress-adjusting structure 140 and the second stress-adjusting structure 240 can act as sealing structures to prevent moisture from entering the bonding interface and to strengthen the bonding strength, thereby improving the overall bonding strength. The aforementioned hybrid bonding process may include a pre-bonding process and a subsequent annealing process. The pre-bonding process is performed at room temperature without providing bonding force, while the annealing process is performed at 350 degrees Celsius for approximately 30 to 60 minutes. The aforementioned microbump bonding process can be performed at 260 degrees Celsius for approximately 5 minutes, and the aforementioned microbump bonding process can be performed at a bonding pressure of 0.4 MPa. Since the first stress-adjusting structure 140 and the second stress-adjusting structure 240 can reduce the warpage of the second semiconductor wafer 200 and the first semiconductor wafer 100, the bonding yield between the second semiconductor wafer 200 and the first semiconductor wafer 100 can be improved.

[0065] Please refer to Figure 4A and Figure 5AAfter the bonding process between the second semiconductor wafer 200 and the first semiconductor wafer 100, a conductive layer 250 electrically connected to the second semiconductor wafer 200 is formed on the second semiconductor substrate 210 (e.g., a reconfigured conductive layer). In some embodiments, before fabricating the conductive layer 250, the second semiconductor substrate 210 can be thinned by a general mechanical polishing process followed by a chemical mechanical polishing process, and a plurality of conductive through vias 260 electrically connected to the memory element layer 225 can be formed in the second semiconductor substrate 210, before the conductive layer 250 is fabricated. In some embodiments, the conductive through vias 260 can be through silicon vias (TSVs). Figure 5A As shown, the conductive layer 250 and the second interconnect structure 220 are located on two opposite sides of the second semiconductor substrate 210, and the conductive layer 250 is electrically connected to the memory element layer 225 through the conductive via 260.

[0066] Please refer to Figure 5A and Figure 6A The first semiconductor wafer 100, the second semiconductor wafer 200, the first stress-adjusting structure 140, the second stress-adjusting structure 240, and the conductive layer 250 are cut along the first dicing channel S1 and the second dicing channel S2 to form multiple monomeric semiconductor bonding structures SS1. For example... Figure 6A As shown, each of the plurality of monolithic semiconductor bonding structures SS1 has a stress-adjusting structure 330 on its sidewall. The first stress-adjusting structure 140 and the second stress-adjusting structure 240 may have a width of approximately 80 micrometers, the width of the second dicing channel S2 may be between approximately 20 micrometers and approximately 40 micrometers, and the width of the stress-adjusting structure 330 may be between approximately 20 micrometers and approximately 30 micrometers. The aforementioned monolithic semiconductor bonding structure SS1 includes a first semiconductor chip 310, a second semiconductor chip 320, a stress-adjusting structure 330, and a conductive layer 250. The second semiconductor chip 320 is disposed on and electrically connected to the first semiconductor chip 310. The stress-adjusting structure 330 is embedded in the sidewalls of the first semiconductor chip 310 and the second semiconductor chip 320. Furthermore, the conductive layer 250 is disposed on and electrically connected to the second semiconductor chip 320.

[0067] It is worth noting that, such as Figure 5A and Figure 6A As shown, the stress adjustment structure 330 in each monomeric semiconductor junction structure SS1 is composed of a portion of the first stress adjustment structure 140 and a portion of the second stress adjustment structure 240. Figure 5A and Figure 6AAs shown, the stress adjustment structure 330 includes a first stress adjustment region 330a and a second stress adjustment region 330b. The first stress adjustment region 330a is the remaining portion after the first stress adjustment structure 140 has been cut, and the second stress adjustment region 330b is the remaining portion after the second stress adjustment structure 240 has been cut. Furthermore, the first stress adjustment region 330a is disposed on the sidewall of the first interconnecting structure 120, and the second stress adjustment region 330b is disposed on the sidewall of the second interconnecting structure 220. In embodiments where the first stress adjustment structure 140 and the second stress adjustment structure 240 are made of the same material, there is no obvious interface between the first stress adjustment region 330a and the second stress adjustment region 330b. In embodiments where the first stress adjustment structure 140 and the second stress adjustment structure 240 are made of different materials, there is a heterogeneous interface between the first stress adjustment region 330a and the second stress adjustment region 330b.

[0068] In some embodiments, the first stress-adjusting region 330a in the stress-adjusting structure 330 includes an annular wall structure distributed on the sidewall of the first interconnect structure 120 of the first semiconductor chip 310 and surrounding the first semiconductor chip 310. In some other embodiments, the first stress-adjusting region 330a in the stress-adjusting structure 330 includes a plurality of columnar structures distributed on the sidewall of the first interconnect structure 120 of the first semiconductor chip 310, arranged around the first semiconductor chip 310, and spaced apart from each other. For example, the aforementioned columnar structures may have various cross-sectional shapes, such as semicircular, rectangular, trapezoidal, hexagonal, stepped, etc., and the width of the aforementioned columnar structures is between several micrometers and hundreds of micrometers. Furthermore, the spacing between the aforementioned columnar structures is between several micrometers and hundreds of micrometers.

[0069] In some embodiments, the second stress-adjusting region 330b in the stress-adjusting structure 330 includes an annular wall structure, wherein the annular wall structure is distributed on the sidewall of the second interconnect structure 220 of the second semiconductor chip 320 and surrounds the second semiconductor chip 320. In some other embodiments, the second stress-adjusting region 330b in the stress-adjusting structure 330 includes a plurality of columnar structures, wherein the plurality of columnar structures are distributed on the sidewall of the second interconnect structure 220 of the second semiconductor chip 320, the plurality of columnar structures are arranged around the second semiconductor chip 320, and the plurality of columnar structures are spaced apart from each other.

[0070] like Figure 6AAs shown, in the monolithic semiconductor junction structure SS1, the height of the first stress-adjusting region 330a is substantially equal to the thickness of the first interconnect structure 120 of the first semiconductor chip 310, and the height of the second stress-adjusting region 330b is substantially equal to the thickness of the second interconnect structure 220 of the second semiconductor chip 320. In other words, the height of the stress-adjusting structure 330 is substantially equal to the sum of the thicknesses of the first interconnect structure 120 and the second interconnect structure 220. Furthermore, the height of the first stress-adjusting region 330a is less than the thickness of the first semiconductor chip 310, and the height of the second stress-adjusting region 330b is less than the thickness of the second semiconductor chip 320.

[0071] Second Embodiment

[0072] Figure 1 , Figure 2 , Figure 3B , Figure 4B , Figure 5B as well as Figure 6B This is a schematic diagram of the manufacturing process of the semiconductor bonding structure SS2 according to the second embodiment of this disclosure.

[0073] Figure 3B , Figure 4B , Figure 5B as well as Figure 6B The manufacturing process illustrated in the figure and Figure 3A , Figure 4A , Figure 5A as well as Figure 6A The manufacturing processes depicted are similar, but the main differences are: Figure 3B , Figure 4B , Figure 5B as well as Figure 6B The manufacturing process further includes the formation of functional material layers 135 and 235. In other words, the semiconductor bonding structure SS2 in this embodiment further includes functional material layers 135 and 235 (such as...). Figure 6B As shown in the figure, the first stress-adjusting region 330a and the second stress-adjusting region 330b are separated from the first interconnect structure 120 of the first semiconductor chip 310 and the second interconnect structure 220 of the second semiconductor chip 320 by functional material layers 135 and 235, respectively. In some embodiments, the first stress-adjusting region 330a and the second stress-adjusting region 330b have stress-adjusting functions, and the materials of the functional material layers 135 and 235 may be heat-dissipating materials with good heat dissipation properties, water-absorbing materials with good water absorption properties, or other functional materials.

[0074] Third Embodiment

[0075] Figure 7 This is a schematic cross-sectional view of the semiconductor bonding structure SS3 according to the third embodiment of this disclosure.

[0076] Please refer to Figure 7 In this embodiment, the semiconductor bonding structure SS3 includes a first semiconductor chip 310, a plurality of second semiconductor chips 320, a plurality of stress-adjusting structures 330, and a conductive layer 250. The plurality of second semiconductor chips 320 are stacked on the first semiconductor chip 310, the plurality of stress-adjusting structures 330 are respectively embedded in the sidewalls of the plurality of second semiconductor chips 320, and the conductive layer 250 is disposed on the second semiconductor chips 320 and electrically connected to the second semiconductor chips 320. In this embodiment, the second semiconductor chip 320 includes a second semiconductor chip 320a and a second semiconductor chip 320b. The second semiconductor chip 320a is disposed on and electrically connected to the first semiconductor chip 310, and the second semiconductor chip 320b is disposed on and electrically connected to the second semiconductor chip 320a. The second semiconductor chip 320b is located between the second semiconductor chip 320a and the first semiconductor chip 310. In addition, the second semiconductor chip 320b can be electrically connected to the first semiconductor chip 310 through the second semiconductor chip 320a.

[0077] The first semiconductor chip 310 in this embodiment is the same as the first semiconductor chip 310 in the first embodiment, so it will not be described again here.

[0078] In this embodiment, the second semiconductor chip 320a includes a second semiconductor substrate 210a, a second interconnect structure 220a, and a plurality of memory element layers 225a. The second interconnect structure 220a is disposed on the second semiconductor substrate 210a and electrically connected to the second semiconductor substrate 210a. The plurality of memory element layers 225a are embedded in the dielectric layer 222a of the second interconnect structure 220a, and the memory element layers 225a are electrically connected to the first semiconductor chip 310 through conductive vias 224a of the second interconnect structure 220a. Furthermore, the second semiconductor chip 320b includes a second semiconductor substrate 210b, a second interconnect structure 220b, and a plurality of memory element layers 225b. The second interconnect structure 220b is disposed on and electrically connected to the second semiconductor substrate 210b. The plurality of memory element layers 225b are embedded in the dielectric layer 222b of the second interconnect structure 220b, and the memory element layers 225b are electrically connected to the conductive vias 224a through the conductive vias 224b of the second interconnect structure 220b.

[0079] In this embodiment, the stress adjustment structure 330 includes a first stress adjustment region 330a, a second stress adjustment region 330b, and a third stress adjustment region 330c. The first stress adjustment region 330a is embedded in the sidewall of the first semiconductor chip 310, the second stress adjustment region 330b is embedded in the sidewall of the second semiconductor chip 320a, and the third stress adjustment region 330c is embedded in the sidewall of the second semiconductor chip 320b. Figure 7 As shown, the first stress adjustment region 330a and the second stress adjustment region 330b are in contact with and joined to each other, and the second stress adjustment region 330b and the third stress adjustment region 330c are separated from each other by the semiconductor substrate 210a of the second semiconductor chip 320a.

[0080] Here, the size, distribution pattern, and material selection of the first stress adjustment region 330a, the second stress adjustment region 330b, and the third stress adjustment region 330c are the same as those of the first stress adjustment region 330a and the second stress adjustment region 330b in the first embodiment, and therefore will not be repeated here.

[0081] In this embodiment, the conductive layer 250 is disposed on the second semiconductor chip 320b, and the conductive layer 250 is electrically connected to the second semiconductor chip 320b. For example... Figure 7 As shown, the conductive layer 250 can be electrically connected to the memory element layer 225b through the conductive via 260 in the second semiconductor chip 320b.

[0082] Fourth embodiment

[0083] Figure 8 This is a cross-sectional schematic diagram of the semiconductor bonding structure according to the fourth embodiment of the present disclosure.

[0084] Please refer to Figure 7 and Figure 8 The semiconductor bonding structure SS4 of this embodiment is similar to the semiconductor bonding structure SS3 of the third embodiment, except that the main difference is that the semiconductor bonding structure SS4 of this embodiment further includes a second semiconductor chip 320d and a fourth stress-adjusting region 330d. The second semiconductor chip 320d is disposed between the second semiconductor chip 320c and the conductive layer 250, while the fourth stress-adjusting region 330d is disposed on the sidewall of the second semiconductor chip 320c, and the conductive layer 250 is electrically connected to the second semiconductor chip 320c through the second semiconductor chip 320d. In addition, the fourth stress-adjusting region 330d and the third stress-adjusting region 330c are separated from each other by the semiconductor substrate 210b of the second semiconductor chip 320b.

[0085] The second semiconductor chip 320c includes a second semiconductor substrate 210c, a second interconnect structure 220c, and a plurality of memory element layers 225c. The second interconnect structure 220c is disposed on the second semiconductor substrate 210c and electrically connected to the second semiconductor substrate 210c. The plurality of memory element layers 225c are embedded in the dielectric layer 222c of the second interconnect structure 220c, and the memory element layers 225c are electrically connected to the second semiconductor chip 320b through conductive vias 224c of the second interconnect structure 220c.

[0086] Fifth Embodiment

[0087] Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A as well as Figure 15A This is a schematic diagram of the manufacturing process of the semiconductor bonding structure SS5 according to the fifth embodiment of this disclosure.

[0088] Please refer to Figure 9 , Figure 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A as well as Figure 15A The manufacturing process of the semiconductor bonding structure SS5 in this embodiment is similar to that in the first embodiment, except that the main difference lies in the fact that the first stress adjustment opening 126' in this embodiment (shown in the figure) Figure 10 The middle part extends into the first semiconductor substrate 110, and the second stress adjustment opening 226' (shown in the figure) extends into the first semiconductor substrate 110. Figure 10 (in the middle) will extend into the second semiconductor substrate 210.

[0089] like Figure 10 As shown, the height of the first stress-adjusting opening 126' is substantially greater than the thickness of the first interconnect structure 120, and the height of the second stress-adjusting opening 226' is substantially greater than the thickness of the second interconnect structure 220. In other words, the patterning process (e.g., etching process) used to pattern the first interconnect structure 120 removes a portion of the first semiconductor substrate 110, and the patterning process (e.g., etching process) used to pattern the second interconnect structure 220 removes a portion of the second semiconductor substrate 210. For example, the etching depths of the aforementioned first semiconductor substrate 110 and second semiconductor substrate 210 are between several hundred nanometers and several hundred micrometers.

[0090] like Figure 11AAs shown, the first stress-adjusting structure 140' formed in the first stress-adjusting opening 126' and the second stress-adjusting structure 240' formed in the second stress-adjusting opening 226' have a relatively large height. In other words, the bottom end of the first stress-adjusting structure 140' is embedded in the first semiconductor substrate 110, and the bottom end of the second stress-adjusting structure 240' is embedded in the second semiconductor substrate 210.

[0091] like Figure 12A , Figure 13A and Figure 14A As shown, during the bonding process between the second semiconductor wafer 200 and the first semiconductor wafer 100 (e.g. Figure 12A (as shown) after and during the fabrication of conductive layer 250 (as shown) Figure 14A Before thinning (as shown), the second semiconductor substrate 210 can be thinned using a general mechanical polishing process followed by chemical mechanical polishing. After thinning the second semiconductor substrate 210, one end of the second stress-adjusting structure 240' (i.e., the aforementioned bottom end) is exposed. Since the stress-adjusting structure 240' is made of a different material than the second semiconductor substrate 210, the stress-adjusting structure 240' can act as a termination layer for the second semiconductor substrate 210 in the thinning process. For example, by detecting eddy current, the stress-adjusting structure 240' can act as a chemical mechanical polishing termination layer for the second semiconductor substrate 210 in the thinning process.

[0092] like Figure 15A As shown, the stress adjustment structure 330 includes a first stress adjustment region 330a and a second stress adjustment region 330b. The first stress adjustment region 330a is the remaining portion after the first stress adjustment structure 140' is cut, and the second stress adjustment region 330b is the remaining portion after the second stress adjustment structure 240' is cut. Furthermore, the first stress adjustment region 330a is disposed on the sidewall of the first interconnect structure 120, and the second stress adjustment region 330b is disposed on the sidewall of the second interconnect structure 220. The height of the first stress adjustment structure 330a is less than the thickness of the first semiconductor chip 310, but greater than the thickness of the first interconnect structure 120 of the first semiconductor chip 310, and the height of the second stress adjustment structure 330b is substantially equal to the thickness of the second semiconductor chip 320.

[0093] Sixth Embodiment

[0094] Figure 9 , Figure 10 , Figure 11B , Figure 12B , Figure 13B , Figure 14B as well as Figure 15BThis is a schematic diagram of the manufacturing process of the semiconductor bonding structure SS6 according to the sixth embodiment of this disclosure.

[0095] Figure 11B , Figure 12B , Figure 13B , Figure 14B as well as Figure 15B The manufacturing process illustrated in the figure and Figure 11A , Figure 12A , Figure 13A , Figure 14A as well as Figure 15A The manufacturing processes depicted are similar, but the main differences are: Figure 11B , Figure 12B , Figure 13B , Figure 14B as well as Figure 15B The manufacturing process of the semiconductor bonding structure SS6 further includes the formation of functional material layers 135' and 235'. In other words, the semiconductor bonding structure SS6 in this embodiment further includes functional material layers 135' and 235' (such as...). Figure 15B As shown in the figure, the first stress-adjusting structure 140' and the second stress-adjusting structure 240' are separated from the first interconnect structure 120 of the first semiconductor chip 310 and the second interconnect structure 220 of the second semiconductor chip 320 by functional material layers 135' and 235'. In some embodiments, the first stress-adjusting region 330a and the second stress-adjusting region 330b have stress-adjusting functions, and the materials of the functional material layers 135' and 235' can be heat-dissipating materials with good heat dissipation properties, water-absorbing materials with good water absorption properties, or other functional materials.

[0096] Seventh Embodiment

[0097] Figure 16 This is a schematic cross-sectional view of the semiconductor bonding structure SS7 according to the seventh embodiment of this disclosure.

[0098] Please refer to Figure 16 The semiconductor bonding structure SS7 of this embodiment is similar to the semiconductor bonding structure SS3 of the third embodiment, except that the main difference between the two is that the stress adjustment structure 330' in the semiconductor bonding structure SS7 of this embodiment.

[0099] In this embodiment, the stress adjustment structure 330' includes a first stress adjustment region 330a, a second stress adjustment region 330b, and a third stress adjustment region 330c. The first stress adjustment region 330a is embedded in the sidewall of the first semiconductor chip 310, the second stress adjustment region 330b is embedded in the sidewall of the second semiconductor chip 320a, and the third stress adjustment region 330c is embedded in the sidewall of the second semiconductor chip 320b. Figure 16 As shown, the first stress adjustment region 330a is in contact with and engaged with the second stress adjustment region 330b, and the second stress adjustment region 330b is in contact with and engaged with the third stress adjustment region 330c.

[0100] Here, the first stress adjustment region 330a, the second stress adjustment region 330b, and the third stress adjustment region 330c, as well as the material selection, are the same as those of the first stress adjustment region 330a and the second stress adjustment region 330b in the first embodiment, and therefore will not be repeated here.

[0101] Eighth embodiment

[0102] Figure 17 This is a schematic cross-sectional view of the semiconductor bonding structure SS8 according to the eighth embodiment of this disclosure.

[0103] Please refer to Figure 16 and Figure 17 The semiconductor bonding structure SS8 of this embodiment is similar to the semiconductor bonding structure SS7 of the third embodiment, except that the main difference between the two is that the stress adjustment structure 330'' in the semiconductor bonding structure SS8 of this embodiment.

[0104] In this embodiment, the semiconductor bonding structure SS8 further includes a second semiconductor chip 320c, and the stress adjustment structure 330” in the semiconductor bonding structure SS8 further includes a fourth stress adjustment region 330d. The second semiconductor chip 320c is disposed between the second semiconductor chip 320b and the conductive layer 250, and the fourth stress adjustment region 330d is disposed on the sidewall of the second semiconductor chip 320c. The conductive layer 250 is electrically connected to the first semiconductor chip 310 through the second semiconductor chip 320c. In addition, the first stress adjustment region 330a and the second stress adjustment region 330b are in contact with and bonded to each other, and the third stress adjustment region 330c is separated from the fourth stress adjustment region 330d above it and the second stress adjustment region 330b below it.

[0105] Ninth Embodiment

[0106] Please refer to Figure 18 , Figure 19 , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A as well as Figure 25A The manufacturing process of this embodiment is used to manufacture the semiconductor bonding structure SS3 in the third embodiment.

[0107] Please refer to Figure 18A first semiconductor wafer 100 is provided. The details of the first semiconductor wafer 100 have been described in the first embodiment and will not be repeated here.

[0108] like Figure 18 As shown, a second semiconductor wafer 200a and a second semiconductor wafer 200b are provided. In this embodiment, the second semiconductor wafer 200a includes a second semiconductor substrate 210a, a second interconnect structure 220a, and a plurality of memory element layers 225a. The second semiconductor substrate 210a may or may not have semiconductor elements. The second interconnect structure 220a is disposed on the second semiconductor substrate 210a, and the plurality of memory element layers 225a are stacked on the second semiconductor substrate 210a and embedded in the second interconnect structure 220a. In some embodiments, the second semiconductor substrate 210a in the second semiconductor wafer 200a includes a group IV semiconductor substrate (e.g., a silicon substrate), a group III-V semiconductor substrate, or a substrate of other materials. The second interconnect structure 220a includes multiple dielectric layers 222a stacked on the second semiconductor substrate 210a and multiple conductive vias 224a embedded in the dielectric layers 222a. In this embodiment, the dielectric layer 222a and the conductive via 224a in the second interconnect structure 220a are fabricated using a back-end process (BEOL). For example, the dielectric layer 222a in the second interconnect structure 220a may be made of SiO2, SiON, SiN, SiC, SiCN, polymer materials, or other insulating materials, while the conductive via 224a may be made of polysilicon, copper, gold, silver, cobalt, or other metals. In some embodiments, each memory element layer 225a is electrically connected to the bottom end of at least one of the conductive vias 224a, while the top end of the conductive via 224a is exposed on the upper surface of the second interconnect structure 220a. Figure 18 As shown, some of the conductive vias 224a are not electrically connected to the memory element layer 225a, but instead directly penetrate the second interconnect structure 220a and extend downward into the second semiconductor substrate 210a.

[0109] In some embodiments, memory element layer 225a includes multiple 3D NAND memory element layers, and memory element layer 225a may include at least 300 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stack. In other feasible embodiments, memory element layer 225a includes multiple 3D NAND memory element layers, and memory element layer 225a may include at least 1000 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stack.

[0110] In this embodiment, the second semiconductor wafer 200b includes a second semiconductor substrate 210b, a second interconnect structure 220b, and a plurality of memory element layers 225b. The second semiconductor substrate 210b may or may not contain semiconductor elements. The second interconnect structure 220b is disposed on the second semiconductor substrate 210b, and the plurality of memory element layers 225b are stacked on the second semiconductor substrate 210b and embedded within the second interconnect structure 220b. In some embodiments, the second semiconductor substrate 210b in the second semiconductor wafer 200b includes a group IV semiconductor substrate (e.g., silicon substrate), a group III-V semiconductor substrate, or a substrate of other materials. The second interconnect structure 220b includes multiple dielectric layers 222b stacked on the second semiconductor substrate 210b and multiple conductive vias 224b embedded in the dielectric layers 222b. In this embodiment, the dielectric layers 222b and conductive vias 224b in the second interconnect structure 220b are fabricated using a back-end process (BEOL). For example, the dielectric layer 222b in the second interconnect structure 220b is made of SiO2, SiON, SiN, SiC, SiCN, polymer materials, or other insulating materials, while the conductive via 224b is made of polysilicon, copper, gold, silver, cobalt, or other metals. In some embodiments, each memory element layer 225b is electrically connected to the bottom end of at least one of the conductive vias 224b, while the top end of the conductive via 224b is exposed on the upper surface of the second interconnect structure 220b.

[0111] In some embodiments, memory element layer 225b includes multiple 3D NAND memory element layers, and memory element layer 225b may include at least 300 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stack. In other feasible embodiments, memory element layer 225b includes multiple 3D NAND memory element layers, and memory element layer 225b may include at least 1000 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stack.

[0112] Please refer to Figure 19 and Figure 20ATo alleviate the stress on the first semiconductor wafer 100, the second semiconductor wafer 200a, and / or the second semiconductor wafer 200b, thereby reducing the warpage of the first semiconductor wafer 100, the second semiconductor wafer 200a, and / or the second semiconductor wafer 200b, at least one of the first semiconductor wafer 100, the second semiconductor wafer 200a, and the second semiconductor wafer 200b may be patterned (e.g., etched), and a stress-adjusting structure may be formed in at least one of the first semiconductor wafer 100, the second semiconductor wafer 200a, and the second semiconductor wafer 200b. In this embodiment, the first semiconductor wafer 100, the second semiconductor wafer 200a, and the second semiconductor wafer 200b may be patterned to form a first stress-adjusting structure 140, a second stress-adjusting structure 240a, and a second stress-adjusting structure 240b, respectively. It is worth noting that this disclosure does not limit the formation order of the first stress adjustment structure 140, the second stress adjustment structure 240a, and the second stress adjustment structure 240b.

[0113] like Figure 19As shown, a patterning process is performed on the first interconnect structure 120 of the first semiconductor wafer 100 to form a first stress-adjusting opening 126 distributed in the first interconnect structure 120 along the first dicing path S1 of the first semiconductor wafer 100. A patterning process is performed on the second interconnect structure 220a of the second semiconductor wafer 200a to form a second stress-adjusting opening 226a distributed in the second interconnect structure 220a along the second dicing path S2 of the second semiconductor wafer 200a. A patterning process is performed on the second interconnect structure 220b of the second semiconductor wafer 200b to form a second stress-adjusting opening 226b distributed in the second interconnect structure 220b along the second dicing path S3 of the second semiconductor wafer 200b. In this embodiment, the height of the first stress-adjusting opening 126 is substantially equal to the thickness of the first interconnect structure 120, the height of the second stress-adjusting opening 226a is substantially equal to the thickness of the second interconnect structure 220a, and the height of the second stress-adjusting opening 226b is substantially equal to the thickness of the second interconnect structure 220b. Furthermore, a portion of the first semiconductor substrate 110 is exposed by the first stress-adjusting opening 126, a portion of the second semiconductor substrate 210a is exposed by the second stress-adjusting opening 226a, and a portion of the second semiconductor substrate 210b is exposed by the second stress-adjusting opening 226b. After the formation of the first stress-adjusting opening 126, the second stress-adjusting opening 226a, and the second stress-adjusting opening 226b, the stress of the first semiconductor wafer 100, the second semiconductor wafer 200a, and the second semiconductor wafer 200b is released by the first stress-adjusting opening 126, the second stress-adjusting opening 226a, and the second stress-adjusting opening 226b, thus the warpage of the first semiconductor wafer 100, the second semiconductor wafer 200a, and the second semiconductor wafer 200b can be improved to a certain extent.

[0114] like Figure 19 and Figure 20AAs shown, stress-adjusting materials are filled into the first stress-adjusting opening 126 and the second stress-adjusting opening 226 to form a first stress-adjusting structure 140, a second stress-adjusting structure 240a, and a second stress-adjusting structure 240b, respectively, in the first stress-adjusting opening 126, the second stress-adjusting opening 226a, and the second stress-adjusting opening 226b. In this embodiment, the first stress-adjusting structure 140 can be formed by forming stress-adjusting materials on the first interconnecting structure 120 and in the first stress-adjusting opening 126, and then removing the stress-adjusting materials outside the first stress-adjusting opening 126 by a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or a combination of the aforementioned processes). Furthermore, the second stress-adjusting structures 240a and 240b can be formed by forming stress-adjusting materials on the second interconnecting structures 220a and 220b and in the second stress-adjusting openings 226a and 226b, and then removing the stress-adjusting materials outside the second stress-adjusting openings 226a and 226b by a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or a combination of the aforementioned processes). In this embodiment, the height of the first stress adjustment structure 140 is substantially equal to the thickness of the first interconnect structure 120, the height of the second stress adjustment structure 240a is substantially equal to the thickness of the second interconnect structure 220a, and the height of the second stress adjustment structure 240b is substantially equal to the thickness of the second interconnect structure 220b.

[0115] In some embodiments, the materials of the first stress-adjusting structure 140 and the second stress-adjusting structures 240a and 240b include polymeric materials, such as polyimide (PI), epoxy resin, benzocyclobutene (BCB), SU-8, or other suitable stress-absorbing materials. The material of the first stress-adjusting structure 140 may be the same as or different from the material of the second stress-adjusting structures 240a and 240b. In other embodiments, the materials of the first stress-adjusting structure 140 and the second stress-adjusting structures 240a and 240b include inorganic materials, such as carbon, silicon, SiCN, silicon carbide (SiC), silicon oxide (SiOx), borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), inorganic two-dimensional materials (2D materials), etc. In other feasible embodiments, the materials of the first stress-adjusting structure 140 and the second stress-adjusting structures 240a and 240b include metallic materials, such as tungsten (W), copper (Cu), aluminum (Al), silver (Ag), gold (Au), metallic two-dimensional materials, etc.

[0116] As mentioned above, in addition to the stress adjustment function, the first stress adjustment structure 140 and the second stress adjustment structures 240a and 240b may also have good heat dissipation characteristics, water absorption characteristics, or other functions.

[0117] Please refer to Figure 21A The second semiconductor wafer 200a is flipped and aligned with the first semiconductor wafer 100. After alignment, the second stress adjustment structure 240a in the second interconnect structure 220a is aligned with the first stress adjustment structure 140 in the first interconnect structure 120, and the conductive via 224a in the second interconnect structure 220a is aligned with the interconnect wire 124a in the first interconnect structure 120. After alignment, a bonding process, such as a hybrid bonding process or a micro-bump bonding process, is performed to bond the patterned first interconnect structure 120 and the patterned second interconnect structure 220a together. While the first interconnect structure 120 and the second interconnect structure 220a are bonded to each other, the second stress-adjusting structure 240a is bonded to the first stress-adjusting structure 140. Since the first stress-adjusting structure 140 and the second stress-adjusting structure 240a can reduce the warpage between the second semiconductor wafer 200a and the first semiconductor wafer 100, the bonding yield between the second semiconductor wafer 200a and the first semiconductor wafer 100 can be improved.

[0118] Please refer to Figure 21A and Figure 22A After the bonding process between the second semiconductor wafer 200a and the first semiconductor wafer 100, the second semiconductor substrate 210a can be thinned by a general mechanical polishing process followed by chemical mechanical polishing to expose a portion of the conductive via 224a. In some embodiments, since the material of the conductive via 224a is different from the material of the dielectric layer 222b in the second interconnect structure 220b (e.g., silicon), the conductive via 224a can serve as a stopping layer for the aforementioned chemical mechanical polishing process.

[0119] Please refer to Figure 22A and Figure 23AThe second semiconductor wafer 200b is flipped and aligned with the second semiconductor wafer 200a. After alignment, the second stress adjustment structure 240b in the second interconnect structure 220b is aligned with the second stress adjustment structure 240a in the second interconnect structure 220a, and the conductive via 224b in the second interconnect structure 220b is aligned with the conductive via 224a in the second interconnect structure 220a. After alignment, a bonding process, such as a hybrid bonding process or a micro-bump bonding process, is performed to bond the patterned second interconnect structure 220a to the patterned second interconnect structure 220b. While the second interconnect structure 220a and the second interconnect structure 220b are bonded to each other, the second stress adjustment structure 240a is bonded to the second stress adjustment structure 240b. Since the first stress adjustment structure 140a, the second stress adjustment structure 240a, and the second stress adjustment structure 240b can reduce the warpage of the first semiconductor wafer 100, the second semiconductor wafer 200a, and the second semiconductor wafer 200b, the bonding yield between the second semiconductor wafer 200a and the first semiconductor wafer 200b can be improved.

[0120] Please refer to Figure 23A and Figure 24A After the bonding process between the second semiconductor wafer 200a and the second semiconductor wafer 200b, a conductive layer 250 electrically connected to the second semiconductor wafer 200b is formed on the second semiconductor substrate 210b. In some embodiments, before fabricating the conductive layer 250, the second semiconductor substrate 210b can be thinned by a general mechanical polishing process followed by chemical mechanical polishing, and a plurality of conductive through vias 260 electrically connected to the memory element layer 225b can be formed in the second semiconductor substrate 210b. Then, the conductive layer 250 is fabricated. In some embodiments, the conductive through vias 260 can be through silicon vias (TSVs). Figure 24A As shown, the conductive layer 250 and the second interconnect structure 220b are located on opposite sides of the second semiconductor substrate 210b, and the conductive layer 250b is electrically connected to the memory element layer 225b through the conductive via 260.

[0121] Please refer to Figure 24A and Figure 25AThe first semiconductor wafer 100, the second semiconductor wafer 200a, the second semiconductor wafer 200b, the first stress adjustment structure 140, the second stress adjustment structure 240a, the second stress adjustment structure 240b, and the conductive layer 250 are cut along the first dicing channel S1, the second dicing channel S2, and the third dicing channel S3 to form a plurality of monomeric semiconductor bonding structures SS3.

[0122] Tenth Embodiment

[0123] Figure 18 , Figure 19 , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B as well as Figure 25B This is a schematic diagram of the manufacturing process of the semiconductor bonding structure according to the tenth embodiment of this disclosure.

[0124] Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B as well as Figure 25B The manufacturing process illustrated in the figure and Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A as well as Figure 25A The manufacturing processes depicted are similar, but the main differences are: Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B as well as Figure 25B The manufacturing process further includes the formation of functional material layers 135, 235a, and 235b. In addition to the differences mentioned above, the semiconductor bonding structure SS9 in this embodiment further includes functional material layers 135, 235a, and 235b (such as...). Figure 6B As shown in the figure, the first stress adjustment region 330a, the second stress adjustment region 330b, and the third stress adjustment region 330c are separated from the first semiconductor chip 310 and the second semiconductor chip 320 by functional material layers 135, 235a, and 235b. In some embodiments, the first stress adjustment region 330a, the second stress adjustment region 330b, and the third stress adjustment region 330c have stress adjustment functions, and the materials of the functional material layers 135, 235a, and 235b can be heat dissipation materials with good heat dissipation properties, water absorption materials with good water absorption properties, or other functional materials.

[0125] Eleventh Embodiment

[0126] Figures 26 to 28 This is a schematic diagram of the manufacturing process of the semiconductor bonding structure according to the eleventh embodiment of this disclosure.

[0127] Please refer to Figure 26 A first semiconductor wafer 100 and a second semiconductor wafer 200 are provided. The details of the first semiconductor wafer 100 and the second semiconductor wafer 200 have been described in the first embodiment and will not be repeated here.

[0128] To alleviate stress on the first semiconductor wafer 100 and / or the second semiconductor wafer 200, thereby reducing the warpage of the first semiconductor wafer 100 and / or the second semiconductor wafer 200, a patterning process (e.g., etching process) can be performed on at least one of the first semiconductor wafer 100 and the second semiconductor wafer 200, forming a stress-adjusting opening in at least one of the first semiconductor wafer 100 and the second semiconductor wafer 200. In this embodiment, a patterning process can be performed on the second semiconductor wafer 200 to form a second stress-adjusting opening 226 in the second semiconductor wafer 200.

[0129] like Figure 26 As shown, a patterning process is performed on the second interconnect structure 220 of the second semiconductor wafer 200 to form second stress-adjusting openings 226 distributed in the second interconnect structure 220 along the second dicing path S2 of the second semiconductor wafer 200. In this embodiment, the height of the second stress-adjusting opening 226 is less than the thickness of the second interconnect structure 220; therefore, the second semiconductor substrate 210 is not exposed by the second stress-adjusting opening 226. After the second stress-adjusting opening 226 is formed, the stress of the second semiconductor wafer 200 is released by the second stress-adjusting opening 226, thus the warpage of the second semiconductor wafer 200 having multiple memory element layers 225 can be improved to a certain extent.

[0130] It is worth noting that in this embodiment, stress-adjusting material and / or other functional materials are not filled into the second stress-adjusting opening 226.

[0131] Please refer to Figures 27 to 28 The wafer bonding process in this embodiment (e.g.) Figure 27 (as shown) and cutting process (such as) Figure 28 (as shown) and the wafer bonding process in the first embodiment (e.g.) Figure 5A (as shown) and cutting process (such as) Figure 6A Similar to (as shown), so it will not be repeated here.

[0132] like Figure 28As shown, after the dicing process is completed, the fabrication of the individual semiconductor bonding structures SS10 is finished. Each of the plurality of individual semiconductor bonding structures SS10 has an adjustable stress groove 226R on its sidewall. In some embodiments, the adjustable stress groove 226R includes annular grooves distributed on the sidewall of the second semiconductor chip 200. In some other embodiments, the adjustable stress groove 226R includes a plurality of grooves distributed on the sidewall of the second semiconductor chip 200, and these grooves are spaced apart from each other.

[0133] Twelfth Embodiment

[0134] Figures 29 to 33 This is a schematic diagram of the manufacturing process of the semiconductor bonding structure according to the twelfth embodiment of this disclosure.

[0135] Please refer to Figure 29 A second semiconductor substrate 210 is provided, and a plurality of grooves 212 are formed on the surface of the second semiconductor substrate 210. In some embodiments, the second semiconductor substrate 210 includes a group IV semiconductor substrate (e.g., a silicon substrate), a group III-V semiconductor substrate, or a substrate of other materials. The grooves 212 can be formed by a photolithography etching process. Figure 29 As shown, the depth of the groove 212 can be less than the thickness of the second semiconductor substrate 210.

[0136] Please refer to Figure 30 Stress-regulating material is filled into the groove 212 to form a stress-regulating structure or stress-regulating region 214. For example... Figure 30As shown, the stress-regulating region is laterally surrounded by a second semiconductor substrate 210. In this embodiment, the stress-regulating region 214 can be formed by forming a stress-regulating material on the second semiconductor substrate 210 and in the groove 212, and then removing the stress-regulating material outside the groove 212 by a planarization process (e.g., chemical mechanical polishing, mechanical polishing, or a combination of the foregoing). In some embodiments, the material of the stress-regulating region 214 includes polymeric materials such as polyimide (PI), epoxy resin, benzocyclobutene (BCB), SU-8, or other suitable stress-buffering materials. The materials of the stress-regulating regions 214 may be the same or different. In other embodiments, the material of the stress-regulating region 214 includes inorganic materials such as carbon, silicon, SiCN, silicon carbide (SiC), silicon oxide (SiOx), borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), inorganic two-dimensional materials (2D materials), etc. In other feasible embodiments, the material of the stress-regulating region 214 includes metallic materials, such as tungsten (W), copper (Cu), aluminum (Al), silver (Ag), gold (Au), and two-dimensional metallic materials. As described above, in addition to its stress-regulating function, the stress-regulating region 214 may also possess good heat dissipation characteristics, water absorption characteristics, or other functions.

[0137] In other feasible embodiments, at least one functional material layer may be selectively formed between the stress adjustment region 214 and the second semiconductor substrate 210 (e.g., on the sidewall of the stress adjustment region 214 and / or on the bottom surface of the stress adjustment region 214), and the aforementioned functional material may be a heat dissipation material with good heat dissipation properties, a water absorption material with good water absorption properties, or other functional materials.

[0138] Please refer to Figure 31A second interconnect structure 220 and a plurality of memory element layers 225 are formed on a second semiconductor substrate 210 having a stress-adjusting region 214. The second interconnect structure 220 is disposed on the second semiconductor substrate 210, and the plurality of memory element layers 225 are stacked on the second semiconductor substrate 210 and embedded in the second interconnect structure 220. In some embodiments, the second interconnect structure 220 includes multiple dielectric layers 222 stacked on the second semiconductor substrate 210 and multiple conductive vias 224 embedded in the dielectric layers 222. In this embodiment, the dielectric layers 222 and conductive vias 224 in the second interconnect structure 220 are fabricated by back-end processing (BEOL). For example, the dielectric layer 222 in the second interconnect structure 220 is made of SiO2, SiON, SiN, SiC, SiCN, polymer materials or other insulating materials, and the conductive vias 224 are made of polysilicon, copper, gold, silver, cobalt or other metals. In some embodiments, each memory element layer 225 is electrically connected to the bottom end of at least one of the conductive vias 224, while the top end of the conductive via 224 is exposed on the upper surface of the second interconnect structure 220.

[0139] In some embodiments, memory element layer 225 includes multiple 3D NAND memory element layers, and memory element layer 225 may include at least 300 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stack. In other feasible embodiments, memory element layer 225 includes multiple 3D NAND memory element layers, and memory element layer 225 may include at least 1000 layers of silicon oxide-silicon nitride-silicon oxide (ONO) stack.

[0140] Please refer to Figure 32 A first semiconductor wafer 100 is provided. The first semiconductor wafer 100 has been described in the first embodiment and will not be repeated here.

[0141] like Figure 32As shown, the second semiconductor wafer 200 is flipped and aligned with the first semiconductor wafer 100. After the second semiconductor wafer 200 and the first semiconductor wafer 100 are aligned, the conductive vias 224 in the second interconnect structure 220 are aligned with the interconnect wires 124a in the first interconnect structure 120. After the alignment of the second semiconductor wafer 200 and the first semiconductor wafer 100 is completed, a bonding process is performed on the second semiconductor wafer 200 and the first semiconductor wafer 100, such as a hybrid bonding process or a micro-bump bonding process, to bond the patterned first interconnect structure 120 and the patterned second interconnect structure 220 together. Since the stress adjustment region 214 can reduce the warpage of the second semiconductor wafer 200, the bonding yield between the second semiconductor wafer 200 and the first semiconductor wafer 100 can be improved.

[0142] In some embodiments, before bonding the second semiconductor wafer 200 to the first semiconductor wafer 100, the second semiconductor substrate 210 can be thinned using a general mechanical polishing process followed by a chemical mechanical polishing process until the stress-regulating region 214 is exposed. In some embodiments, since the material of the stress-regulating region 214 is different from the material of the second semiconductor substrate 210 (e.g., silicon), the stress-regulating region 214 can serve as a stopping layer for the aforementioned chemical mechanical polishing process. In this case, the thickness of the stress-regulating region 214 is substantially equal to the thickness of the thinned second semiconductor substrate 210. In other feasible embodiments, the thinning process of the second semiconductor substrate 210 may not require exposing the stress-regulating region 214. In this case, the thickness of the stress-regulating region 214 is substantially less than the thickness of the thinned second semiconductor substrate 210.

[0143] Please refer to Figure 32 and Figure 33 After the bonding process between the second semiconductor wafer 200 and the first semiconductor wafer 100 is performed, a conductive layer 250 electrically connected to the second semiconductor wafer 200 can be formed on the second semiconductor substrate 210 having a stress-adjusting region 214. In some embodiments, before fabricating the conductive layer 250, a plurality of conductive through vias 260 electrically connected to the memory element layer 225 can be formed in the second semiconductor substrate 210. In some embodiments, the conductive through vias 260 can be a plurality of through-silicon vias (TSVs) penetrating the stress-adjusting region 214. Figure 33As shown, the conductive layer 250 and the second interconnect structure 220 are located on two opposite sides of the second semiconductor substrate 210, and the conductive layer 250 is electrically connected to the memory element layer 225 through the conductive via 260.

[0144] The wafer bonding process in this embodiment (e.g.) Figure 32 (as shown) and cutting process (such as Figure 33 (as shown) and the wafer bonding process in the first embodiment (e.g.) Figure 5A (as shown) and cutting process (such as Figure 6A Similar to (as shown), so it will not be repeated here.

[0145] In summary, the embodiments described above employ different types of stress-adjusting structures, stress-adjusting openings, or adjustable stress grooves to reduce the warpage of semiconductor wafers, thereby improving the bonding yield between semiconductor wafers. Furthermore, the embodiments described above can improve the heat dissipation performance of the semiconductor bonding structure through stress-adjusting structures, stress-adjusting openings, or adjustable stress grooves, thereby enhancing the operational performance of the semiconductor bonding structure.

[0146] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A semiconductor bonding structure, comprising: a first semiconductor chip; at least one second semiconductor chip, disposed on the first semiconductor chip and electrically connected to the first semiconductor chip; a stress regulating structure disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip; as well as The conductive layer is disposed on the at least one second semiconductor chip, and the conductive layer is electrically connected to the at least one second semiconductor chip.

2. The semiconductor bonding structure according to claim 1, wherein the stress adjustment structure comprises a first stress adjustment region configured in a first semiconductor chip, and the first semiconductor chip comprises: A first semiconductor substrate including a plurality of semiconductor elements; as well as The first interconnect structure is disposed on the first semiconductor substrate and electrically connected to the first semiconductor substrate, wherein the first stress adjustment region in the stress adjustment structure is disposed on the sidewall of the first interconnect structure.

3. The semiconductor bonding structure according to claim 1, wherein the stress regulation structure comprises a first stress regulation region configured in a first semiconductor chip, and the first semiconductor chip comprises: A first semiconductor substrate including a plurality of semiconductor elements; as well as The first interconnect structure is disposed on the first semiconductor substrate and electrically connected to the first semiconductor substrate, wherein the first stress adjustment region is disposed on the sidewall of the first semiconductor substrate and the sidewall of the first interconnect structure. 4 . The semiconductor bonding structure according to claim 1 , wherein the stress adjustment structure comprises a first stress adjustment region configured in a first semiconductor chip, and the first stress adjustment region comprises an annular wall structure, and the annular wall structure surrounds the first semiconductor chip.

5. The semiconductor bonding structure according to claim 1, wherein the stress adjustment structure comprises a first stress adjustment region configured in a first semiconductor chip, and the first stress adjustment region comprises a plurality of columnar structures, the plurality of columnar structures are configured around the first semiconductor chip, and the plurality of columnar structures are separated from each other.

6. The semiconductor bonding structure of claim 1 , wherein the stress regulation structure comprises a second stress regulation region disposed in a second semiconductor chip, and the second semiconductor chip comprises: a second semiconductor substrate; as well as The second interconnect structure is disposed on the second semiconductor substrate and electrically connected to the second semiconductor substrate, wherein the second interconnect structure includes a plurality of memory element layers, and the second stress adjustment region is disposed on a sidewall of the second interconnect structure.

7. The semiconductor bonding structure according to claim 1, wherein the stress regulation structure comprises a second stress regulation region configured in a second semiconductor chip, and the second semiconductor chip comprises: a second semiconductor substrate; as well as The second interconnect structure is configured on the second semiconductor substrate and electrically connected to the second semiconductor substrate, wherein the second interconnect structure includes a plurality of memory element layers, and the second stress adjustment region is configured on the sidewall of the second semiconductor substrate and the sidewall of the second interconnect structure.

8. The semiconductor bonding structure of claim 1 , wherein the stress regulation structure comprises a second stress regulation region disposed in a second semiconductor chip, and the second semiconductor chip comprises: a second semiconductor substrate, wherein the second stress adjustment region is embedded in the second semiconductor substrate, and the second stress adjustment region is surrounded by the second semiconductor substrate; as well as The second interconnect structure is disposed on the second semiconductor substrate and electrically connected to the second semiconductor substrate, wherein the second interconnect structure includes a plurality of memory element layers, and the second stress adjustment region contacts the second interconnect structure. 9 . The semiconductor bonding structure according to claim 8 , wherein a height of the second stress adjustment region is less than or equal to a thickness of the second semiconductor substrate. 10 . The semiconductor bonding structure of claim 1 , wherein the stress adjustment structure comprises a second stress adjustment region disposed in a second semiconductor chip, and the second stress adjustment region comprises an annular wall structure, and the annular wall structure surrounds the second semiconductor chip.

11. The semiconductor bonding structure according to claim 1, wherein the stress adjustment structure comprises a second stress adjustment region configured in a second semiconductor chip, and the second stress adjustment region comprises a plurality of columnar structures, the plurality of columnar structures are configured around the second semiconductor chip, and the plurality of columnar structures are separated from each other.

12. A semiconductor bonding structure according to claim 1, wherein the stress adjustment structure includes a second stress adjustment region configured in a second semiconductor chip, and the second stress adjustment region includes a plurality of stress-adjustable grooves, the plurality of stress-adjustable grooves are distributed on the side walls of the second semiconductor chip, and the plurality of stress-adjustable grooves are separated from each other. 13 . The semiconductor bonding structure according to claim 1 , wherein a height of the first stress adjustment region is less than a thickness of the first semiconductor chip, and a height of the second stress adjustment region is less than or equal to a thickness of the second semiconductor chip.

14. A method for manufacturing a semiconductor bonding structure, comprising: Providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a first semiconductor substrate and a first interconnect structure disposed on the first semiconductor substrate; patterning the first interconnect structure of the first semiconductor wafer to form a first stress regulating opening along a first scribe line of the first semiconductor wafer; A second semiconductor wafer is provided, wherein the second semiconductor wafer includes a second semiconductor substrate and a second interconnect structure disposed on the second semiconductor substrate: patterning the second interconnect structure of the second semiconductor wafer to form a second stress regulation opening along a second scribe line of the second semiconductor wafer; joining the first interconnect structure and the second interconnect structure; After bonding the first interconnect structure to the second interconnect structure, forming a conductive layer on the second semiconductor substrate; as well as The first semiconductor wafer, the second semiconductor wafer and the conductive layer are cut along the first cutting line and the second cutting line to form a plurality of individualized chip bonding structures, wherein each of the plurality of individualized chip bonding structures has a groove on its sidewall for adjusting stress.

15. The method for manufacturing a semiconductor bonding structure according to claim 14, further comprising: Before bonding the first interconnect structure and the second interconnect structure, a stress adjustment material is filled into the first stress adjustment opening and the second stress adjustment opening.

16. The method for manufacturing a semiconductor bonding structure according to claim 15, wherein during cutting of the first semiconductor wafer, the second semiconductor wafer and the conductive layer along the first cutting street and the second cutting street, the stress adjustment material is cut to form a stress adjustment structure located in the stress-adjustable groove.

17. The method for manufacturing a semiconductor bonding structure according to claim 14, further comprising: Before forming a conductive layer on the second semiconductor substrate, a conductive via is formed in the second semiconductor substrate, wherein the conductive layer is electrically connected to the second interconnect structure through the conductive via.

18. The method for manufacturing a semiconductor bonding structure according to claim 14, further comprising: Before forming a conductive layer on the second semiconductor substrate, thinning the second semiconductor substrate; as well as A conductive via is formed in the thinned second semiconductor substrate, wherein the conductive layer is electrically connected to the second interconnect structure through the conductive via.

19. A method for manufacturing a semiconductor bonding structure, comprising: Providing a first semiconductor wafer, wherein the first semiconductor wafer comprises a first semiconductor substrate and a first interconnect structure configured on the first semiconductor substrate; Providing a second semiconductor wafer, the second semiconductor wafer comprising a second semiconductor substrate, a plurality of stress adjustment structures embedded in the second semiconductor substrate, and a second interconnect structure disposed on the second semiconductor substrate and the plurality of stress adjustment structures, wherein the second interconnect structure comprises a plurality of memory element layers disposed on the second semiconductor substrate; bonding the first semiconductor wafer and the second semiconductor wafer; as well as After bonding the first semiconductor wafer to the second semiconductor wafer, a reconfiguration conductive layer is formed on the second semiconductor substrate and the plurality of stress adjustment structures.

20. The method for manufacturing a semiconductor bonding structure according to claim 19, wherein the method of providing the second semiconductor wafer comprises: forming a plurality of grooves separated from each other on the surface of the second semiconductor substrate; forming the plurality of stress regulating structures in the plurality of grooves; thinning the second semiconductor substrate; as well as The second interconnect structure is formed on the second semiconductor substrate and the plurality of stress regulating structures.

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