Array substrate manufacturing method and low-temperature polycrystalline silicon liquid crystal display panel

Abstract

The invention discloses an array substrate manufacturing method and a low-temperature polycrystalline silicon liquid crystal display panel. The method comprises the steps that a signal line metal layer is manufactured, and a first insulating layer is manufactured on the signal line metal layer; manufacturing a second insulating layer on the first insulating layer, manufacturing an active layer of the first triode in the second insulating layer, and forming a first opening in the second insulating layer, so that the metal signal line layer is connected with the active layer of the first triode through the first opening; and second holes are formed in the second insulating layer and the third insulating layer, so that the active layer of the first triode, the common gate metal layer and the active layer of the second triode are vertically connected in series in sequence. An active layer and a common grid metal layer in a film layer structure of a triode of the array substrate adopt a vertical series connection structure, so that the pixel area occupied by the triode is greatly reduced, the windowing area is increased, the aperture opening ratio of the low-temperature polycrystalline silicon liquid crystal display panel is increased, and the pixel transmittance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel structures of low-temperature polysilicon liquid crystal display panels, and in particular to an array substrate manufacturing method and a low-temperature polysilicon liquid crystal display panel. Background Art

[0002] Liquid crystal display panels are widely used in various display fields. Liquid crystal display panels generally include an array substrate, a color filter substrate, and a liquid crystal layer filled between the array substrate and the color filter substrate. Pixel electrodes and common electrodes are formed on at least one of the array substrate and the color filter substrate. A voltage is applied to form an electric field between the pixel electrode and the common electrode. The orientation angle of the liquid crystal molecules is modulated by controlling the change in the electric field intensity, thereby changing the light transmittance of the backlight source.

[0003] According to different specific principles, the liquid crystal display panel has developed from the early TN (Twisted Nematic, TN) mode to the current VA mode and IPS (In-plane Switching, IPS) mode.

[0004] In the Multi-domain Vertical Alignment (MVA) mode, the liquid crystal molecules in the liquid crystal box are vertically arranged in the liquid crystal layer by relying on the surface anchoring energy of the alignment film layer. When an external bias is applied to the indium tin oxide (ITO) plates on the upper and lower sides of the liquid crystal layer, an electric field is formed in the liquid crystal layer, and the liquid crystal molecules are deflected under the action of the electric field, and the optical path difference is generated in conjunction with the setting of the polarizer and the backlight source, and different transmittances are obtained, so that images can be displayed. The main advantages of the VA mode are high contrast, strong detail performance in dark places, and a wide viewing angle.

[0005] The existing low-temperature polysilicon liquid crystal display panel is opaque in the transistor switch area, resulting in a small window area and low transmittance. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide an array substrate manufacturing method and a low-temperature polysilicon liquid crystal display panel to solve the problems of small window area and low transmittance of the existing low-temperature polysilicon liquid crystal display panel.

[0007] In a first aspect, a method for manufacturing an array substrate includes: Step 100: manufacturing a signal line metal layer, and manufacturing a first insulating layer on the signal line metal layer; Step 200, forming a second insulating layer on the first insulating layer, forming an active layer of a first triode in the second insulating layer, and forming a first opening in the second insulating layer, so that the metal signal line layer is connected to the active layer of the first triode through the first opening; Step 300, sequentially fabricate a common gate metal layer and a third insulating layer, and then fabricate an active layer of a second triode, and open a second opening in the second insulating layer and the third insulating layer, so that the active layer of the first triode, the common gate metal layer, and the active layer of the second triode are sequentially vertically connected in series.

[0008] Furthermore, the step 100 includes: Step 110 : forming a light-shielding pattern of the signal line metal layer on a glass substrate, wherein the light-shielding pattern is used to shield the active layer of the first transistor.

[0009] Furthermore, the step 100 further includes: Step 120 : manufacturing a touch metal layer on the glass substrate at the same layer as the signal line metal layer.

[0010] Furthermore, the step 200 includes: Step 210, forming first poly layer patterns on both sides and forming second poly layer patterns in the middle in the second insulating layer in sequence, wherein the first poly layer patterns and the second poly layer patterns form a first doped region and a second doped region; Step 220, annealing the first poly layer pattern and the second poly layer pattern; Step 230 , performing CHD material doping and ND material doping in the first doping region and the second doping region respectively to obtain an active layer of the first transistor.

[0011] Furthermore, the step 220 includes: Step 221, obtaining a laser annealing device, and configuring parameters of the laser annealing device to ensure irradiation uniformity; Step 222: Use the laser annealing equipment to irradiate the first poly layer pattern and the second poly layer pattern respectively for annealing.

[0012] Furthermore, the step 300 includes: Step 310, forming a pattern of the second insulating layer on the first insulating layer; Step 320, forming a pattern of the common gate metal layer on the second insulating layer; Step 330 , forming a pattern of a third insulating layer on the common gate metal layer.

[0013] Furthermore, the step 320 includes: Step 321, forming a pattern of the common gate metal layer on the second insulating layer; Step 322: perform LDD doping on the common gate metal layer to form a first transistor together with the active layer of the first transistor.

[0014] Furthermore, the step 300 also includes: Step 340, forming third poly layer patterns on both sides and a fourth poly layer pattern in the middle on the third insulating layer in sequence, wherein the third poly layer pattern and the fourth poly layer pattern form a third doped region and a fourth doped region; Step 350, annealing the third poly layer pattern and the fourth poly layer pattern; Step 360 , performing CHD material doping and ND material doping in the third doping region and the fourth doping region respectively to obtain an active layer of a second triode, wherein the active layer of the second triode and the common gate metal layer constitute a second triode.

[0015] Furthermore, the array substrate manufacturing method further includes: Step 400, forming a first ITO layer on the same layer as the active layer of the second triode; Step 500: fabricate a fourth insulating layer on the first ITO layer, and form a second ITO layer on the fourth insulating layer.

[0016] In a second aspect, a low-temperature polysilicon liquid crystal display panel includes an array substrate manufactured by the array substrate manufacturing method described in the first aspect.

[0017] Compared with the prior art, the embodiments of the present application mainly have the following technical effects: by adopting a vertical series connection structure for the active layer and the common gate metal layer in the film layer structure of the transistor of the array substrate, the pixel area occupied by the transistor is greatly reduced, the window area is increased, the aperture ratio of the low-temperature polycrystalline silicon liquid crystal display panel is increased, and the transmittance of the pixel is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the scheme in the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A flowchart of an embodiment of a method for manufacturing an array substrate according to the present application; Figure 2 yes Figure 1 A flowchart of a specific implementation of S200; Figure 3 yes Figure 2 A flowchart of a specific implementation of S220; Figure 4 yes Figure 1 A flowchart of a specific implementation of S300; Figure 5 yes Figure 4 A flowchart of a specific implementation of S320; Figure 6 yes Figure 4 A flowchart of a specific implementation method after S330; Figure 6 yes Figure 4 A flowchart of a specific implementation method after S330; Figure 7 A flowchart of another embodiment of a method for manufacturing an array substrate according to the present application; Figure 8 It is a schematic diagram of the pixel structure of an existing polysilicon liquid crystal display panel; Fig. 9 is a top view schematic diagram of a pixel structure of a polysilicon liquid crystal display panel in the present application; Fig.10 is a left-side schematic diagram of a pixel structure of a polysilicon liquid crystal display panel in the present application; Fig.11 It is a schematic diagram of the main view of the pixel structure of the polysilicon liquid crystal display panel in this application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the invention to clearly and completely describe the technical solutions in the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, other embodiments obtained by ordinary technicians in this field without creative work are all within the scope of protection of the present invention.

[0021] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0023] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0024] The purpose of the embodiments of the present application is to provide an array substrate manufacturing method and a low-temperature polysilicon liquid crystal display panel to solve the problems of small window area and low transmittance of the existing low-temperature polysilicon liquid crystal display panel.

[0025] like Figure 8 , Figure 8 It is a schematic diagram of the pixel structure of an existing polysilicon liquid crystal display panel; that is, the triode design of the existing low-temperature polysilicon LCD, the M2 metal layer is used as a common gate metal layer for two triodes, and the pixel signal is provided by the M1 metal layer. When the M2 metal layer works at a high potential, the two triodes are turned on at the same time, and the pixel signal is charged from the M1 metal layer through the two triodes to the pixel.

[0026] But if Figure 8 As shown, the transistor switch area 101 is opaque, which leads to a reduction in the area of ​​the pixel window area.

[0027] First, as Figure 1 , Figure 1 A flowchart of an embodiment of a method for manufacturing an array substrate according to the present application; a method for manufacturing an array substrate includes: S100 , manufacturing a signal line metal layer 110 (M1 metal), and manufacturing a first insulating layer 210 (ILD1) on the signal line metal layer 110 (M1 metal).

[0028] In this embodiment, the first insulating layer 210 (ILD1) is used for insulation between the signal line metal layer 110 (M1 metal) and the active layer 130 (poly1) of the first transistor. The signal line metal layer 110 (M1 metal) is manufactured on a glass substrate.

[0029] In a preferred embodiment, S100 includes: S110 , forming a light shielding pattern of a signal line metal layer 110 (M1 metal) on a glass substrate, wherein the light shielding pattern is used to shield the active layer 130 of the first transistor.

[0030] In this embodiment, in order to prevent the poly semiconductor material of the active layer 130 (poly1) of the first transistor from being affected by light, thereby affecting the characteristics of the transistor, when manufacturing the signal line metal layer 110 (M1 metal) pattern, the pattern is made into a shading pattern, thereby preventing backlight from directly irradiating the poly semiconductor material of the active layer, thereby ensuring the switching characteristics of the first transistor.

[0031] In a preferred embodiment, S100 further includes: S120 , manufacturing a touch metal layer on the glass substrate at the same layer as the signal line metal layer 110 (M1 metal).

[0032] In this embodiment, when manufacturing the signal line metal layer 110 (M1 metal), if the low-temperature polysilicon liquid crystal display panel needs a touch function, a touch layer needs to be manufactured on the same layer as the signal line metal layer 110 (M1 metal).

[0033] S200, forming a second insulating layer 220 (GI1) on the first insulating layer 210 (ILD1), forming an active layer 130 of a first transistor in the second insulating layer 220 (GI1), and forming a first opening 120 in the second insulating layer 220 (GI1), so that the metal signal line layer is connected to the active layer 130 of the first transistor through the first opening 120.

[0034] In this embodiment, the active layer 130 of the first transistor is made of poly semiconductor material, is made in the second insulating layer 220 (GI1), and is overlapped with the signal line metal layer 110 (M1 metal) through the first opening 120.

[0035] In a specific implementation, the active layer 130 of the first triode needs to be formed and doped twice to form the first triode of the low-temperature polysilicon liquid crystal display panel.

[0036] In a preferred embodiment, Figure 2 , Figure 2 yes Figure 1A flowchart of a specific implementation of S200; S200 includes: including: S210, respectively, in the second insulating layer 220 (GI1), the first poly layer pattern on both sides and the second poly layer pattern in the middle are formed in sequence, and the first poly layer pattern and the second poly layer pattern form a first doping region 131 and a second doping region 132; S220, annealing the first poly layer pattern and the second poly layer pattern; S230, CHD material doping and ND material doping are performed in the first doping region 131 and the second doping region 132, respectively, to obtain the active layer 130 of the first transistor.

[0037] During film formation, the first poly layer pattern is first formed, and then the second poly layer pattern is formed. The first poly layer patterns on both sides and the second poly layer pattern in the middle constitute the first doped region 131 and the second doped region 132 respectively.

[0038] In this embodiment, after the first poly layer pattern and the second poly layer pattern are formed, the poly film layer is annealed. Through annealing, the poly semiconductor material is transformed from an amorphous state or a partially crystalline state to a more crystalline state, thereby reducing defect density and improving carrier mobility.

[0039] In a preferred embodiment, Figure 3 , Figure 3 yes Figure 2 A flowchart of a specific implementation of S220; S220 includes: S221, obtaining a laser annealing device, configuring the parameters of the laser annealing device to ensure irradiation uniformity; S222, using the laser annealing device to irradiate the first poly layer pattern and the second poly layer pattern respectively for annealing.

[0040] In this embodiment, laser annealing is used to irradiate the film layers of the first poly layer pattern and the second poly layer pattern with a high-energy laser beam, and the film layers are annealed by precisely controlling the power, wavelength and scanning speed of the laser. Laser annealing can achieve precise annealing of the poly pattern without affecting other film layers.

[0041] S300, sequentially fabricating a common gate metal layer 160 (M2 metal) and a second insulating layer 220 (GI2), and then fabricating an active layer 150 of a second triode, and opening a second opening 140 in the second insulating layer 220 (GI1) and a third insulating layer 230 (GI2), so that the active layer 130 of the first triode, the common gate metal layer 160 (M2 metal), and the active layer 150 of the second triode are sequentially vertically connected in series.

[0042] In a preferred embodiment, Figure 4, Figure 4 yes Figure 1 A flowchart of a specific implementation of S300; S300 includes: S310, forming a pattern of the second insulating layer 220 (GI1) on the first insulating layer 210 (ILD1); S320, making a pattern of the common gate metal layer 160 (M2 metal) on the second insulating layer 220 (GI1); S330, forming a pattern of the third insulating layer 230 (GI2) on the common gate metal layer 160 (M2 metal).

[0043] In this embodiment, the second insulating layer 220 (GI1) is used for insulation between the common gate metal layer 160 (M2 metal) and the active layer 130 (poly1) of the first transistor, and the third insulating layer 230 (GI2) is used for insulation between the common gate metal layer 160 (M2 metal) and the active layer 150 (poly2) of the second transistor.

[0044] In this embodiment, the second opening 140 passes through the active layer 130 (poly1) of the first transistor, the common gate metal layer 160 (M2 metal), and the active layer 150 (poly2) of the second transistor, so that the three are vertically overlapped.

[0045] In a preferred embodiment, if Figure 5 , Figure 5 yes Figure 4 A flowchart of a specific implementation of S320; S320 includes: S321, forming a pattern of a common gate metal layer 160 (M2 metal) on the second insulating layer 220 (GI1); S322, performing LDD doping on the common gate metal layer 160 (M2 metal) to form a first transistor with the active layer 130 of the first transistor.

[0046] In this embodiment, the common gate metal layer 160 (M2 metal) is LDD doped, and the doping ions are accelerated and injected into the common gate metal layer 160 (M2 metal) to achieve light doping, thereby improving the switching performance of the triode, for example, increasing the switching speed, reducing the leakage current, and improving the stability and accuracy of signal transmission. It can also reduce the hot carrier effect, extend the service life of the array substrate, and reduce the failure rate.

[0047] In a preferred embodiment, Figure 6 , Figure 6 yes Figure 4 A flowchart of a specific implementation method after S330; S300 also includes: S340, respectively, sequentially perform third poly layer patterning on both sides and fourth poly layer patterning in the middle on the third insulating layer 230 (GI2), and the third poly layer pattern and the fourth poly layer pattern form a third doping region 151 and a fourth doping region 152; S350, anneal the third poly layer pattern and the fourth poly layer pattern; S360, perform CHD material doping and ND material doping on the third doping region 151 and the fourth doping region 152, respectively, to obtain an active layer 150 of a second triode, and the active layer 150 of the second triode and the common gate metal layer 160 (M2 metal) constitute a second triode.

[0048] During film formation, the third poly layer pattern is first formed, and then the fourth poly layer pattern is formed. The third poly layer patterns on both sides and the fourth poly layer pattern in the middle constitute the third doped region 151 and the fourth doped region 152 respectively.

[0049] In this embodiment, after the third poly layer pattern and the fourth poly layer pattern are formed, the poly film layer is annealed. Through annealing, the poly semiconductor material is transformed from an amorphous state or a partially crystalline state to a more crystalline state, thereby reducing defect density and improving carrier mobility.

[0050] In this embodiment, laser annealing is used to irradiate the film layers of the third poly layer pattern and the fourth poly layer pattern with a high-energy laser beam, and the film layers are annealed by precisely controlling the power, wavelength and scanning speed of the laser. Laser annealing can achieve precise annealing of the poly pattern without affecting other film layers.

[0051] Further, such as Figure 7 , Figure 7 According to a flowchart of another embodiment of a method for manufacturing an array substrate of the present application, the method for manufacturing an array substrate further includes: S400 , forming a first ITO layer 310 on the same layer as the active layer 150 of the second transistor; S500 , manufacturing a fourth insulating layer 240 ( ILD2 ) on the first ITO layer 310 , and forming a second ITO layer 320 on the fourth insulating layer 240 ( ILD2 ).

[0052] In this embodiment, the fourth insulating layer 240 (ILD2) is used as a storage capacitor insulating layer, and vias are etched in the film layer to connect to the underlying metal layer in preparation for the final ITO layer.

[0053] like Fig. 9 , Fig.10 , Fig.11 , Fig. 9 is a top view schematic diagram of the pixel structure of the polysilicon liquid crystal display panel in this application, Fig.10 is a left-side schematic diagram of a pixel structure of a polysilicon liquid crystal display panel in this application, Fig.11 This is a schematic diagram of the pixel structure of the polysilicon liquid crystal display panel in the present application. By adopting a vertical series connection structure for the active layer and the common gate metal layer 160 (M2 metal) in the film layer structure of the triode of the array substrate, the pixel area occupied by the triode is greatly reduced, the window area is increased, the aperture ratio of the low-temperature polysilicon liquid crystal display panel is increased, and the transmittance of the pixel is improved.

[0054] In a second aspect, a low-temperature polysilicon liquid crystal display panel includes an array substrate manufactured by the array substrate manufacturing method of the first aspect.

[0055] Compared with the prior art, the embodiments of the present application mainly have the following technical effects: by adopting a vertical series connection structure for the active layer and the common gate metal layer 160 (M2 metal) in the film layer structure of the transistor of the array substrate, the pixel area occupied by the transistor is greatly reduced, the window area is increased, the aperture ratio of the low-temperature polysilicon liquid crystal display panel is increased, and the transmittance of the pixel is improved.

[0056] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for manufacturing an array substrate, comprising: Step 100: manufacturing a signal line metal layer, and manufacturing a first insulating layer on the signal line metal layer; Step 200, forming a second insulating layer on the first insulating layer, forming an active layer of a first triode in the second insulating layer, and forming a first opening in the second insulating layer, so that the metal signal line layer is connected to the active layer of the first triode through the first opening; Step 300, sequentially fabricate a common gate metal layer and a third insulating layer, and then fabricate an active layer of a second triode, and open a second opening in the second insulating layer and the third insulating layer, so that the active layer of the first triode, the common gate metal layer, and the active layer of the second triode are sequentially vertically connected in series.

2. The method for manufacturing an array substrate according to claim 1, characterized in that: The step 100 comprises: Step 110 : forming a light-shielding pattern of the signal line metal layer on a glass substrate, wherein the light-shielding pattern is used to shield the active layer of the first transistor.

3. The method for manufacturing an array substrate according to claim 1, characterized in that: The step 100 further includes: Step 120 : manufacturing a touch metal layer on the glass substrate at the same layer as the signal line metal layer.

4. The method for manufacturing an array substrate according to claim 1, characterized in that: The step 200 includes: Step 210, forming first poly layer patterns on both sides and forming second poly layer patterns in the middle in the second insulating layer in sequence, wherein the first poly layer patterns and the second poly layer patterns form a first doped region and a second doped region; Step 220, annealing the first poly layer pattern and the second poly layer pattern; Step 230 , performing CHD material doping and ND material doping in the first doping region and the second doping region respectively to obtain an active layer of the first transistor.

5. The method for manufacturing an array substrate according to claim 4, characterized in that: The step 220 includes: Step 221, obtaining a laser annealing device, and configuring parameters of the laser annealing device to ensure irradiation uniformity; Step 222: Use the laser annealing equipment to irradiate the first poly layer pattern and the second poly layer pattern respectively for annealing.

6. The method for manufacturing an array substrate according to claim 1, characterized in that: The step 300 includes: Step 310, forming a pattern of the second insulating layer on the first insulating layer; Step 320, forming a pattern of the common gate metal layer on the second insulating layer; Step 330 , forming a pattern of a third insulating layer on the common gate metal layer.

7. The method for manufacturing an array substrate according to claim 6, characterized in that: The step 320 includes: Step 321, forming a pattern of the common gate metal layer on the second insulating layer; Step 322: perform LDD doping on the common gate metal layer to form a first transistor together with the active layer of the first transistor.

8. The method for manufacturing an array substrate according to claim 1, characterized in that: The step 300 further includes: Step 340, forming third poly layer patterns on both sides and a fourth poly layer pattern in the middle on the third insulating layer in sequence, wherein the third poly layer pattern and the fourth poly layer pattern form a third doped region and a fourth doped region; Step 350, annealing the third poly layer pattern and the fourth poly layer pattern; Step 360 , performing CHD material doping and ND material doping in the third doping region and the fourth doping region respectively to obtain an active layer of a second triode, wherein the active layer of the second triode and the common gate metal layer constitute a second triode.

9. The method for manufacturing an array substrate according to claim 1, characterized in that: The array substrate manufacturing method further includes: Step 400, forming a first ITO layer on the same layer as the active layer of the second triode; Step 500: fabricate a fourth insulating layer on the first ITO layer, and form a second ITO layer on the fourth insulating layer.

10. A low temperature polysilicon liquid crystal display panel, characterized in that: It comprises an array substrate manufactured by the array substrate manufacturing method according to any one of claims 1 to 9.

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