Display device

Abstract

Disclosed in an embodiment of the present invention are a pixel and a display device including the pixel, the pixel including a thin film transistor connected to a node between a driving transistor and a light emitting diode and a thin film transistor connected to a gate of the driving transistor, and thereby enabling initialization and compensation, wherein one terminal of the driving transistor and one electrode of the light emitting diode have different initialization timings.

Description

Technical Field

[0001] One or more embodiments relate to a pixel and a display device including the pixel. Background Art

[0002] Recently, display devices have been used for various purposes. Also, as display devices become thinner and lighter, their use range has been widened.

[0003] As the display device is used in various ways, various methods may be used to design the display device, and further, more and more functions may be combined or associated with the display device. Summary of the invention

[0004] Technical issues

[0005] One or more embodiments include a display device with improved display quality.However, these issues are merely examples and the scope of the present disclosure is not limited thereto.

[0006] Solutions to technical problems

[0007] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor including a first gate and a second gate, a second transistor connected between the first gate of the first transistor and a data line, a third transistor connected between the first gate of the first transistor and a first voltage line, a fourth transistor connected between the first transistor and the second voltage line, a fifth transistor connected between the first transistor and the third voltage line, a sixth transistor connected between the first transistor and the fourth voltage line, a light emitting diode connected to the first transistor, a first capacitor connected between the first gate of the first transistor and the light emitting diode, and a second capacitor connected between the third voltage line and the light emitting diode.

[0008] In an embodiment, the second gate of the first transistor may be connected to a node connected to the first transistor and the light emitting diode.

[0009] In an embodiment, the pixel may operate with a non-emission period and an emission period during a frame period, and the non-emission period may include a first period, a writing period, and a second period, the third transistor and the fourth transistor are turned on in the first period, the second transistor is turned on in the writing period, the writing period is after the first period, the sixth transistor is turned on in the second period, and the second period is after the writing period.

[0010] In an embodiment, the non-emission period may further include a third period in which the third transistor and the fifth transistor are turned on and the first voltage is supplied from the first voltage line to the first gate of the first transistor through the turned-on third transistor, and the third period is set between the first period and the writing period.

[0011] In an embodiment, the pixel may further include a seventh transistor connected between the first transistor and the light emitting diode.

[0012] In an embodiment, the seventh transistor may be turned on in the first period and the second period, and turned off in the third period and the writing period.

[0013] In an embodiment, the second transistor may be turned on in the writing period, and the data signal may be supplied to the first gate of the first transistor through the turned-on second transistor.

[0014] In an embodiment, the fourth voltage line may include a 4-1 voltage line and a 4-2 voltage line, a sixth transistor of a first pixel among multiple pixels that emits light of a first color may be connected to the 4-1 voltage line, a sixth transistor of a second pixel among multiple pixels that emits light of a second color may be connected to the 4-2 voltage line, and a voltage supplied to the 4-1 voltage line and a voltage supplied to the 4-2 voltage line may be different from each other.

[0015] In an embodiment, each of the first to fourth voltage lines may extend in a first direction, and the display device may further include first to fourth longitudinal voltage lines, which extend in a second direction perpendicular to the first direction and are respectively connected to the first to fourth voltage lines.

[0016] In an embodiment, each of the first to fourth voltage lines may be arranged in each row, and each of the first to fourth longitudinal voltage lines may be arranged at a certain interval between two columns.

[0017] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a light emitting diode, a first transistor including a first gate and a second gate, a second transistor connected to the first gate of the first transistor and a data line, a third transistor connected to the first gate of the first transistor and a first voltage line, a fourth transistor connected to the first transistor and the second voltage line, a fifth transistor connected to the first transistor and the light emitting diode, a sixth transistor connected to the fifth transistor and the third voltage line, a first capacitor connected to the first gate of the first transistor and the fifth transistor, and a second capacitor connected to the second voltage line and the fifth transistor.

[0018] In an embodiment, the second gate of the first transistor may be connected to a node connected to the first transistor and the fifth transistor.

[0019] In an embodiment, the sixth transistor may be connected between the third voltage line and a node to which the first transistor and the fifth transistor are connected.

[0020] In an embodiment, the pixel may further include a seventh transistor connected between the first transistor and the fourth voltage line.

[0021] In an embodiment, the pixel may operate with a non-emission period and an emission period during a frame period, and the non-emission period may include a first period, a writing period, a second period, and a third period. In the first period, the third transistor, the fifth transistor, and the sixth transistor are turned on, and in the writing period, the second transistor is turned on and the fifth transistor is turned off. The writing period is after the first period, and in the second period, the fifth transistor and the seventh transistor are turned on. The second period is after the writing period, and in the third period, the third transistor and the fourth transistor are turned on and the fifth transistor is turned off. The third period is set between the first period and the writing period.

[0022] In an embodiment, the fourth voltage line may include a 4-1 voltage line and a 4-2 voltage line, a seventh transistor of a first pixel among multiple pixels that emits light of a first color may be connected to the 4-1 voltage line, a seventh transistor of a second pixel among multiple pixels that emits light of a second color may be connected to the 4-2 voltage line, and a voltage supplied to the 4-1 voltage line and a voltage supplied to the 4-2 voltage line may be different from each other.

[0023] In an embodiment, the pixel may further include a seventh transistor connected between the fourth voltage line and a node to which the fifth transistor and the light emitting diode are connected.

[0024] In an embodiment, the pixel may operate with a non-emission period and an emission period during a frame period, and the non-emission period may include a first period, a writing period, a second period, and a third period. The third transistor and the sixth transistor are turned on in the first period, the second transistor is turned on in the writing period, the writing period is after the first period, the seventh transistor is turned on in the second period, the second period is after the writing period, the third transistor and the fourth transistor are turned on in the third period, the third period is set between the first period and the writing period, and the fifth transistor may be turned off in the non-emission period and turned on in the emission period.

[0025] In an embodiment, the fourth voltage line may include a 4-1 voltage line and a 4-2 voltage line, a seventh transistor of a first pixel among multiple pixels that emits light of a first color may be connected to the 4-1 voltage line, a seventh transistor of a second pixel among multiple pixels that emits light of a second color may be connected to the 4-2 voltage line, and a voltage supplied to the 4-1 voltage line and a voltage supplied to the 4-2 voltage line may be different from each other.

[0026] In an embodiment, the sixth transistor may be connected between the third voltage line and a node to which the fifth transistor and the light emitting diode are connected.

[0027] In an embodiment, the pixel may operate with a non-emission period and an emission period during a frame period, and the non-emission period may include a first period, a writing period, and a second period, in which the third transistor, the fifth transistor, and the sixth transistor are turned on, in which the second transistor is turned on, the writing period follows the first period, in which the fifth transistor and the sixth transistor are turned on and the third transistor is turned off, and the second period follows the writing period.

[0028] In an embodiment, the non-emission period may further include a third period in which the third and fourth transistors are turned on and the fifth and sixth transistors are turned off, the third period being provided between the first period and the writing period.

[0029] In an embodiment, in a writing period, the second transistor may be turned on and the data signal may be supplied to the first gate of the first transistor through the turned-on second transistor.

[0030] In an embodiment, the third voltage line may include a 3-1 voltage line and a 3-2 voltage line, a sixth transistor of a first pixel emitting light of a first color among a plurality of pixels may be connected to the 3-1 voltage line, a sixth transistor of a second pixel emitting light of a second color among a plurality of pixels may be connected to the 3-2 voltage line, and a voltage supplied to the 3-1 voltage line and a voltage supplied to the 3-2 voltage line may be different from each other.

[0031] In an embodiment, each of the first to third voltage lines may extend in a first direction, and the display device may further include first to third longitudinal voltage lines extending in a second direction perpendicular to the first direction and respectively connected to the first to third voltage lines.

[0032] In an embodiment, each of the first to third voltage lines may be arranged in each row, and each of the first to third longitudinal voltage lines may be arranged at a certain interval between two columns.

[0033] Effects of the Invention

[0034] According to the embodiment, it is possible to provide a display device with improved display quality by minimizing the luminance deviation of each pixel. However, the scope of the present disclosure is not limited to these effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1a , Figure 1b and Figure 2 is a diagram schematically showing a display device according to an embodiment.

[0036] Figure 3 is an equivalent circuit diagram of a pixel according to the embodiment.

[0037] Figure 4 is shown for describing Figure 3 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0038] Figure 5 , Figure 6 , Figure 7 and Figure 8 is a diagram schematically showing a connection relationship between a pixel and a second initialization voltage line according to an embodiment.

[0039] Fig. 9 is a diagram schematically showing a connection relationship between signal lines arranged in a display area according to an embodiment.

[0040] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 , Fig.18 and Fig.19 It is schematically shown layer by layer. Figure 3 Layout diagram of elements of a pixel.

[0041] Fig. 20 is along Fig.15 A cross-sectional view of a pixel taken along line II'.

[0042] Fig.21 is along Fig.15 Cross-sectional view of a pixel taken along line II-II' and line III-III'.

[0043] Fig. 22 is a diagram schematically showing an arrangement of emission regions of a plurality of pixels according to an embodiment.

[0044] Fig.23 is a diagram schematically showing a display device according to an embodiment.

[0045] Fig.24 is an equivalent circuit diagram of a pixel according to the embodiment.

[0046] Fig.25 is shown for describing Fig.24 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0047] Fig.26 , Fig. 27 , Fig.28 and Fig.29 is a diagram schematically showing a connection relationship between a pixel and a second initialization voltage line according to an embodiment.

[0048] Fig.30is a diagram schematically showing a connection relationship between signal lines arranged in a display area according to an embodiment.

[0049] Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 , Fig.36 , Fig.37 , Fig.38 and Fig.39 It is schematically shown layer by layer. Fig.24 Layout diagram of elements of a pixel.

[0050] Fig.40 is along Fig.36 A cross-sectional view of a pixel taken along line IV-IV'.

[0051] Fig.41 is along Fig.36 Cross-sectional view of a pixel taken along line V-V' and line VI-VI'.

[0052] Fig.42 is an equivalent circuit diagram of a pixel according to the embodiment.

[0053] Fig.43 is an equivalent circuit diagram of a pixel according to the embodiment.

[0054] Fig.44 is shown for describing Fig.43 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0055] Fig.45 is an equivalent circuit diagram of a pixel according to the embodiment.

[0056] Fig.46 is shown for describing Fig.45 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0057] Fig.47 is an equivalent circuit diagram of a pixel according to the embodiment.

[0058] Fig.48 is shown for describing Fig.47 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0059] Best Mode for Carrying Out the Invention

[0060] According to one or more embodiments, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a first transistor including a first gate and a second gate, a second transistor connected between the first gate of the first transistor and a data line, a third transistor connected between the first gate of the first transistor and a first voltage line, a fourth transistor connected between the first transistor and the second voltage line, a fifth transistor connected between the first transistor and the third voltage line, a sixth transistor connected between the first transistor and the fourth voltage line, a light emitting diode connected to the first transistor, a first capacitor connected between the first gate of the first transistor and the light emitting diode, and a second capacitor connected between the third voltage line and the light emitting diode. DETAILED DESCRIPTION

[0061] The present disclosure may include various embodiments and modifications, and some embodiments thereof are shown in the accompanying drawings and will be described in detail herein. The effects and features of the present disclosure and methods for implementing the same will become apparent through the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and may be implemented in various ways.

[0062] It will be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms and these terms are only used to distinguish one element from another.

[0063] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0064] Furthermore, it will be understood that the terms “comprising,” “including,” and “having” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0065] It will be understood that when a layer, region, area, component or element is referred to as being “on” another layer, region, area, component or element, it can be “directly on” the other layer, region, area, component or element or can be “indirectly on” the other layer, region, area, component or element via one or more intervening layers, regions, areas, components or elements.

[0066] For the convenience of description, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the elements in the drawings are arbitrarily shown for the convenience of description, the present disclosure is not limited thereto.

[0067] As used herein, "A and / or B" means the case of A, B, or A and B. In addition, "at least one of A and B" means the case of A, B, or A and B.

[0068] In the following embodiments, when X and Y are connected to each other, X and Y may be electrically connected to each other, X and Y may be functionally connected to each other, or X and Y may be directly connected to each other. Here, X and Y may be target objects (e.g., equipment, devices, circuits, wires, electrodes, terminals, conductive layers or layers). Therefore, the present disclosure is not limited to a specific connection relationship (e.g., a connection relationship indicated in the drawings or detailed description), and may also include any connection relationship other than the connection relationship indicated in the drawings or detailed description.

[0069] For example, when X and Y are electrically connected to each other, one or more devices (eg, switches, transistors, capacitors, inductors, resistors, or diodes) that implement electrical connection between X and Y may be connected between X and Y.

[0070] In the following embodiments, "ON" used with respect to a device state may indicate an activated state of the device, and "OFF" may indicate an inactivated state of the device. "ON" used with respect to a signal received by a device may indicate a signal that activates the device, and "OFF" may indicate a signal that inactivates the device. A device may be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) may be activated by a low level voltage, and an N-channel transistor (N-type transistor) may be activated by a high level voltage. Therefore, it should be understood that the "ON" voltage for a P-type transistor and an N-type transistor is an opposite (low and high) voltage level.

[0071] In the following embodiments, the meaning of a line “extending in the first direction or the second direction” may include not only extending in a straight line shape in the first direction or the second direction but also extending in a zigzag or bent shape.

[0072] In the following embodiments, when referred to as "in a plan view", it may mean observing the target portion from above, and when referred to as "in a cross-sectional view", it may mean observing the cross section of the target portion cut vertically from the side. In the following embodiments, when referred to as "overlapping", it may include overlapping "in a plan view" and overlapping "in a cross-sectional view".

[0073] Moreover, in this article, the x direction, y direction and z direction are not limited to the directions along the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x direction, y direction and z direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0074] When a specific embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially at the same time, or can be performed in the reverse order of the described order.

[0075] In the detailed description of the present disclosure and the appended claims, depending on the context, the term "corresponding" can be used to specify elements arranged in the same region among multiple elements. For example, when a first element "corresponds" to a second element, it may mean that the second element is arranged in the same region as the first element.

[0076] The display device according to the embodiment can be implemented as an electronic device such as a smart phone, a mobile phone, a smart watch, a navigation device, a game console, a television (TV), a vehicle head unit, a notebook computer, a laptop computer, a tablet computer, a personal media player (PMP) or a personal digital assistant (PDA). In addition, the electronic device can be a flexible device.

[0077] Figure 1a , Figure 1b and Figure 2 is a diagram schematically showing a display device according to an embodiment.

[0078] Reference Figure 1a , the display device 10 may include a display area DA displaying an image and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0079] In a plan view, the display area DA may have a rectangular shape. In other embodiments, the display area DA may have a polygonal shape such as a triangular shape, a pentagonal shape, or a hexagonal shape, a circular shape, an elliptical shape, an atypical shape, or the like. The corners of the edges of the display area DA may have a rounded shape. In an embodiment, as shown in FIG. Figure 1a As shown in , the display device 10 may include a display area DA having a shape in which the length in the x direction is greater than the length in the y direction. Figure 1b As shown in , the display device 10 may include a display area DA having a shape in which a length in the y direction is greater than a length in the x direction.

[0080] Reference Figure 2 The display device 10 a according to the embodiment may include a pixel unit 11 , a gate driving circuit 13 , a data driving circuit 15 , a power supply circuit 17 , and a controller 19 .

[0081] The pixel unit 11 may be provided in the display area DA. Various conductive lines for transmitting electrical signals to the display area DA, peripheral circuits electrically connected to the pixel circuits, and / or pads configured to be connected to the printed circuit board or driver IC chip may be located in the peripheral area PA. For example, the gate drive circuit 13, the data drive circuit 15, the power supply circuit 17, and the controller 19 may be provided in the peripheral area PA.

[0082] like Figure 2As shown in , a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected to the plurality of gate lines GL and the plurality of data lines DL may be arranged in the display area DA. The plurality of pixels PX may be arranged in various forms such as strip arrangement, pentile arrangement (diamond arrangement), and mosaic arrangement to realize an image. Each pixel PX may include an organic light emitting diode OLED as a display element (light emitting element), and the organic light emitting diode OLED may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel PX may emit, for example, red light, green light, blue light, or white light from the organic light emitting diode OLED. Each pixel PX may be connected to at least one corresponding gate line among the plurality of gate lines GL and a corresponding data line among the plurality of data lines DL.

[0083] Each of the gate lines GL may extend in the x direction (row direction) to be connected to the pixels PX positioned in the same row. Each of the gate lines GL may be configured to transmit a gate signal to the pixels PX positioned in the same row. Each of the data lines DL may extend in the y direction (column direction) to be connected to the pixels PX positioned in the same column. Each of the data lines DL may be configured to transmit a data signal to each of the pixels PX positioned in the same column in synchronization with the gate signal.

[0084] In an embodiment, the peripheral area PA may be a non-display area in which the pixels PX are not arranged. In another embodiment, a plurality of pixels PX may be arranged to overlap the gate driving circuit 13. Accordingly, the dead zone may be reduced and the display area DA may be expanded.

[0085] The gate driving circuit 13 may be connected to a plurality of gate lines GL, may generate a gate signal in response to a gate control signal GCS from the controller 19, and may sequentially supply the gate signal to the gate lines GL. The gate line GL may be connected to the gate of a transistor included in the pixel PX. The gate signal may be a gate control signal for controlling the turning on and off of a transistor whose gate is connected to the gate line GL. The gate signal may be a square wave signal including an on-voltage at which the transistor may be turned on and an off-voltage at which the transistor may be turned off. In an embodiment, the on-voltage may be a high level voltage (a first level voltage) or a low level voltage (a second level voltage).

[0086] Figure 2It is shown that the pixel PX is connected to one gate line GL; however, this is only an example, and the pixel PX may be connected to two or more gate lines, and the gate drive circuit 13 may supply two or more gate signals with different timings to the two or more gate lines when applying the on voltage. For example, the pixel PX may be connected to the first gate line to the fourth gate line and the emission control line, and the gate drive circuit 13 may apply the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal GB and the emission control signal EM to the first gate line, the second gate line, the third gate line, the fourth gate line and the emission control line, respectively. The emission control signal EM may be a gate control signal for controlling the on and off of a transistor whose gate is connected to the emission control line.

[0087] The data driving circuit 15 may be connected to a plurality of data lines DL, and may supply data signals to the data lines DL in response to a data control signal DCS from the controller 19. The data signals supplied from the data lines DL may be supplied to the pixels PX to which the gate signals are supplied. The data driving circuit 15 may convert input image data having grayscales input from the controller 19 into data signals in the form of voltage or current.

[0088] The power supply circuit 17 may generate a voltage required for driving the pixel PX in response to a power control signal PCS from the controller 19. The power supply circuit 170 may generate a first driving voltage ELVDD and a second driving voltage ELVSS, and supply them to the pixel PX. The first driving voltage ELVDD may be a high-level voltage provided to a first electrode (pixel electrode or anode) of a display element included in the pixel PX. The second driving voltage ELVSS may be a low-level voltage provided to a second electrode (opposite electrode or cathode) of a display element included in the pixel PX. The power supply circuit 17 may generate a reference voltage Vref, a first initialization voltage Vint, and a second initialization voltage Vaint, and supply them to the pixel PX.

[0089] The voltage level of the first driving voltage ELVDD may be higher than the voltage level of the second driving voltage ELVSS. The voltage level of the reference voltage Vref may be lower than the voltage level of the first driving voltage ELVDD. The voltage level of the first initialization voltage Vint may be lower than the voltage level of the second driving voltage ELVSS.

[0090] The voltage level of the second initialization voltage Vaint may be higher than the voltage level of the first initialization voltage Vint. The voltage level of the second initialization voltage Vaint may be equal to or higher than the voltage level of the second driving voltage ELVSS.

[0091] The controller 19 may generate control signals GCS, DCS, and PCS based on signals input from the outside, and supply them to the gate driving circuit 13, the data driving circuit 15, and the power supply circuit 17, respectively. The gate control signal GCS output to the gate driving circuit 13 may include a plurality of clock signals and a gate start signal. The data control signal DCS output to the data driving circuit 15 may include a source start signal and a clock signal.

[0092] The display device 10a may include a display panel, and the display panel may include a substrate. The pixel PX may be arranged in a display area DA on the substrate. Some or all of the gate drive circuit 13 may be directly formed in the peripheral area PA on the substrate during the process of forming the transistors constituting the pixel circuit in the display area DA on the substrate. Each of the data drive circuit 15, the power supply circuit 17 and the controller 19 may be formed in the form of a separate integrated circuit chip or a single integrated circuit chip, and is arranged on a flexible printed circuit board (FPCB) electrically connected to a pad arranged on one side of the substrate. In other embodiments, the data drive circuit 15, the power supply circuit 17 and the controller 19 may be directly arranged on the substrate by using a chip on glass (COG) method or a chip on plastic (COP) method.

[0093] In an embodiment, a plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors. In another embodiment, a plurality of transistors included in the pixel circuit may be P-type silicon thin film transistors. In another embodiment, some of the plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors, and the other transistors may be P-type silicon thin film transistors.

[0094] The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which the active pattern (semiconductor layer) includes an oxide. However, this is only an example, and the N-type transistor is not limited thereto. For example, the active pattern (semiconductor layer) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor. The silicon thin film transistor may be a low temperature polycrystalline silicon (LTPS) thin film transistor in which the active pattern (semiconductor layer) includes amorphous silicon, polycrystalline silicon, or the like.

[0095] The display device 10a may support a variable refresh rate (VRR). The refresh rate may be the frequency at which the data signal is actually written into the driving transistor of the pixel PX, and may also be referred to as a screen scan rate or a screen refresh rate, and may represent the number of image frames played per second. In an embodiment, the refresh rate may be the output frequency of the gate drive circuit 13 and / or the data drive circuit 15. The frequency corresponding to the refresh rate may be the driving frequency. The display device 10a may adjust the output frequency of the gate drive circuit 13 and the output frequency of the data drive circuit 15 corresponding thereto according to the driving frequency. The display device 10a supporting a variable refresh rate (VRR) may be operated by changing the driving frequency within the range of the maximum driving frequency and the minimum driving frequency. For example, when the refresh rate is about 60 Hz, a gate signal for writing a data signal may be supplied from the gate drive circuit 13 to each horizontal line (row) 60 times per second. The display device 10a may display an image while changing the driving frequency according to the refresh rate.

[0096] When the maximum driving frequency of the display device 10a is referred to as the first driving frequency, and the driving frequency lower than the maximum driving frequency is referred to as the second driving frequency, the display device 10a can be operated at the second driving frequency to reduce power consumption. For example, when no operation control signal (e.g., a signal input from a keyboard) is input for a certain time, when a still image is displayed, when it is driven in a standby mode, or the like, the display device 10a can be driven at a low speed by operating at the second driving frequency.

[0097] Figure 3 is an equivalent circuit diagram of a pixel according to the embodiment. Figure 4 is shown for describing Figure 3 ] is a waveform diagram of signals for pixel operation shown in FIG. Figure 3 The pixel PXa shown in FIG. 1 may be Figure 2 An embodiment of a pixel PX is shown in FIG.

[0098] Reference Figure 3, the pixel PXa may include an organic light emitting diode OLED as a display element and a pixel circuit PC connected to the organic light emitting diode OLED. The pixel circuit PC may include a first transistor T1 to a sixth transistor T6 and a first capacitor C1 and a second capacitor C2. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal, and the second transistor T2 to the sixth transistor T6 may be a switching transistor configured to transmit a signal. The first terminal (first electrode) of each of the first transistor T1 to the sixth transistor T6 may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, when the first terminal is a drain, the second terminal may be a source. The node to which the first gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0099] The pixel PXa may be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fourth gate line GBL configured to transmit a fourth gate signal GB, an emission control line EML configured to transmit an emission control signal EM, and a data line DL configured to transmit a data signal Vdata. Furthermore, the pixel PXa may be connected to a driving voltage line PL configured to transmit a first driving voltage ELVDD, a first initialization voltage line VL1 configured to transmit a first initialization voltage Vint, a second initialization voltage line VL2 configured to transmit a second initialization voltage Vaint, and a reference voltage line VRL configured to transmit a reference voltage Vref.

[0100] The first transistor T1 may be connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the second node N2. The gate of the first transistor T1 may include a first gate connected to the first node N1 and a second gate connected to the second node N2. The first gate and the second gate may be arranged on different layers to face each other. For example, the first gate and the second gate of the first transistor T1 may be positioned to face each other across the semiconductor layer. The first terminal of the first transistor T1 may be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal thereof may be connected to the pixel electrode of the organic light emitting diode OLED. The first transistor T1 may receive a data signal Vdata to control the amount of driving current flowing through the organic light emitting diode OLED according to the switching operation of the second transistor T2.

[0101] The second transistor T2 may be connected between the first gate of the first transistor T1 and the data line DL. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second transistor T2 may be turned on by a first gate signal GW received through the first gate line GWL to electrically connect the data line DL with the first node N1, and transmit a data signal Vdata received through the data line DL to the first node N1.

[0102] The third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The third transistor T3 may be turned on by a third gate signal GR received through the third gate line GRL to transmit the reference voltage Vref received through the reference voltage line VRL to the first node N1.

[0103] The fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1. The fourth transistor T4 may be turned on by a second gate signal GI received through the second gate line GIL to transmit the first initialization voltage Vint received through the first initialization voltage line VL1 to the second node N2.

[0104] The fifth transistor T5 may be connected between the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the emission control line EML, a first terminal connected to the driving voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off according to an emission control signal EM received through the emission control line EML.

[0105] The sixth transistor T6 may be connected between the first transistor T1 and the second initialization voltage line VL2. The sixth transistor T6 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2. The sixth transistor T6 may be turned on by a fourth gate signal GB received through the fourth gate line GBL to transmit the second initialization voltage Vaint received through the second initialization voltage line VL2 to the second node N2.

[0106] The first capacitor C1 may be connected between the first gate electrode of the first transistor T1 and the organic light emitting diode OLED. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode thereof may be connected to the second node N2. The first capacitor C1 may be a storage capacitor, and may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal.

[0107] The second capacitor C2 may be connected between the driving voltage line PL and the organic light emitting diode OLED. A first electrode of the second capacitor C2 may be connected to the driving voltage line PL, and a second electrode thereof may be connected to the second node N2. The capacitance of the first capacitor C1 may be greater than that of the second capacitor C2.

[0108] The organic light emitting diode OLED may be connected to the first transistor T1. The organic light emitting diode OLED may include a pixel electrode (anode) connected to the second node N2 and an opposing electrode (cathode) facing the pixel electrode. The opposing electrode may receive a second driving voltage ELVSS. The opposing electrode may be a common electrode commonly connected to a plurality of pixels PX.

[0109] The pixel PXa can display an image in each frame period. Figure 4 One frame period may include a non-emission period NEP in which the pixel PXa does not emit light and an emission period EP in which the pixel PXa emits light. The non-emission period NEP may include a first initialization period P1, a compensation period P2, a writing period P3, and a second initialization period P4.

[0110] Each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal GB, and the emission control signal EM may have a high level voltage during some periods, and may have a low level voltage during some periods. Here, the high level voltage may be a turn-on voltage for turning on the transistor, and the low level voltage may be a turn-off voltage for turning off the transistor.

[0111] In the first initialization period P1, the second gate signal GI of the turn-on voltage may be supplied to the second gate line GIL, and the third gate signal GR of the turn-on voltage may be supplied to the third gate line GRL. The first gate signal GW, the fourth gate signal GB, and the emission control signal EM may supply the turn-off voltage. The fourth transistor T4 may be turned on by the second gate signal GI, and the third transistor T3 may be turned on by the third gate signal GR. The first node N1 (which is connected to the first gate of the first transistor T1) may be initialized to the reference voltage Vref by the turned-on third transistor T3. The second node N2 (which is connected to the pixel electrode of the organic light emitting diode OLED) may be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4.

[0112] In the compensation period P2, the third gate signal GR of the turn-on voltage may be supplied to the third gate line GRL, and the emission control signal EM of the turn-on voltage may be supplied to the emission control line EML. The first gate signal GW, the second gate signal GI, and the fourth gate signal GB may supply the turn-off voltage. The second transistor T2, the fourth transistor T4, and the sixth transistor T6 may be turned off by the first gate signal GW, the second gate signal GI, and the fourth gate signal GB. The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the emission control signal EM. Accordingly, the reference voltage Vref may be supplied to the first node N1, and the first driving voltage ELVDD may be supplied to the first terminal of the first transistor T1, and thus the first transistor T1 may be turned on. When the voltage of the second terminal of the first transistor T1 changes to the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 may be turned off. Also, a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be stored in the first capacitor C1 to compensate for the threshold voltage (Vth) of the first transistor T1.

[0113] In the writing period P3, the first gate signal GW of the turn-on voltage may be supplied to the first gate line GWL to turn on the second transistor T2. In this case, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be turned off by the second gate signal GI of the turn-off voltage, the third gate signal GR, the fourth gate signal GB, and the emission control signal EM. The second transistor T2 may be configured to transmit the data signal Vdata from the data line DL to the first node N1 (which is connected to the first gate of the first transistor T1). Accordingly, the voltage of the first node N1 may be changed from the reference voltage Vref to a voltage corresponding to the data signal Vdata. In this case, the voltage of the second node N2 may also change corresponding to the amount of change in the voltage of the first node N1. The voltage of the second node N2 may be a voltage (Vref-Vth+α×(Vdata-Vref)) that changes according to the capacitance ratio (α=C1 / (C1+C2)) of the first capacitor C1 to the second capacitor C2. Accordingly, the gate-source voltage (Vgs) of the first transistor T1 (ie, the voltage between the first node N1 and the second node N2) can be expressed as the following equation (1).

[0114] Vgs=(1-α)×(Vdata-Vref)+Vth

[0115] ={(C2 / (C1+C2)}(Vdata-Vref)+Vth...(1)

[0116] In the second initialization period P4, the fourth gate signal GB of the turn-on voltage may be supplied to the fourth gate line GBL. The first gate signal GW, the second gate signal GI, the third gate signal GR, and the emission control signal EM may supply the turn-off voltage. The sixth transistor T6 may be turned on by the fourth gate signal GB, and thus the second node N2 (which is connected to the pixel electrode of the organic light emitting diode OLED) may be initialized to the second initialization voltage Vaint. In this case, the gate-source voltage (Vgs) of the first transistor T1 may be expressed as the following formula (2).

[0117] Vgs=(1-α)×(Vdata-Vref)+Vth

[0118] ={(C2 / (C1+C2)}(Vdata-Vref)+Vth-Vaint...(2)

[0119] Due to the voltage remaining in the organic light emitting diode OLED, brightness changes may occur, and such brightness changes may be highly visible in the case of high temperature and low grayscale display. For example, an organic light emitting diode OLED that displays black in black grayscale may emit light with a brightness higher than the black brightness. The embodiment can effectively prevent the micro-luminescence phenomenon of the pixel PXa by initializing the organic light emitting diode OLED through the sixth transistor T6 before the emission period EP using the second initialization voltage Vaint. Accordingly, by minimizing the brightness change of the organic light emitting diode OLED under high temperature and low grayscale, the image quality can be further improved.

[0120] In addition, the afterimage (color drag) phenomenon of the previous image that occurs when displaying an image may be caused by the hysteresis characteristics of the driving transistor, and the threshold voltage of the driving transistor may be offset due to the hysteresis characteristics. The embodiment can control the gate-source voltage (Vgs) of the first transistor T1 by supplying a second initialization voltage Vaint higher than the first initialization voltage Vint to the source (second terminal) of the first transistor T1 in the second initialization period P4 located before the emission period EP, thereby preventing the shift of the threshold voltage of the first transistor T1. Accordingly, the brightness deviation caused by the shift of the threshold voltage of the first transistor T1 and the brightness deviation caused by the degradation of the organic light emitting diode OLED can be minimized.

[0121] In the emission period EP, the emission control signal EM may be turned into a turn-on voltage, and the first gate signal GW, the second gate signal GI, the third gate signal GR, and the fourth gate signal GB may be a turn-off voltage. The second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 may be turned off by the first gate signal GW, the second gate signal GI, the third gate signal GR, and the fourth gate signal GB, and the fifth transistor T5 may be turned on by the emission control signal EM, and thus the first driving voltage ELVDD may be supplied to the first terminal of the first transistor T1.

[0122] The first transistor T1 may output a driving current (Id∝(Vgs-Vth)) having a magnitude corresponding to the voltage stored in the first capacitor C1 (i.e., a voltage (Vgs-Vth) obtained by subtracting a threshold voltage (Vth) of the first transistor T1 from a gate-source voltage (Vgs) of the first transistor T1). 2 ), and the organic light emitting diode OLED can emit light having brightness corresponding to a magnitude of the driving current regardless of the threshold voltage (Vth) of the first transistor T1.

[0123] As a comparative example, in the case where the sixth transistor T6 is Figure 3 In a display device in which a pixel is omitted from a pixel circuit of the display device, the second initialization period P4 may be omitted, and one frame period may include a first initialization period P1, a compensation period P2, a writing period P3, and an emission period EP. In addition, by increasing the first initialization voltage Vint, the brightness deviation between high-speed driving (e.g., 120 Hz driving) and low-speed driving (e.g., 1 Hz driving) may be reduced. However, the increase in the first initialization voltage Vint may reduce the gate-source voltage (Vgs) of the first transistor T1 in the compensation period P2, thereby hindering the threshold voltage compensation. As a result, stains in the image may increase due to insufficient threshold voltage compensation.

[0124] The embodiment can separate the initialization before the compensation period P2 and the initialization after the compensation period P2 by using the fourth transistor T4 connected between the second node N2 and the first initialization voltage line VL1 and the sixth transistor T6 connected between the second node N2 and the second initialization voltage line VL2. By applying the first initialization voltage Vint to the second node N2 and the reference voltage Vref to the first node N1 in the first initialization period P1 before the compensation period P2, the gate initialization and threshold voltage compensation of the first transistor T1 can be ensured. In addition, by initializing the second node N2 to the second initialization voltage Vaint higher than the first initialization voltage Vint in the second initialization period P4 after the compensation period P2, the initialization of the organic light emitting diode OLED and the brightness deviation between high-speed driving and low-speed driving can be minimized.

[0125] Embodiments can reduce brightness deviation due to temperature brightness shift, threshold voltage shift of transistors, and degradation of organic light emitting diodes by respectively utilizing a first initialization voltage Vint used in the first initialization period P1 and a second initialization voltage Vaint used in the second initialization period P4 .

[0126] Figures 5 to 8 is a diagram schematically illustrating connection between a pixel and a second initialization voltage line according to an embodiment.

[0127] The plurality of pixels PX may include a first pixel PX1 emitting light of a first color, a second pixel PX2 emitting light of a second color, and a third pixel PX3 emitting light of a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. In an embodiment, by considering the light emitting characteristics of the first pixel PX1, the second pixel PX2, and the third pixel PX3, different second initialization voltages Vaint may be supplied to the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0128] For example, Figure 5 As shown in , the first pixel PX1 and the third pixel PX3 may be connected to the 2-1st initialization voltage line VL21 for supplying the 2-1st initialization voltage Vaint1, and the second pixel PX2 may be connected to the 2-2nd initialization voltage line VL22 for supplying the 2-2nd initialization voltage Vaint2. Alternatively, as Figure 6 As shown in , the first pixel PX1 may be connected to the 2-1st initialization voltage line VL21 for supplying the 2-1st initialization voltage Vaint1, and the second pixel PX2 and the third pixel PX3 may be connected to the 2-2nd initialization voltage line VL22 for supplying the 2-2nd initialization voltage Vaint2. Alternatively, as Figure 7 As shown in , the first pixel PX1 and the second pixel PX2 may be connected to the 2-1st initialization voltage line VL21 for supplying the 2-1st initialization voltage Vaint1, and the third pixel PX3 may be connected to the 2-2nd initialization voltage line VL22 for supplying the 2-2nd initialization voltage Vaint2. Alternatively, as Figure 8 As shown in , the first pixel PX1 can be connected to the 2-1st initialization voltage line VL21 for supplying the 2-1st initialization voltage Vaint1, the second pixel PX2 can be connected to the 2-2nd initialization voltage line VL22 for supplying the 2-2nd initialization voltage Vaint2, and the third pixel PX3 can be connected to the 2-3rd initialization voltage line VL23 for supplying the 2-3rd initialization voltage Vaint3.

[0129] By respectively providing a second initialization voltage line VL2 connected to at least one of the first pixel PX1, the second pixel PX2 and the third pixel PX3 and supplying a different second initialization voltage Vaint to each second initialization voltage line VL2, the embodiment can improve the low grayscale brightness variation and color variation problems caused by the difference in characteristics of the organic light emitting diode OLED.

[0130] Although not shown, it looks like Figures 5 to 8 Similarly, by considering the light-emitting characteristics of the first pixel PX1, the second pixel PX2 and the third pixel PX3, the embodiment may respectively provide a first initialization voltage line VL1 connected to at least one of the first pixel PX1, the second pixel PX2 and the third pixel PX3 and supply a different initialization voltage Vint to each first initialization voltage line VL1.

[0131] In the following, we will base on Figure 5 Description will be given of an embodiment shown in FIG. 1 in which the first pixel PX1 and the third pixel PX3 are connected to the 2-1st initialization voltage line VL21 and the second pixel PX2 is connected to the 2-2nd initialization voltage line VL22 .

[0132] Fig. 9 is a diagram schematically illustrating connections between signal lines arranged in the display area DA according to an embodiment.

[0133] like Fig. 9As shown in , a plurality of unit pixel areas PCAu may be defined in the display area DA. The unit pixel area PCAu may include two or more pixel areas, and each pixel area may be an area where a row (R) and a column (M) intersect each other and may be an area where a pixel circuit is arranged. In an embodiment, the unit pixel area PCAu may include three pixel areas. The unit pixel area PCAu may include a first pixel area PCA1, a second pixel area PCA2, and a third pixel area PCA3 that are adjacent to each other in the x direction. For example, the first pixel area PCA1 may be an area where a pixel circuit of a first pixel PX1 is arranged. The second pixel area PCA2 may be an area where a pixel circuit of a second pixel PX2 is arranged. The third pixel area PCA3 may be an area where a pixel circuit of a third pixel PX3 is arranged.

[0134] Transverse conductive lines HCL extending in the x-direction and longitudinal conductive lines VCL extending in the y-direction may be arranged in the display area DA.

[0135] The transverse conductive line HCL may include a reference voltage line VRL, a driving voltage line PL, a first initialization voltage line VL1, and a second initialization voltage line VL2. The second initialization voltage line VL2 may include a 2-1st initialization voltage line VL21 and a 2-2nd initialization voltage line VL22. The reference voltage line VRL, the driving voltage line PL, the first initialization voltage line VL1, the 2-1st initialization voltage line VL21, and the 2-2nd initialization voltage line VL22 may be arranged in each row.

[0136] The vertical conductive line VCL may include a vertical reference voltage line VRLv, a vertical driving voltage line PLv, a first vertical initialization voltage line VL1v and a second vertical initialization voltage line VL2v. The second vertical initialization voltage line VL2v may include a 2-1st vertical initialization voltage line VL21v and a 2-2nd vertical initialization voltage line VL22v.

[0137] The reference voltage line VRL may be electrically connected to the longitudinal reference voltage line VRLv through the contact hole CH1 to form a grid structure in the display area DA. The driving voltage line PL may be electrically connected to the longitudinal driving voltage line PLv through the contact hole CH2 to form a grid structure in the display area DA. The first initialization voltage line VL1 may be electrically connected to the first longitudinal initialization voltage line VL1v through the contact hole CH3 to form a grid structure in the display area DA. The 2-1st initialization voltage line VL21 may be electrically connected to the 2-1st longitudinal initialization voltage line VL21v through the contact hole CH4 to form a grid structure in the display area DA. The 2-2nd initialization voltage line VL22 may be electrically connected to the 2-2nd longitudinal initialization voltage line VL22v through the contact hole CH5 to form a grid structure in the display area DA.

[0138] In the display area DA, a common voltage line EL may also be arranged as one of the longitudinal conductive lines VCL. The common voltage line EL may be electrically connected to the common voltage supply line EPL arranged in the peripheral area PA through the contact hole CH6. In an embodiment, the counter electrode may be electrically connected to the common voltage line EL at a specific interval in the display area DA.

[0139] Although not shown, a voltage supply line electrically connected to the horizontal conductive line HCL and / or the vertical conductive line VCL may be further disposed in the peripheral area PA. The voltage supply line may be disposed on at least one of the upper side, lower side, left side, and right side of the display area PA.

[0140] Each of the longitudinal conductive lines VCL may be arranged at a specific interval between adjacent pairs of pixel regions in the x direction. The longitudinal conductive lines VCL may include a first longitudinal conductive line VCL1 and a second longitudinal conductive line VCL2. The first longitudinal conductive line VCL1 may include a longitudinal driving voltage line PLv and a common voltage line EL. The second longitudinal conductive line VCL2 may include a longitudinal reference voltage line VRLv, a first longitudinal initialization voltage line VL1v, a 2-1st longitudinal initialization voltage line VL21v, and a 2-2nd longitudinal initialization voltage line VL22v.

[0141] One of the first longitudinal conductive lines VCL1 and one of the second longitudinal conductive lines VCL2 may be arranged in the unit pixel area PCAu.

[0142] The longitudinal driving voltage lines PLv and the common voltage lines EL may be arranged alternately at intervals of the unit pixel areas PCAu (i.e., at intervals of three pixel areas or three columns) in the x direction. The longitudinal driving voltage lines PLv may be arranged at intervals of two unit pixel areas PCAu (i.e., at intervals of six pixel areas or six columns) in the x direction. The common voltage lines EL may be arranged at intervals of two unit pixel areas PCAu (i.e., at intervals of six pixel areas or six columns) in the x direction.

[0143] The longitudinal reference voltage line VRLv, the first longitudinal initialization voltage line VL1v, the 2-1st longitudinal initialization voltage line VL21v, and the 2-2nd longitudinal initialization voltage line VL22v may be arranged alternately at intervals of the unit pixel area PCAu (i.e., at intervals of three pixel areas or three columns) in the x direction. The longitudinal reference voltage line VRLv may be arranged at intervals of four unit pixel areas PCAu (i.e., at intervals of 12 pixel areas or 12 columns) in the x direction. The 2-1st longitudinal initialization voltage line VL21v may be arranged at intervals of four unit pixel areas PCAu (i.e., at intervals of 12 pixel areas or 12 columns) in the x direction. The first longitudinal initialization voltage line VL1v may be arranged at intervals of four unit pixel areas PCAu (i.e., at intervals of 12 pixel areas or 12 columns) in the x direction. The 2-2 th longitudinal initialization voltage line VL22v may be arranged at intervals of four unit pixel areas PCAu (ie, at intervals of 12 pixel areas or 12 columns) in the x direction.

[0144] In an embodiment, the longitudinal conductive lines VCL may be arranged in different layers from the transverse conductive lines HCL. Some of the transverse conductive lines HCL may be arranged in the same layer, and others may be arranged in different layers. The longitudinal conductive lines VCL may be arranged in the same layer.

[0145] Figures 10 to 19 It is schematically shown layer by layer. Figure 3 Layout diagram of elements of a pixel. Fig.14 is shown as Fig.13 FIG. 1 is a plan view of an element of a portion of the first pixel area PCA1. Fig. 20 is along Fig.15 A cross-sectional view of a pixel taken along line II', in which a display element is provided. Fig.21 is along Fig.15 sectional views of a pixel taken along lines II-II' and III-III', in which a display element is disposed. Fig. 20 and Fig.21 Similar to Figures 16 to 18 corresponding area.

[0146] The display area DA defined at the substrate 100 may include a plurality of pixel areas. Each of the pixel areas may be an area where rows and columns intersect each other and a pixel circuit is arranged. The same element may be arranged on each layer of the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3, which are three areas adjacent to each other in the x direction. The same element may be arranged on each layer of the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3 except for the intermediate layer located in the organic light emitting diode OLED. For the convenience of illustration, reference numerals are given to the elements of the pixel circuit arranged in the first pixel area PCA1. Fig. 20 and Fig.21 The cross-sectional view of is a cross-sectional view of the second pixel area PCA2. Figures 10 to 21 Give a description.

[0147] The pixel circuits arranged in the first pixel area PCA1 and the pixel circuits arranged in the second pixel area PCA2 may be symmetrical to each other with respect to a boundary line IBL1 disposed between the first pixel area PCA1 and the second pixel area PCA2. The pixel circuits arranged in the second pixel area PCA2 and the pixel circuits arranged in the third pixel area PCA3 may be symmetrical with respect to a boundary line IBL2 disposed between the second pixel area PCA2 and the third pixel area PCA3.

[0148] The substrate 100 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. The substrate 100 may include a single-layer structure of an organic layer or a multi-layer structure of an organic layer and an inorganic layer. For example, the substrate 100 may include a stacked structure of a first base layer / barrier layer / second base layer. Each of the first base layer and the second base layer may include an organic layer including a polymer resin. The first base layer and the second base layer may include a transparent polymer resin. The barrier layer may prevent penetration of external foreign matter and may include a layer including a silicon nitride (SiN x ) or silicon oxide (SiO x ) of a single layer or multiple layers of inorganic material.

[0149] Reference Fig.10 , the first conductive layer may be disposed on the substrate 100. The first conductive layer may include a reference voltage line VRL, a second gate electrode G12 of the first transistor T1, a driving voltage line PL, and a 2-1st initialization voltage line VL21. In another embodiment, a barrier layer may be further disposed between the substrate 100 and the first conductive layer. In another embodiment, the barrier layer may include a lower barrier layer and an upper barrier layer, and the first conductive layer may be disposed between the lower barrier layer and the upper barrier layer.

[0150] The reference voltage line VRL, the driving voltage line PL, and the 2-1st initialization voltage line VL21 may extend in the x direction and may be arranged in the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3. The driving voltage line PL may include a protruding portion PLp protruding from a main line extending in the x direction and extending in the y direction in each pixel area.

[0151] The second gate electrode G12 as the lower gate electrode (bottom gate electrode) of the first transistor T1 may be provided as an island (isolated) type. The second gate electrode G12 of the first transistor T1 may include a protruding portion G12p. The second gate electrode G12 of the first transistor T1 may be a first capacitor C1 (see Fig. 20 )'s second electrode, the lower electrode C13.

[0152] In an embodiment, the first conductive layer may further include a repair line RL The repair line RL may extend in the x-direction and may be arranged in the first pixel area PCA1 , the second pixel area PCA2 , and the third pixel area PCA3 .

[0153] The buffer layer 110 may be disposed on the first conductive layer, and the semiconductor layer ACT may be disposed on the buffer layer 110. The semiconductor layer ACT may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material such as an oxide semiconductor. Fig.11 As shown in , the semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, a third semiconductor layer ACT3, and a fourth semiconductor layer ACT4. The semiconductor layer ACT may include a channel region of each of the first transistor T1 to the sixth transistor T6 and a source region and a drain region disposed on both sides of the channel region. In some cases, the source region or the drain region may be interpreted as a source electrode or a drain electrode of the transistor.

[0154] Reference Fig.14 , the first semiconductor layer ACT1 may include the source region S1 and the drain region D1 of the first transistor T1 and the source region S5 and the drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and the drain region D2 of the second transistor T2 and the source region S3 and the drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S4 and the drain region D4 of the fourth transistor T4. The fourth semiconductor layer ACT4 may include the source region S6 and the drain region D6 of the sixth transistor T6.

[0155] The channel regions of the first transistor T1 in the first and third pixel regions PCA1 and PCA3 may have a straight line shape, and the channel region of the first transistor T1 in the second pixel region PCA2 may have a meandering shape including a slit portion.

[0156] The second semiconductor layers ACT2 of the two pixel regions may be connected to each other. For example, the second semiconductor layers ACT2 of the first pixel region PCA1 and the second pixel region PCA2 may be connected to each other.

[0157] The first insulating layer 111 may be disposed on the semiconductor layer ACT, and the second conductive layer may be disposed on the first insulating layer 111. Fig.12 As shown in , the second conductive layer may include gate electrodes G1 to G6 of the first to sixth transistors T1 to T6. Also, the second conductive layer may include first to second gate lines GWL, GIL, GRL, GBL, and an emission control line EML.

[0158] The first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line GBL, and the emission control line EML may extend in the x-direction and may be arranged in the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3.

[0159] The gate electrodes G1 to G6 of the first to sixth transistors T1 to T6 may overlap with a channel region of the semiconductor layer ACT.

[0160] Reference Fig.14 , the first gate electrode G11 of the first transistor T1 as an upper gate electrode (top gate electrode) may be provided as an island type. The first gate electrode G11 of the first transistor T1 may overlap with the first semiconductor layer ACT1. The first gate electrode G11 of the first transistor T1 may overlap with the second gate electrode G12. The first gate electrode G11 of the first transistor T1 may be the first electrode C11 of the first capacitor C1. The gate electrode G2 of the second transistor T2 may be a portion of the first gate line GWL intersecting (overlapping) with the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be a portion of the third gate line GRL intersecting (overlapping) with the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be a portion of the second gate line GIL intersecting (overlapping) with the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 may be a portion of the emission control line EML intersecting (overlapping) with the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 may be a portion of the fourth gate line GBL intersecting (overlapping) with the fourth semiconductor layer ACT4.

[0161] The second insulating layer 112 may be disposed on the first insulating layer 111 to cover the second conductive layer, and the third conductive layer may be disposed on the second insulating layer 112. Fig.13 As shown in , the third conductive layer may include an upper electrode C12 of the second electrode of the first capacitor C1, a first initialization voltage line VL1, and a 2-2nd initialization voltage line VL22.

[0162] The upper electrode C12 of the second electrode of the first capacitor C1 may be provided as an island type. The upper electrode C12 of the second electrode of the first capacitor C1 may overlap with the lower electrode C13 of the second electrode of the first capacitor C1 and the first electrode C11 and cover the lower electrode C13 of the second electrode of the first capacitor C1 and the first electrode C11. An open SOP may be formed in the upper electrode C12 of the second electrode of the first capacitor C1. The first capacitor C1 may include the lower electrode C13 of the second electrode, the first electrode C11, and the upper electrode C12 of the second electrode, and may overlap with the first transistor T1.

[0163] The first initialization voltage line VL1 and the 2-2nd initialization voltage line VL22 may extend in the x-direction and may be arranged in the first, second, and third pixel areas PCA1, PCA2, and PCA3.

[0164] The third insulating layer 113 may be disposed on the second insulating layer 112 to cover the third conductive layer, and the fourth conductive layer may be disposed on the third insulating layer 113. Figures 15 to 18 As shown in , the fourth conductive layer may include a data line DL, a first node electrode 131, a second node electrode 132, conductive patterns 133, 134, 135, 136a, 136b, and 137, and a longitudinal conductive line VCL.

[0165] The conductive pattern 136a may be provided in at least one of the pixel regions in the unit pixel region PCAu (e.g., the first pixel region PCA1 and the third pixel region PCA3). The conductive pattern 136b may be provided in at least one of the pixel regions in the unit pixel region PCAu (e.g., the second pixel region PCA2). The conductive pattern 137 may be provided in at least one of the pixel regions in the unit pixel region PCAu (e.g., the first pixel region PCA1).

[0166] The data line DL may be arranged in each pixel region to extend in the y direction and may be electrically connected to the drain region D2 of the second transistor T2 via a contact hole 31 formed through the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 .

[0167] The first node electrode 131 may electrically connect the first gate electrode G11 of the first transistor T1 to the second transistor T2 and the third transistor T3 through the opening SOP of the upper electrode C12 of the second electrode of the first capacitor C1. One end of the first node electrode 131 may be electrically connected to the first gate electrode G11 of the first transistor T1 via a contact hole 32 formed through the second insulating layer 112 and the third insulating layer 113. The other end of the first node electrode 131 may be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 33 formed through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0168] The second node electrode 132 may electrically connect the source region S1 of the first transistor T1 to the fourth transistor T4 and the sixth transistor T6 .

[0169] A first portion of one end of the second node electrode 132 may be electrically connected to the source region S1 of the first transistor T1 via a contact hole 36 formed through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. A second portion of one end of the second node electrode 132 may be electrically connected to the protruding portion G12p of the second gate electrode G12 of the first transistor T1 via a contact hole 37 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. A third portion of one end of the second node electrode 132 may be electrically connected to the upper electrode C12 of the second electrode of the first capacitor C1 via a contact hole 38 formed through the third insulating layer 113. Accordingly, the lower electrode C13 of the second electrode of the first capacitor C1 and the upper electrode C12 of the second electrode of the first capacitor C1 may be electrically connected to each other.

[0170] A middle portion of the second node electrode 132 may be electrically connected to the drain region D4 of the fourth transistor T4 via a contact hole 43 formed through the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 .

[0171] The other end of the second node electrode 132 may be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 44 formed through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. An overlapping region between the second node electrode 132 and the driving voltage line PL may form a second capacitor C2. The second capacitor C2 may include a first electrode C21 as a portion of the driving voltage line PL and a second electrode C22 as a portion of the second node electrode 132.

[0172] A portion 132 p extending from one end of the second node electrode 132 in the second pixel area PCA2 and the third pixel area PCA3 may be electrically connected to the pixel electrode by making contact with the pixel electrode.

[0173] The conductive pattern 133 can be electrically connected to the source region S3 of the third transistor T3 via a contact hole 34 formed by the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113, and can be electrically connected to the reference voltage line VRL via a contact hole 35 formed by the buffer layer 110, the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0174] The conductive pattern 134 can be electrically connected to the driving voltage line PL via a contact hole 39 formed by the buffer layer 110, the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113, and can be electrically connected to the drain region D5 of the fifth transistor T5 via a contact hole 40 formed by the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0175] The conductive pattern 135 may be electrically connected to the source region S4 of the fourth transistor T4 via a contact hole 41 formed through the first, second, and third insulating layers 111 , 112 , and 113 , and may be electrically connected to the first initialization voltage line VL1 via a contact hole 42 formed through the third insulating layer 113 .

[0176] In the first pixel area PCA1 and the third pixel area PCA3, the conductive pattern 136a can be electrically connected to the 2-1 initialization voltage line VL21 via a contact hole 45 formed by the second insulating layer 112 and the third insulating layer 113, and can be electrically connected to the source area S6 of the sixth transistor T6 via a contact hole 46 formed by the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0177] In the second pixel area PCA2, the conductive pattern 136b can be electrically connected to the 2-2 initialization voltage line VL22 via a contact hole 47 formed through the third insulating layer 113, and can be electrically connected to the source region S6 of the sixth transistor T6 via a contact hole 48 formed through the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0178] The conductive pattern 137 may be electrically connected to the upper electrode C12 of the second electrode of the first capacitor C1 via a contact hole 49 formed through the third insulating layer 113. In the first pixel area PCA1, a portion 137p of the conductive pattern 137 may be electrically connected to the pixel electrode by contacting the pixel electrode.

[0179] The longitudinal conductive lines VCL may extend in the y direction and may be arranged apart from each other in the x direction. One of the first longitudinal conductive lines VCL1 and one of the second longitudinal conductive lines VCL2 may be arranged in the unit pixel area PCAu. One of the first longitudinal conductive lines VCL1 may be disposed on a boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2. One of the second longitudinal conductive lines VCL2 may be disposed on a boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3. The first longitudinal conductive line VCL1 may be disposed between a first node electrode 131 of the first pixel area PCA1 and a first node electrode 131 of the second pixel area PCA2. The second longitudinal conductive line VCL2 may be disposed between a data line DL of the second pixel area PCA2 and a data line DL of the third pixel area PCA3.

[0180] like Fig. 9 and Fig.15 As shown in FIG, the vertical driving voltage line PLv may be disposed on a boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the vertical reference voltage line VRLv may be disposed on a boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3.

[0181] The longitudinal driving voltage line PLv may be electrically connected to the driving voltage line PL via a contact hole 50 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. Accordingly, the driving voltage line PL may have a mesh structure in the display area DA. The longitudinal reference voltage line VRLv may be electrically connected to the reference voltage line VRL via a contact hole 51 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. Accordingly, the reference voltage line VRL may have a mesh structure in the display area DA.

[0182] like Fig. 9 and Fig.16 As shown in FIG. 1 , the common voltage line EL may be disposed on a boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the 2-1st vertical initialization voltage line VL21v may be disposed on a boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3.

[0183] The 2-1st vertical initialization voltage line VL21v may be electrically connected to the 2-1st initialization voltage line VL21 via a contact hole 52 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. Accordingly, the 2-1st initialization voltage line VL21 may have a mesh structure in the display area DA.

[0184] like Fig. 9 and Fig.17 As shown in the figure, the vertical driving voltage line PLv may be disposed on the boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the first vertical initialization voltage line VL1v may be disposed on the boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3.

[0185] The first vertical initialization voltage line VL1v may be electrically connected to the first initialization voltage line VL1 via a contact hole 53 formed through the third insulating layer 113. Accordingly, the first initialization voltage line VL1 may have a mesh structure in the display area DA.

[0186] like Fig. 9 and Fig.18 As shown in FIG. 1 , the common voltage line EL may be disposed on a boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the 2-2nd vertical initialization voltage line VL22v may be disposed on a boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3.

[0187] The 2-2nd vertical initialization voltage line VL22v may be electrically connected to the 2-2nd initialization voltage line VL22 via a contact hole 54 formed through the third insulating layer 113. Accordingly, the 2-2nd initialization voltage line VL22 may have a mesh structure in the display area DA.

[0188] The fourth insulating layer 114 may be disposed on the third insulating layer 113 to cover the fourth conductive layer, and the organic light emitting diode OLED may be disposed on the fourth insulating layer 114 as a display element. The organic light emitting diode OLED may include a pixel electrode 211, an opposing electrode 215, and an intermediate layer disposed between the pixel electrode 211 and the opposing electrode 215.

[0189] In an embodiment, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113 may be inorganic insulating layers. The fourth insulating layer 114 may be an organic insulating layer.

[0190] The pixel electrode 211 may be connected to the first transistor T1 through a second node connected to the lower conductive pattern via a contact hole 55 formed through the fourth insulating layer 114. Fig.19, the pixel electrode 211 connected to the pixel circuit of the first pixel PX1 may be connected to the first transistor T1 by being electrically connected to the portion 137p of the conductive pattern 137 arranged in the first pixel area PCA1. The pixel electrode 211 connected to the pixel circuit of the second pixel PX2 may be connected to the first transistor T1 by being electrically connected to the portion 132p of the second node electrode 132 arranged in the second pixel area PCA2. The pixel electrode 211 connected to the pixel circuit of the third pixel PX3 may be connected to the first transistor T1 by being electrically connected to the portion 132p of the second node electrode 132 arranged in the third pixel area PCA3.

[0191] In an embodiment, the pixel electrode 211 of the pixel circuit connected to the first pixel PX1 and the pixel electrode 211 of the pixel circuit connected to the second pixel PX2 may overlap with the first pixel area PCA1 and the second pixel area PCA2, and may be arranged adjacent to each other in the y direction. The pixel electrode 211 of the pixel circuit connected to the third pixel PX3 may overlap with the pixel circuit of the third pixel area PCA3. Each of the pixel electrode 211 of the pixel circuit connected to the first pixel PX1 and the pixel electrode 211 of the pixel circuit connected to the second pixel PX2 may have a substantially square shape, and the pixel electrode 211 of the pixel circuit connected to the third pixel PX3 may have a rectangular shape having a long side in the y direction.

[0192] The pixel defining layer 115 may be disposed on the pixel electrode 211 to cover the edge of the pixel electrode 211. An opening 115OP may be defined in the pixel defining layer 115 to expose a portion of the pixel electrode 211 and define an emission area EA. The pixel defining layer 115 may include a single layer or multiple layers including an organic insulating layer and / or an inorganic insulating layer.

[0193] The intermediate layer may include an emission layer 213, a first functional layer disposed above the emission layer 213, and / or a second functional layer disposed below the emission layer 213. The first functional layer may include a hole transport layer (HTL). Alternatively, the first functional layer may include a hole injection layer (HIL) and an HTL. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer and the second functional layer may be integrally formed to correspond to a plurality of organic light emitting diodes OLED included in the display area DA. The first functional layer or the second functional layer may be omitted.

[0194] The opposing electrode 215 may be integrally formed to correspond to a plurality of organic light emitting diodes OLED included in the display area DA.

[0195] Fig. 22 is a diagram schematically showing an arrangement of emission regions of a plurality of pixels according to an embodiment.

[0196] Reference Fig. 22 , a plurality of pixels arranged in the display area DA may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be repeatedly arranged in the x direction and the y direction according to a specific pattern. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a pixel circuit and an organic light emitting diode OLED electrically connected to the pixel circuit. The organic light emitting diode OLED of each pixel may be disposed above the pixel circuit. The organic light emitting diode OLED may be disposed directly above the pixel circuit to overlap with the pixel circuit, or may be arranged to partially overlap with the pixel circuit of another pixel arranged in an adjacent row and / or column by being offset from the pixel circuit.

[0197] Fig. 22 1 and 2 are shown for each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The emission region EA may be a region in which an emission layer 213 of an organic light emitting diode OLED is disposed. The emission region EA may be defined by an opening 115OP of a pixel defining layer 115. Since the emission layer 213 is disposed on the pixel electrode 211, Fig. 22 The arrangement of the emission areas shown in may represent the arrangement of pixel electrodes or the arrangement of pixels.

[0198] The emission area EA may have a shape such as a polygonal shape such as a quadrilateral shape or an octagonal shape, a circular shape, or an elliptical shape, and the polygonal shape may also include a shape having rounded corners (vertices).

[0199] like Fig. 22 As shown in , the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may be arranged adjacent to each other in the y direction, and the emission area EA of the third pixel PX3 may be arranged adjacent to the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 in the x direction. Accordingly, the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may be alternately arranged in the y direction along the imaginary line IL1, and the emission area EA of the third pixel PX3 may be repeatedly arranged in the y direction along the imaginary line IL2.

[0200] The x-direction length and the y-direction length of the emission area EA of the first pixel PX1, the emission area EA of the second pixel PX2, and the emission area EA of the third pixel PX3 may be equal to or different from each other. For example, the emission area EA of the first pixel PX1 and the emission area EA of the second pixel PX2 may have a square shape, and the emission area EA of the third pixel PX3 may have a rectangular shape having a long side in the y direction. The y-direction length of the emission area EA of the third pixel PX3 may be greater than or equal to the sum of the y-direction lengths of the emission area EA of the first pixel PX1 and the y-direction lengths of the emission area EA of the second pixel PX2.

[0201] The emission area EA of the first pixel PX1, the emission area EA of the second pixel PX2, and the emission area EA of the third pixel PX3 may have different areas (sizes). In an embodiment, the emission area EA of the third pixel PX3 may have an area larger than the area of ​​the emission area EA of the first pixel PX1. The emission area EA of the third pixel PX3 may have an area larger than the area of ​​the emission area EA of the second pixel PX2. The emission area EA of the first pixel PX1 may have the same area as the area of ​​the emission area EA of the second pixel PX2.

[0202] Fig.23 is a diagram schematically showing a display device according to an embodiment. Fig.24 is an equivalent circuit diagram of a pixel according to the embodiment. Fig.25 is shown for describing Fig.24 ] is a waveform diagram of signals for pixel operation shown in FIG. Figure 26 to Figure 29 is a diagram schematically showing a connection relationship between a pixel and a second initialization voltage line according to an embodiment. Fig.30 FIG. 1 is a diagram schematically showing a connection relationship between signal lines arranged in a display area according to an embodiment. Figures 2 to 22 The differences between the described embodiments will be described below, and their redundant descriptions will be omitted for the sake of brevity.

[0203] Reference Fig.23 The display device 10 b according to the embodiment may include a pixel unit 11 , a gate driving circuit 13 , a data driving circuit 15 , a power supply circuit 17 , and a controller 19 .

[0204] In terms of the signals output by the gate drive circuit 13 and the power supply circuit 17, Fig.23 The display device 10b can be used with Figure 2The display device 10a of FIG. 1 is different. For example, the pixel PX may be connected to a plurality of gate lines and emission control lines, and the gate driving circuit 13 may apply the first gate signal GW, the second gate signal GI, the third gate signal GR, the fifth gate signal EMB and the emission control signal EM to the corresponding gate lines and emission control lines, respectively. The power supply circuit 17 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage Vref and an initialization voltage Vint and supply them to the pixel PX.

[0205] Fig.24 The pixel PXb shown in FIG. 1 may be Fig.23 Referring to the embodiment of the pixel PX shown in Fig.24 The pixel PXb may include an organic light emitting diode OLED and a pixel circuit PC connected to the organic light emitting diode OLED. The pixel circuit PC may include first to fifth transistors T1 to T5, a seventh transistor T7, and first and second capacitors C1 and C2.

[0206] The pixel PXb may be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, an emission control line EML configured to transmit an emission control signal EM, and a data line DL configured to transmit a data signal Vdata. Furthermore, the pixel PXb may be connected to a driving voltage line PL configured to transmit a first driving voltage ELVDD, an initialization voltage line VL configured to transmit an initialization voltage Vint, and a reference voltage line VRL configured to transmit a reference voltage Vref.

[0207] The first transistor T1 may be connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a first gate connected to the first node N1 and a second gate connected to the second node N2.

[0208] The second transistor T2 may be connected between the first gate of the first transistor T1 and the data line DL. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1.

[0209] The third transistor T3 may be connected between the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL configured to supply a reference voltage Vref.

[0210] The fourth transistor T4 may be connected between the first transistor T1 and the initialization voltage line VL. The fourth transistor T4 may be connected between the seventh transistor T7 and the initialization voltage line VL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the initialization voltage line VL configured to supply the initialization voltage Vint.

[0211] The fifth transistor T5 may be connected between the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the emission control line EML, a first terminal connected to the driving voltage line PL configured to supply the first driving voltage ELVDD, and a second terminal connected to the first terminal of the first transistor T1.

[0212] The seventh transistor T7 may be connected between the first transistor T1 and the organic light emitting diode OLED. The seventh transistor T7 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED.

[0213] The first capacitor C1 may be connected between the first gate electrode of the first transistor T1 and the organic light emitting diode OLED. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first capacitor C1 may be a storage capacitor and may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal.

[0214] The second capacitor C2 may be connected between the driving voltage line PL and the organic light emitting diode OLED. The second capacitor C2 may include a first electrode connected to the driving voltage line PL and a second electrode connected to the second node N2. The capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2.

[0215] The organic light emitting diode OLED may be connected to the seventh transistor T7. The organic light emitting diode OLED may be connected to the first transistor T1 through the seventh transistor T7. The organic light emitting diode OLED may include a pixel electrode (anode) connected to the second terminal of the seventh transistor T7 and an opposite electrode (cathode) facing the pixel electrode.

[0216] Reference Fig.25 , the pixel PXb may operate in a non-emission period NEP and an emission period EP in each frame period. The non-emission period NEP may include a first initialization period P1, a compensation period P2, a writing period P3, and a second initialization period P4.

[0217] Each of the first gate signal GW, the second gate signal GI, the third gate signal GR, the fifth gate signal EMB, and the emission control signal EM may have a high level voltage during some periods, and may have a low level voltage during some periods. Here, the high level voltage may be a turn-on voltage for turning on the transistor, and the low level voltage may be a turn-off voltage for turning off the transistor.

[0218] In the first initialization period P1, the second gate signal GI of the turn-on voltage may be supplied to the second gate line GIL, the third gate signal GR of the turn-on voltage may be supplied to the third gate line GRL, and the fifth gate signal EMB of the turn-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW and the emission control signal EM may supply the turn-off voltage. The fourth transistor T4 may be turned on by the second gate signal GI, the third transistor T3 may be turned on by the third gate signal GR, and the seventh transistor T7 may be turned on by the fifth gate signal EMB. The first gate of the first transistor T1 may be initialized to the reference voltage Vref by the turned-on third transistor T3. The pixel electrode of the organic light emitting diode OLED may be initialized to the initialization voltage Vint by the turned-on fourth transistor T4 and the seventh transistor T7.

[0219] In the compensation period P2, the third gate signal GR of the turn-on voltage may be supplied to the third gate line GRL, and the emission control signal EM of the turn-on voltage may be supplied to the emission control line EML. The first gate signal GW, the second gate signal GI, and the fifth gate signal EMB may supply the turn-off voltage. The second transistor T2, the fourth transistor T4, and the seventh transistor T7 may be turned off by the first gate signal GW, the second gate signal GI, and the fifth gate signal EMB having the turn-off voltage. The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the emission control signal EM. The reference voltage Vref may be supplied to the first gate of the first transistor T1 by the turned-on third transistor T3, and the first driving voltage ELVDD may be supplied to the first terminal of the first transistor T1, and thus the first transistor T1 may be turned on.

[0220] When the voltage of the second terminal of the first transistor T1 changes to the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 may be turned off. Also, a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be charged in the first capacitor C1 to compensate for the threshold voltage (Vth) of the first transistor T1.

[0221] As a comparative example, in a case where Fig.24In the case of a display device in which the pixel circuit of the seventh transistor T7 is omitted in the pixel circuit shown in , in the compensation period P2, as the current output by the first transistor T1 flows through the organic light emitting diode OLED, the parasitic capacitor of the organic light emitting diode OLED may be charged. Accordingly, in the compensation period P2, a capacitor charging deviation of the organic light emitting diode OLED and / or a charging deviation caused by a change in the impedance of the organic light emitting diode OLED due to degradation of the organic light emitting diode OLED may occur. As a result, an image brightness deviation may occur, and thus image stains may occur.

[0222] Embodiments may block the electrical connection between the first transistor T1 and the organic light emitting diode OLED by providing the seventh transistor T7 in the pixel PXb and turning off the seventh transistor T7 in the compensation period P2. Therefore, in the compensation period P2, compensation deviation may not occur, and thus brightness deviation may be reduced.

[0223] In the writing period P3, the first gate signal GW of the turn-on voltage may be supplied to the first gate line GWL to turn on the second transistor T2. In this case, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 may be turned off by the second gate signal GI of the turn-off voltage, the third gate signal GR, the fifth gate signal EMB, and the emission control signal EM. The second transistor T2 may be configured to transmit the data signal Vdata from the data line DL to the first node N1 (which is connected to the first gate of the first transistor T1). Accordingly, the gate-source voltage (Vgs) of the first transistor T1 may be expressed as the above formula (1).

[0224] In the second initialization period P4, the second gate signal GI of the turn-on voltage may be supplied to the second gate line GIL, and the fifth gate signal EMB of the turn-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the third gate signal GR, and the emission control signal EM may supply the turn-off voltage. The seventh transistor T7 may be turned on by the fifth gate signal EMB to connect the pixel electrode of the organic light emitting diode OLED to the second terminal of the first transistor T1, and the fourth transistor T4 may be turned on by the second gate signal GI to initialize the pixel electrode of the organic light emitting diode OLED to the initialization voltage Vint.

[0225] In the emission period EP, the emission control signal EM and the fifth gate signal EMB may be supplied with a turn-on voltage, and the first gate signal GW, the second gate signal GI, and the third gate signal GR may be supplied with a turn-off voltage. The second transistor T2, the third transistor T3, and the fourth transistor T4 may be turned off by the first gate signal GW, the second gate signal GI, and the third gate signal GR, and the fifth transistor T5 and the seventh transistor T7 may be turned on by the emission control signal EM and the fifth gate signal EMB.

[0226] The first transistor T1 may output a driving current having a magnitude corresponding to the voltage stored in the first capacitor C1 (Id∝(Vgs-Vth) 2 ), and the organic light emitting diode OLED can emit light having brightness corresponding to a magnitude of the driving current regardless of the threshold voltage (Vth) of the first transistor T1.

[0227] The embodiment can prevent compensation deviation between pixels by disconnecting the organic light emitting diode OLED from the pixel circuit PC during the compensation period P2, thereby minimizing the brightness deviation between pixels. In addition, the brightness deviation between pixels can be minimized by initializing the gate of the first transistor T1 before the compensation period P2 and initializing the organic light emitting diode OLED after the compensation period P2.

[0228] In an embodiment, different initialization voltages Vint may be supplied to the first pixel PX1, the second pixel PX2, and the third pixel PX3. Fig.26 As shown in , the first pixel PX1 and the third pixel PX3 may be connected to a first initialization voltage line VL11 configured to supply a first initialization voltage Vint1, and the second pixel PX2 may be connected to a second initialization voltage line VL12 configured to supply a second initialization voltage Vint2. Alternatively, as Fig. 27 As shown in , the first pixel PX1 may be connected to a first initialization voltage line VL11 configured to supply a first initialization voltage Vint1, and the second pixel PX2 and the third pixel PX3 may be connected to a second initialization voltage line VL12 configured to supply a second initialization voltage Vint2. Alternatively, as Fig.28 As shown in , the first pixel PX1 and the second pixel PX2 may be connected to a first initialization voltage line VL11 configured to supply a first initialization voltage Vint1, and the third pixel PX3 may be connected to a second initialization voltage line VL12 configured to supply a second initialization voltage Vint2. Alternatively, as Fig.29As shown in the figure, the first pixel PX1 can be connected to the first initialization voltage line VL11 configured to supply the first initialization voltage Vint1, the second pixel PX2 can be connected to the second initialization voltage line VL12 configured to supply the second initialization voltage Vint2, and the third pixel PX3 can be connected to the third initialization voltage line VL13 configured to supply the third initialization voltage Vint3.

[0229] In the following, we will base on Fig.26 Description will be given of an embodiment shown in FIG. 1 in which the first pixel PX1 and the third pixel PX3 are connected to the first initialization voltage line VL11 and the second pixel PX2 is connected to the second initialization voltage line VL12 .

[0230] Reference Fig.30 , transverse conductive lines HCL extending in the x-direction and longitudinal conductive lines VCL extending in the y-direction may be arranged in the display area DA.

[0231] The transverse conductive line HCL may include a reference voltage line VRL, a driving voltage line PL, and an initialization voltage line VL. The initialization voltage line VL may include a first initialization voltage line VL11 and a second initialization voltage line VL12. The reference voltage line VRL, the driving voltage line PL, the first initialization voltage line VL11, and the second initialization voltage line VL12 may be arranged in each row.

[0232] The longitudinal conductive line VCL may include a first longitudinal conductive line VCL1 and a second longitudinal conductive line VCL2. The first longitudinal conductive line VCL1 may include a longitudinal driving voltage line PLv and a common voltage line EL. The second longitudinal conductive line VCL2 may include a longitudinal reference voltage line VRLv and a longitudinal initialization voltage line VLv. The longitudinal initialization voltage line VLv may include a first longitudinal initialization voltage line VL11v and a second longitudinal initialization voltage line VL12v.

[0233] The reference voltage line VRL may be electrically connected to the longitudinal reference voltage line VRLv through the contact hole CH7 to form a grid structure in the display area DA. The driving voltage line PL may be electrically connected to the longitudinal driving voltage line PLv through the contact hole CH8 to form a grid structure in the display area DA. The first initialization voltage line VL11 may be electrically connected to the first longitudinal initialization voltage line VL11v through the contact hole CH9 to form a grid structure in the display area DA. The second initialization voltage line VL12 may be electrically connected to the second longitudinal initialization voltage line VL12v through the contact hole CH10 to form a grid structure in the display area DA. The common voltage line EL may be electrically connected to the common voltage supply line EPL arranged in the peripheral area PA through the contact hole CH11.

[0234] One of the first longitudinal conductive lines VCL1 and one of the second longitudinal conductive lines VCL2 may be arranged in the unit pixel area PCAu. The longitudinal driving voltage line PLv may be arranged at intervals of two unit pixel areas PCAu in the x direction (i.e., at intervals of six pixel areas or six columns). The common voltage line EL may be arranged at intervals of two unit pixel areas PCAu in the x direction (i.e., at intervals of six pixel areas or six columns). The longitudinal reference voltage line VRLv may be arranged at intervals of two unit pixel areas PCAu in the x direction (i.e., at intervals of 6 pixel areas or 6 columns). Each of the first longitudinal initialization voltage line VL11v and the second longitudinal initialization voltage line VL12v may be arranged alternately at intervals of four unit pixel areas PCAu in the x direction (i.e., at intervals of 12 pixel areas or 12 columns).

[0235] Figure 31 to Figure 39 It is schematically shown layer by layer. Fig.24 Layout diagram of elements of a pixel. Fig.35 is shown as Fig.34 FIG. 1 is a plan view of an element of a portion of the first pixel area PCA1. Fig.40 is along Fig.36 A cross-sectional view of a pixel taken along line IV-IV', in which a display element is reflected. Fig.41 is along Fig.36 A cross-sectional view of a pixel taken along lines V-V' and VI-VI', wherein a display element is reflected. Fig.40 and Fig.41 Similar to Fig.37 and Fig.38 In the following, we will mainly focus on Figures 10 to 21 The differences between the elements shown in FIG. 1 and FIG. 5 are described below, and their redundant descriptions will be omitted for the sake of brevity.

[0236] Reference Fig.31 , the first conductive layer may be disposed on the substrate 100. The first conductive layer may include a reference voltage line VRL, a second gate electrode G12 of the first transistor T1, a driving voltage line PL, and a first initialization voltage line VL11. The first conductive layer may also include a repair line RL. The reference voltage line VRL, the driving voltage line PL, the first initialization voltage line VL11, and the repair line RL may extend in the x direction and may be arranged in the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3. The second gate electrode G12 of the first transistor T1 may be provided as an island type. The second gate electrode G12 of the first transistor T1 may be a lower electrode C13 of the second electrode of the first capacitor C1.

[0237] The buffer layer 110 may be disposed on the first conductive layer, and the semiconductor layer ACT may be disposed on the buffer layer 110. Fig.32 The semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, and a third semiconductor layer ACT3. Fig.35 As shown in , the first semiconductor layer ACT1 may include the source region S1 and the drain region D1 of the first transistor T1 and the source region S5 and the drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and the drain region D2 of the second transistor T2 and the source region S3 and the drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S4 and the drain region D4 of the fourth transistor T4 and the source region S7 and the drain region D7 of the seventh transistor T7.

[0238] The first insulating layer 111 may be disposed on the semiconductor layer ACT, and the second conductive layer may be disposed on the first insulating layer 111. Fig.33 The second conductive layer may include gate electrodes G1 to G5 and G7 of the first to fifth transistors T1 to T5 and the seventh transistor T7. Also, the second conductive layer may include a first gate line GWL, a second gate line GIL, a third gate line GRL, a fifth gate line EMBL and an emission control line EML.

[0239] The first gate line GWL, the second gate line GIL, the third gate line GRL, the fifth gate line EMBL, and the emission control line EML may extend in the x-direction and may be arranged in the first pixel area PCA1, the second pixel area PCA2, and the third pixel area PCA3.

[0240] like Fig.35 As shown in , the first gate electrode G11 of the first transistor T1 may be provided as an island type and may overlap with the second gate electrode G12 and the first semiconductor layer ACT1. The first gate electrode G11 of the first transistor T1 may be the first electrode C11 of the first capacitor C1. The gate electrode G2 of the second transistor T2 may be a portion of the first gate line GWL intersecting (overlapping) with the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be a portion of the third gate line GRL intersecting (overlapping) with the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be a portion of the second gate line GIL intersecting (overlapping) with the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 may be a portion of the emission control line EML intersecting (overlapping) with the first semiconductor layer ACT1. The gate electrode G7 of the seventh transistor T7 may be a portion of the fifth gate line EMBL intersecting (overlapping) with the third semiconductor layer ACT3.

[0241] The second insulating layer 112 may be disposed on the first insulating layer 111 to cover the second conductive layer, and the third conductive layer may be disposed on the second insulating layer 112. Fig.34, the third conductive layer may include an upper electrode C12 of the second electrode of the first capacitor C1 and a second initialization voltage line VL12.

[0242] The upper electrode C12 of the second electrode of the first capacitor C1 may be provided as an island type and may overlap the lower electrode C13 of the second electrode of the first capacitor C1 and the first electrode C11. An open SOP may be formed in the upper electrode C12 of the second electrode of the first capacitor C1. The first capacitor C1 may include the lower electrode C13 of the second electrode, the first electrode C11, and the upper electrode C12 of the second electrode, and may overlap the first transistor T1.

[0243] The second initialization voltage line VL12 may extend in the x-direction and may be arranged in the first, second, and third pixel regions PCA1, PCA2, and PCA3.

[0244] The third insulating layer 113 may be disposed on the second insulating layer 112 to cover the third conductive layer, and the fourth conductive layer may be disposed on the third insulating layer 113. Figure 36 to Figure 38 As shown in , the fourth conductive layer may include a data line DL, a first node electrode 141, a second node electrode 142, conductive patterns 143, 144, 145, 146a and 146b, and a longitudinal conductive line VCL.

[0245] The data line DL may be arranged in each pixel region to extend in the y direction and may be electrically connected to the drain region D2 of the second transistor T2 via a contact hole 61 formed through the first insulating layer 111 , the second insulating layer 112 , and the third insulating layer 113 .

[0246] One end of the first node electrode 141 may be electrically connected to the first gate electrode G11 of the first transistor T1 via a contact hole 62 formed through the second insulating layer 112 and the third insulating layer 113. The other end of the first node electrode 141 may be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 63 formed through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0247] A first portion of one end of the second node electrode 142 may be electrically connected to the source region S1 of the first transistor T1 via a contact hole 66 formed through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. A second portion of one end of the second node electrode 142 may be electrically connected to a protruding portion G12p of a second gate electrode G12 of the first transistor T1 via a contact hole 67 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. A third portion of one end of the second node electrode 142 may be electrically connected to an upper electrode C12 of a second electrode of the first capacitor C1 via a contact hole 68 formed through the third insulating layer 113. The other end of the second node electrode 142 may be electrically connected to a drain region D4 of the fourth transistor T4 and a drain region D7 of the seventh transistor T7 via a contact hole 69 formed through the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0248] The conductive pattern 143 can be electrically connected to the source region S3 of the third transistor T3 via a contact hole 64 formed by the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113, and can be electrically connected to the reference voltage line VRL via a contact hole 65 formed by the buffer layer 110, the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0249] The conductive pattern 144 can be electrically connected to the driving voltage line PL via a contact hole 71 formed by the buffer layer 110, the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113, and can be electrically connected to the drain region D5 of the fifth transistor T5 via a contact hole 70 formed by the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0250] The conductive pattern 145 may be electrically connected to the source region S7 of the seventh transistor T7 via a contact hole 72 formed through the first, second, and third insulating layers 111, 112, and 113. A portion 145p of the conductive pattern 145 may be electrically connected to the pixel electrode by contacting the pixel electrode.

[0251] In the first pixel area PCA1 and the third pixel area PCA3, the conductive pattern 146a can be electrically connected to the first initialization voltage line VL11 via a contact hole 73 formed by the buffer layer 110, the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113, and can be electrically connected to the source area S4 of the fourth transistor T4 via a contact hole 74 formed by the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0252] In the second pixel area PCA2, the conductive pattern 146b can be electrically connected to the second initialization voltage line VL12 via a contact hole 76 formed through the third insulating layer 113, and can be electrically connected to the source region S4 of the fourth transistor T4 via a contact hole 75 formed through the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0253] like Fig.30 and Fig.36 As shown in , the longitudinal driving voltage line PLv may be disposed on the boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the longitudinal reference voltage line VRLv may be disposed on the boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3. The longitudinal driving voltage line PLv may be electrically connected to the driving voltage line PL via a contact hole 77 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The longitudinal reference voltage line VRLv may be electrically connected to the reference voltage line VRL via a contact hole 78 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0254] like Fig.30 and Fig.37 As shown in , the common voltage line EL may be disposed on a boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the first vertical initialization voltage line VL11v may be disposed on a boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3. The first vertical initialization voltage line VL11v may be electrically connected to the first initialization voltage line VL11 via a contact hole 79 formed through the buffer layer 110, the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0255] like Fig.30 , Fig.36 and Fig.38 As shown in , the vertical driving voltage line PLv may be disposed on the boundary line IBL1 between the first pixel area PCA1 and the second pixel area PCA2, and the second vertical initialization voltage line VL12v may be disposed on the boundary line IBL2 between the second pixel area PCA2 and the third pixel area PCA3. The second vertical initialization voltage line VL12v may be electrically connected to the second initialization voltage line VL12 via a contact hole 80 formed through the third insulating layer 113.

[0256] The fourth insulating layer 114 may be disposed on the third insulating layer 113 to cover the fourth conductive layer, and the organic light emitting diode OLED may be disposed on the fourth insulating layer 114 as a display element. The organic light emitting diode OLED may include a pixel electrode 211, an opposing electrode 215, and an intermediate layer disposed between the pixel electrode 211 and the opposing electrode 215.

[0257] Reference Fig.39 , the pixel electrode 211 may be connected to the first transistor T1 via a contact hole 81 formed through the fourth insulating layer 114 and electrically connected to a portion 145p of the conductive pattern 145. The pixel electrode 211 may be connected to the first transistor T1 connected to the second node via the seventh transistor T7 by being electrically connected to a portion 145p of the conductive pattern 145 via the contact hole 81 formed through the fourth insulating layer 114. In an embodiment, the pixel electrode 211 of the pixel circuit connected to the first pixel PX1 may overlap the first pixel area PCA1, the pixel electrode 211 of the pixel circuit connected to the second pixel PX2 may overlap the second pixel area PCA2, and the pixel electrode 211 of the pixel circuit connected to the third pixel PX3 may overlap the pixel circuit of the third pixel area PCA3. Each of the pixel electrodes 211 may have a rectangular shape having a long side in the y direction.

[0258] The pixel electrode 211 and the emission area EA of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged adjacent to each other in the x direction. In an embodiment, the emission area EA of the first pixel PX1, the emission area EA of the second pixel PX2, and the emission area EA of the third pixel PX3 may have the same area (size).

[0259] Fig.42 is an equivalent circuit diagram of a pixel according to the embodiment.

[0260] Fig.42 The pixel circuit PC of the pixel PXc is Figure 3 The pixel circuit PC of the pixel PXa may be different in that it further includes a seventh transistor T7, and the fourth transistor T4 is connected between the initialization voltage line VL and the third node N3 to which the seventh transistor T7 and the organic light emitting diode OLED are connected. Fig.42 The pixel circuit PC of the pixel PXc can be connected with Fig.24 The pixel circuit PC of the pixel PXb is different in that the fourth transistor T4 is connected between the third node N3 and the initialization voltage line VL.

[0261] The fourth transistor T4 may be connected between the first transistor T1 and the initialization voltage line VL. The fourth transistor T4 may be connected between the seventh transistor T7 and the initialization voltage line VL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VRL configured to supply the initialization voltage Vint.

[0262] Its other configuration and operation can be Fig.24 and Fig.25 The configuration and operation of the pixel PXb shown in FIG. 1 are the same.

[0263] The pixel PXc may include Figure 26 to Figure 29 , the first pixel PX1, the second pixel PX2, and the third pixel PX3 disclosed in . The pixel PXc may be connected to a plurality of initialization voltage lines VL supplying different initialization voltages. Each of the plurality of initialization voltage lines VL may be connected to at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The plurality of initialization voltage lines VL may supply different initialization voltages to the organic light emitting diode OLED in consideration of the light emitting characteristics of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0264] Fig.43 is an equivalent circuit diagram of a pixel according to the embodiment. Fig.44 is shown for describing Fig.43 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0265] Fig.43 The pixel circuit PC of the pixel PXd is Figure 3 The pixel circuit PC of the pixel PXa may differ in that it further includes a seventh transistor T7. Fig.43 The pixel circuit PC of the pixel PXd is Fig.24 The pixel circuit PC of the pixel PXb may differ in that it further includes a sixth transistor T6.

[0266] The fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1. The fourth transistor T4 may be connected between the seventh transistor T7 and the first initialization voltage line VL1. The fourth transistor T4 may be connected between the second node N2 and the first initialization voltage line VL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1 configured to supply the first initialization voltage Vint.

[0267] The sixth transistor T6 may be connected between the first transistor T1 and the second initialization voltage line VL2. The sixth transistor T6 may be connected between the seventh transistor T7 and the second initialization voltage line VL2. The sixth transistor T6 may be connected between the second node N2 and the second initialization voltage line VL2. The sixth transistor T6 may include a gate connected to the fourth gate line GBL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2 configured to supply a second initialization voltage Vaint.

[0268] The seventh transistor T7 may be connected between the first transistor T1 and the organic light emitting diode OLED. The seventh transistor T7 may be connected to the fourth transistor T4 and the organic light emitting diode OLED. The seventh transistor T7 may be connected between the sixth transistor T6 and the organic light emitting diode OLED. The seventh transistor T7 may be connected between the second node N2 and the organic light emitting diode OLED. The seventh transistor T7 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED.

[0269] Reference Fig.44 One frame period may include a non-emission period NEP in which the pixel PXd does not emit light and an emission period EP in which the pixel PXd emits light. The non-emission period NEP may include a first initialization period P1, a compensation period P2, a writing period P3, and a second initialization period P4.

[0270] In the first initialization period P1, the second gate signal GI of the turn-on voltage may be supplied to the second gate line GIL, the third gate signal GR of the turn-on voltage may be supplied to the third gate line GRL, and the fifth gate signal EMB of the turn-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the fourth gate signal GB, and the emission control signal EM may supply the turn-off voltage. The fourth transistor T4 may be turned on by the second gate signal GI, the third transistor T3 may be turned on by the third gate signal GR, and the seventh transistor T7 may be turned on by the fifth gate signal EMB. The gate of the first transistor T1 may be initialized to the reference voltage Vref by the turned-on third transistor T3. The pixel electrode of the organic light emitting diode OLED may be initialized to the first initialization voltage Vint by the turned-on fourth transistor T4 and the seventh transistor T7.

[0271] In the compensation period P2, the third gate signal GR of the turn-on voltage may be supplied to the third gate line GRL, and the emission control signal EM of the turn-on voltage may be supplied to the emission control line EML. The first gate signal GW, the second gate signal GI, the fourth gate signal GB, and the fifth gate signal EMB may supply the turn-off voltage. The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the emission control signal EM. The second transistor T2, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 may be turned off by the first gate signal GW, the second gate signal GI, the fourth gate signal GB, and the fifth gate signal EMB. The threshold voltage (Vth) of the first transistor T1 may be compensated by the turned-on third transistor T3 and the fifth transistor T5.

[0272] In the writing period P3, the first gate signal GW of the turn-on voltage may be supplied to the first gate line GWL to turn on the second transistor T2. In this case, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be turned off by the second gate signal GI of the turn-off voltage, the third gate signal GR, the fourth gate signal GB, the fifth gate signal EMB, and the emission control signal EM. The second transistor T2 may be configured to transmit the data signal Vdata from the data line DL to the first node N1 (which is connected to the first gate of the first transistor T1). Accordingly, the gate-source voltage (Vgs) of the first transistor T1 may be expressed as the above formula (1).

[0273] In the second initialization period P4, the fourth gate signal GB of the turn-on voltage may be supplied to the fourth gate line GBL, and the fifth gate signal EMB of the turn-on voltage may be supplied to the fifth gate line EMBL. The first gate signal GW, the second gate signal GI, the third gate signal GR, and the emission control signal EM may supply the turn-off voltage. The seventh transistor T7 may be turned on by the fifth gate signal EMB to connect the pixel electrode of the organic light emitting diode OLED to the second terminal of the first transistor T1, and the sixth transistor T6 may be turned on by the fourth gate signal GB to initialize the pixel electrode of the organic light emitting diode OLED to the second initialization voltage Vaint.

[0274] In the emission period EP, the emission control signal EM and the fifth gate signal EMB may be supplied with a turn-on voltage, and the first gate signal GW, the second gate signal GI, and the third gate signal GR may be supplied with a turn-off voltage. The second transistor T2, the third transistor T3, and the fourth transistor T4 may be turned off by the first gate signal GW, the second gate signal GI, and the third gate signal GR, and the fifth transistor T5 and the seventh transistor T7 may be turned on by the emission control signal EM and the fifth gate signal EMB.

[0275] The first transistor T1 may output a driving current having a magnitude corresponding to the voltage stored in the first capacitor C1 (Id∝(Vgs-Vth) 2 ), and the organic light emitting diode OLED can emit light having brightness corresponding to a magnitude of the driving current regardless of the threshold voltage (Vth) of the first transistor T1.

[0276] In an embodiment, different first initialization voltages Vint and / or second initialization voltages Vaint may be supplied to the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 by considering light emission characteristics of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0277] Fig.45 is an equivalent circuit diagram of a pixel according to the embodiment. Fig.46 is shown for describing Fig.45 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0278] Fig.45 The pixel circuit PC of the pixel PXe is Figure 3 The pixel circuit PC of the pixel PXa may differ in that it further includes a seventh transistor T7, and the sixth transistor T6 is connected between the second initialization voltage line VL2 and the third node N3 to which the seventh transistor T7 and the organic light emitting diode OLED are connected. Fig.45 The pixel circuit PC of the pixel PXe is Fig.43 The pixel circuit PC of the pixel PXd may be different in that the sixth transistor T6 is connected between the third node N3 and the second initialization voltage line VL2.

[0279] The sixth transistor T6 may be connected between the seventh transistor T7 and the second initialization voltage line VL2. The sixth transistor T6 may be connected between the organic light emitting diode OLED and the second initialization voltage line VL2. The sixth transistor T6 may be connected between the third node N3 and the second initialization voltage line VL2. The sixth transistor T6 may include a gate connected to the fourth gate line GBL, a first terminal connected to the third node N3, and a second terminal connected to the second initialization voltage line VL2 configured to supply a second initialization voltage Vaint.

[0280] The fifth gate signal EMB may be supplied with a turn-on voltage in the emission period EP, and may be supplied with a turn-off voltage in the non-emission period NEP. Fig.46As shown in FIG, the fifth gate signal EMB can supply a turn-off voltage in the first initialization period P1, the compensation period P2, the writing period P3, and the second initialization period P4, and can supply a turn-on voltage in the emission period EP. Accordingly, the seventh transistor T7 can be turned on in the emission period EP and turned off in the non-emission period NEP.

[0281] Its other configuration and operation can be Fig.43 and Fig.44 The configuration and operation of the pixel PXd shown in FIG. 1 are the same.

[0282] Fig.47 is an equivalent circuit diagram of a pixel according to the embodiment. Fig.48 is shown for describing Fig.47 ] is a waveform diagram of signals for pixel operation shown in FIG.

[0283] Fig.47 The pixel circuit PC of the pixel PXf is Fig.45 The pixel circuit PC of the pixel PXe may be different in that the gate of the fourth transistor T4 and the gate of the sixth transistor T6 are connected to the second gate line GIL.

[0284] The fourth transistor T4 may be connected between the first transistor T1 and the first initialization voltage line VL1. The fourth transistor T4 may be connected between the seventh transistor T7 and the first initialization voltage line VL1. The fourth transistor T4 may be connected between the second node N2 and the first initialization voltage line VL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the first initialization voltage line VL1 configured to supply the first initialization voltage Vint.

[0285] The sixth transistor T6 may be connected between the seventh transistor T7 and the second initialization voltage line VL2. The sixth transistor T6 may be connected between the organic light emitting diode OLED and the second initialization voltage line VL2. The sixth transistor T6 may be connected between the third node N3 and the second initialization voltage line VL2. The sixth transistor T6 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the second initialization voltage line VL2 configured to supply a second initialization voltage Vaint.

[0286] The second gate signal GI may provide an off voltage in the emission period EP, and may provide an on voltage or an off voltage in the non-emission period NEP. Fig.48As shown in , the second gate signal GI may be supplied with a turn-on voltage in the first initialization period P1 and the second initialization period P4, and may be supplied with a turn-off voltage in the compensation period P2, the writing period P3, and the emission period EP. Accordingly, the fourth transistor T4 and the sixth transistor T6 may be turned on in the first initialization period P1 and the second initialization period P4, and may be turned off in the compensation period P2, the writing period P3, and the emission period EP.

[0287] Its other configuration and operation can be Fig.45 and Fig.46 The configuration and operation of the pixel PXe shown in FIG. 1 are the same.

[0288] Fig.43 The pixel PXd, Fig.45 The pixel PXe and Fig.47 Each of the pixels PXf may include Figures 5 to 8 The first pixel PX1, the second pixel PX2 and the third pixel PX3 disclosed in the figure. The pixels may be connected to a plurality of second initialization voltage lines VL2 supplying different initialization voltages. Each of the plurality of second initialization voltage lines VL2 may be connected to at least one of the first pixel PX1, the second pixel PX2 and the third pixel PX3. The plurality of second initialization voltage lines VL2 may supply a different second initialization voltage Vaint to each second initialization voltage line VL2 in consideration of the light emitting characteristics of the first pixel PX1, the second pixel PX2 and the third pixel PX3. And / or, it may include a plurality of different first initialization voltage lines VL1 respectively connected to at least one of the first pixel PX1, the second pixel PX2 and the third pixel PX3, and a different first initialization voltage Vint may be supplied to each first initialization voltage line VL1.

[0289] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising a plurality of pixels, in, Each of the plurality of pixels comprises: a first transistor, the first transistor comprising a first gate and a second gate; a second transistor connected between the first gate of the first transistor and a data line; a third transistor, the third transistor being connected between the first gate of the first transistor and a first voltage line; a fourth transistor connected between the first transistor and a second voltage line; a fifth transistor connected between the first transistor and a third voltage line; a sixth transistor connected between the first transistor and a fourth voltage line; a light emitting diode connected to the first transistor; a first capacitor connected between the first gate of the first transistor and the light emitting diode; and A second capacitor is connected between the third voltage line and the light emitting diode.

2. The display device according to claim 1, wherein: The second gate of the first transistor is connected to a node to which the first transistor and the light emitting diode are connected.

3. The display device according to claim 1, wherein: The pixel operates with a non-emission period and an emission period during one frame period, and The non-transmission period includes: A first time period in which the third transistor and the fourth transistor are turned on; a writing period during which the second transistor is turned on, the writing period being after the first period; and The sixth transistor is turned on for a second period, and the second period is after the writing period.

4. The display device according to claim 3, wherein: The non-transmission period also includes: A third period in which the third transistor and the fifth transistor are turned on and a first voltage is supplied from the first voltage line to the first gate of the first transistor through the turned-on third transistor is located between the first period and the writing period.

5. The display device according to claim 4, wherein: The pixel also includes: A seventh transistor is connected between the first transistor and the light emitting diode.

6. The display device according to claim 5, wherein: The seventh transistor is turned on in the first period and the second period, and is turned off in the third period and the writing period.

7. The display device according to claim 3, wherein: The second transistor is turned on in the writing period, and a data signal is supplied to the first gate of the first transistor through the turned-on second transistor.

8. The display device according to claim 1, wherein: The fourth voltage line includes a 4-1st voltage line and a 4-2nd voltage line, wherein the sixth transistor of the first pixel emitting light of the first color among the plurality of pixels is connected to the 4-1st voltage line, wherein the sixth transistor of a second pixel emitting light of a second color among the plurality of pixels is connected to the 4-2nd voltage line, and The voltage supplied to the 4-1 voltage line and the voltage supplied to the 4-2 voltage line are different from each other.

9. The display device according to claim 1, wherein: Each of the first to fourth voltage lines extends in a first direction, and The display device further includes first to fourth longitudinal voltage lines extending in a second direction perpendicular to the first direction and connected to the first to fourth voltage lines, respectively.

10. The display device according to claim 9, wherein: Each of the first to fourth voltage lines is arranged in each row, and Each of the first to fourth longitudinal voltage lines is arranged at a specific interval between two columns.

11. A display device comprising a plurality of pixels, in, Each of the plurality of pixels comprises: Light Emitting Diodes; a first transistor, the first transistor comprising a first gate and a second gate; a second transistor connected to the first gate of the first transistor and a data line; a third transistor connected to the first gate of the first transistor and a first voltage line; a fourth transistor connected to the first transistor and a second voltage line; a fifth transistor connected to the first transistor and the light emitting diode; a sixth transistor connected to the fifth transistor and a third voltage line; a first capacitor connected to the first gate of the first transistor and the fifth transistor; and A second capacitor is connected to the second voltage line and the fifth transistor.

12. The display device according to claim 11, wherein: The second gate of the first transistor is connected to a node to which the first transistor and the fifth transistor are connected.

13. The display device according to claim 11, wherein: The sixth transistor is connected between the third voltage line and a node to which the first transistor and the fifth transistor are connected.

14. The display device according to claim 13, wherein: The pixel also includes: A seventh transistor is connected between the second terminal of the first transistor and a fourth voltage line.

15. The display device according to claim 14, wherein: The pixel operates with a non-emission period and an emission period during one frame period, and The non-transmission period includes: A first time period in which the third transistor, the fifth transistor and the sixth transistor are turned on; a writing period in which the second transistor is turned on and the fifth transistor is turned off, the writing period being after the first period; a second period during which the fifth transistor and the seventh transistor are turned on, the second period being after the writing period; and A third period in which the third transistor and the fourth transistor are turned on and the fifth transistor is turned off, the third period being between the first period and the writing period.

16. The display device according to claim 14, wherein: The fourth voltage line includes a 4-1st voltage line and a 4-2nd voltage line, wherein the seventh transistor of the first pixel emitting light of the first color among the plurality of pixels is connected to the 4-1st voltage line, wherein the seventh transistor of a second pixel emitting light of a second color among the plurality of pixels is connected to the 4-2nd voltage line, and The voltage supplied to the 4-1 voltage line and the voltage supplied to the 4-2 voltage line are different from each other.

17. The display device according to claim 13, wherein: The pixel also includes: A seventh transistor is connected between the fourth voltage line and a node to which the fifth transistor and the light emitting diode are connected.

18. The display device according to claim 17, wherein: The pixel operates with a non-emission period and an emission period during one frame period, The non-transmission period includes: A first time period in which the third transistor and the sixth transistor are turned on; a writing period during which the second transistor is turned on, the writing period being after the first period; a second time period during which the seventh transistor is turned on, the second time period being after the writing time period; and a third period during which the third transistor and the fourth transistor are turned on, the third period being located between the first period and the writing period, and The fifth transistor is turned off in the non-emission period and turned on in the emission period.

19. The display device according to claim 17, wherein: The fourth voltage line includes a 4-1st voltage line and a 4-2nd voltage line, wherein the seventh transistor of the first pixel emitting light of the first color among the plurality of pixels is connected to the 4-1st voltage line, wherein the seventh transistor of a second pixel emitting light of a second color among the plurality of pixels is connected to the 4-2nd voltage line, and The voltage supplied to the 4-1 voltage line and the voltage supplied to the 4-2 voltage line are different from each other.

20. The display device according to claim 11, wherein The sixth transistor is connected between the third voltage line and a node to which the fifth transistor and the light emitting diode are connected.

21. The display device according to claim 11, wherein: The pixel operates with a non-emission period and an emission period during one frame period, and The non-transmission period includes: A first time period in which the third transistor, the fifth transistor and the sixth transistor are turned on; a writing period during which the second transistor is turned on, the writing period being after the first period; and A second period in which the fifth transistor and the sixth transistor are turned on and the third transistor is turned off, the second period being after the writing period.

22. The display device according to claim 21, wherein: The non-transmission period also includes: A third period in which the third transistor and the fourth transistor are turned on and the fifth transistor and the sixth transistor are turned off, the third period being between the first period and the writing period.

23. The display device according to claim 21, wherein: In the writing period, the second transistor is turned on, and a data signal is supplied to the first gate of the first transistor through the turned-on second transistor.

24. The display device according to claim 11, wherein: The third voltage line includes a 3-1st voltage line and a 3-2nd voltage line, wherein the sixth transistor of the first pixel emitting light of the first color among the plurality of pixels is connected to the 3-1st voltage line, wherein the sixth transistor of a second pixel emitting light of a second color among the plurality of pixels is connected to the 3-2nd voltage line, and The voltage supplied to the 3-1 voltage line and the voltage supplied to the 3-2 voltage line are different from each other.

25. The display device according to claim 11, wherein: Each of the first to third voltage lines extends in a first direction, and The display device further includes first to third longitudinal voltage lines extending in a second direction perpendicular to the first direction and connected to the first to third voltage lines, respectively.

26. The display device according to claim 25, wherein: Each of the first to third voltage lines is arranged in each row, and Each of the first to third longitudinal voltage lines is arranged at a specific interval between two columns.

Images