Display device

Abstract

The display device includes a semiconductor pattern. The first capacitor electrode is disposed below the semiconductor pattern. The second capacitor electrode is disposed on the semiconductor pattern and a portion thereof constitutes a gate electrode. The first electrode and the second electrode are disposed in the same layer on the second capacitor electrode. The at least one light emitting element is disposed between the first electrode and the second electrode. The first pixel electrode is disposed on the first electrode and connected to a first end of the at least one light emitting element. The second pixel electrode is disposed on the second electrode and connected to a second end of the at least one light emitting element. The first electrode is electrically connected to the first capacitor electrode and the semiconductor pattern. The semiconductor pattern and the gate electrode constitute a transistor. The first capacitor is formed of a first capacitor electrode and a second capacitor electrode.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to a display device. Background Art

[0002] With the increase in interest in information display and the increase in demand for using portable information media, the demand for display devices has increased significantly, and commercialization thereof is in progress. Summary of the invention

[0003] Technical issues

[0004] Various embodiments of the present disclosure are directed to a display device with improved display quality.

[0005] Technical Solution

[0006] One or more embodiments of the present disclosure may provide a display device, the display device comprising: a semiconductor pattern; a first capacitor electrode, under the semiconductor pattern; a second capacitor electrode, on the semiconductor pattern, the second capacitor electrode including a portion forming a gate electrode; a first electrode and a second electrode, at the same layer on the second capacitor electrode; at least one light-emitting element, between the first electrode and the second electrode; a first pixel electrode, on the first electrode and connected to a first end of the at least one light-emitting element; and a second pixel electrode, on the second electrode and connected to a second end of the at least one light-emitting element. The first electrode may be electrically connected to the first capacitor electrode and the semiconductor pattern. The semiconductor pattern and the gate electrode may form a transistor. The first capacitor may be formed by the first capacitor electrode and the second capacitor electrode. The second capacitor may be formed by the second capacitor electrode and the first electrode.

[0007] The signal line and the power line may not be at a layer between the second capacitor electrode and the first electrode.

[0008] At least one of the source electrode and the drain electrode of the transistor may be at the same layer as the second capacitor electrode.

[0009] A data line connected to the transistor is at the same layer as the first capacitor electrode.

[0010] A power line connected to the transistor may be at the same layer as at least one of the first capacitor electrode and the second capacitor electrode.

[0011] The first pixel electrode may be electrically connected to the transistor through the first electrode.

[0012] The display device may further include a bridge electrode at the same layer as the first electrode and the second electrode and spaced apart from the first electrode and the second electrode. The second pixel electrode may be connected to the power line through the bridge electrode.

[0013] The second electrode may extend across the plurality of sub-pixels in a plan view. Each of the first electrode and the bridge electrode has an island shape in each of the sub-pixels.

[0014] The first insulating layer may be on the first electrode and the second electrode. The first insulating layer may not be in a boundary region between two adjacent sub-pixels among the plurality of sub-pixels.

[0015] In a plan view, the first electrode may cover the first capacitor electrode and the second capacitor electrode.

[0016] The first electrode may be connected to the first capacitor electrode and the semiconductor pattern through the opening of the second capacitor electrode.

[0017] The display device may further include: a wavelength conversion pattern on the at least one light emitting element and configured to convert a wavelength band of light incident on the wavelength conversion pattern from the at least one light emitting element to a desired wavelength band and emit light; and a color filter on the wavelength conversion pattern.

[0018] The at least one light emitting element may include inorganic light emitting diodes connected in parallel to each other.

[0019] A display device according to one or more embodiments of the present disclosure may include: a semiconductor pattern; a first capacitor electrode, under the semiconductor pattern; a gate electrode, on the semiconductor pattern; a first electrode and a second electrode, at the same layer on the gate electrode; at least one light-emitting element, between the first electrode and the second electrode; a first pixel electrode, on the first electrode and connected to the first end of the at least one light-emitting element; and a second pixel electrode, on the second electrode and connected to the second end of the at least one light-emitting element. The first electrode may be electrically connected to the first capacitor electrode and the semiconductor pattern. The semiconductor pattern and the gate electrode may form a transistor. The portion of the semiconductor pattern doped with impurities may form a second capacitor electrode. The first capacitor may be formed by the first capacitor electrode and the second capacitor electrode. The second capacitor may be formed by the second capacitor electrode and the first electrode overlapping the second capacitor electrode.

[0020] The gate electrode may be electrically connected to the second capacitor electrode.

[0021] The signal line and the power line may not be at a layer between the second capacitor electrode and the gate electrode.

[0022] Each of the data line and the power line connected to the transistor may be at the same layer as at least one of the first capacitor electrode and the second capacitor electrode.

[0023] The display device may further include a bridge electrode at the same layer as the first electrode and the second electrode and spaced apart from the first electrode and the second electrode. The second pixel electrode may be connected to the power line through the bridge electrode.

[0024] The first insulating layer may be on the first electrode and the second electrode. The first insulating layer may not be in a boundary region between two adjacent sub-pixels among the plurality of sub-pixels.

[0025] In a plan view, the first electrode may cover the first capacitor electrode and the second capacitor electrode.

[0026] Beneficial Effects

[0027] In a display device according to one or more embodiments of the present disclosure, the first alignment electrode and the second capacitor electrode as a gate electrode or a doped semiconductor pattern may form a second capacitor. The second capacitor may be connected in parallel to the first capacitor to form a storage capacitor. Therefore, the capacitance (or capacity) of the storage capacitor may be substantially increased.

[0028] In addition, the first alignment electrode can cover or shield the second capacitor electrode (or the gate electrode of the driving transistor). Therefore, the influence of the adjacent signal line and / or the power line on the second capacitor electrode can be eliminated. The data signal can be more accurately charged to the storage capacitor or maintained in the storage capacitor. The sub-pixel can emit light at a target brightness. Therefore, the quality of the image displayed on the display device can be improved.

[0029] The effects, aspects, and features of the embodiments of the present disclosure are not limited to the foregoing, and other various effects, aspects, and features are contemplated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a plan view showing a display device according to one or more embodiments of the present disclosure.

[0031] Figure 2A , Figure 2B , Figure 2C and Figure 2D It is shown that the Figure 1 Circuit diagram of one or more embodiments of a sub-pixel in a display device.

[0032] Figure 3 and Figure 4 Each is shown in Figure 1 Layout diagram of an implementation of a pixel in a display device.

[0033] Figure 5 is a diagram showing a method according to one or more embodiments of the present invention. Figure 1 A plan view of a pixel in a display device.

[0034] Figure 6 is a diagram showing a method of performing a Figures 3 to 5 sectional view of the first sub-pixel taken along line II' and line II-II'.

[0035] Fig. 7A and Figure 7B is a diagram showing a method according to one or more embodiments of the present invention. Figure 1 A cross-sectional view of a pixel in a display device.

[0036] Figure 8 It is used to describe manufacturing Figure 1 Layout diagram of the process of display device.

[0037] Fig. 9 is a diagram showing a method according to one or more embodiments of the present invention. Figure 1 Diagram of the layout of pixels in a display device.

[0038] Fig.10 is a diagram showing a method of performing a Fig. 9 sectional views of the first sub-pixel taken along lines III-III' and II-II'.

[0039] Fig.11 is a diagram illustrating a light emitting element according to one or more embodiments. DETAILED DESCRIPTION

[0040] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific practice mode, and it should be understood that all changes, equivalents and substitutions that do not depart from the spirit and technical scope of the present disclosure are included in the present disclosure.

[0041] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the present disclosure, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise.

[0042] It will also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, in the case where a first part such as a layer, a film, a region or a plate is disposed on a second part, the first part may not only be directly on the second part, but also a third part may be interposed between them. In addition, when it is indicated that a first part such as a layer, a film, a region or a plate is formed on a second part, the surface of the second part on which the first part is formed is not limited to the upper surface of the second part, but may include other surfaces of the second part such as a side surface or a lower surface. Conversely, in the case where a first part such as a layer, a film, a region or a plate is below the second part, the first part may not only be directly below the second part, but also a third part may be interposed between them.

[0043] With attached Figure 1 With reference to the embodiments described in detail later, aspects, effects and features of the present disclosure and methods for achieving the same will become clear. However, it should be noted that the present disclosure is not limited to the embodiments, but can be implemented in various other ways. In this specification, "connection / coupling" means that one component is not only directly connected to another component, but also indirectly connected to another component through an intermediate component. In addition, in one or more embodiments of the present disclosure, the term "connection" between two components may include electrical connection and physical connection.

[0044] Hereinafter, a display device according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0045] Figure 1 is a plan view showing a display device according to one or more embodiments of the present disclosure. Figure 1 A display panel PNL provided in a display device is shown.

[0046] Focusing on the display area DA, Figure 1 The structure of the display panel PNL according to one or more embodiments is shown. In one or more embodiments, at least one driving circuit (eg, at least one of a scan driver and a data driver), a line and / or a pad may be further disposed on the display panel PNL.

[0047] refer to Figure 1 , the display panel PNL may include a substrate SUB and pixels PXL disposed on the substrate SUB.

[0048] The substrate SUB (or base layer) may form the base of the display panel PNL and may be a rigid substrate or film or a flexible substrate or film. For example, the substrate SUB may be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer. The material and / or properties of the substrate SUB are not particularly limited.

[0049] In one or more embodiments, the substrate SUB may be substantially transparent. Here, the term "substantially transparent" may mean that light can pass through the substrate SUB at a specific transmittance or greater. In one or more embodiments, the substrate SUB may be translucent or opaque. In addition, in some embodiments, the substrate SUB may include a reflective material.

[0050] The display panel PNL and the substrate SUB for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA except the display area DA. The non-display area NDA may surround the display area DA along an edge or periphery of the display area DA.

[0051] The pixels PXL may be disposed in the display area DA. Various lines, pads, and / or internal circuits connected to the pixels PXL in the display area DA may be disposed in the non-display area NDA.

[0052] The pixel PXL may include sub-pixels SPX1 to SPX3. For example, the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0053] Each of the sub-pixels SPX1 to SPX3 may emit light of a specific color. In one or more embodiments, the sub-pixels SPX1 to SPX3 may emit light of different colors. For example, the first sub-pixel SPX1 may emit light of a first color. The second sub-pixel SPX2 may emit light of a second color. The third sub-pixel SPX3 may emit light of a third color. For example, the first sub-pixel SPX1 may be a red pixel configured to emit red light, the second sub-pixel SPX2 may be a green pixel configured to emit green light, and the third sub-pixel SPX3 may be a blue pixel configured to emit blue light. However, the present disclosure is not limited thereto.

[0054] In one or more embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include a light-emitting element associated with a first color, a light-emitting element associated with a second color, and a light-emitting element associated with a third color as light sources, so that the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of the first color, the second color, and the third color, respectively. In one or more embodiments, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may include light-emitting elements configured to emit light of the same color, and color conversion layers (or wavelength conversion layers) and / or color filters associated with different colors may be provided on the corresponding light-emitting elements, so that the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may emit light of the first color, the second color, and the third color, respectively. However, the colors, types, and / or numbers of the sub-pixels SPX1 to SPX3 forming each pixel PXL are not particularly limited. In other words, the color of the light emitted from each pixel PXL may be changed in various ways.

[0055] The sub-pixels SPX1 to SPX3 may be arranged in a stripe structure or Arrange the structure regularly. The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, Matrix structure or RGBG structure (for example, structure)). is a registered trademark of Samsung Display Co., Ltd. of South Korea. However, the arrangement structure of the sub-pixels SPX1 to SPX3 is not limited thereto, and the sub-pixels SPX1 to SPX3 may be arranged in the display area DA by using various structures and / or methods. For example, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may be repeatedly arranged sequentially along the first direction DR1, and may also be repeatedly arranged along the second direction DR2. At least one first sub-pixel SPX1, at least one second sub-pixel SPX2, and at least one third sub-pixel SPX3 disposed adjacent to each other may form a pixel PXL that may emit light of various colors. The arrangement structure of the sub-pixels SPX1 to SPX3 is not limited thereto, and the sub-pixels SPX1 to SPX3 may be arranged in the display area DA in various structures and / or schemes.

[0056] In one or more embodiments, each of the sub-pixels SPX1 to SPX3 may be formed by an active pixel. For example, each of the sub-pixels SPX1 to SPX3 may include at least one light source (e.g., a light-emitting element) driven by a control signal (e.g., a scan signal and a data signal) and / or a power source (e.g., a first power source and a second power source). However, the type, structure, and / or driving scheme of the sub-pixels SPX1 to SPX3 applicable to the display device are not particularly limited.

[0057] Figure 2A , Figure 2B , Figure 2C and Figure 2D It is shown that the Figure 1 A circuit diagram of one or more embodiments of a sub-pixel SPX in a display device.

[0058] In one or more embodiments, FIG. 2A to FIG. 2D The sub-pixel SPX shown in FIG. 1 may be arranged in Figure 1 Any one of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 in the display panel PNL of the display panel PNL. The first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may have substantially the same or similar structures.

[0059] refer to FIG. 2A to FIG. 2D The sub-pixel SPX may include a light source unit LSU configured to generate light having brightness corresponding to the data signal and a pixel circuit PXC configured to drive the light source unit LSU.

[0060] The light source unit LSU may include at least one light emitting element LD electrically connected between a first power source VDD and a second power source VSS. The first power source VDD and the second power source VSS may have different potentials to allow the light emitting element LD to emit light. For example, the first power source VDD may be set as a high potential power source, and the second power source VSS may be set as a low potential power source. Here, during at least an emission period of the sub-pixel SPX, the potential difference between the first power source VDD and the second power source VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0061] The light emitting element LD may emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit PXC. The light emitting element LD may be formed of an inorganic light emitting diode such as a micro light emitting diode or a quantum dot light emitting diode. In one or more embodiments, the light emitting element LD may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size, for example, in the range of nanometer to micrometer scale. The present disclosure is not limited thereto, and the light emitting element LD may be formed of an organic light emitting diode.

[0062] In one or more embodiments, the light source unit LSU may include a plurality of light emitting elements LD connected to each other in parallel.

[0063] like Figure 2B As shown in , the light source unit LSU may include a first electrode CNE1 electrically connected to a first power source VDD via a pixel circuit PXC and a first power line PL1, a second electrode CNE2 electrically connected to a second power source VSS via a second power line PL2, and a plurality of light emitting elements LD electrically connected to each other in the same direction between the first electrode CNE1 and the second electrode CNE2. In one or more embodiments, the first electrode CNE1 (or the first pixel electrode) may be an anode electrode or correspond to an anode electrode. The second electrode CNE2 (or the second pixel electrode) may be a cathode electrode or correspond to a cathode electrode.

[0064] Each of the light emitting elements LD may include a first end (e.g., a p-type end) electrically connected to a first power source VDD through a first electrode CNE1 and / or a pixel circuit PXC and a second end (e.g., an n-type end) electrically connected to a second power source VSS through a second electrode CNE2. In other words, the light emitting elements LD may be connected in parallel between the first electrode CNE1 and the second electrode CNE2 in a forward direction. Each light emitting element LD connected between the first power source VDD and the second power source VSS in the forward direction may be grouped to form an effective light source. Such an effective light source may form a light source unit LSU of a pixel PXL.

[0065] A first end (e.g., a p-type end) of the light emitting element LD may be commonly connected to the pixel circuit PXC through one electrode (e.g., a first electrode CNE1) of the light source unit LSU, and may be electrically connected to the first power supply VDD through the pixel circuit PXC and the first power line PL1. A second end (e.g., an n-type end) of the light emitting element LD may be commonly connected to the second power supply VSS through the second power line PL2 and another electrode (e.g., a second electrode CNE2) of the light emitting unit LSU.

[0066] In one or more embodiments, the light source unit LSU may include a plurality of light emitting elements LD connected in series to each other. That is, the light source unit LSU may include light emitting elements LD forming at least two series groups and connected in series / parallel to each other.

[0067] like Figure 2CAs shown in , the light source unit LSU may include light emitting elements LD that form two series groups and are connected in series / parallel to each other. In this case, each series group may include a pair of electrodes (e.g., two electrodes) and at least one light emitting element LD electrically connected between the pair of electrodes. Here, the number of light emitting elements LD forming the respective series groups may be the same as or different from each other. The number of light emitting elements LD in each series group is not particularly limited. For example, the first series group may include at least one first light emitting element LD1 electrically connected between the first electrode CNE1 and the intermediate electrode CTE (or the third electrode). The second series group may include at least one second light emitting element LD2 electrically connected between the intermediate electrode CTE and the second electrode CNE2.

[0068] like Figure 2D As shown in , the light source unit LSU may include light emitting elements LD that form four series groups and are connected in series / parallel to each other. For example, the first series group may include at least one first light emitting element LD1 electrically connected between the first electrode CNE1 and the first intermediate electrode CTE1. The second series group may include at least one second light emitting element LD2 electrically connected between the first intermediate electrode CTE1 and the second intermediate electrode CTE2. The third series group may include at least one third light emitting element LD3 electrically connected between the second intermediate electrode CTE2 and the third intermediate electrode CTE3. The fourth series group may include at least one fourth light emitting element LD4 electrically connected between the third intermediate electrode CTE3 and the second electrode CNE2.

[0069] Assuming that the light source unit LSU is configured to use light-emitting elements LD having the same conditions (e.g., the same size and / or number) as effective light sources, if the light-emitting elements LD are connected to each other in a series or series / parallel combination structure, power efficiency can be improved. For example, in the light source unit LSU in which the light-emitting elements LD are connected in a series or series / parallel structure, the brightness presented based on the same current can be higher than the case where the light-emitting elements LD are only connected in parallel to each other. In addition, in the light source unit LSU in which the light-emitting elements LD are connected in a series or series / parallel structure, the driving current required to present the same brightness can be reduced compared to the case in which the light-emitting elements LD are connected in parallel to each other. In addition, in the sub-pixel SPX in which the light-emitting elements LD are connected in a series or series / parallel combination structure, even if a short circuit defect or the like occurs in some series groups, a certain degree of brightness can be presented by the light-emitting elements LD of other series groups, thereby reducing the probability of black spot defects in the sub-pixel SPX.

[0070] The pixel circuit PXC may be electrically connected between the first power supply VDD and the light source unit LSU. The pixel circuit PXC may be electrically connected to the scan line Si (or gate line) and the data line Dj. In addition, the pixel circuit PXC may be further electrically connected to the sensing control line SSi and the sensing line SLj. For example, if the sub-pixel SPX is disposed on the i-th (i is a natural number) horizontal line (or row or pixel row) and the j-th (j is a natural number) vertical line (or column or pixel column) of the display area DA, the pixel circuit PXC of the sub-pixel SPX may be electrically connected to the i-th scan line Si, the i-th sensing control line SSi, the j-th data line Dj and the sensing line SLj of the display area DA.

[0071] In one or more embodiments, the pixel circuit PXC may include a plurality of transistors and at least one capacitor. For example, the pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst (eg, C1 and C2).

[0072] The first transistor T1 may be electrically connected between a first power supply VDD and a light source unit LSU. For example, a first electrode (or a first terminal, a first transistor electrode, for example, a drain electrode) of the first transistor T1 may be electrically connected to the first power supply VDD. A second electrode (or a second terminal, a second transistor electrode, for example, a source electrode) of the first transistor T1 may be electrically connected to one end (for example, an anode electrode) of the light source unit LSU. A gate electrode of the first transistor T1 is electrically connected to a first node N1. A back gate electrode of the first transistor T1 may be electrically connected to a second node N2. The first transistor T1 may control a driving current provided to the light source unit LSU in response to a voltage of the first node N1. In other words, the first transistor T1 may be a driving transistor configured to control a driving current of a sub-pixel SPX.

[0073] The second transistor T2 may be electrically connected between the data line Dj and the first node N1. For example, the first electrode of the second transistor T2 may be electrically connected to the data line Dj, and the second electrode of the second transistor T2 may be electrically connected to the first node N1. The gate electrode of the second transistor T2 is electrically connected to the scan line Si. When a scan signal SCi having a gate-on voltage (e.g., a high-level voltage) is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the first node N1 to the data line Dj. During each frame period, a data signal DSj of a corresponding frame is provided to the data line Dj, and the data signal DSj is transmitted to the first node N1 by the second transistor T2 that is turned on during the period in which the scan signal SCi having the gate-on voltage is provided. In other words, the second transistor T2 may be a switching transistor configured to transmit each data signal DSj to the inside of the sub-pixel SPX.

[0074] The third transistor T3 is electrically connected between the first transistor T1 and the sensing line SLj. For example, the first electrode of the third transistor T3 may be electrically connected to the sensing line SLj. The second electrode of the third transistor T3 may be electrically connected to the second node N2 (or the second electrode of the first transistor T1). The gate electrode of the third transistor T3 is connected to the sensing control line SSi. In the case where the sensing control line SSi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si (or the previous scan line on the row before the scan line Si or the next scan line after the scan line Si). The third transistor T3 may be turned on by a sensing control signal SSCi having a gate-on voltage and provided to the sensing control line SSi during a specific sensing period, so that the sensing line SLj and the first transistor T1 may be electrically connected to each other. In one or more embodiments, a specific reference voltage (or initialization voltage) may be applied to the sensing line SLj. The reference voltage may have a voltage level between the voltage of the first power supply VDD and the voltage of the second power supply VSS, but the present disclosure is not limited thereto.

[0075] The storage capacitor Cst (eg, C1 and C2) may be formed or electrically connected between the first node N1 and the second node N2. The storage capacitor Cst (eg, C1 and C2) may charge a voltage corresponding to the data signal DSj supplied to the first node N1 during each frame period.

[0076] In one or more embodiments, the storage capacitor Cst may include a first capacitor C1 and a second capacitor C2 separated from each other. The first capacitor C1 and the second capacitor C2 may be connected in parallel to each other between the first node N1 and the second node N2. The first electrode of each of the first capacitor C1 and the second capacitor C2 may be electrically connected to the second node N2. The second electrode of each of the first capacitor C1 and the second capacitor C2 may be electrically connected to the first node N1.

[0077] Although the following will refer to Figure 6 Description, but the first capacitor C1 and the second capacitor C2 may overlap each other. The storage capacitor Cst may include the first capacitor C1 and the second capacitor C2 instead of one capacitor, thereby having a maximized capacitance in a limited space (or plane space).

[0078] For reference, a parasitic capacitor (or parasitic capacitance) may be formed between the first node N1 and a signal line and / or a power line adjacent to the first node N1, or the first node N1 may be coupled to the signal line and / or the power line. The parasitic capacitor or coupling may affect the voltage (or voltage change) of the first node N1, so that the sub-pixel SPX may not emit light at a desired brightness. In the case where the capacitance of the storage capacitor Cst is maximized by the first capacitor C1 and the second capacitor C2, the influence of the parasitic capacitor formed between the first node N1 and other signal lines and / or power lines (e.g., the first power line PL1) may be mitigated or eliminated. In the case where the influence of the parasitic capacitor is eliminated, the sub-pixel SPX may accurately emit light at a desired brightness, and the quality of the image displayed on the display device may be improved.

[0079] although FIG. 2A to FIG. 2D The transistors (e.g., the first transistor T1, the second transistor T2, and the third transistor T3) included in the pixel circuit PXC are shown to be N-type transistors, but the present disclosure is not limited thereto. At least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be changed to a P-type transistor. In addition, the pixel circuit PXC may be a pixel circuit that may have various structures and / or be operated by various driving schemes.

[0080] Figure 3 to Figure 4 Each is shown in Figure 1 A layout diagram of an embodiment of a pixel in a display device of FIG. Figure 3 and Figure 4 In, focus on FIG. 2A to FIG. 2D The pixel circuit PXC (or pixel circuit layer) of the sub-pixel SPX shows the layout of the sub-pixel.

[0081] refer to Figures 1 to 4 , the pixel PXL may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may have substantially the same or similar pixel structures (or circuit structures). Therefore, the common configuration of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 will be described based on the first sub-pixel SPX1, and its redundant explanation will be omitted.

[0082] The first vertical power line PL1_V, the sensing lines SL1 to SL3, the data lines D1 to D3, and the second vertical power line PL2_V may extend substantially in the second direction DR2 and may be arranged along the first direction DR1. The sensing lines SL1 to SL3 may have a partially bent shape, but the present disclosure is not limited thereto.

[0083] The first vertical power line PL1_V may be disposed on the left side of the first capacitor electrode CE1 of the first sub-pixel SPX1. The sensing lines SL1 to SL3 and the data lines D1 to D3 may be disposed on the right side of the first capacitor electrode CE1 of the corresponding sub-pixel. For example, each of the first sensing line SL1 and the first data line D1 may be disposed on the right side of the first capacitor electrode CE1 of the first sub-pixel SPX1. The second vertical power line PL2_V may be disposed on the right side of the third sub-pixel SPX3 (or pixel PXL).

[0084] The first vertical power line PL1_V, the sensing lines SL1 to SL3 , the data lines D1 to D3 , the second vertical power line PL2_V, and the first capacitor electrode CE1 may include the same material and may be disposed at the same layer through the same process.

[0085] The second horizontal power line PL2_H, the gate line SC, and the first horizontal power line PL1_H may extend in the first direction DR1 and may be arranged along the second direction DR2. The second horizontal power line PL2_H and the gate line SC may be disposed on the upper side of the second capacitor electrode CE2 of the first subpixel SPX1. The first horizontal power line PL1_H may be disposed on the lower side of the second capacitor electrode CE2. The gate line SC may correspond to FIG. 2A to FIG. 2D The scan lines Si and the sensing control lines SSi shown in FIG.

[0086] The second horizontal power line PL2_H, the gate line SC, the first horizontal power line PL1_H, the second capacitor electrode CE2, and the first, second, and third bridge patterns BRP1, BRP2, and BRP3 (or connection patterns) may include the same material and may be disposed on the same layer through the same process.

[0087] The second capacitor electrode CE2 and the first capacitor electrode CE1 may overlap each other to form the first capacitor C1. In a plan view, most of the second capacitor electrode CE2 may be covered by the first capacitor electrode CE1. The surface area of ​​the second capacitor electrode CE2 may be smaller than the surface area of ​​the first capacitor electrode CE1. In order to increase or maximize the capacitance (or capacity) of the first capacitor C1, the first capacitor electrode CE1 may include a plurality of electrodes CE2 and CE12. Figure 4 Most of the portions other than the portions corresponding to the first contact hole CNT1 and the second contact hole CNT2 shown in FIG. 5 may overlap with the second capacitor electrode CE2 .

[0088] The second horizontal power line PL2_H may cross the second vertical power line PL2_V and may be connected to the second vertical power line PL2_V through a contact hole (and a bridge pattern) in the crossing region. The second horizontal power line PL2_H and the second vertical power line PL2_V may form an overall mesh structure and may form the second power line PL2 (refer to FIG. 2A to FIG. 2D ).

[0089] Likewise, the first horizontal power line PL1_H may cross the first vertical power line PL1_V and may be connected to the first vertical power line PL1_V through a contact hole (and a bridge pattern) in the crossing region. The first horizontal power line PL1_H and the first vertical power line PL1_V may form an overall mesh structure and may form the first power line PL1 (refer to Figure 2C ). The positions of the first horizontal power line PL1_H and the second horizontal power line PL2_H may be switched with each other.

[0090] The first semiconductor pattern ACT1 may be located on lower sides of the first and second capacitor electrodes CE1 and CE2 and may partially overlap the first and second capacitor electrodes CE1 and CE2. A central portion of the first semiconductor pattern ACT1 overlapping the first and second capacitor electrodes CE1 and CE2 may form a first transistor T1 (refer to Figure 2C ) channel. The second capacitor electrode CE2 may form a gate electrode of the first transistor T1. The first capacitor electrode CE1 may form a back gate electrode of the first transistor T1. A first portion (e.g., a lower portion) of the first semiconductor pattern ACT1 may be electrically connected to a protrusion of the first vertical power line PL1_V through a first bridge pattern BRP1 (and a contact hole). The first portion of the first semiconductor pattern ACT1 or the first bridge pattern BRP1 may be a first electrode of the first transistor T1. In an opening of the second capacitor electrode CE2 (i.e., an opening exposing the first capacitor electrode CE1), a second portion (e.g., an upper portion) of the first semiconductor pattern ACT1 may be electrically connected to a protrusion of the first vertical power line PL1_V through a first bridge pattern BRP1 (and a contact hole). Figure 4 ) and the first alignment electrode ELT1 (reference Figure 4 ) is electrically connected to the first capacitor electrode CE1. A second portion of the first semiconductor pattern ACT1 or the first alignment electrode ELT1 may be a second electrode of the first transistor T1.

[0091] The second semiconductor pattern ACT2 may be disposed on the upper side of the second capacitor electrode CE2 and may partially overlap the gate line SC. The central portion of the second semiconductor pattern ACT2 overlapping the gate line SC may form a channel of the second transistor T2. The gate line SC may form a gate electrode of the second transistor T2. The second portion of the second semiconductor pattern ACT2 may be electrically connected to the second capacitor electrode CE2. For example, the second capacitor electrode CE2 may contact the second portion of the second semiconductor pattern ACT2 through a contact hole. The second portion of the second semiconductor pattern ACT2 or the second capacitor electrode CE2 may be the second electrode of the second transistor T2. The first portion of the second semiconductor pattern ACT2 may be electrically connected to the first data line D1 through a second bridge pattern BRP2 (and a contact hole). The first portion of the second semiconductor pattern ACT2 or the second bridge pattern BRP2 may be the first electrode of the second transistor T2.

[0092] The third semiconductor pattern ACT3 may be disposed on the upper side of the first capacitor electrode CE1 and may partially overlap the gate line SC. A central portion of the third semiconductor pattern ACT3 overlapping the gate line SC may form a channel of the third transistor T3. The gate line SC may form a gate electrode of the third transistor T3. A second portion of the third semiconductor pattern ACT3 may be formed through the second contact hole CNT2 (reference Figure 4 ) and the first alignment electrode ELT1 (reference Figure 4 ) is electrically connected to the first capacitor electrode CE1. The second portion of the third semiconductor pattern ACT3 or the first alignment electrode ELT1 may be a second electrode of the third transistor T3. The first portion of the third semiconductor pattern ACT3 may be electrically connected to the first sensing line SL1 through the third bridge pattern BRP3 (and the contact hole). The first portion of the third semiconductor pattern ACT3 or the third bridge pattern BRP3 may be a first electrode of the third transistor T3.

[0093] The semiconductor patterns ACT1 to ACT3 may include the same material and may be disposed at the same layer by the same process. The semiconductor patterns ACT1 to ACT3 may include polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel (or channel region) of each of the semiconductor patterns ACT1 to ACT3 may be an undoped semiconductor pattern. The first and second portions (or regions outside the channel) of each of the semiconductor patterns ACT1 to ACT3 may be semiconductor patterns doped with impurities.

[0094] like Figure 4As shown in , the first alignment electrode ELT1 (or the first electrode or the first reflective electrode) and the second alignment electrode ELT2 (or the second electrode or the second reflective electrode) may extend in the second direction DR2 and may be arranged along the first direction DR1. For ease of explanation, the second alignment electrode ELT2 located on the right side of the first sub-pixel SPX1 (or the corresponding sub-pixel) will be referred to as the third alignment electrode ELT3 (or the third electrode or the third reflective electrode).

[0095] The second alignment electrode ELT2 may extend to a sub-pixel adjacent to the first sub-pixel SPX1 in the second direction DR2. In other words, the second alignment electrode ELT2 may extend across a plurality of sub-pixels. The second alignment electrode ELT2 may overlap the first vertical power line PL1_V (and the second vertical power line PL2_V). The second alignment electrode ELT2 may be electrically connected to the first vertical power line PL1_V through a contact hole.

[0096] The first alignment electrode ELT1 may be located between the second alignment electrode ELT2 and the third alignment electrode ELT3, and may be located between the second horizontal power line PL2_H and the first horizontal power line PL1_H in the second direction DR2. The first alignment electrode ELT1 may be separated from another first alignment electrode adjacent thereto in the second direction DR2, with the electrode opening ELO interposed therebetween. For example, the first alignment electrode ELT1 and the first alignment electrode adjacent thereto in the second direction DR2 may be formed as a single electrode, in other words, may be formed integrally with each other, and thereafter separated from each other by removing a portion of the single electrode corresponding to the electrode opening ELO. The first alignment electrode ELT1 may be provided in each of the sub-pixels SPX1 to SPX3 in the form of an island.

[0097] In a plan view, the first alignment electrode ELT1 may overlap the first capacitor electrode CE1 and the second capacitor electrode CE2, and may cover the first capacitor electrode CE1 and the second capacitor electrode CE2. The first alignment electrode ELT1 may overlap the second capacitor electrode CE2 to form a second capacitor C2. The second capacitor C2 and the first capacitor C1 (refer to Figure 3 ) can share the second capacitor electrode CE2. The first alignment electrode ELT1 can contact the first capacitor electrode CE1 through the first contact hole CNT1 or can be electrically connected to the first capacitor electrode CE1 through the first contact hole CNT1. Therefore, the first capacitor C1 and the second capacitor C2 can be connected to each other in parallel.

[0098] The first alignment electrode ELT1 may overlap with most of the circuit components of the first sub-pixel SPX1. For example, the first alignment electrode ELT1 may cover or shield the first transistor T1, the second transistor T2, and the third transistor T3 (or the channel or gate electrode of the third transistor T3). In this case, the components disposed on the first alignment electrode ELT1 may be prevented from affecting (or coupling with) the circuit components of the first sub-pixel SPX1 (for example, the second capacitor electrode CE2 or the gate electrode of the first transistor T1).

[0099] The bridging electrode BRE may be spaced apart or separated from the first alignment electrode ELT1 and the second alignment electrode ELT2, and may overlap with the second horizontal power line PL2_H. The bridging electrode BRE may contact the second horizontal power line PL2_H through a contact hole or may be electrically connected to the second horizontal power line PL2_H through a contact hole. For reference, the bridging electrode BRE and the first alignment electrode ELT1 may be formed as a single electrode, in other words, may be formed integrally with each other, and thereafter, the bridging electrode BRE may be separated from the first alignment electrode ELT1 by removing a portion of the single electrode corresponding to the electrode opening ELO. The bridging electrode BRE may be provided in each of the sub-pixels SPX1 to SPX3 in the form of an island.

[0100] The first alignment electrode ELT1 , the second alignment electrode ELT2 , and the bridge electrode BRE may include the same material, and may be provided at the same layer through the same process.

[0101] As described above, the first capacitor electrode CE1 and the second capacitor electrode CE2 may form a first capacitor C1. The second capacitor electrode CE2 and the first alignment electrode ELT1 may form a second capacitor C2. Therefore, the capacitance (or capacity) of the storage capacitor Cst (e.g., C1 and C2) may be sufficiently increased. In addition, the first alignment electrode ELT1 forming one electrode of the second capacitor C2 may cover or shield the second capacitor electrode CE2 (or the gate electrode of the first transistor T1). Therefore, the data signal may be more accurately charged or maintained in the storage capacitor Cst (or the gate electrode of the first transistor T1), and the sub-pixel may emit light at a target brightness more reliably, thereby improving the display quality.

[0102] Figure 5 is a diagram showing a method according to one or more embodiments of the present invention. Figure 1 1 is a plan view of a pixel PXL in a display device. Figure 5 based on Figure 2D The light source unit LSU of the sub-pixel SPX (reference Figure 2D) simply illustrates the pixel PXL. Because the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 of the pixel PXL may be substantially the same or similar to each other, the first subpixel SPX1 will be described as a representative example, and redundant explanations thereof will be omitted.

[0103] refer to Figures 1 to 5 , the alignment electrodes ELT1 to ELT3 may be used as alignment electrodes for aligning the light emitting element LD. During the process of manufacturing the display device, the light emitting element LD provided to the emission area EMA may be aligned in a desired direction and / or position by an electric field formed between the alignment electrodes ELT1 to ELT3. For example, the light emitting element LD may be arranged between the first alignment electrode ELT1 and the second alignment electrode ELT2 (or the third alignment electrode ELT3) so that the longitudinal direction of the light emitting element LD is substantially parallel to the first direction DR1.

[0104] The first electrode CNE1 may overlap the first end of the first light emitting element LD1 and the first alignment electrode ELT1. The first electrode CNE1 may electrically connect the first end of the first light emitting element LD1 to the first alignment electrode ELT1. Figure 4 As described, the first alignment electrode ELT1 may form one electrode of the storage capacitor Cst and may be connected to the second electrode of the first transistor T1 , so that the first electrode CNE1 may be electrically connected to the second electrode of the first transistor T1 .

[0105] The first intermediate electrode CTE1 may overlap the second end of the first light emitting element LD1 and the second alignment electrode ELT2 (or the third electrode ELT3). In addition, the first intermediate electrode CTE1 may overlap the first end of the second light emitting element LD2 and the first alignment electrode ELT1. To this end, a portion of the first intermediate electrode CTE1 may have a bent shape. The first intermediate electrode CTE1 may physically and / or electrically connect the second end of the first light emitting element LD1 to the first end of the second light emitting element LD2.

[0106] The second intermediate electrode CTE2 may overlap the second end of the second light emitting element LD2 and the second alignment electrode ELT2 (or the third electrode ELT3). In addition, the second intermediate electrode CTE2 may overlap the first end of the third light emitting element LD3 and the first alignment electrode ELT1. The second intermediate electrode CTE2 may have a shape that bypasses the first intermediate electrode CTE1. The second intermediate electrode CTE2 may physically and / or electrically connect the second end of the second light emitting element LD2 to the first end of the third light emitting element LD3.

[0107] The third intermediate electrode CTE3 may overlap the second end of the third light emitting element LD3 and the second alignment electrode ELT2. In addition, the third intermediate electrode CTE3 may be disposed to overlap the first end of the fourth light emitting element LD4 and the first alignment electrode ELT1. To this end, a portion of the third intermediate electrode CTE3 may have a bent shape. The third intermediate electrode CTE3 may physically and / or electrically connect the second end of the third light emitting element LD3 to the first end of the fourth light emitting element LD4.

[0108] The second electrode CNE2 may overlap the second end of the fourth light emitting element LD4 and the second alignment electrode ELT2. In addition, the second electrode CNE2 may overlap and contact the bridge electrode BRE. The second electrode CNE2 may electrically connect the second end of the fourth light emitting element LD4 to the bridge electrode BRE. Figure 4 As described, the bridge electrode BRE may be connected to the second horizontal power line PL2_H so that the second electrode CNE2 may be electrically connected to the second horizontal power line PL2_H (or the second power line PL2 ).

[0109] As described above, the light emitting elements LD1 to LD4 may be connected in series between the first electrode CNE1 and the second electrode CNE2. The shape of each of the alignment electrodes ELT1 to ELT3, the first electrode CNE1 and the second electrode CNE2, and the intermediate electrodes CTE1 to CTE3 may be changed in various ways according to the arrangement and / or series / parallel structure of the light emitting elements LD. In addition, at least one of the first intermediate electrode CTE1, the second intermediate electrode CTE2, or the third intermediate electrode CTE3 may be omitted.

[0110] Figure 6 It is shown along Figures 3 to 5 sectional views of an embodiment of a first sub-pixel taken along lines II' and II-II'.

[0111] although Figure 6 The first sub-pixel SPX1 (or sub-pixel) is simply illustrated, for example, it is illustrated that each electrode is formed of a single electrode and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0112] refer to Figures 3 to 6 , the first sub-pixel SPX1 may include a pixel circuit layer PCL and a display element layer DPL disposed on the substrate SUB.

[0113] For convenience, the pixel circuit layer PCL will be described first, and then the display element layer DPL will be described.

[0114] The pixel circuit layer PCL may include a first conductive layer (or a first metal layer), a first transistor T1, and a second conductive layer (or a second metal layer).

[0115] The first conductive layer may be disposed on the substrate SUB and include a first vertical power line PL1_V, a back gate electrode BGE, a first capacitor electrode CE1, a first sensing line SL1, and a first data line D1. The back gate electrode BGE may be a portion (or region) of the first capacitor electrode CE1 that overlaps the first semiconductor pattern ACT1 in a thickness direction (eg, third direction DR3) of the substrate SUB.

[0116] The first conductive layer may include a conductive material. For example, the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag) and / or an alloy thereof. The first conductive layer may have a single-layer structure, a double-layer structure or a multi-layer structure. For example, in order to reduce the line resistance, the first conductive layer may have a double-layer or multi-layer structure formed of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) and / or silver (Ag) as low-resistance materials.

[0117] The buffer layer BFL may be disposed and / or formed on the substrate SUB and the first conductive layer, and prevents impurities from diffusing into the first transistor T1. The buffer layer BFL may be an inorganic insulating layer including an inorganic material. For example, the inorganic material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ) and such as aluminum oxide (AlO x ). Although the buffer layer BFL may be provided as a single-layer structure, the buffer layer BFL may be provided as a multi-layer structure having at least two layers. In the case where the buffer layer BFL has a multi-layer structure, each layer may be formed of the same material or different materials. Depending on the material or process conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0118] The first semiconductor pattern ACT1 of the first transistor T1 may be disposed and / or formed on the buffer layer BFL. The first semiconductor pattern ACT1 may include a first contact region, a second contact region, and a channel region formed between the first contact region and the second contact region. The first contact region may contact the first transistor electrode TE1 (or the first bridge pattern BRP1). The second contact region may contact the second transistor electrode TE2 (or the first alignment electrode ELT1). The channel region may overlap with the gate electrode GE of the first transistor T1 in the third direction DR3. The first semiconductor pattern ACT1 may be a semiconductor pattern made of amorphous silicon, polycrystalline silicon, low temperature polycrystalline silicon, an oxide semiconductor, an organic semiconductor, etc. For example, the channel region may be a semiconductor pattern not doped with impurities, and may be an intrinsic semiconductor. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities.

[0119] The gate insulating layer GI may be disposed on the first semiconductor pattern ACT1 and the buffer layer BFL. The gate insulating layer GI may include an inorganic material. Various materials capable of providing insulating properties to the gate insulating layer GI may be used. For example, the gate insulating layer GI may be formed of an organic material. Although the gate insulating layer GI may be disposed in a single-layer structure, the gate insulating layer GI may be disposed in a multilayer structure having at least two layers.

[0120] The second conductive layer may be disposed on the gate insulating layer GI, and may include a first transistor electrode TE1 (or a first bridge pattern BRP1), a gate electrode GE of the first transistor T1, a second capacitor electrode CE2, and a second horizontal power line PL2_H. The gate electrode GE may overlap with the channel region of the first semiconductor pattern ACT1 in the third direction DR3. The second capacitor electrode CE2 may overlap with the first capacitor electrode CE1 to form a first capacitor C1. The second conductive layer may include a conductive material. The second conductive layer may include the same material as that of the first conductive layer, or include one or more materials selected from the materials exemplified as constituent materials of the first conductive layer.

[0121] The interlayer insulating layer ILD (or passivation layer PSV) may be disposed on the second conductive layer and the gate insulating layer GI. The interlayer insulating layer ILD (or passivation layer PSV) may include an organic material and / or an inorganic material. The organic material may include, for example, a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or a benzocyclobutene resin. For example, the interlayer insulating layer ILD may be configured to include an organic layer, an inorganic layer, or a structure of an organic layer disposed on an inorganic layer.

[0122] The display element layer DPL may be disposed on the interlayer insulating layer ILD (or the passivation layer PSV).

[0123] The display element layer DPL may include an alignment electrode layer, first and second bank patterns BNP1 and BNP2 (or banks), a light emitting element LD, first and second electrodes CNE1 and CNE2, and at least a first intermediate electrode CTE1. In addition, the display element layer DPL may include first and second insulating layers INS1 and INS2.

[0124] The alignment electrode layer may be disposed on the interlayer insulating layer ILD, and may include a first alignment electrode ELT1, a second alignment electrode ELT2, and a bridge electrode BRE.

[0125] The first alignment electrode ELT1 may contact the first semiconductor pattern ACT1 of the first transistor T1 and the first capacitor electrode CE1 (and the back gate electrode BGE). As described above, the first alignment electrode ELT1 together with the second capacitor electrode CE2 may form the second capacitor C2. Figure 4 and Figure 6 As shown in FIG, conductive components such as other signal lines or power lines other than the interlayer insulating layer ILD (or insulating layer) may not be disposed between the first alignment electrode ELT1 and the second capacitor electrode CE2. The first alignment electrode ELT1 together with the first electrode CNE1 may form an anode electrode of the first subpixel SPX1.

[0126] The second alignment electrode ELT2 may make contact with the vertical power line PL1_V through a contact hole or may be electrically connected with the vertical power line PL1_V through a contact hole, but the present disclosure is not limited thereto.

[0127] The bridge electrode BRE may make contact with the second horizontal power line PL2_H through the contact hole or may be electrically connected to the second horizontal power line PL2_H through the contact hole. The bridge electrode BRE may electrically connect the second electrode CNE2 to the second horizontal power line PL2_H.

[0128] During the process of manufacturing the display device, the first alignment electrode ELT1 (or the first alignment electrode ELT1 before being separated from the bridging electrode BRE) and the second alignment electrode ELT2 may be provided with a specific alignment signal (or alignment voltage) and used as an alignment line for aligning the light emitting element LD. For example, the first alignment electrode ELT1 may be provided with a first alignment signal (or first alignment voltage) from a component of the pixel circuit layer PCL (e.g., the second horizontal power line PL2_H), and thus used as a first alignment line. The second alignment electrode ELT2 may be provided with a second alignment signal (or second alignment voltage) from another component of the pixel circuit layer PCL (e.g., the first vertical power line PL1_V), and thus used as a second alignment line.

[0129] The alignment electrode layer may be made of a material having a specific reflectivity so that the light emitted from the light emitting element LD can travel in the image display direction (e.g., the third direction DR3) of the display device. The alignment electrode layer may be formed of a conductive material having a specific reflectivity. The conductive material may include an opaque metal that is suitable for reflecting the light emitted from the light emitting element LD in the image display direction of the display device. For example, the opaque metal may include metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti) and / or their alloys. In one or more embodiments, the alignment electrode layer may include a transparent conductive material. The transparent conductive material may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), transparent conductive oxides such as indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO), and / or conductive polymers such as poly (3,4-ethylenedioxythiophene) (PEDOT). In the case where the alignment electrode layer includes a transparent conductive material, a separate conductive layer formed of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device may be added. However, the material of the alignment electrode layer is not limited to the aforementioned materials.

[0130] The alignment electrode layer may be arranged and / or formed to have a single-layer structure, but the present disclosure is not limited thereto. In one or more embodiments, the alignment electrode layer may be arranged and / or formed to have a multilayer structure formed by stacking at least two materials of metal, alloy, conductive oxide, and conductive polymer. The alignment electrode layer may be formed by a multilayer structure including at least two layers to reduce or minimize distortion caused by signal delay when a signal (or voltage) is transmitted to the light-emitting element LD. For example, the first alignment electrode ELT1 may be formed by a multilayer structure formed by stacking layers in the order of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0131] The first bank pattern BNP1 and the second bank pattern BNP2 may be disposed and / or formed on the alignment electrode layer. For example, the first bank pattern BNP1 may be disposed on the first alignment electrode ELT1, and the second bank pattern BNP2 may be disposed on the second alignment electrode ELT2. The first bank pattern BNP1 and the second bank pattern BNP2 may be support components for supporting the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1. The first bank pattern BNP1 and the second bank pattern BNP2 may change the surface profile (or shape) of the first and second electrodes CNE1 and CNE2 and the first intermediate electrode CTE1.

[0132] In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 (or banks) may define an emission area EMA (refer to FIG. 1 ) of the first sub-pixel SPX1. Figure 5 The first bank pattern BNP1 and the second bank pattern BNP2 (or banks) may form a dam structure configured to prevent a solution including the light emitting element LD from being introduced into an adjacent pixel PXL in the step of providing the light emitting element LD on the first insulating layer INS1, or to control the amount of the solution so that a constant amount of the solution is provided to each sub-pixel.

[0133] Each of the first bank pattern BNP1 and the second bank pattern BNP2 may include an inorganic material or an organic material. In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may each include a single organic layer and / or a single inorganic layer, but the present disclosure is not limited thereto. In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may each be provided in the form of a multilayer structure formed by stacking at least one organic layer and at least one inorganic layer. However, the materials of the first bank pattern BNP1 and the second bank pattern BNP2 are not limited to the aforementioned embodiments. In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may include a conductive material.

[0134] The first bank pattern BNP1 and the second bank pattern BNP2 may each have a trapezoidal cross-section having a width that decreases in an upward direction (e.g., a third direction DR3), but the present disclosure is not limited thereto. In one or more embodiments, each of the first bank pattern BNP1 and the second bank pattern BNP2 may include a curved surface having a cross-sectional shape such as a semi-elliptical shape or a semi-circular shape (or a hemispherical shape) whose width decreases upward in the third direction DR3. The present disclosure is not limited thereto.

[0135] Although in the foregoing embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 are described as being disposed on the electrode layer, the present disclosure is not limited thereto. In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may be disposed between the electrode layer and the interlayer insulating layer ILD (or the passivation layer PSV). In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may be formed by the same process as that of the interlayer insulating layer ILD (or the passivation layer PSV). In this case, the first bank pattern BNP1 and the second bank pattern BNP2 may each be a region of the interlayer insulating layer ILD (or the passivation layer PSV). In one or more embodiments, the first bank pattern BNP1 and the second bank pattern BNP2 may be omitted.

[0136] The first insulating layer INS1 may be disposed and / or formed on the first and second bank patterns BNP1 and BNP2 and the electrode layers (eg, ELT1, ELT2). The first insulating layer INS1 may include an inorganic material. However, the present disclosure is not limited thereto. The first insulating layer INS1 may be formed of an organic insulating layer suitable for planarizing the support surface of the light emitting element LD.

[0137] The light emitting element LD may be disposed on the first insulating layer INS1 between the first bank pattern BNP1 and the second bank pattern BNP2. Also, in a plan view, the light emitting element LD may be aligned between the first alignment electrode ELT1 (or the first bank pattern BNP1) and the second alignment electrode ELT2 (or the second bank pattern BNP2).

[0138] The light emitting element LD may be formed by a light emitting diode made of a material having an inorganic crystal structure and having, for example, an ultra-small size ranging from nanometer to micrometer. For example, the light emitting element LD may include a first semiconductor layer, a second semiconductor layer, an active layer, and an insulating layer. The first semiconductor layer may include a semiconductor layer having a specific type. The second semiconductor layer may include a semiconductor layer having a type different from that of the first semiconductor layer. For example, the first semiconductor may include an N-type semiconductor layer, and the second semiconductor layer may include a P-type semiconductor layer. The first semiconductor layer and the second semiconductor layer may each include at least one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. The active layer may be located between the first semiconductor layer and the second semiconductor layer, and may have a single quantum well structure or a multi-quantum well structure. In the case where an electric field having a specific voltage or higher voltage is applied between the opposite ends of the light emitting element LD, light may be emitted by the coupling of electron-hole pairs in the active layer.

[0139] The number of light emitting elements LD provided to the first subpixel SPX1 may be at least two to several tens. In one or more embodiments, the number of light emitting elements LD provided to the first subpixel SPX1 may be changed in various ways.

[0140] The light emitting element LD may emit any one of colored lights and / or white light. In one or more embodiments, the light emitting element LD may emit blue light of a short wavelength band, but the present disclosure is not limited thereto.

[0141] The second insulating layer INS2 (or the second insulating pattern) may be disposed and / or formed on the light emitting element LD. The second insulating layer INS2 may be disposed and / or formed on the light emitting element LD and partially covers the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of each of the light emitting elements LD. The second insulating layer INS2 may prevent the active layer of the light emitting element LD from contacting an external conductive material. The second insulating layer INS2 may cover only a portion of the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the light emitting element LD so that the opposite end of the light emitting element LD may be exposed to the outside.

[0142] The second insulating layer INS2 may have a single layer or multilayer structure and include at least one inorganic material and / or organic material. After the alignment of the light emitting element LD is completed, the second insulating layer INS2 is formed on the light emitting element LD so as to prevent the light emitting element LD from moving away from the aligned position.

[0143] The first electrode CNE1 may be disposed on the first bank pattern BNP1 and the first alignment electrode ELT1, and may be connected to the first alignment electrode ELT1 through a contact hole passing through the first bank pattern BNP1. In addition, the first electrode CNE1 may be disposed / formed on the first end EP1 of the first light emitting element LD1, and may be connected to the first end EP1 of the light emitting element LD.

[0144] In one or more embodiments, in the case where a capping layer is disposed on the first alignment electrode ELT1, the first electrode CNE1 may be disposed on the capping layer and may be connected to the first alignment electrode ELT1 through the capping layer. The capping layer may protect the first alignment electrode ELT1 from defects that may occur during a process of manufacturing a display device, etc., and increase adhesion between the first alignment electrode ELT1 and a pixel circuit layer PCL disposed thereunder. The capping layer may include a transparent conductive material (or substance) such as indium zinc oxide (IZO).

[0145] The first intermediate electrode CTE1 may be disposed on the second bank pattern BNP2 and the second alignment electrode ELT2. In addition, the first intermediate electrode CTE1 may be disposed and / or formed on and connected to the second end EP2 of the light emitting element LD.

[0146] The second electrode CNE2 may be disposed on the second bank pattern BNP2 and the second alignment electrode ELT2. In addition, the second electrode CNE2 may overlap the bridge electrode BRE and may be connected to the bridge electrode BRE through a contact hole passing through the first insulating layer INS1. Figure 5As described above, the second electrode CNE2 can be electrically connected to the first intermediate electrode CTE1 through the light emitting element LD. Therefore, the second end EP2 of the light emitting element LD can be electrically connected to the bridge electrode BRE through the first intermediate electrode CTE1 and the second electrode CNE2. In one or more embodiments, in the case where the first intermediate electrode CTE1 is omitted (for example, in Figure 2B In the case of the sub-pixel SPX, the second end EP2 of the light emitting element LD may be electrically connected to the bridge electrode BRE through the second electrode CNE2.

[0147] In order to allow the light emitted from the light emitting element LD to travel without light loss in the image display direction of the display device, the first electrode CNE1, the second electrode CNE2 and the first intermediate electrode CTE1 may be formed of various transparent conductive materials. The materials of the first electrode CNE1, the second electrode CNE2 and the first intermediate electrode CTE1 are not limited to the above materials. In one or more embodiments, the first electrode CNE1, the second electrode CNE2 and the first intermediate electrode CTE1 may also be formed of various opaque conductive materials (or substances). The first electrode CNE1, the second electrode CNE2 and the first intermediate electrode CTE1 may each have a single-layer or multi-layer structure.

[0148] The shape of each of the first and second electrodes CNE1, CNE2 and the first intermediate electrode CTE1 may not be limited to a specific shape and may be changed in various ways within a range that can reliably electrically connect to the light emitting element LD. In addition, the shape of each of the first and second electrodes CNE1, CNE2 and the first intermediate electrode CTE1 may be changed in various ways in consideration of a connection relationship with an electrode disposed therebelow.

[0149] The first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode CTE1 may be separated from each other. For example, the first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode CTE1 may be separated from each other with the second insulating layer INS2 interposed therebetween. The first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode CTE1 may be formed on the same layer by the same process, but the present disclosure is not limited thereto. For example, at least two of the first electrode CNE1 and the second electrode CNE2 and the first intermediate electrode CTE1 may be disposed on different layers and formed by different processes.

[0150] In one or more embodiments, a third insulating layer (or overcoat layer) may be disposed and / or formed on the first and second electrodes CNE1, CNE2 and the first intermediate electrode CTE1. The third insulating layer may include an inorganic material or an organic material. For example, the third insulating layer may have a structure formed by alternately stacking at least one inorganic layer and at least one organic layer. The third insulating layer may cover the entire display element layer DPL and prevent external water or moisture from being introduced into the display element layer DPL including the light emitting element LD. The third insulating layer may flatten the upper surface of the display element layer DPL.

[0151] In one or more embodiments, the display element layer DPL may further selectively include an optical layer. For example, the display element layer DPL may further include a color conversion layer including color conversion particles for converting the color of light emitted from the light emitting element LD into a specific color. In addition, the display element layer DPL may further include a color filter configured to allow only light of a specific wavelength band to pass therethrough.

[0152] Fig. 7A and Figure 7B is a diagram showing a method according to one or more embodiments of the present invention. Figure 1 A cross-sectional view of a pixel in a display device of FIG. For the purpose of explanation, Fig. 7A and Figure 7B , individual components of the pixel circuit layer PCL and the display element layer DPL are schematically shown.

[0153] refer to Fig. 7A , the light-emitting elements LD disposed in the corresponding sub-pixels SPX1 to SPX3 may emit light of the same color. For example, the sub-pixels SPX1 to SPX3 may include a light-emitting element LD configured to emit light of a third color (e.g., blue light). A color conversion layer CCL (or color conversion component) and / or a color filter layer CFL may be disposed in the sub-pixels SPX1 to SPX3 so that a full-color image can be displayed. However, the present disclosure is not limited thereto. The sub-pixels SPX1 to SPX3 may include light-emitting elements LD configured to emit light of different colors.

[0154] The color conversion layer CCL may be disposed in the same layer as the display element layer DPL. For example, the color conversion layer CCL may be disposed between the banks BNK.

[0155] The bank BNK may be disposed in the non-emission area NEA of the sub-pixels SPX1 to SPX3. The bank BNK may be formed between the sub-pixels SPX1 to SPX3 to surround each emission area EMA, thereby defining the emission area EMA of each of the sub-pixels SPX1 to SPX3. The bank BNK may serve as a dam structure that prevents a solution for forming a wavelength conversion pattern WCP and a light transmission pattern LTP in each emission area EMA from being introduced into the emission area EMA of an adjacent sub-pixel, or controls the amount of the solution so that a specific amount of the solution is provided to each emission area EMA.

[0156] The bank BNK may include an organic material or an inorganic material. In one or more embodiments, the bank BNK may include a black matrix material (or a light blocking material). In this case, the bank BNK may prevent light generated from a sub-pixel (e.g., the second sub-pixel SPX2) from traveling to an adjacent sub-pixel (e.g., the first sub-pixel SPX1 or the third sub-pixel SPX3).

[0157] Openings through which the display element layer DPL is exposed may be formed in the bank BNK at respective positions corresponding to the emission areas EMA.

[0158] The color conversion layer CCL may include wavelength conversion patterns (or color conversion particles) WCP, light transmissive patterns LTP, and a first capping layer CAP1. The wavelength conversion patterns WCP may include first and second wavelength conversion patterns WCP1 and WCP2.

[0159] The first wavelength conversion pattern WCP1 may be disposed to overlap the emission area EMA of the first sub-pixel SPX1. For example, the first wavelength conversion pattern WCP1 may be disposed in a corresponding opening of the bank BNK. The second wavelength conversion pattern WCP2 may be disposed to overlap the emission area EMA of the second sub-pixel SPX2. The light transmission pattern LTP may be disposed to overlap the emission area EMA of the third sub-pixel SPX3.

[0160] In one or more embodiments, the first wavelength conversion pattern WCP1 may include first color conversion particles for converting light of a third color emitted from the light emitting element LD into light of a first color. For example, in the case where the light emitting element LD is a blue light emitting element configured to emit blue light and the first sub-pixel SPX1 is a red pixel, the first wavelength conversion pattern WCP1 may include first quantum dots for converting blue light emitted from the blue light emitting element into red light.

[0161] For example, the first wavelength conversion pattern WCP1 may include a plurality of first quantum dots dispersed in a suitable matrix material (e.g., a predetermined matrix material) such as a base resin. The first quantum dots may absorb blue light, change its wavelength according to energy conversion, and thus emit red light. In the case where the first sub-pixel SPX1 is a pixel configured to emit light of a different color, the first wavelength conversion pattern WCP1 may include first quantum dots corresponding to the color of the first sub-pixel SPX1.

[0162] In one or more embodiments, the second wavelength conversion pattern WCP2 may include second color conversion particles for converting light of a third color emitted from the light emitting element LD into light of a second color. For example, when each light emitting element LD is a blue light emitting element configured to emit blue light and the second sub-pixel SPX2 is a green pixel, the second wavelength conversion pattern WCP2 may include second quantum dots for converting blue light emitted from the blue light emitting element into green light.

[0163] For example, the second wavelength conversion pattern WCP2 may include a plurality of second quantum dots dispersed in a suitable matrix material (eg, a predetermined matrix material) such as a base resin. The second quantum dots may absorb blue light, change its wavelength according to energy conversion, and thus emit green light.

[0164] The first quantum dot and the second quantum dot may each have a spherical shape, a pyramid shape, a multi-arm shape or a cubic shape of nanoparticles, nanotubes, nanofibers, planar nanoparticles, etc., but the present disclosure is not limited thereto. The shape of each of the first quantum dot and the second quantum dot may be changed in various ways.

[0165] In one or more embodiments, when blue light having a relatively short wavelength in the visible light region is incident on each of the first quantum dot and the second quantum dot, the absorption coefficient of the first quantum dot and the second quantum dot can be increased. Ultimately, the efficiency of light emitted from each of the first subpixel SPX1 and the second subpixel SPX2 can be enhanced, and satisfactory color reproducibility can be ensured. In addition, the pixel PXL can be formed by a light-emitting element (e.g., a blue light-emitting element) configured to emit light of the same color, thereby improving the production efficiency of the display device.

[0166] In one or more embodiments, the light-transmitting pattern LTP may be configured to effectively use the light of the third color emitted from the light-emitting element LD. For example, in the case where each light-emitting element LD is a blue light-emitting element configured to emit blue light and the third subpixel SPX3 is a blue pixel, the light-transmitting pattern LTP may include at least one type of light scattering particles to effectively use the light emitted from the light-emitting element LD.

[0167] For example, the light-transmitting pattern LTP may include a plurality of light-scattering particles dispersed in a suitable matrix material (e.g., a predetermined matrix material) such as a base resin. For example, the light-transmitting pattern LTP includes light-scattering particles made of a material such as silicon dioxide, but the constituent material of the light-scattering particles is not limited thereto.

[0168] The light scattering particles need not be disposed only in the emission area EMA of the third sub-pixel SPX3 For example, the light scattering particles may also be selectively included in the first wavelength conversion pattern WCP1 and / or the second wavelength conversion pattern WCP2.

[0169] The first capping layer CAP1 may seal (or cover) the wavelength conversion pattern WCP and the light transmission pattern LTP. The first capping layer CAP1 may be disposed between the low refractive layer LRL and the display element layer DPL. The first capping layer CAP1 may be disposed across the sub-pixels SPX1 to SPX3. The first capping layer CAP1 may prevent the color conversion layer CCL from being damaged or contaminated by penetration of external impurities such as water or air.

[0170] In one or more embodiments, the first capping layer CAP1 may have a single-layer or multi-layer structure, wherein the single-layer or multi-layer structure includes a silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium dioxide (TiO x ) in at least one insulating material, but the present disclosure is not limited thereto.

[0171] The optical layer OPL may include a low refractive layer LRL and a second capping layer CAP2. The optical layer OPL may be disposed on the color conversion layer CCL. The optical layer OPL may be disposed on the display element layer DPL.

[0172] The low refractive layer LRL may be disposed between the first capping layer CAP1 and the second capping layer CAP2. The low refractive layer LRL may be disposed between the color conversion layer CCL and the color filter layer CFL. The low refractive layer LRL may be disposed across the sub-pixels SPX1 to SPX3.

[0173] The low refraction layer LRL may serve to recycle light provided from the color conversion layer CCL through total reflection and thus improve light efficiency. Therefore, the low refraction layer LRL may have a relatively low refractive index compared to the refractive index of the color conversion layer CCL.

[0174] In one or more embodiments, the low refractive layer LRL may include a base resin and hollow particles dispersed in the base resin. The hollow particles may be hollow silica particles. Alternatively, the hollow particles may have pores formed by a porogen, but the present disclosure is not limited thereto. In addition, the low refractive layer LRL may include zinc oxide (ZnO) particles, titanium dioxide (TiO 2 ) particles or at least one of nanosilicate particles, but the present disclosure is not limited thereto.

[0175] The second capping layer CAP2 may be disposed on the low refractive layer LRL. The second capping layer CAP2 may be disposed between the color filter layer CFL and the low refractive layer LRL. The second capping layer CAP2 may be disposed across the sub-pixels SPX1 to SPX3. The second capping layer CAP2 may prevent the low refractive layer LRL from being damaged or contaminated by the penetration of external impurities such as water or air. The second capping layer CAP2 may include the same material as that of the first capping layer CAP1, or may include one or more materials selected from the materials exemplified as the constituent materials of the first capping layer CPA1.

[0176] The color filter layer CFL may be disposed on the second capping layer CAP2. The color filter layer CFL may be disposed across the sub-pixels SPX1 to SPX3. The color filter layer CFL may include color filters CF1 to CF3, a planarization layer PLA, and an overcoat layer OC.

[0177] In one or more embodiments, the color filters CF1 to CF3 may be disposed on the second capping layer CAP2. In a plan view, the color filters CF1 to CF3 may overlap the corresponding emission areas EMA of the sub-pixels SPX1 to SPX3.

[0178] In one or more embodiments, the first color filter CF1 may allow light of a first color to pass therethrough and prevent light of a second color and light of a third color from passing therethrough. For example, the first color filter CF1 may include a colorant of a first color.

[0179] In one or more embodiments, the second color filter CF2 may allow the second color light to pass therethrough and prevent the first color light and the third color light from passing therethrough. For example, the second color filter CF2 may include a colorant of the second color.

[0180] In one or more embodiments, the third color filter CF3 may allow the third color light to pass therethrough and prevent the first color light and the second color light from passing therethrough. For example, the third color filter CF3 may include a colorant of the third color.

[0181] In one or more embodiments, the planarization layer PLA may be disposed on the color filters CF1 to CF3. The planarization layer PLA may cover the color filters CF1 to CF3. The planarization layer PLA may remove the step difference caused by the color filters CF1 to CF3. The planarization layer PLA may be disposed across the sub-pixels SPX1 to SPX3.

[0182] In one or more embodiments, the planarization layer PLA may include an organic material, but the present disclosure is not limited thereto. That is, the planarization layer PLA may include an inorganic material.

[0183] The overcoat layer OC may be disposed on the planarization layer PLA. The overcoat layer OC may be disposed between the upper film layer UFL and the planarization layer PLA. The overcoat layer OC may be disposed across the sub-pixels SPX1 to SPX3. The overcoat layer OC may cover the lower component including the color filter layer CFL. The overcoat layer OC may prevent water or air from penetrating into the lower component. In addition, the overcoat layer OC may protect the lower component from foreign matter such as dust.

[0184] The overcoat layer OC may include an organic material or an inorganic material. For example, the overcoat layer OC may include one or more materials selected from the materials exemplified as the constituent materials of the planarization layer PLA.

[0185] The upper film layer UFL may be disposed on the color filter layer CFL. The upper film layer UFL may be disposed in a peripheral portion of the display device to reduce external influences on the display device. The upper film layer UFL may be disposed across the sub-pixels SPX1 to SPX3.

[0186] In one or more embodiments, the upper film layer UFL may include an anti-reflection (AR) coating. The AR coating may refer to a component formed by applying a material having an anti-reflection function to the surface of a specific component. Here, the applied material may have a low reflectivity. In one or more embodiments, the material used to form the AR coating may include silicon oxide (SiO x ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) Any one of. However, the present disclosure is not limited thereto, and various known materials can be used.

[0187] Although already Fig. 7A 4. It is described in FIG. 5 that the color conversion layer CCL is provided on the same layer as that of the display element layer DPL, but the present disclosure is not limited thereto.

[0188] refer to Figure 7B, the color conversion layer CCL may be disposed on the display element layer DPL. For example, the first capping layer CAP1 may seal (or cover) a region in which the light emitting element LD is disposed. The color conversion layer CCL may be disposed on the first capping layer CAP1.

[0189] In one or more embodiments, the color conversion layer CCL may further include a light blocking layer LBL (or a light blocking pattern). The light blocking layer LBL may be disposed on the display element layer DPL and the first capping layer CAP1. The light blocking layer LBL may be disposed between the first capping layer CAP1 and the second capping layer CAP2. The light blocking layer LBL may be disposed in a boundary between the sub-pixels SPX1 to SPX3 (e.g., in the non-emission area NEA) to surround the first wavelength conversion pattern WCP1, the second wavelength conversion pattern WCP2, and the light transmission pattern LTP.

[0190] The light blocking layer LBL may define an emission area EMA and a non-emission area NEA. For example, in a plan view, the light blocking layer LBL may not overlap with the emission area EMA. In a plan view, the light blocking layer LBL may overlap with the non-emission area NEA. In an embodiment, a region where the light blocking layer LBL is not provided may be defined as an emission area EMA of the sub-pixels SPX1 to SPX3.

[0191] In one or more embodiments, the light blocking layer LBL may be formed of an organic material including at least one of graphite, carbon block, black pigment, or black dye, or of a metal including chromium (Cr). The material of the light blocking layer LBL is not limited as long as the material can prevent light transmission and absorb light.

[0192] The second capping layer CAP2 may seal (or cover) the first wavelength conversion pattern WCP1 , the second wavelength conversion pattern WCP2 , and the light transmitting pattern LTP.

[0193] The low refractive layer LRL may be disposed between the second capping layer CAP2 and the third capping layer CAP3. The third capping layer CAP3 may include the same material as that of the first capping layer CPA1, or may include one or more materials selected from the materials exemplified as the constituent materials of the first capping layer CPA1. The color filter layer CFL and the upper film layer UFL may be disposed on the first capping layer CPA1.

[0194] Figure 8 It is used to describe manufacturing Figure 1 Layout diagram of the process of display device. Figure 8 Can correspond to Figure 4 .

[0195] refer to Figure 1 , Figures 3 to 6 as well as Figure 8, an electrode layer may be formed on the interlayer insulating layer ILD. The electrode layer may include a reference alignment electrode ELT0 (or a first alignment line) and a second alignment electrode ELT2 (or a second alignment line). The reference alignment electrode ELT0 may be Figure 4 The first alignment electrode ELT1 and the bridge electrode BRE are separated from each other before. In a manner similar to the second alignment electrode ELT2, the reference alignment electrode ELT0 may extend to a sub-pixel adjacent to the first sub-pixel SPX1 in the second direction DR2.

[0196] Thereafter, a Figure 6 The first and second bank patterns BNP1 and BNP2 (or banks) shown in FIG. 1 may form a first insulating layer INS1 on the electrode layer and the first and second bank patterns BNP1 and BNP2.

[0197] Subsequently, the light emitting element LD may be provided to the emission area EMA (refer to Figure 5 ). For example, the light emitting element LD may be prepared in a diffused form in a suitable solution (eg, a predetermined solution, such as ink), and then provided to the emission area EMA through an inkjet printing scheme, a slit coating scheme, or the like.

[0198] While or after providing the light emitting element LD, an alignment signal may be applied to the reference alignment electrode ELT0 and the second alignment electrode ELT2. For example, a ground voltage may be applied to the reference alignment electrode ELT0 and an AC voltage may be applied to the second alignment electrode ELT2, but the present disclosure is not limited thereto.

[0199] If an alignment signal is applied to the reference alignment electrode ELT0 and the second alignment electrode ELT2 , an electric field may be formed between the reference alignment electrode ELT0 and the second alignment electrode ELT2 , so that the light emitting element LD may be self-aligned between the reference alignment electrode ELT0 and the second alignment electrode ELT2 .

[0200] After the light emitting element LD is aligned, the solvent may be removed by volatilization or other methods.

[0201] Afterwards, it can be formed Figure 6 The second insulating layer INS2 is shown in FIG.

[0202] Subsequently, by removing the electrode opening ELO (reference alignment electrode ELTO) of the reference alignment electrode ELTO, Figure 4 ) corresponding to a portion, the reference alignment electrode ELT0 can be divided into the first alignment electrode ELT1 and the bridge electrode BRE. For reference, the reference alignment electrode ELT0 can be removed by removing the reference alignment electrode ELT0 from the electrode opening ELO. Figure 6Therefore, the alignment electrode and the first insulating layer INS1 may not exist or be disposed Figure 4 An opening corresponding to the electrode opening ELO may be formed in the first insulating layer INS1 (ie, a boundary region between sub-pixels adjacent in the second direction DR2 ).

[0203] Afterwards, it can be formed Figure 6 In one or more embodiments, the first electrode CNE1 and the second electrode CNE2 (and the first intermediate electrode CTE1) may be formed continuously. Fig. 7A and Figure 7B The color conversion layer CCL, the color filter layer CFL, etc. shown in FIG.

[0204] As described above, the first alignment electrode ELT1 (or reference alignment electrode ELT0) may be used as an electrode for aligning the light emitting element LD during a process of manufacturing a display device. After the light emitting element LD is aligned, the first alignment electrode ELT1 may be separated from the bridge electrode BRE and used as one electrode of the storage capacitor Cst.

[0205] Fig. 9 is a diagram showing a method according to one or more embodiments of the present invention. Figure 1 The layout of pixels in a display device. Fig. 9 In, focus on FIG. 2A to FIG. 2D The pixel circuit PXC (or pixel circuit layer) of the sub-pixel SPX shows the layout of the sub-pixel. Fig. 9 Can correspond to Figure 3 . Fig.10 is a diagram showing a method of performing a Fig. 9 sectional views of the first sub-pixel taken along lines III-III' and II-II'. Fig.10 Can correspond to Figure 6 .

[0206] refer to Figure 1 , Figures 3 to 6 as well as Fig. 9 and Fig.10 , except for the second capacitor electrode CE2_1 and the fourth bridge pattern BRP4, Fig. 9 and Fig.10 The pixel PXL can be used with Figures 3 to 6 The pixels PXL are substantially the same or similar. Therefore, repeated explanation thereof will be omitted.

[0207] The second capacitor electrode CE2_1 may be included in the same layer as the first semiconductor pattern ACT1. Fig. 9As shown in , the second capacitor electrode CE2_1 may be formed integrally with the second semiconductor pattern ACT2. For example, the second capacitor electrode CE2_1 may be a partial region of the second semiconductor pattern ACT2 doped with impurities. However, the present disclosure is not limited thereto. For example, the second capacitor electrode CE2_1 may be a separate semiconductor pattern separated from the second semiconductor pattern ACT2.

[0208] The second capacitor electrode CE2_1 may overlap with the first capacitor electrode CE1 to form the first capacitor C1_1. In a plan view, most of the second capacitor electrode CE2_1 may be covered by the first capacitor electrode CE1 in the third direction DR3. The surface area of ​​the second capacitor electrode CE2_1 may be smaller than the surface area of ​​the first capacitor electrode CE1. In order to increase or maximize the capacitance (or capacity) of the first capacitor C1, the second capacitor electrode CE2_1 may overlap with the first capacitor electrode CE1 except for the first capacitor electrode CE1. Figure 4 The first contact hole CNT1 and the second contact hole CNT2 shown in FIG. 1 overlap with most of the area other than the area corresponding to the fourth bridge pattern BRP4 forming the gate electrode of the first transistor T1 .

[0209] Fig. 9 and Fig.10 The pixel PXL may include Figure 5 The light source unit LSU shown in Figure 2D ) of the components (ie, the first alignment electrodes ELT1 and the second alignment electrodes ELT2, the bridging electrode BRE, etc.).

[0210] In this case, if Fig.10 As shown in , the first alignment electrode ELT1 may overlap the second capacitor electrode CE2_1 to form the second capacitor C2_1. The second capacitor C2_1 and the first capacitor C1_1 may share the second capacitor electrode CE2_1. Because the first alignment electrode ELT1 contacts the first capacitor electrode CE1 through the first contact hole CNT1 or is electrically connected to the first capacitor electrode CE1 through the first contact hole CNT1, the first capacitor C1_1 and the second capacitor C2_1 may be connected to each other in parallel.

[0211] The fourth bridge pattern BRP4 may be included in the same layer as the gate electrode of the first transistor T1 and the other bridge patterns BRP1 to BRP3. In other words, the fourth bridge pattern BRP4 may be included in the reference Figure 6One end (e.g., an upper end) of the fourth bridge pattern BRP4 may overlap with the second capacitor electrode CE2_1 and may contact with the second capacitor electrode CE2_1 through a contact hole or may be connected to the second capacitor electrode CE2_1 through a contact hole. The remaining end (e.g., a lower end) of the fourth bridge pattern BRP4 may overlap with the first semiconductor pattern ACT1 to form a gate electrode of the first transistor T1.

[0212] A capacitor may be formed between the fourth bridge pattern BRP4 and the first capacitor electrode CE1, and may also be formed between the fourth bridge pattern BRP4 and the first alignment electrode ELT1. The capacitor may be included in the storage capacitor Cst.

[0213] As described above, the first capacitor electrode CE1 and the second capacitor electrode CE2_1 (and the fourth bridge pattern BRP4) as the doped semiconductor pattern (e.g., a partial region of the second semiconductor pattern ACT2) may form a first capacitor C1_1. The second capacitor electrode CE2_1 (and the fourth bridge pattern BRP4) and the first alignment electrode ELT1 may form a second capacitor C2_1. Therefore, the capacitance (or capacity) of the storage capacitor Cst may be increased, and the sub-pixel may emit light accurately at a target brightness, thereby improving display quality.

[0214] Despite Figure 6 and Fig.10 It has been described that each of the second capacitor electrodes CE2 and CE2_1 as the common electrode of the first capacitor C1 and the second capacitor C2 is a gate electrode or a semiconductor pattern, but the present disclosure is not limited thereto. For example, a portion of the common electrode may be formed in the same layer as the gate electrode, and the remaining portion of the common electrode may be formed of a semiconductor pattern.

[0215] Fig.11 is a diagram showing a light emitting element according to one or more embodiments. Fig.11 A pillar-type light emitting element LD is shown, but the type and / or shape of the light emitting element LD is not limited thereto.

[0216] refer to Fig.11 , the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, if the direction in which the light emitting element LD extends refers to a longitudinal direction (L), the light emitting element LD may include the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 continuously stacked in the longitudinal direction (L).

[0217] The light emitting element LD may be provided in a columnar shape extending in one direction. The light emitting element LD may include a first end EP1 and a second end EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided on the first end EP1 of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided on the second end EP2 of the light emitting element LD.

[0218] In one or more embodiments, the light emitting element LD may be a light emitting element manufactured in the form of a column by an etching scheme or the like. In this specification, the term "column type" includes a rod-like shape and a bar-like shape (such as a cylindrical shape and a prism shape) extending in the longitudinal direction (ie, having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0219] The light emitting element LD may have a small size corresponding to a range from nanometer level to micrometer level. For example, the light emitting element LD may have a diameter D (or width) and / or a length L ranging from nanometer level to micrometer level. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., display devices) using a light emitting device having the light emitting element LD as a light source.

[0220] The first semiconductor layer 11 may be a first conductive semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer including any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material for forming the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be formed of various other materials.

[0221] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be changed in various ways according to the type of the light emitting element LD.

[0222] A cladding layer doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of AlGaN or InAlGaN. In one or more embodiments, the active layer 12 may be formed using a material such as AlGaN or InAlGaN, and various other materials may be used to form the active layer 12.

[0223] The second semiconductor layer 13 may be disposed on the active layer 12, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include a p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including any one semiconductor material selected from InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material for forming the second semiconductor layer 13 is not limited thereto, and various other materials may be used to form the second semiconductor layer 13.

[0224] If a voltage equal to or greater than the threshold voltage is applied between opposite ends of the light emitting element LD, the light emitting element LD can emit light by coupling of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as various light emitting devices of a display device and a light source of a pixel.

[0225] The light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the active layer 12, and may also surround a region of each of the first semiconductor layer 11 and the second semiconductor layer 13.

[0226] In one or more embodiments, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may allow one end of each of the first semiconductor layer 11 and the second semiconductor layer 13 disposed on the first end EP1 and the second end EP2 of the light emitting element LD to be exposed. In one or more embodiments, the insulating film INF may allow a side portion of each of the first semiconductor layer 11 and the second semiconductor layer 13 adjacent to the first end EP1 and the second end EP2 of the light emitting element LD having different polarities to be exposed.

[0227] In one or more embodiments, the insulating film INF may have a layer including a silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) and titanium oxide (TiO x ) of at least one insulating material (e.g., a single layer structure or a multilayer structure of aluminum oxide (AlO x ) and silicon oxide (SiO x) formed of a double-layer structure). However, the present disclosure is not limited thereto. In one or more embodiments, the insulating film INF may be omitted.

[0228] When the insulating film INF is provided to cover the surface of the light emitting element LD (specifically, the outer surface (e.g., the outer peripheral surface or the outer circumferential surface) of the active layer 12), the active layer 12 can be prevented from being short-circuited with the first pixel electrode or the second pixel electrode to be described below. Therefore, the electrical stability of the light emitting element LD can be ensured.

[0229] If the insulating film INF is provided on the surface of the light emitting element LD, defects on the surface of the light emitting element LD can be reduced or minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, even when a plurality of light emitting elements LD are provided adjacent to each other, an undesirable short circuit between the light emitting elements LD can be prevented.

[0230] In one or more embodiments, the light emitting element LD may further include additional components in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF surrounding the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13. For example, the light emitting element LD may further include at least one fluorescent layer, at least one active layer, at least one semiconductor layer, and / or at least one electrode layer disposed on one end of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13. For example, a contact electrode layer may be disposed on each of the first end EP1 and the second end EP2 of the light emitting element LD. Although Fig.11 A pillar-type light emitting element LD is shown, but the type, structure and / or shape of the light emitting element LD may be changed in various ways. For example, the light emitting element LD may be formed of a core-shell structure having a polygonal pyramid shape.

[0231] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in a display device, but also in various devices that require a light source. For example, a plurality of light-emitting elements LD can be arranged in each pixel of a display panel, so that the light-emitting element LD can be used as a light source of the pixel. However, the application field of the light-emitting element LD is not limited to the aforementioned example. For example, the light-emitting element LD can also be used in other types of devices (such as lighting equipment) that require a light source.

[0232] While various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure.

[0233] Therefore, the embodiments disclosed in this specification are only for illustrative purposes, rather than limiting the technical spirit of the present disclosure. The scope of the present disclosure must be defined by the appended claims and their equivalents.

Claims

1. Display equipment, including: Semiconductor patterning; a first capacitor electrode under the semiconductor pattern; a second capacitor electrode on the semiconductor pattern, the second capacitor electrode including a portion forming a gate electrode; a first electrode and a second electrode at a same layer on the second capacitor electrode; at least one light emitting element between the first electrode and the second electrode; a first pixel electrode on the first electrode and connected to a first end of the at least one light emitting element; as well as a second pixel electrode on the second electrode and connected to a second end of the at least one light emitting element, wherein the first electrode is electrically connected to the first capacitor electrode and the semiconductor pattern, wherein the semiconductor pattern and the gate electrode form a transistor, wherein a first capacitor is formed by the first capacitor electrode and the second capacitor electrode, and The second capacitor is formed by the second capacitor electrode and the first electrode.

2. The display device according to claim 1, wherein: A signal line and a power line are not at a layer between the second capacitor electrode and the first electrode.

3. The display device according to claim 2, wherein: At least one of a source electrode and a drain electrode of the transistor is at the same layer as the second capacitor electrode.

4. The display device according to claim 2, wherein: A data line connected to the transistor is at the same layer as the first capacitor electrode.

5. The display device according to claim 4, wherein: The power line connected to the transistor is at the same layer as at least one of the first capacitor electrode and the second capacitor electrode.

6. The display device according to claim 1, wherein: The first pixel electrode is electrically connected to the transistor through the first electrode.

7. The display device according to claim 1, further comprising a bridge electrode at the same layer as the first electrode and the second electrode and spaced apart from the first electrode and the second electrode, in, The second pixel electrode is connected to a power line through the bridge electrode.

8. The display device according to claim 7, wherein: In a plan view, the second electrode extends across a plurality of sub-pixels, and Each of the first electrode and the bridge electrode has an island shape in each of the plurality of sub-pixels.

9. The display device according to claim 7, wherein: a first insulating layer on the first electrode and the second electrode, and The first insulating layer is not in a boundary region between two adjacent sub-pixels among the plurality of sub-pixels.

10. The display device according to claim 1, wherein: In a plan view, the first electrode covers the first capacitor electrode and the second capacitor electrode.

11. The display device according to claim 10, wherein: The first electrode is connected to the first capacitor electrode and the semiconductor pattern through the opening of the second capacitor electrode.

12. The display device according to claim 1, further comprising: a wavelength conversion pattern on the at least one light emitting element and configured to convert a wavelength band of light incident on the wavelength conversion pattern from the at least one light emitting element to a desired wavelength band and emit the light; as well as A color filter is on the wavelength conversion pattern.

13. The display device according to claim 1, wherein: The at least one light emitting element includes inorganic light emitting diodes connected in parallel with each other.

14. Display equipment, including: Semiconductor patterning; a first capacitor electrode under the semiconductor pattern; a gate electrode on the semiconductor pattern; a first electrode and a second electrode at a same layer on the gate electrode; at least one light emitting element between the first electrode and the second electrode; a first pixel electrode on the first electrode and connected to a first end of the at least one light emitting element; as well as a second pixel electrode on the second electrode and connected to a second end of the at least one light emitting element, wherein the first electrode is electrically connected to the first capacitor electrode and the semiconductor pattern, wherein the semiconductor pattern and the gate electrode form a transistor, wherein the portion of the semiconductor pattern doped with impurities forms a second capacitor electrode, wherein a first capacitor is formed by the first capacitor electrode and the second capacitor electrode, and The second capacitor is formed by the second capacitor electrode and the first electrode overlapping the second capacitor electrode.

15. The display device according to claim 14, wherein: The gate electrode is electrically connected to the second capacitor electrode.

16. The display device according to claim 14, wherein: A signal line and a power line are not at a layer between the second capacitor electrode and the gate electrode.

17. The display device according to claim 16, wherein: Each of the data line and the power line connected to the transistor is at the same layer as at least one of the first capacitor electrode and the second capacitor electrode.

18. The display device according to claim 14, further comprising a bridge electrode at the same layer as the first electrode and the second electrode and spaced apart from the first electrode and the second electrode, in, The second pixel electrode is connected to a power line through the bridge electrode.

19. The display device according to claim 18, wherein: a first insulating layer on the first electrode and the second electrode, and The first insulating layer is not in a boundary region between two adjacent sub-pixels among the plurality of sub-pixels.

20. The display device according to claim 14, wherein: In a plan view, the first electrode covers the first capacitor electrode and the second capacitor electrode.

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