IGBT defect detection method and device based on on-off process gate voltage signal

Abstract

The application provides an IGBT defect detection method and device based on an on-off process gate voltage signal, comprising: obtaining an IGBT actual working target stage voltage waveform based on an IGBT on-off process gate voltage signal; calculating an IGBT actual working target stage gate loop discharge time according to the IGBT actual working target stage voltage waveform; and analyzing and judging whether the IGBT to be detected has a gate-emitter loop defect according to the IGBT actual working target stage gate loop discharge time. The application analyzes the change of the gate loop discharge time through the IGBT on-off process gate voltage waveform, and then judges whether the IGBT has a gate-emitter loop defect, thereby improving the detection efficiency. When the IGBT has a gate-emitter loop defect, the technical scheme of the application can also know the specific number of packaged chips of the IGBT having the gate-emitter loop defect, and quantitative detection can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, in particular to an IGBT defect detection method and device based on gate turn-on voltage signal. BACKGROUND

[0002] Insulate-Gate Bipolar Transistor (IGBT) devices have both the advantages of fast switching speed of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices and low on-state loss of bipolar devices, and are widely used in new energy converters, flexible DC power transmission equipment, dynamic reactive power compensation equipment and other occasions. IGBT is a three-terminal device, including a gate, a collector and an emitter. However, it is difficult to detect the internal defect state of IGBT in actual application. SUMMARY

[0003] The main purpose of the embodiment of the present application is to provide an IGBT defect detection method and device based on gate turn-on voltage signal, which analyzes the change of gate loop discharge time through IGBT gate turn-on current waveform to determine whether the IGBT has occurred gate-emitter loop defect. The present application has certain guiding significance for IGBT state detection.

[0004] In order to achieve the above purpose, the embodiment of the present application provides an IGBT defect state detection method, comprising:

[0005] Collecting an IGBT gate turn-on voltage signal in a to-be-tested converter loop; the converter loop further comprises a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor and a gate turn-off resistor; in the converter loop, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-off resistor are connected in parallel, and the gate turn-on resistor and the gate turn-off resistor are connected in series with the IGBT respectively; the IGBT internally encapsulates a plurality of chips, each chip comprising a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance and a gate-side parasitic inductance; the second end of the collector-side parasitic inductance of each chip is connected with the collector of the IGBT, the first end of the emitter-side parasitic inductance of each chip is connected with the emitter of the IGBT, and the first end of the gate-side parasitic inductance of each chip is connected with the gate of the IGBT;

[0006] According to the IGBT gate turn-on voltage signal, a target stage voltage waveform of the IGBT actual working is drawn;

[0007] calculating the target stage gate loop discharge time of the IGBT when the IGBT is actually working based on the target stage voltage waveform of the IGBT when the IGBT is actually working;

[0008] judging whether the IGBT in the flow loop to be tested has a gate electrode loop defect by analyzing the target stage gate loop discharge time of the IGBT when the IGBT is actually working.

[0009] In one embodiment, the calculating the target stage gate loop discharge time of the IGBT when the IGBT is actually working based on the target stage voltage waveform of the IGBT when the IGBT is actually working comprises:

[0010] obtaining the gate voltage of the IGBT at each moment of the target stage of the IGBT when the IGBT is actually working according to the target stage voltage waveform of the IGBT when the IGBT is actually working;

[0011] obtaining the target stage gate loop discharge time of the IGBT when the IGBT is actually working based on the gate voltage of the IGBT at each moment of the target stage of the IGBT when the IGBT is actually working.

[0012] In one embodiment, the target stage gate loop discharge time of the IGBT when the IGBT is actually working is calculated by the following formula:

[0013]

[0014] wherein, t A is the target stage gate loop discharge time of the IGBT when the IGBT is actually working, n is the total number of IGBT package chips, τ0 is the single chip gate electrode loop time, U G,on is the control voltage of the driving power supply when turned on, U T is the threshold voltage of the IGBT gate, and U G,off is the control voltage of the driving power supply when turned off.

[0015] In one embodiment, the single chip gate electrode loop time τ0 is calculated by the following formula:

[0016] τ0 = R G,on C GE ;

[0017] wherein, R G,on is the gate turn-on resistance, and C GE is the gate electrode capacitance.

[0018] In one embodiment, the judging whether the IGBT in the flow loop to be tested has a gate electrode loop defect by analyzing the target stage gate loop discharge time of the IGBT when the IGBT is actually working comprises:

[0019] When the target stage gate loop discharge time of the IGBT in actual operation is less than a threshold value, then the IGBT to be tested has a gate electrode loop defect.

[0020] In one embodiment, the threshold value is the target stage gate loop discharge time of the IGBT in normal operation.

[0021] In one embodiment, the method further comprises: if the IGBT to be tested has a gate electrode loop defect, then calculating the number of chips in the IGBT having a gate electrode loop defect according to the target stage gate loop discharge time of the IGBT in actual operation.

[0022] In one embodiment, the number of chips m in the IGBT having a gate electrode loop defect is calculated by the following formula:

[0023] ;

[0024] Wherein, n is the total number of IGBT packaged chips, t A is the target stage gate loop discharge time of the IGBT in actual operation, t′ A is the target stage gate loop discharge time of the IGBT in normal operation.

[0025] The embodiment of the present application also provides an IGBT defect detection device based on gate voltage signals in the on process, comprising:

[0026] A collection module is configured to collect gate voltage signals of IGBTs in the on process in a to-be-tested commutation loop; the commutation loop further comprises a DC bus capacitor, a freewheeling diode, a load inductor, a gate on-resistance, and a gate off-resistance; in the commutation loop, the IGBT and the freewheeling diode are connected in series, the freewheeling diode and the load inductor are connected in parallel, the DC bus capacitor and the IGBT and the freewheeling diode are connected in parallel, the gate on-resistance and the gate off-resistance are connected in parallel, and the gate on-resistance and the gate off-resistance are connected in series with the IGBT respectively; the IGBT internally encapsulates a plurality of chips, each chip comprises a gate electrode capacitor, a Miller capacitor, a collector electrode capacitor, a collector electrode side parasitic inductor, an emitter electrode side parasitic inductor, and a gate electrode side parasitic inductor; the second end of the collector electrode side parasitic inductor of each chip is connected with the collector electrode of the IGBT, the first end of the emitter electrode side parasitic inductor of each chip is connected with the emitter electrode of the IGBT, and the first end of the gate electrode side parasitic inductor of each chip is connected with the gate electrode of the IGBT;

[0027] A drawing module is configured to draw a target stage voltage waveform of the IGBT in actual operation according to the gate voltage signals of the IGBT in the on process;

[0028] a calculation module, configured to calculate the target stage gate loop discharge time of the IGBT in actual operation based on the target stage voltage waveform of the IGBT in actual operation;

[0029] a judgment module, configured to analyze and judge whether the IGBT in the flow loop to be measured has a gate-emitter loop defect based on the target stage gate loop discharge time of the IGBT in actual operation.

[0030] The embodiment of the present application further provides a computer device, including a memory, a processor and a computer program stored in the memory and running on the processor, and the processor implements the steps of the method according to any one of the above embodiments when executing the computer program.

[0031] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, and the computer program implements the steps of the method according to any one of the above embodiments when executed by a processor.

[0032] The embodiment of the present application further provides a computer program product, which includes a computer program, and the computer program implements the method according to any one of the above embodiments when executed by a processor.

[0033] The embodiment of the present application provides an IGBT defect detection method and device based on gate voltage signals in a conduction process, obtains a target stage voltage waveform of an IGBT in actual operation based on a gate voltage signal of the IGBT in the conduction process, calculates a target stage gate loop discharge time of the IGBT in actual operation according to the target stage voltage waveform of the IGBT in actual operation, and analyzes and judges whether the IGBT to be measured has a gate-emitter loop defect according to the target stage gate loop discharge time of the IGBT in actual operation. Compared with the prior art, the embodiment of the present application analyzes the change of the gate loop discharge time through the gate voltage waveform in the conduction process of the IGBT, and then judges whether the IGBT has a gate-emitter loop defect, so that the defect state of the IGBT can be detected conveniently, and the detection efficiency is improved. When the IGBT has a gate-emitter loop defect, the technical solution of the embodiment of the present application can also know the number of packaged chips of the IGBT that have the gate-emitter loop defect, and quantitative detection can be realized, which has certain guiding significance for IGBT state detection. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0035] Figure 1is a commutation loop structure schematic diagram provided by an embodiment of the present application;

[0036] Figure 2 is an IGBT internal structure schematic diagram provided by an embodiment of the present application;

[0037] Figure 3 is an IGBT turn-on transient process schematic diagram provided by an embodiment of the present application;

[0038] Figure 4 is a flowchart of an IGBT defect detection method based on a turn-on process gate voltage signal provided by an embodiment of the present application;

[0039] Figure 5 is a structure schematic diagram of an IGBT defect detection device based on a turn-on process gate voltage signal provided by an embodiment of the present application;

[0040] Figure 6 is a structure block diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0042] Those skilled in the art know that the embodiments of the present application can be implemented as a system, device, apparatus, method or computer program product. Therefore, the present disclosure can be embodied as follows: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0043] IGBTs are widely used in new energy converters, flexible DC power transmission devices, dynamic reactive power compensation devices and the like. However, it is difficult to detect the internal defect state of the IGBT in actual application. To solve the problems in the prior art, the present application analyzes the change of gate loop discharge time through the gate voltage waveform of the IGBT turn-on process, and then judges whether the IGBT has a gate-emitter loop defect. The defect state of the IGBT can be conveniently detected, and the detection efficiency is improved. When the IGBT has a gate-emitter loop defect, the technical solution of the present application can also know the number of packaged chips in which the IGBT has a gate-emitter loop defect, which has certain guiding significance for IGBT state detection.

[0044] To facilitate understanding of the technical solution provided in this application, the research background of the technical solution in this application will be briefly explained below.

[0045] Figure 1 This is a schematic diagram of a converter circuit structure provided in an embodiment of the present invention. Figure 1 This is a circuit structure model for power electronic converter devices. Most converter devices (such as dynamic reactive power compensation equipment, flexible DC equipment, wind power converters, traction converters, etc.) can be modeled using this method. Figure 1 The topology shown is analyzed. Figure 1 The commutation circuit shown mainly includes the DC bus capacitor C0 and the insulated gate bipolar transistor (IGBT) (gate-emitter capacitor C0). GE Miller capacitance C GC collector-emitter capacitor C CE Structures such as G (gate, C (collector, E (emitter)) and freewheeling diodes (FWD) have voltage and current reference directions already defined. Figure 1 The bid was successful. Figure 1 L load For the load inductance, L s,1 For the parasitic inductance of the IGBT circuit, L s,2 For the parasitic inductance of the FWD circuit; u chip,F The voltage of the freewheeling diode's internal chip, u s,F The parasitic inductance voltage within the freewheeling diode's internal package, u F U is the voltage flowing through the freewheeling diode. s,2 Parasitic inductance L of FWD circuit s,2 voltage; u GE u is the gate voltage of the IGBT. CE U is the collector-emitter voltage of the IGBT. chip,CE The collector-emitter voltage u is the collector-emitter voltage of the IGBT internal chip during the turn-off delay process. CE =u chip,CE u CG i is the collector-gate voltage of the IGBT; C For collector current, i G For gate current, i GE For flow through C GE The current, i GC For flow through C GC The current, I L For the inductance L flowing through the load load The current. L s,F and L s,CE L represents the parasitic parameters of the main circuit inside the FWD and IGBT packages, respectively. s,F Including parasitic inductances on the anode and cathode sides of the FWD, L s,CE Including L s,C L s,ETwo parts, L s,C L is the parasitic inductance on the collector side of the IGBT. s,E For the parasitic inductance on the emitter side of the IGBT; in addition, R G,on R is the gate turn-on resistance. G,off U is the gate turn-off resistor. G,on To enable the control voltage for the drive power supply, U G,off This invention provides a power supply shutdown control voltage. It is primarily used for detection. Figure 1 Does the gate-emitter circuit (GE) in the device have defects, including gate defects and emitter defects?

[0046] Figure 2 This is a schematic diagram of the internal structure of an IGBT provided in an embodiment of the present invention. The Insulated Gate Bipolar Transistor (IGBT) includes a gate-emitter capacitor C. GE Miller capacitance C GC collector-emitter capacitor C CE G is the gate, C is the collector, E is the emitter, and L is the emitter. s,C For collector-side parasitic inductance, L s,E For emitter-side parasitic inductance, L s,G This represents the gate-side parasitic inductance. In the diagram, n represents the total number of internal IGBT packaged chips, and each internal IGBT packaged chip includes a gate-emitter capacitor C. GE Miller capacitance C GC collector-emitter capacitor C CE G is the gate, C is the collector, E is the emitter, and the collector-side parasitic inductance L is... s,C Emitter-side parasitic inductance L s,E Gate-side parasitic inductance L s,G The collector-side parasitic inductance L of each IGBT internal package chip s,C The second terminal is connected to the collector C of the IGBT, and the emitter-side parasitic inductance L of the internal package chip of each IGBT is... s,E The first terminal is connected to the emitter E of the IGBT, and the gate-side parasitic inductance L of the internal package chip of each IGBT is... s,G The first terminal is connected to the IGBT gate G. IGBT packaging defects can be divided into three categories: gate defects ( Figure 2 (Note ①), collector defects () Figure 2 (Note ②), emitter defect ( Figure 2 (Note ③). This invention is mainly used to detect whether there are gate-emitter circuit defects in ① and ③, that is, whether there are gate-emitter circuit defects in IGBTs.

[0047] Figure 3 This is a schematic diagram of the IGBT turn-on transient process provided by an embodiment of the present invention. The t0 to t1 stage in the figure is the target stage of interest in the present invention.

[0048] To achieve the above objectives, embodiments of the present invention provide an IGBT defect detection method based on the gate voltage signal during the turn-on process. Figure 4 This is a flowchart of an IGBT defect detection method based on the gate voltage signal during the turn-on process, provided by an embodiment of the present invention. The main steps include:

[0049] S1. Acquire the gate voltage signal during the IGBT turn-on process in the commutation circuit under test; the commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor; in the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode is connected in parallel with the load inductor, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are connected in series with the IGBT respectively; the IGBT internally encapsulates several chips, each chip including a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance; the second terminal of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first terminal of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first terminal of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT.

[0050] Specifically, this invention can acquire the gate voltage signal during the turn-on process of the IGBT under test using a voltage signal detector. In the commutation circuit, the insulated-gate bipolar transistor (IGBT) and the freewheeling diode (FWD) are connected in series, and the freewheeling diode FWD is connected to the load inductor L. load The DC bus capacitor C0 is connected in parallel with the insulated-gate bipolar transistor (IGBT) and the freewheeling diode FWD. The gate turn-on resistor and gate turn-on resistance are connected in parallel, and the gate turn-on resistor and gate turn-on resistance are connected in series with the IGBT. The collector of the IGBT is connected to the parasitic inductance L on the collector side of the IGBT. s,C First terminal (positive), parasitic inductance L on the collector side of the IGBT s,C The second terminal (negative terminal) is connected to the parasitic inductance L of the FWD circuit. s,2 First terminal (positive), load inductor L load The second terminal (negative terminal), the parasitic inductance L of the FWD circuit s,2 The second terminal (negative terminal) is connected to the FWD parasitic inductor L. s,F First terminal (positive), FWD parasitic inductance L s,F The second terminal (negative) is connected to the first terminal (positive) of the FWD, and the second terminal (negative) of the FWD is connected to the load inductor L. load First terminal (positive) and parasitic inductance L of IGBT circuit s,1 First terminal (positive), parasitic inductance L of the IGBT circuit s,1The second terminal (negative) is connected to the first terminal (positive) of the DC bus capacitor C0, and the second terminal (negative) of the DC bus capacitor C0 is connected to the parasitic inductance L on the emitter side of the IGBT. s,E First terminal (positive), gate turn-on resistor R G,on Second terminal (negative terminal), gate turn-off resistor R G,off The second terminal (negative terminal), the parasitic inductance L on the emitter side of the IGBT. s,E The second terminal (negative terminal) is connected to the emitter of the IGBT, and the gate of the IGBT is connected to the gate turn-on resistor R. G,on First terminal (positive), gate turn-off resistor R G,off First terminal (positive electrode).

[0051] S2. Based on the gate voltage signal during the IGBT turn-on process, plot the voltage waveform of the target stage when the IGBT is actually working;

[0052] Specifically, the present invention can acquire the gate voltage signal of the IGBT under test during the turn-on process through a voltage signal detector, and then transmit the voltage signal to waveform drawing software. Alternatively, the voltage signal can be directly captured and the voltage waveform displayed through electronic measuring instruments such as an oscilloscope.

[0053] S3. Based on the target stage voltage waveform during actual operation of the IGBT, the gate circuit discharge time during the target stage of actual operation of the IGBT is calculated;

[0054] In one embodiment, calculating the gate circuit discharge time of the IGBT during the target stage of actual operation based on the voltage waveform of the target stage during actual operation includes:

[0055] S301. Obtain the gate voltage at each moment of the target stage during the actual operation of the IGBT from the voltage waveform of the target stage during the actual operation of the IGBT;

[0056] S302. Calculate the gate circuit discharge time of the target stage during the actual operation of the IGBT by using the gate voltage at each moment of the target stage.

[0057] In one embodiment, the gate circuit discharge time of the target stage during actual IGBT operation can be obtained by calculating the gate voltage at each moment of the target stage in the voltage waveform diagram of the target stage during actual IGBT operation. The gate circuit discharge time of the target stage during actual IGBT operation is calculated by the following formula:

[0058]

[0059] Among them, t AThe gate circuit discharge time during the actual operation of the IGBT is the target stage, where n is the total number of IGBT packaged chips, τ0 is the gate-emitter circuit time of a single chip, and U G,on To enable the control voltage for the drive power supply, U T U is the gate threshold voltage of the IGBT. G,off The control voltage is used to shut off the drive power supply.

[0060] Specifically, during the IGBT turn-on transient process, the gate-emitter capacitance (C) GE ) and Miller capacitance (C GC Current direction as follows Figure 1 As shown.

[0061] 1) For C GE If the voltage reference direction is G→E, then the process C GE Charging, gate-emitter voltage u GE rise.

[0062] 2) For C CG If the voltage reference direction is C→G, then in this process C CG Discharge, u CG and u CE reduce.

[0063] Gate current i G The following relationship exists between Q and voltage (Q) G (Charge amount of gate discharge for a single chip):

[0064]

[0065] If we consider the collector-gate voltage u CG ≈Gate-emitter voltage u CE ,exist:

[0066]

[0067] C GE It is a constant (not dependent on u) GE (Changes with change), and C CG It is a variable (which varies with u) CG Or u CE (Changes with the changes). Considering the t0 to t1 stage, u GE Change, and u CG Or u CE It does not change, therefore C CG Nothing changes during this process.

[0068] Table 1 summarizes the changes in voltage and capacitance during the period before the collector current begins to rise (t0 to t1):

[0069] Table 1

[0070] u GE ]]> [C GE ]]> u CG ]]> [C CG ]]> [phase t0~t1] Change No change No change No change

[0071] Considering the changes in voltage and capacitance at different stages, i G It can be represented as:

[0072]

[0073] In summary, the gate voltage u during the t0 to t1 stage GE Waveforms can be used to analyze gate-emitter (GE) circuit defects, including gate defects. Figure 2 (Note ①), emitter defect ( Figure 2 The two categories are labeled ③). In another embodiment, the gate voltage u during the t0~t1 stage can also be used. GE The gate current i during the t0 to t1 stage was calculated. G Then by controlling the gate current i G The amount of charge charged on the gate capacitor during the target stage of IGBT operation can be obtained by calculation.

[0074] The gate-emitter loop time τ0 of a single chip can be calculated using the following formula:

[0075] τ0=R G,on C GE .

[0076] In the formula, R G,on C is the gate turn-on resistance. GE This is the gate-emitter capacitor.

[0077] The overall time constant τ of the gate circuit can be calculated using the following formula:

[0078] τ=n×τ0=R G,on ×nC GE .

[0079] In the formula, R G,on C is the gate turn-on resistance. GE is the gate-emitter capacitance, and n is the total number of IGBT packaged chips.

[0080] Gate discharge during process t0 to t satisfies the following relationship:

[0081]

[0082] In the formula, n is the total number of IGBT packaged chips, u GE U represents the gate voltage at various moments during the target stage of IGBT actual operation. G,on To enable the control voltage for the drive power supply, U G,off The control voltage is used to shut off the drive power supply.

[0083] If a gate (G) or emitter (E) contact defect occurs in the gate-emitter circuit, the gate circuit discharge time constant will decrease.

[0084] In one embodiment, the gate voltage u GE From U G,on Rise to U T The gate circuit discharge time during the process (i.e., t0~t1) is calculated using the following formula:

[0085]

[0086] Among them, t A The gate circuit discharge time during the actual operation of the IGBT is the target stage, where n is the total number of IGBT packaged chips, τ0 is the gate-emitter circuit time of a single chip, and U G,on The control voltage for turning on the drive power supply, i.e., the gate voltage corresponding to the start time t0 of the target stage, is U. T U is the IGBT gate threshold voltage, which is the gate voltage corresponding to the end time t1 of the target stage. G,off The control voltage is used to shut off the drive power supply.

[0087] S4. By analyzing the gate circuit discharge time during the actual operation of the IGBT, it is determined whether there is a gate-emitter circuit defect in the IGBT in the commutation circuit under test.

[0088] In one embodiment, determining whether the IGBT under test has a gate-emitter circuit defect by analyzing the gate circuit discharge time during the actual operation of the IGBT includes:

[0089] If the gate circuit discharge time during the target stage of the IGBT is less than the threshold when the IGBT is actually working, then the IGBT under test has a gate-emitter circuit defect.

[0090] In one embodiment, the threshold is the gate circuit discharge time of the target stage when the IGBT is operating normally. The gate circuit discharge time of the target stage when the IGBT is operating normally can also be calculated using the aforementioned method, and will not be repeated here.

[0091] In one embodiment, the method further includes: S5. If the IGBT under test has a gate-emitter circuit defect, the number of chips in the IGBT with gate-emitter circuit defects is calculated based on the gate circuit discharge time of the target stage when the IGBT is actually working.

[0092] In one embodiment, the number m of chips with gate-emitter loop defects in the IGBT is calculated using the following formula:

[0093]

[0094] Where n is the total number of IGBT packaged chips, tA is the gate circuit discharge time of the target stage during actual IGBT operation, and t′ is... A This refers to the gate circuit discharge time during the target stage when the IGBT is operating normally.

[0095] Specifically, given the gate voltage u GE From U G,on (The gate voltage corresponding to the starting time t0 of the target stage) rises to U T When considering the change in gate circuit discharge time during the process of (the gate voltage corresponding to the end time t1 of the target stage), the number of chips with gate-emitter circuit defects in the IGBT can be calculated using the above formula.

[0096] Specifically, when there is an abnormal gate or emitter contact in a package structure containing m IGBT chips, the gate loop time T′ is calculated using the following formula:

[0097] T′=(nm)×τ0=R G，on ×(nm)C GE .

[0098] In the above case, the gate voltage u GE From U G,on Rise to U T Process time (i.e., the process time from t0 to t1) t A,fault It is calculated using the following formula:

[0099]

[0100] Where n is the total number of IGBT packaged chips, τ0 is the gate-emitter loop time of a single chip, and U G,on The control voltage for turning on the drive power supply, i.e., the gate voltage corresponding to the start time t0 of the target stage, is U. T U is the IGBT gate threshold voltage, which is the gate voltage corresponding to the end time t1 of the target stage. G,off The control voltage is used to shut off the drive power supply.

[0101] From the above equation, we can see that Δt A =t A,fault —t A <0;

[0102] Gate voltage u GE From U G,on Rise to U T The decrease in process time (i.e., the time from t0 to t1) indicates that the IGBT has a gate-emitter (GE) circuit defect.

[0103] In a specific embodiment, taking a traction converter as an example, the IGBT defect detection method based on the gate voltage signal during the turn-on process provided by this invention is used to detect whether there are defects in the gate-emitter circuit (GE) inside the IGBT of the traction converter. First, the gate voltage signal during the IGBT turn-on process is acquired by an oscilloscope and the voltage waveform of the target stage during actual IGBT operation is displayed. Then, the voltage waveform of the target stage during actual IGBT operation is transmitted to an analyzer for analysis and processing. The analyzer obtains the gate voltage at each moment of the target stage during actual IGBT operation from the voltage waveform of the target stage during actual IGBT operation. Based on the gate voltage at each moment of the target stage during actual IGBT operation, the gate circuit discharge time of the target stage during actual IGBT operation is calculated. When the gate circuit discharge time of the target stage during actual IGBT operation is less than the gate circuit discharge time of the target stage during normal operation of the current IGBT, then the current IGBT has a gate-emitter circuit defect. This application can improve the defect detection efficiency of IGBT. Furthermore, if the current IGBT has a gate-emitter circuit defect, the number of defective chips in the IGBT can also be calculated based on the gate circuit discharge time of the target stage. The analyzer can detect and issue early warnings in real time whether there are gate-emitter circuit defects in the IGBT based on the target stage voltage waveform during actual IGBT operation, thus reminding maintenance personnel to perform maintenance, improving subsequent maintenance efficiency and reducing maintenance costs. It can also display the specific number of faulty packaged chips within the IGBT, which can further improve maintenance efficiency.

[0104] Compared to existing technologies, this invention analyzes the gate voltage waveform during the IGBT turn-on process to determine the change in gate circuit discharge time, thereby identifying whether the IGBT has a gate-emitter circuit defect. This allows for convenient detection of IGBT defect states and improves detection efficiency. In particular, when an IGBT has a gate-emitter circuit defect, the technical solution of this invention can also determine the specific number of packaged chips with this defect, enabling quantitative detection. This provides valuable guidance for IGBT condition monitoring.

[0105] Based on the same inventive concept, this invention also provides an IGBT defect status detection device. Figure 5 This is a schematic diagram of the structure of an IGBT defect state detection device provided in an embodiment of the present invention, comprising:

[0106] The acquisition module is used to acquire the gate voltage signal during the IGBT turn-on process in the commutation circuit under test. The commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor. In the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode is connected in parallel with the load inductor, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-on resistor are connected in parallel, and the gate turn-on resistor and the gate turn-on resistor are connected in series with the IGBT respectively. The IGBT internally encapsulates several chips, each chip including a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance. The second terminal of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first terminal of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first terminal of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT.

[0107] The drawing module is used to draw the target stage voltage waveform of the IGBT during actual operation based on the gate voltage signal during the IGBT turn-on process.

[0108] The calculation module is used to calculate the gate circuit discharge time of the IGBT during the target stage of actual operation based on the voltage waveform of the target stage when the IGBT is actually working.

[0109] The computing module includes a first unit and a second unit;

[0110] The first unit is used to obtain the gate voltage at each moment of the target stage when the IGBT is actually working from the voltage waveform of the target stage when the IGBT is actually working;

[0111] The second unit is used to calculate the gate circuit discharge time of the target stage during the actual operation of the IGBT by using the gate voltage at each moment of the target stage.

[0112] In one embodiment, the gate circuit discharge time t A It is calculated using the following formula:

[0113]

[0114] Where n is the total number of IGBT packaged chips, τ0 is the gate-emitter loop time of a single chip, and U G,on To enable the control voltage for the drive power supply, U T U is the gate threshold voltage of the IGBT. G,off The control voltage is used to shut off the drive power supply.

[0115] The judgment module is used to determine whether there is a gate-emitter circuit defect in the IGBT under test by analyzing the gate circuit discharge time during the target stage of the IGBT's actual operation.

[0116] The judgment module includes a third unit and a fourth unit;

[0117] The third unit is used to obtain a threshold value; the threshold value is the gate circuit discharge time of the target stage when the IGBT under test is working normally.

[0118] The fourth unit is used to compare the gate circuit discharge time of the target stage when the IGBT is actually working with the threshold obtained by the third unit. When the gate circuit discharge time of the target stage when the IGBT is actually working is less than the threshold, it is considered that the IGBT under test has a gate-emitter circuit defect.

[0119] The quantitative detection module is used to calculate the number of chips with gate-emitter circuit defects in the IGBT based on the gate circuit discharge time of the target stage when the judgment result sent by the judgment module indicates that the IGBT under test has a gate-emitter circuit defect.

[0120] In one embodiment, the number m of IGBT chips with gate-emitter circuit defects is calculated using the following formula:

[0121]

[0122] Where n is the total number of IGBT packaged chips, t A t′ represents the gate circuit discharge time during the target stage of IGBT actual operation. A This refers to the gate circuit discharge time during the target stage when the IGBT is operating normally.

[0123] The remaining embodiments of the device can be implemented one-to-one with the aforementioned method embodiments, and will not be described in detail here.

[0124] This invention also provides a computer device, such as... Figure 6 The diagram shown is a structural block diagram of a computer device provided by an embodiment of the present invention, including a memory, a processor, and a computer program stored in the memory and running on the processor. When the processor executes the computer program, it implements any of the methods described above.

[0125] This invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the methods described above.

[0126] This invention also provides a computer program product, which includes a computer program that, when executed by a processor, implements any of the methods described above.

[0127] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0128] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0129] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0130] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0131] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for detecting defects in IGBTs based on gate voltage signals during the turn-on process, characterized in that, include: The gate voltage signal during the turn-on process of the IGBT in the commutation circuit under test is acquired. The commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor. In the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode is connected in parallel with the load inductor, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-off resistor are connected in parallel, and the gate turn-on resistor and the gate turn-off resistor are connected in series with the gate of the IGBT. The IGBT internally encapsulates several chips, each chip including a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance. The second terminal of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first terminal of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first terminal of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT. Based on the gate voltage signal during the IGBT turn-on process, plot the voltage waveform of the target stage when the IGBT is actually working. The target stage is the stage before the collector current starts to rise. Based on the target stage voltage waveform during actual IGBT operation, the gate circuit discharge time during the target stage of actual IGBT operation is calculated. The gate circuit discharge time of the IGBT during the actual operation of the IGBT is analyzed to determine whether there are gate-emitter circuit defects in the IGBT in the commutation circuit under test.

2. The method according to claim 1, characterized in that, The calculation of the gate circuit discharge time during the target stage of IGBT operation, based on the voltage waveform during the actual operation of the IGBT, includes: Based on the voltage waveform of the target stage during actual operation of the IGBT, the gate voltage at each moment of the target stage during actual operation of the IGBT is obtained; Based on the gate voltage at each moment of the target stage during the actual operation of the IGBT, the gate circuit discharge time of the target stage during the actual operation of the IGBT is obtained.

3. The method according to claim 2, characterized in that, The gate circuit discharge time during the actual operation of the IGBT is calculated using the following formula: ； in, t A The gate circuit discharge time is the target stage during actual IGBT operation, where n is the total number of IGBT packaged chips. τ 0 represents the gate-emitter loop time of a single chip. U G,on To turn on the control voltage for the drive power supply, U T This refers to the gate threshold voltage of the IGBT. U G,off The control voltage is used to shut off the drive power supply.

4. The method according to claim 3, characterized in that, The gate-emitter loop time of a single chip τ 0 is calculated using the following formula: ； in, R G,on For gate turn-on resistance, C GE This is the gate-emitter capacitor.

5. The method according to any one of claims 1-4, characterized in that, The method of determining whether the IGBT under test has gate-emitter circuit defects by analyzing the gate circuit discharge time during the actual operation of the IGBT includes: If the gate circuit discharge time during the target stage of the IGBT is less than the threshold when the IGBT is actually working, then the IGBT under test has a gate-emitter circuit defect.

6. The method according to claim 5, characterized in that, The threshold is the gate circuit discharge time of the target stage when the IGBT under test is working normally.

7. The method according to claim 5, characterized in that, The method further includes: if the IGBT under test has a gate-emitter circuit defect, then the number of chips in the IGBT with gate-emitter circuit defects is calculated based on the gate circuit discharge time of the target stage when the IGBT is actually working.

8. The method according to claim 7, characterized in that, The number of IGBT chips with gate-emitter circuit defects is calculated using the following formula: ； Where m is the number of IGBT chips with gate-emitter circuit defects, and n is the total number of IGBT packaged chips. t A This refers to the gate circuit discharge time during the target stage of IGBT actual operation. This refers to the gate circuit discharge time during the target stage when the IGBT is operating normally.

9. An IGBT defect detection device based on the gate voltage signal during the turn-on process, characterized in that, include: The acquisition module is used to acquire the gate voltage signal during the IGBT turn-on process in the commutation circuit under test. The commutation circuit also includes a DC bus capacitor, a freewheeling diode, a load inductor, a gate turn-on resistor, and a gate turn-off resistor. In the commutation circuit, the IGBT and the freewheeling diode are connected in series, the freewheeling diode is connected in parallel with the load inductor, the DC bus capacitor is connected in parallel with the IGBT and the freewheeling diode, the gate turn-on resistor and the gate turn-off resistor are connected in parallel, and the gate turn-on resistor and the gate turn-off resistor are connected in series with the gate of the IGBT. The IGBT internally encapsulates several chips, each chip including a gate-emitter capacitor, a Miller capacitor, a collector-emitter capacitor, a collector-side parasitic inductance, an emitter-side parasitic inductance, and a gate-side parasitic inductance. The second terminal of the collector-side parasitic inductance of each chip is connected to the collector of the IGBT, the first terminal of the emitter-side parasitic inductance of each chip is connected to the emitter of the IGBT, and the first terminal of the gate-side parasitic inductance of each chip is connected to the gate of the IGBT. The plotting module is used to plot the target stage voltage waveform of the IGBT during actual operation based on the gate voltage signal during the IGBT turn-on process. The target stage is the stage before the collector current starts to rise. The calculation module is used to calculate the gate circuit discharge time of the IGBT during the target stage of actual operation based on the voltage waveform of the target stage when the IGBT is actually working. The judgment module is used to determine whether there is a gate-emitter circuit defect in the IGBT in the commutation circuit under test by analyzing the gate circuit discharge time of the IGBT during the target stage of actual operation.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 8.

Images