Testing device

Abstract

The testing device comprises a first fixing plate, a second fixing plate and a circuit board, the first fixing plate and the second fixing plate are arranged at a preset interval in the first direction, the circuit board is arranged on the side, away from the first fixing plate, of the second fixing plate, and the second fixing plate comprises a groove; a plurality of thimbles connected to the circuit board are arranged in the groove, the first fixing plate is used for picking up an integrated circuit to be tested and moving the integrated circuit to the groove, the thimbles are used for electrically connecting the integrated circuit to be tested and the circuit board, the circuit board is used for carrying out electrical performance testing on the integrated circuit to be tested, and the first fixing plate comprises a conductive layer and a first grounding layer; the conductive layer is adjacent to the second fixing plate, the first grounding layer is arranged on one side, far away from the second fixing plate, of the conductive layer, and the conductive layer is electrically connected to the grounding layer and is used for simulating the shielding effect of a shielding case on the integrated circuit in the electronic equipment so as to eliminate the error of the integrated circuit between the testing device and the electronic equipment due to the shielding case.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a testing device. Background Art

[0002] With the continuous development of the field of electronic equipment technology, the requirements for the thickness of electronic devices such as mobile phones are getting thinner and thinner. Therefore, the internal space of electronic devices needs to be further compressed. Among them, the integrated circuit (IC) inside the electronic device, that is, the chip is usually provided with a shielding cover. While the thickness of the electronic device is reduced, the height of the shielding cover also needs to be further reduced, resulting in the distance between the shielding cover and the chip getting smaller and smaller, causing the components inside the chip to be affected by the shielding cover and performance deviation. Among them, the chip is manufactured by a series of steps such as lithography, corrosion, and doping. In the actual integrated circuit (IC) design and production process, various defects will inevitably occur. Electrical functional testing is required before the product is delivered to the customer. Since the chip will be affected by the shielding cover in the electronic device, the performance of the chip in the electronic device will deviate from the test results. Therefore, how to eliminate the test result deviation caused by the shielding cover and improve the chip effect is an urgent problem to be solved. Summary of the invention

[0003] In order to solve the aforementioned technical problem, an embodiment of the present application provides a testing device for eliminating performance deviation of a chip between the testing device and an electronic device.

[0004] In a first aspect, an embodiment of the present application provides a test device, comprising a first fixing plate, a second fixing plate and a circuit board, wherein the first fixing plate and the second fixing plate are arranged at a preset distance along a first direction, the circuit board is arranged on a side of the second fixing plate away from the first fixing plate, the second fixing plate comprises a groove, a plurality of ejectors connected to the circuit board are arranged in the groove, the first fixing plate is used to pick up an integrated circuit to be tested and move it into the groove, the ejectors are used to electrically connect the integrated circuit to be tested and the circuit board, the circuit board is used to perform an electrical performance test on the integrated circuit to be tested, wherein the first fixing plate comprises a conductive layer and a first grounding layer, the conductive layer is arranged adjacent to the second fixing plate, the first grounding layer is arranged on a side of the conductive layer away from the second fixing plate, the conductive layer is electrically connected to the grounding layer, and the conductive layer is used to shield the integrated circuit to be tested. By arranging the conductive layer in the first fixing plate and electrically connecting the conductive layer to the grounding layer, the conductive layer can achieve a shielding effect on the integrated circuit to be tested in the test device, that is, it can simulate the shielding cover around the integrated circuit when it is arranged in the electronic device, so that when the test device performs an electrical performance test on the integrated circuit to be tested, the deviation of the test result caused by the shielding cover in the electronic device can be eliminated.

[0005] Optionally, the first fixed plate includes a main body portion and a grabbing portion which are stacked in sequence along the first direction, the first grounding layer is arranged in the main body portion, the grabbing portion is arranged opposite to the groove, the grabbing portion includes a base plate, the conductive layer and a vacuum tube, the conductive layer and the base plate are stacked in sequence along the first direction, the conductive layer is arranged adjacent to the main body portion, the vacuum tube is penetrated through the conductive layer and the base plate along the first direction, and the grabbing portion picks up the integrated circuit to be tested through the vacuum tube.

[0006] By setting the conductive layer in the grasping part and controlling the grasping part to be set opposite to the groove, the grasping part covers the groove when the grasping part moves the integrated circuit to be tested into the groove, so that the conductive layer can cover the integrated circuit to be tested, and then the signal of the integrated circuit to be tested is shielded by the analog shielding cover when the integrated circuit to be tested is subjected to electrical performance testing.

[0007] Optionally, the main body portion also includes a fixing layer, which is arranged between the first grounding layer and the grabbing portion, the first fixing plate also includes at least one first conductive member, and the second fixing plate also includes at least one second conductive member, the first conductive member is arranged around the grabbing portion and partially embedded in the fixing layer adjacent to the second fixing plate, the second conductive member is arranged around the groove and partially embedded in the second fixing plate, the first conductive member and the second conductive member are arranged opposite to each other along the first direction, and when the first fixing plate and the second fixing plate are overlapped and assembled with each other, the first conductive member abuts against the second conductive member and is electrically connected.

[0008] Optionally, a plurality of conductors are provided in the fixed layer, the first conductive member, the conductive layer and the first grounding layer are electrically connected through the conductors, the circuit board includes a second grounding layer, the second conductive member is electrically connected to the second grounding layer, the integrated circuit to be tested is electrically connected to the second grounding layer through the ejector pin, and when the integrated circuit to be tested is located in the groove, a grounding loop is formed between the conductive layer, the first conductive member, the second conductive member and the integrated circuit to be tested.

[0009] Optionally, the multiple conductors include at least one first conductor arranged along the first direction and at least one second conductor arranged along the second direction, the first conductor is connected to the first ground layer and the conductive layer, and the second conductor is connected between the first conductor and the first conductive member, wherein the first direction is perpendicular to the second direction.

[0010] By setting a first conductive member and a second conductive member, and when the grasping part moves the integrated circuit to be tested into the groove, the first conductive member abuts against the second conductive member, so that the first conductive member, the second conductive member and the conductive layer form a close-range grounding loop, thereby eliminating the parasitic capacitance between the first grounding layer and the second grounding layer, thereby further improving the conductive effect of the conductive layer.

[0011] Optionally, the conductive layer is in a sheet structure or a mesh structure. By setting the conductive layer in a sheet structure, the shielding effect of the conductive layer on the integrated circuit to be tested can be improved, and by setting the conductive layer in a mesh structure, the stability inside the gripping part can be improved.

[0012] Optionally, the testing device also includes an elastic member, which is arranged between the first conductive member and the second conductive member, and the elastic member is electrically connected to the first grounding layer through the second conductive member and the first conductive member, and / or the elastic member is arranged between the second conductive member and the second grounding layer, and the second conductive member is electrically connected to the second grounding layer through the elastic member.

[0013] By arranging an elastic member between the first conductive member and the second conductive member, it is possible to avoid damage to the conductive member due to excessive pressure when controlling the abutment between the first conductive member and the second conductive member.

[0014] Optionally, the bottom of the groove includes a contact area, and the plurality of ejector pins are arranged in an array in the contact area. The second fixing plate also includes at least one shielding plate, and the shielding plate extends along the first direction and is arranged between the side wall of the groove and the contact area for shielding the integrated circuit to be tested.

[0015] Optionally, the second fixing plate includes four shielding plates, the contact area is rectangular in shape, and the four shielding plates are extended along the first direction and disposed in the groove and are respectively adjacent to four sides of the contact area to enclose the contact area.

[0016] Optionally, the four shielding plates are connected end to end in the groove to form a containing space, and the contact area is located in the containing space. By arranging four shielding plates in the groove to form a containing space, when the grasping portion moves the integrated circuit to be tested to the containing space, the four shielding plates can shield the integrated circuit to be tested, and are used to achieve the effect of simulating a shielding cover together with the conductive layer.

[0017] Compared with the problems of the prior art, an embodiment of the present application provides a testing device, which is used to set a conductive layer and a first conductive member in a first fixed plate, and set a second conductive member in a second fixed plate, so that when a grasping part moves the integrated circuit to be tested into a groove of the second fixed plate, the conductive layer and the first conductive member and the second conductive member form a grounding loop for simulating a shielding cover to perform signal shielding when performing electrical performance testing on the integrated circuit to be tested, so as to eliminate performance deviations of the integrated circuit between the testing device and the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 The present invention is a schematic diagram of a disassembled structure of an electronic device; Figure 2 for Figure 1 Schematic diagram of the layout of integrated circuits in electronic devices; Figure 3 A structural schematic diagram of a testing device provided in the related art; Figure 4 A schematic diagram of the structure of a testing device provided in an embodiment of the present application; Figure 5 for Figure 4 A schematic diagram of the layout of the first conductive member; Figure 6 for Figure 4 A schematic diagram of the layout of the second conductive member; Figure 7 for Figure 4 Schematic diagram of the layout of the middle groove; Figure 8 Another example provided in this embodiment is Figure 4 Schematic diagram of the layout of the middle groove; Fig. 9 for Figure 4 The structural diagram of the test device during the test; Fig.10 for Fig. 9 Schematic diagram of the circuit architecture of parasitic capacitance in the test device; Fig.11 for Fig. 9 Schematic diagram of the ground loop in the test device; Fig.12 for Figure 4 Schematic diagram of the plane layout of the middle fixed plate; Fig.13 for Figure 4 Schematic diagram of the split structure of the middle fixed plate; Fig.14 It is a schematic diagram of the split structure of another fixed plate; Fig.15 for Figure 4 Schematic diagram of the process flow of the thickness adjustment method of the midsole plate. DETAILED DESCRIPTION

[0020] In order to clearly describe the technical solution of the present application, the words "first", "second" and the like are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the difference.

[0021] References to "one embodiment" or "some embodiments" etc. described in the specification of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in the specification of the present application do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0022] In order to enable persons skilled in the art to more clearly understand the solution of the present application, the application scenario of the technical solution of the present application is first described below.

[0023] See also Figure 1 , Figure 1 The figure is a schematic diagram of the disassembled structure of an electronic device.

[0024] like Figure 1 As shown, the electronic device 200 includes: a display module 201, a middle frame 202, a back cover 203, a printed circuit board 204 and a battery 205. The middle frame 202, the printed circuit board 204 and the battery 205 are arranged between the display module 201 and the back cover 203. The printed circuit board 204 and the battery 205 can be arranged on the middle frame 202, for example, the printed circuit board 204 and the battery 205 are arranged on the side of the middle frame 202 facing the back cover 203. In other embodiments, the printed circuit board 204 and the battery 205 can also be arranged on the side of the middle frame 202 facing the display module 201.

[0025] The battery 205 can be charged and discharged by the charge and discharge management chip ( Figure 1The charge and discharge management chip can receive the electric energy output by the battery 205 and power the processor, internal memory, external memory, display module 201, camera and communication module in the electronic device 200. The charge and discharge management chip can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance). The charge and discharge management chip can also receive external input electric energy to charge the battery 205. In some embodiments, the charge and discharge management chip can be integrated in the printed circuit board 204.

[0026] The printed circuit board 204 may be integrated with a control chip, and the control chip includes but is not limited to an application processor (AP), a double data rate synchronous dynamic random access memory (DDR), and a universal flash storage (UFS). It should be noted that the printed circuit board 204 may be a rigid circuit board, a flexible circuit board, or a rigid-flexible circuit board. The printed circuit board 204 includes but is not limited to a FR-4 dielectric board, a Rogers dielectric board, or a mixed dielectric board of FR-4 and Rogers. Among them, FR-4 is a code for a flame retardant material grade, and the Rogers dielectric board is a high-frequency board.

[0027] like Figure 2 As shown, Figure 2 for Figure 1 Schematic diagram of the layout of integrated circuits in the electronic device 200. Integrated circuit B is arranged on the printed circuit board 204, and the electronic device 200 also includes a shielding cover 206, which covers the integrated circuit B. The integrated circuit B can be a radio frequency chip, and the shielding cover 206 is used to prevent the signal emitted by the radio frequency chip from being interfered with. The thickness of the radio frequency chip is about 0.6-0.8mm, and the thickness of the shielding cover 206 is usually 1.2mm. As the thickness of the electronic device 200 is further reduced, the thickness of the shielding cover 206 is further reduced to about 0.9mm, resulting in a distance of about 0.1mm between the shielding cover 206 and the integrated circuit B. As the distance between the shielding cover 206 and the integrated circuit B becomes smaller, the radio frequency chip will be affected by the shielding cover 206, resulting in performance deviation.

[0028] See also Figure 3 , Figure 3 The present invention is a schematic diagram of the structure of a testing device provided in the related art.

[0029] like Figure 3As shown, the test device 100 is used to perform tests on RF chips before they leave the factory, such as FT tests or ATE tests, etc., to determine whether the chips are good products. The test device 100 includes a first fixed plate 10, a second fixed plate 20 and a circuit board 30, wherein the first fixed plate 10 and the second fixed plate 20 are arranged opposite to each other along the first direction F1, and the circuit board 30 is stacked on the side of the second fixed plate 20 away from the first fixed plate 10. The first fixed plate 10 includes a main body 11 and a gripping portion 12, wherein the gripping portion 12 is arranged on the side of the main body 11 facing the second fixed plate 20, and the first fixed plate 10 grips the integrated circuit A to be tested through the gripping portion 12. The second fixed plate 20 is provided with a groove 21, and a plurality of ejector pins 22 are also provided in the groove 21, wherein the ejector pins 22 are electrically connected to the circuit board 30.

[0030] Under the control of the external robot arm, the first fixing plate 10 moves the IC A to be tested to the groove 21 through the grasping portion 12, and applies pressure to the IC A to be tested, so as to control the pins in the IC A to be tested to be electrically connected to the ejector pins 22 in the groove 21, so that the IC A to be tested is electrically connected to the circuit board 30 through the ejector pins 22, thereby testing the IC A to be tested. After the test is completed, the first fixing plate 10 takes out the IC A to be tested through the grasping portion 12.

[0031] Among them, the grasping part 12 may include a base plate 121 and a vacuum tube 123. The base plate 121 is arranged adjacent to the main body 11. The vacuum tube 123 is arranged in the central area of ​​the base plate 121 and partially extends to the first fixed plate 10. In the process of grasping the integrated circuit A to be tested, when the base plate 121 is facing the integrated circuit A to be tested, the integrated circuit A to be tested is adsorbed by pumping out the air in the vacuum tube 123, thereby grasping the integrated circuit A to be tested.

[0032] Since the integrated circuit B is affected by the shielding cover 206 in the electronic device 200, resulting in performance deviation, and the shielding cover as an influencing factor is not detected during factory testing, the FT test result of the integrated circuit B will deviate from the operating effect in the electronic device 200, thereby affecting the operating effect of the integrated circuit B. Based on this, the present application provides a testing device for eliminating the problem of integrated circuit test result deviation caused by the influence of the shielding cover.

[0033] See also Figure 4 , Figure 4 A schematic diagram of the structure of a testing device provided in an embodiment of the present application.

[0034] like Figure 4As shown, the test device 100 includes a first fixing plate 10, a second fixing plate 20 and a circuit board 30, wherein the first fixing plate 10 and the second fixing plate 20 are arranged opposite to each other at a preset distance along a first direction F1, and the circuit board 30 is arranged on a side of the second fixing plate 20 away from the first fixing plate 10. The first fixing plate 10 is used to pick up the integrated circuit A to be tested and move it to a preset position of the second fixing plate 20, and is electrically connected to the circuit board 30 through the second fixing plate 20, and the circuit board 30 is used to perform electrical performance test on the integrated circuit A to be tested.

[0035] The first fixing plate 10 includes a main body 11 and a gripping portion 12. The main body 11 includes a first grounding layer 111 and a fixing layer 112. The first grounding layer 111 and the fixing layer 112 are stacked in sequence along the first direction F1. The main body 11 also includes at least one first conductive member 113. The first conductive member 113 is disposed adjacent to the gripping portion 12 along the second direction F2, and is embedded in the fixing layer 112 adjacent to the second fixing plate 20, and protrudes outward along the first direction F1. A conductor L is also disposed in the fixing layer 112, and the first conductive member 113 is electrically connected to the first grounding layer 111 through the conductor L.

[0036] The main body 11 and the gripping part 12 are stacked in sequence from top to bottom, wherein the gripping part 12 is arranged on the side of the main body 11 adjacent to the second fixed plate 20, that is, the gripping part 12 is closer to the second fixed plate 20 than the main body 11. The first fixed plate 10 picks up the integrated circuit A to be tested through the gripping part 12. The gripping part 12 includes a bottom plate 121, a conductive layer 122 and a vacuum tube 123, wherein the bottom plate 121 is stacked on the side of the fixed layer 112 adjacent to the second fixed plate 20, the conductive layer 122 is arranged between the bottom plate 121 and the fixed layer 112 along the second direction F2, or is arranged in the bottom plate 121, and is electrically connected to the first grounding layer 111 and the first conductive member 113 through the conductor L. The vacuum tube 123 is arranged through the fixed layer 112 and the bottom plate 121 along the first direction F1, and is arranged flush with the bottom plate 121 on the side adjacent to the second fixed plate 20. During the process of grabbing the IC A, when the bottom plate 121 faces and is close to the IC A, the IC A is adsorbed by pumping out the air in the vacuum tube 123, thereby grabbing the IC A.

[0037] The conductor L includes at least one first conductor L1 extending along the first direction F1 and at least one second conductor L2 extending along the second direction F2, wherein the conductive layer 122 is electrically connected to the first ground layer 111 through the first conductor L1, and the first conductive member 113 is electrically connected to the first conductor L1 through the second conductor L2, so as to be electrically connected to the first ground layer 111 and the conductive layer 122 through the first conductor L1.

[0038] The second fixing plate 20 includes a groove 21, a pin 22 and at least one second conductive member 23, wherein the groove 21 is arranged opposite to the gripping portion 12 along the first direction F1, the pin 22 is arranged in the groove 21, the second conductive member 23 is arranged adjacent to the groove 21 along the second direction F2, and is arranged opposite to the first conductive member 113 along the first direction F1. The circuit board 30 includes a second grounding layer 32, and the second conductive member 23 is electrically connected to the second grounding layer 32.

[0039] In this embodiment, the fixing layer 112 may be made of an insulating material or a metallic conductive material, and the bottom plate 121 is made of an insulating material, wherein the insulating material may be a resin material.

[0040] When the test device 100 in this embodiment tests the integrated circuit A to be tested, the first conductive member 113 is electrically connected to the second conductive member 23. Since the first conductive member 113 is electrically connected to the first grounding layer 111 and the conductive layer 122 through the conductor L, and the second conductive member 23 is electrically connected to the second grounding layer 32, that is, a ground loop is formed among the first conductive member 113, the second conductive member 23 and the conductive layer 122, so that the conductive layer 122, the first conductive member 113 and the second conductive member 23 are equivalent to the shielding cover 206 in the electronic device 200, thereby simulating the influence of the shielding cover 206 on the integrated circuit A to be tested, and further eliminating the problem of test result deviation caused by the influence of the shielding cover 206.

[0041] Please also read Figure 5 and Figure 6 , Figure 5 for Figure 4 Schematic diagram of the layout of the first conductive member 113, Figure 6 for Figure 4 Schematic diagram of the layout of the second conductive member 23. Figure 5 As shown, the test device 100 further includes at least one elastic member 114, which is disposed between the second conductive body L2 and the first conductive body 113, and the elastic member 114 is electrically connected to the first grounding layer 111 through the second conductive body L2 and the first conductive body L1. Figure 6As shown, the elastic member 114 can also be arranged between the second conductive member 23 and the second grounding layer 32, and the second conductive member 23 is electrically connected to the second grounding layer 32 through the elastic member 114. Exemplarily, any first conductive member 113 and a second conductive member 23 arranged opposite to each other are regarded as a group of conductive members, wherein at least one elastic member is arranged in a group of conductive members, that is, in a group of conductive members, the elastic member 114 abuts against the first conductive member 113, or abuts against the second conductive member 23. Alternatively, a group of conductive members includes two elastic members 114, and the first conductive member 113 and the second conductive member 23 abut against the two elastic members 114 respectively, so that the first conductive member 113 is electrically connected to the second conductor L2 through the elastic member, and the second conductive member 23 is electrically connected to the second grounding layer 32 through the elastic member 114. By disposing an elastic member 114 between the first conductive member 113 and the second conductive body L2 and / or between the second conductive member 23 and the second grounding layer 32 , excessive pressure that may cause damage to the conductive members when controlling the contact between the first conductive member 113 and the second conductive member 23 is avoided.

[0042] Please also read Figure 7 and Figure 8 , Figure 7 for Figure 4 Schematic diagram of the layout of the middle groove 21, Figure 8 Another example provided in this embodiment is Figure 4 Schematic diagram of the layout of the middle groove 21.

[0043] like Figure 7 and Figure 8 As shown, the groove 21 includes a contact area 211, and the contact area 211 is rectangular in shape. A plurality of ejector pins 22 are arranged in an array in the contact area 211. The second fixing plate 20 also includes at least one shielding plate 24, and the shielding plate 24 is arranged adjacent to the contact area 211, or the shielding plate 24 is arranged on the inner wall of the groove 21. Exemplarily, the second fixing plate 20 may include four shielding plates 24, and the contact area 211 is rectangular in shape. The four shielding plates 24 are respectively arranged around the contact area 211 to form a receiving space, that is, the contact area 211 is located in the receiving space, and the grasping portion 12 is used to move the integrated circuit A to be tested to the receiving space so that the integrated circuit A to be tested is connected to the ejector pins 22 in the contact area 211. The four shielding plates 24 are used to apply a shielding effect when testing the integrated circuit A to be tested, and are used to simulate the effect of the shielding cover 206 in the electronic device. Among them, the four shielding plates 24 are arranged independently, and of course, the four shielding plates 24 can also be connected end to end to form a square receiving space ( Figure 7 ), used to accommodate the integrated circuit A to be tested, so as to further improve the shielding effect of the accommodating space.

[0044] When the integrated circuit A to be tested is located in the accommodating space in the groove 21 for testing, the accommodating space formed by the four shielding plates 24 and the conductive layer 122 in the grasping portion 12 together constitute a shielding cover with the same structure as that in the electronic device 200, and the conductive layer 122 is electrically connected to the grounding layer through the first conductive member 113 and the second conductive member 23, thereby forming a grounding loop, thereby realizing the simulation of the shielding effect of the shielding cover.

[0045] See also Fig. 9 , Fig. 9 for Figure 4 Schematic diagram of the structure of the test device during testing.

[0046] like Fig. 9 As shown, during the testing process of the integrated circuit A under test by the testing device 100, the grasping portion 12 moves the integrated circuit A under test to the groove 21, and applies pressure to the integrated circuit A under test to control the integrated circuit A under test to be electrically connected to the ejector pin 22 in the groove 21, so as to perform an electrical performance test on the integrated circuit A under test. At the same time, the first conductive member 113 is electrically connected to the second conductive member 23. Since the first conductive member 113 is electrically connected to the first grounding layer 111 through the conductor L, and the second conductive member 23 is electrically connected to the second grounding layer 32, a ground loop is formed between the first conductive member 113, the second conductive member 23, the conductive layer 122, the first grounding layer 111, and the second grounding layer 32. When the integrated circuit A under test is tested, the influence of the shielding cover 206 on the integrated circuit A under test can be simulated, thereby avoiding the integrated circuit A under test in the electronic device due to the shielding cover 206 ( Figure 2 ) causes the problem of test result deviation.

[0047] See also Fig.10 , Fig.10 for Fig. 9 Schematic diagram of the circuit architecture of parasitic capacitance in the test device.

[0048] like Fig.10 As shown, during the testing process of the integrated circuit A under test by the test device 100, when the grasping portion 12 moves the integrated circuit A under test to the groove 21 and controls the integrated circuit A under test to be electrically connected to the ejector pin 22 in the groove 21, if the first conductive member 113 is not provided to form a ground loop between the first conductive member 113 and the second conductive member 23 and the conductive layer 122, at this time, the conductive layer 122 can only be connected to the first grounding layer 111 in the main body 11 through the conductor L, and the integrated circuit A under test can only be connected to the second grounding layer 32 through the ejector pin 22, that is, the reference ground of the integrated circuit A under test is the second grounding layer 32, and at this time, the first grounding layer 111 is a non-ideal ground, resulting in a parasitic capacitance R between the first grounding layer 111 and the second grounding layer 32, thereby causing a deviation in the final test result.

[0049] See also Fig.11 , Fig.11 for Fig. 9 Schematic diagram of the ground loop in the test device.

[0050] like Fig.11 As shown, by setting the first conductive member 113, the first conductive member 113 is electrically connected to the conductive layer 122 through the conductor L, and the first conductive member 113 is connected to the second conductive member 23, so that the integrated circuit A to be tested can be connected to the conductive layer 122 through the second conductive member 23, the first conductive member 113 and the conductor L, thereby forming a short-distance grounding loop, avoiding parasitic capacitance formed by an excessively long grounding loop, and thus avoiding test result deviations caused by parasitic capacitance.

[0051] Please also read Fig.12 , Fig.13 and Fig.14 , Fig.12 for Figure 4 Schematic diagram of the plane layout of the middle fixed plate, Fig.13 for Figure 4 Schematic diagram of the split structure of the middle fixed plate, Fig.14 A schematic diagram of the split structure of another fixed plate.

[0052] like Fig.12 , Fig.13 and Fig.14 As shown, the fixed layer 112, the conductive layer 122 and the bottom plate 121 are stacked along the thickness direction, that is, the first direction F1. The cross-sections of the fixed layer 112, the conductive layer 122 and the bottom plate 121 are rectangular, and the vacuum tube 123 is set through the fixed layer 112, the conductive layer 122 and the center of the bottom plate 121. A plurality of first conductive members 113 are set around the bottom plate 121 and are electrically connected to the first grounding layer 111 through the fixed layer 112. The conductive layer 122 can be a whole metal sheet structure ( Figure 6 ), or it can be a mesh structure ( Fig.10 ).

[0053] The conductive layer 122 simulates the shielding cover in the electronic device 200, and the thickness of the bottom plate 121 can be determined according to the shielding cover 206 ( Figure 2 ) is set to simulate the distance between the IC A to be tested and the shielding cover 206 in the electronic device 200. When the bottom plate 121 is made of resin material, the dielectric constant of the resin material is somewhat different from that of air, usually between 2 and 4. Therefore, when setting the thickness of the bottom plate 121, it is necessary to calculate according to the actual situation to reduce the error. For example, taking a 50 ohm microstrip line as an example, according to the microstrip line characteristic impedance calculation formula:

[0054] It can be seen that when the thickness of the resin with a dielectric constant of 2.5 is about 1.63mm, it is equivalent to the effect of 1mm of air medium. At the same time, due to the complexity of the internal circuit of the integrated circuit or the radio frequency circuit, when determining the thickness of the resin material, it is also necessary to perform electromagnetic field simulation between the radio frequency chip and the shielding cover to ultimately determine the thickness of the base plate 121.

[0055] See also Fig.15 , Fig.15 for Figure 4 Schematic diagram of the process flow of the thickness adjustment method of the bottom plate 121 in the first fixing plate of the testing device.

[0056] like Figure 4 As shown, when the test device 100 performs an electrical performance test on the integrated circuit A to be tested, the ground loop formed by the conductive layer 122, the first conductive member 113 and the second conductive member 23 simulates the effect of the shielding cover 206 in the electronic device 200. The distance between the conductive layer 122 and the integrated circuit A to be tested is mainly controlled to simulate the effect of the shielding cover 206 in the electronic device 200. Figure 2 The shielding cover 206 in the electronic device 200 shown in the figure can achieve the same shielding effect. Therefore, it is necessary to reversely adjust the distance between the conductive layer 122 and the integrated circuit A to be tested through the distance between the shielding cover 206 and the integrated circuit B. When the grasping part controls the integrated circuit A to be tested to be located in the groove 21, there is a bottom plate 121 between the integrated circuit A to be tested and the conductive layer 122. The bottom plate 121 is an insulating layer. Therefore, the distance between the conductive layer 122 and the integrated circuit A to be tested can be adjusted by adjusting the thickness of the bottom plate 121.

[0057] like Fig.15 As shown, in the process of manufacturing the first fixing plate 10 of the testing device or adjusting the thickness of the bottom plate 121 during use, the specific steps include: S101, determining the distance between an integrated circuit and a shielding cover in an electronic device, and obtaining a first scattering parameter value through simulation.

[0058] When integrated circuit B ( Figure 2 ) is set on the printed circuit board 204 in the electronic device 200, assuming that the distance between the integrated circuit B and the shielding cover 206 is 0.1mm, that is, the medium between the integrated circuit B and the shielding cover 206 is air. Then, the scattering parameter between the integrated circuit B and the shielding cover 206, that is, the S parameter, is determined by simulation, that is, the scattering parameter when the medium between the simulated integrated circuit B and the shielding cover 206 is air, recorded as the first scattering parameter value. Among them, the integrated circuit A to be tested is the integrated circuit when it is tested at the factory, and the integrated circuit B is the integrated circuit set in the electronic device, and the difference between the two is only the different setting positions.

[0059] S102: a preset dielectric material is provided between the integrated circuit and the shielding cover, and the thickness of the preset dielectric material is adjusted to obtain a second scattering parameter value through simulation.

[0060] Specifically, the base plate 121 between the integrated circuit B and the shielding cover 206 is set with a preset dielectric material, for example, it can be set to a resin material, and the scattering parameters between the integrated circuit B and the shielding cover 206 are determined through simulation, that is, the scattering parameters when the base plate 121 is between the simulated integrated circuit B and the shielding cover 206, which is recorded as the second scattering parameter value.

[0061] S103, when the difference between the first scattering parameter value and the second scattering parameter value is within a preset range, obtaining the thickness of a preset dielectric material and using it as the thickness of a bottom plate in the test device, wherein the preset dielectric material is the same as the bottom plate material.

[0062] By adjusting the preset dielectric material to a preset thickness, the difference between the first scattering parameter and the second scattering parameter is controlled within a preset range. Preferably, the first scattering parameter is equal to the second scattering parameter. At this time, the scattering parameter when the integrated circuit B and the shielding cover 206 are air medium is equivalent to the scattering parameter when the integrated circuit B and the shielding cover 206 are preset dielectric material. The bottom plate 121 in the test device 100 is also made of the preset dielectric material. Therefore, it can be determined that the scattering parameter of the bottom plate 121 when reaching the preset thickness is the same as the scattering parameter between the integrated circuit B and the shielding cover 206 in the electronic device 200, thereby achieving the simulation of the shielding effect of the shielding cover 206 in the electronic device. In other words, the distance between the conductive layer 122 and the integrated circuit A to be tested in the test device can be adjusted by adjusting the thickness of the bottom plate 121, thereby achieving the simulation of the shielding effect of the shielding cover 206 in the electronic device 200, thereby eliminating the deviation of the integrated circuit between the test device and the electronic device.

[0063] The above disclosure is only part of the embodiments of the present application, which certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of implementing the above embodiments and equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A testing device, characterized in that: The invention comprises a first fixing plate, a second fixing plate and a circuit board, wherein the first fixing plate and the second fixing plate are arranged at a preset distance along a first direction, the circuit board is arranged on a side of the second fixing plate away from the first fixing plate, the second fixing plate comprises a groove, a plurality of ejectors connected to the circuit board are arranged in the groove, the first fixing plate is used to pick up an integrated circuit to be tested and move it into the groove, the ejectors are used to electrically connect the integrated circuit to be tested and the circuit board, and the circuit board is used to perform an electrical performance test on the integrated circuit to be tested, wherein the first fixing plate comprises a conductive layer and a first grounding layer, the conductive layer is arranged adjacent to the second fixing plate, the first grounding layer is arranged on a side of the conductive layer away from the second fixing plate, the conductive layer is electrically connected to the grounding layer, and the conductive layer is used to shield the integrated circuit to be tested.

2. The testing device according to claim 1, characterized in that: The first fixed plate includes a main body and a grabbing part which are stacked in sequence along the first direction, the first grounding layer is arranged in the main body, the grabbing part is arranged opposite to the groove, the grabbing part includes a base plate, the conductive layer and a vacuum tube, the conductive layer and the base plate are stacked in sequence along the first direction, the conductive layer is arranged adjacent to the main body, the vacuum tube is arranged through the conductive layer and the base plate along the first direction, and the grabbing part picks up the integrated circuit to be tested through the vacuum tube.

3. The testing device according to claim 2, characterized in that: The main body also includes a fixing layer, which is arranged between the first grounding layer and the grabbing portion, the first fixing plate also includes at least one first conductive member, and the second fixing plate also includes at least one second conductive member. The first conductive member is arranged around the grabbing portion and partially embedded in the fixing layer on a side adjacent to the second fixing plate, the second conductive member is arranged around the groove and partially embedded in the second fixing plate, the first conductive member and the second conductive member are arranged opposite to each other along the first direction, and when the first fixing plate and the second fixing plate are overlapped and assembled with each other, the first conductive member abuts against the second conductive member and is electrically connected.

4. The testing device according to claim 3, characterized in that: A plurality of conductors are arranged in the fixed layer, the first conductive member, the conductive layer and the first grounding layer are electrically connected through the conductive members, the circuit board includes a second grounding layer, the second conductive member is electrically connected to the second grounding layer, the integrated circuit to be tested is electrically connected to the second grounding layer through the ejector pin, and when the integrated circuit to be tested is located in the groove, a grounding loop is formed between the conductive layer, the first conductive member, the second conductive member and the integrated circuit to be tested.

5. The testing device according to claim 4, characterized in that: The multiple conductors include at least one first conductor arranged along the first direction and at least one second conductor arranged along the second direction, the first conductor is connected to the first ground layer and the conductive layer, and the second conductor is connected between the first conductor and the first conductive member, wherein the first direction is perpendicular to the second direction.

6. The testing device according to claim 4, characterized in that: The conductive layer is in a sheet-like structure or a mesh-like structure.

7. The testing device according to claim 5, characterized in that: The testing device also includes at least one elastic member, which is arranged between the first conductive member and the second conductive member, and the elastic member is electrically connected to the first grounding layer through the second conductive member and the first conductive member, and / or the elastic member is arranged between the second conductive member and the second grounding layer, and the second conductive member is electrically connected to the second grounding layer through the elastic member.

8. The testing device according to claim 7, characterized in that: The bottom of the groove includes a contact area, and the plurality of ejector pins are arranged in an array in the contact area. The second fixing plate also includes at least one shielding plate, which extends along the first direction and is arranged between the side wall of the groove and the contact area for shielding the integrated circuit to be tested.

9. The testing device according to claim 8, characterized in that: The second fixing plate includes four shielding plates. The contact area is rectangular in shape. The four shielding plates are extended along the first direction and disposed in the groove and are respectively adjacent to four sides of the contact area to enclose the contact area.

10. The testing device according to claim 9, characterized in that: The four shielding plates are connected end to end in the groove to form an accommodating space, and the contact area is located in the accommodating space.

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