Parasitic resistance network connectivity detection method and device and readable storage medium

Abstract

The invention discloses a parasitic resistance network connectivity detection method and device and a readable storage medium. The detection method comprises the following steps: A, establishing an empty node set; b, traversing each resistor in the resistor network, and obtaining all node IDs connected with each resistor; c, detecting the ID of each node, and judging whether nodes with the same ID can be found in the resistor node set or not; d, detecting the number of node groups in the resistor node set; and E, outputting detailed information of the resistance node set. By adopting the method and the device, the problems of difficulty in positioning and long time consumption when the parasitic resistance network breakpoint and the disconnection reason are positioned can be solved.

Description

Technical Field

[0001] The present invention relates to integrated circuit (IC) electronic design automation (EDA) technology, and in particular to a connectivity detection method, device and readable storage medium for a parasitic resistance network. Background Art

[0002] With the rapid development of integrated circuits (ICs), the complexity of circuits is also increasing. At present, with the development of very large-scale integrated circuits, the complexity of circuits has increased exponentially, making the adverse effects of parasitic parameters on circuit performance and functional realization more and more obvious. The accurate extraction and analysis of parasitic parameters is crucial to the performance of integrated circuits.

[0003] After extracting the parasitic parameters of the integrated circuit layout, it is also necessary to judge the connectivity of the extracted resistor network to verify and ensure the correctness of the parasitic parameter extraction. In addition, the ability to quickly locate the open circuit position in the resistor network is also crucial for analyzing the cause of the problem and shortening the iteration time of the integrated circuit design.

[0004] In the prior art, when it is found that the resistor network is not connected, that is, open / disconnected, it is often necessary to manually find all the disconnected resistor nodes, and then combine the layout (Layout) to analyze the connection relationship between each node / vertex (Node) and the connected graph (Graph) one by one. The nodes (Node) mentioned here include the nodes in the resistor network taken out, and specifically also include through holes, pins, and virtual points generated by cutting connecting lines during software analysis. The graph (Graph) includes the design drawing on the layout (Layout) where the node (Node) is located, such as the connecting lines, through holes, devices and other graphics drawn on different design layers in chip design.

[0005] The above process of manually searching for open / broken resistor nodes in a resistor network requires a lot of time to locate the actual location of the open / broken circuit. Especially in large-scale and ultra-large-scale integrated circuits, locating the location of the open / broken circuit will become more difficult and take longer. Summary of the invention

[0006] In view of this, the main purpose of the present invention is to provide a connectivity detection method, device and readable storage medium for a parasitic resistance network to solve the problem of difficult and time-consuming positioning when locating the breakpoints and disconnection causes of the parasitic resistance network.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] A method for detecting connectivity of a parasitic resistance network includes:

[0009] A. Create an empty node set;

[0010] B. Traverse each resistor in the resistor network and obtain all node IDs connected to each resistor;

[0011] C. Detect each node ID and determine whether a node with the same ID can be found in the resistor node set;

[0012] D. Detecting how many node groups there are in the resistance node set;

[0013] E. Detailed information of the output resistance node set.

[0014] Wherein: the step C also includes:

[0015] If not found, a new group is created and all node IDs are added to the node group; if it is found that a certain ID already exists in a node group in the node set, all node IDs are added to the existing node group.

[0016] The step D comprises:

[0017] If there is only one node group, it means that the parasitic resistance network is fully connected; otherwise, it means that there is an open circuit in the parasitic resistance network.

[0018] The detailed information of the output resistance node set in step E includes the number of node groups, the number of nodes contained in each node group and the specific node ID.

[0019] After step E, the step of determining the connectivity of all resistance nodes in each graph is further included, specifically:

[0020] F. Traverse all graphs involved in parasitic parameter extraction and obtain the nodes of the parasitic resistance network contained in each graph;

[0021] G. Determine whether each resistance node belongs to the same node group ID in the node set; if so, it means that the connectivity of the graph is complete; otherwise, it means that the parasitic resistance network extracted from the graph has an open circuit, and output detailed information of the graph.

[0022] Furthermore, the detailed information of the graph is outputted, including the graph coordinates, the layer, the resistor nodes included, and the node group to which each resistor node belongs.

[0023] The step G further comprises:

[0024] If the number of resistor network nodes contained in the graph is 0 or 1, further inspection is required in combination with the layout information.

[0025] A device for detecting connectivity of a parasitic resistance network, the device comprising:

[0026] A node set establishment module, used to establish an empty resistance node set;

[0027] A resistor network traversal module, used to traverse each resistor in the resistor network and obtain all node IDs connected to each resistor;

[0028] The node group creation and node storage module is used to detect each node ID and determine whether a node with the same ID can be found in the resistor node set; if not found, a new group is created and all node IDs are added to the node group; if a certain ID is found to already exist in a node group in the node set, all node IDs are added to the existing node group;

[0029] The node group detection module is used to detect how many node groups there are in the resistance node set; if there is only one node group, it means that the parasitic resistance network is fully connected; otherwise, it means that there is an open circuit in the parasitic resistance network.

[0030] The detection device also includes:

[0031] A layout traversal module is used to traverse all graphics involved in parasitic parameter extraction and obtain the node ID of the parasitic resistance network contained in each graphic;

[0032] The graph extraction and parasitic resistance network connectivity judgment module is used to judge whether each resistance node belongs to the same node group ID in the node set; if each node group ID belongs to the same node group, it means that the connectivity of the graph is complete; otherwise, if they do not belong to the same node group, it means that the parasitic resistance network extracted from the graph has an open circuit / break circuit; if there is an open circuit / break circuit, the information of the graph is output in detail, including the graph coordinates, the layer, the resistance nodes contained, and the node group information to which each resistance node belongs.

[0033] A readable storage medium stores a computer program, wherein the computer program is configured to implement the connectivity detection method of a parasitic resistance network when executed by at least one processor.

[0034] A device for detecting connectivity of a parasitic resistor network comprises the program module described in the detection device, and also comprises a memory and at least one processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes the steps of the method for detecting connectivity of the parasitic resistor network.

[0035] The connectivity detection method, device and readable storage medium of the parasitic resistance network of the present invention have the following beneficial effects:

[0036] The connectivity detection method and device of the parasitic resistor network of the present invention can automatically detect the connectivity problem of the parasitic resistor network to verify the parasitic parameters, especially the correctness of the parasitic resistor network design. The present invention can not only automatically detect the open circuit / breakpoint of the parasitic resistor network, but also output detailed error reports and positioning information, accurate to the network connectivity information of each graph, and can assist in quickly locating the cause of the open circuit / break circuit, greatly improving the efficiency of integrated circuit design verification, and can effectively shorten the iteration cycle of integrated circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic flow chart of a method for detecting connectivity of a parasitic resistance network according to an embodiment of the present invention;

[0038] Figure 2 It is a schematic flow chart of a method for determining connectivity of a graph-level parasitic resistance network according to an embodiment of the present invention;

[0039] Figure 3 Schematic diagram of a resistor network structure including five nodes in an embodiment of the present invention;

[0040] Figure 4 Schematic diagram of the function of a connectivity detection device for a parasitic resistance network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The technical scheme in the embodiments of the present application is described in detail below in conjunction with the accompanying drawings and embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of this application.

[0042] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0043] In order to achieve the purpose of the present invention, it is necessary to first obtain the parasitic resistance network of the integrated circuit. Then the resistance network is judged for connectivity to identify the full connection and open / open circuit situations in the resistance network. When the existence of an open circuit / open circuit is detected, a log file containing the above-mentioned problem information is automatically generated and recorded, such as a node list of each connected part in the resistance network. Further, if there is an open circuit / open circuit, the connectivity of all resistance nodes of each graph will be judged, and disconnected graphs will be identified. For the disconnected graph, the connected part to which the node belongs is output to assist the user in locating the location information of the disconnected problem. If the number of nodes in the graph is 0 or 1, the user is prompted to check the connection relationship of the graph in the layout, as well as the correctness of other input files. Finally, a detailed error report is generated. The detailed error report includes contents such as the open circuit / open circuit position, the affected graphic information, the number of nodes and the node information.

[0044] Figure 1 Schematic diagram of a flow chart of a method for detecting connectivity of a parasitic resistance network according to an embodiment of the present invention.

[0045] like Figure 1 As shown, the connectivity detection method of the parasitic resistance network includes the following steps:

[0046] Step 11: Create an empty node set.

[0047] Step 12: Traverse each resistor in the resistor network and obtain all node IDs connected to each resistor.

[0048] The present invention Figure 3 The resistor network shown contains five nodes as an example.

[0049] like Figure 3 As shown, the traversal algorithm is first executed to traverse each resistor in the resistor network to obtain all resistors in the resistor network and their node IDs, such as resistor (R): 0 4; R: 4 3; R: 3 2; R: 2 1.

[0050] Step 13: Detect each node ID and determine whether a node with the same ID can be found in the resistor node set.

[0051] After traversing each resistor, if all nodes can be placed in the same node group in the node set, it means that the entire parasitic resistance network is fully connected.

[0052] like Figure 3As shown in the figure, all the resistors in the resistor network: R:0 4; R:4 3; R:3 2; R:2 1. can be put into the same node group in the node set, which means that the five nodes in the resistor network are fully connected, that is, they form a resistor connection path.

[0053] If none of them are found, a new node group is created and all node IDs are added to the node group; if it is found that a certain ID already exists in a node group in the node set, all node IDs are added to the existing node group.

[0054] Step 14: Detect how many node groups there are in the resistance node set. If there is only one node group, it means that the parasitic resistance network is fully connected. Otherwise, if there are multiple node groups, it means that there is an open circuit / break circuit in the parasitic resistance network.

[0055] like Figure 3 As shown, it is assumed that there are resistors: R:0 4; R:4 3; R:2 1. It shows that the five resistor nodes are assigned to two node groups, namely node group 1: including nodes 0, 3, and 4; node group 2: including nodes 1 and 2. Since the resistor node set contains more than one node group, it means that there is an open circuit / broken circuit (Open) in the resistor network.

[0056] Step 15: Output detailed information of the resistance node set. The output node set information includes the number of node groups, the number of nodes contained in each node group, and which nodes are contained, that is, node IDs and other information.

[0057] Here, the output information can be used to assist the user in locating problems (open circuits) in the parasitic resistance network connectivity of the parasitic resistance network.

[0058] As assumed in step 14, the generated log file is "part1: 0 3 4part2: 1 2", indicating that there are two independent connected parts in the resistor network, that is, nodes 0, 3, and 4 are connected to each other, and nodes 2 and 1 are connected. However, there is no resistance connection between the two connected parts.

[0059] Furthermore, the above-mentioned parasitic resistance network connectivity detection method also includes a connectivity judgment process for the graphic-level parasitic resistance network in the layout.

[0060] Figure 2 The figure is a schematic flow chart of a method for determining connectivity of a graph-level parasitic resistance network according to an embodiment of the present invention.

[0061] like Figure 2As shown, the connectivity determination method of the graphical level parasitic resistance network includes the following steps:

[0062] Step 21: Traverse all graphs involved in parasitic parameter extraction.

[0063] Step 22: Get the node ID of the parasitic resistance network contained on each graph.

[0064] Step 23: Determine whether each resistance node belongs to the same node group ID in the node set. If each node group ID belongs to the same node group, it means that the connectivity of the graph is complete. Otherwise, if they do not belong to the same node group, it means that the parasitic resistance network extracted from the graph has an open circuit / break circuit.

[0065] refer to Figure 3 , assuming that the extracted parasitic resistance network has a node set: R:0 4; R:4 3; R:2 1. The generated node set has two node groups, namely node group 1: including nodes 0, 3, and 4; node group 2: including nodes 1 and 2. This means that there is an open circuit / break between the above two node groups.

[0066] like Figure 3 As shown, when Shape3 in the figure shown is processed, it contains nodes 1, 2, and 3. Among them, 1 and 2 belong to node group 2, and 3 belongs to node group 1. This indicates that the parasitic resistance network extracted from the figure has an open circuit / broken circuit.

[0067] Step 24: If there is an open circuit / broken circuit, the information of the graph is output in detail, such as the graph coordinates, the layer it is in, the resistance nodes it contains, the node group to which each resistance node belongs, etc.

[0068] This can help integrated circuit designers quickly locate the location of problems (such as open circuits / broken circuits), thereby facilitating rapid detection of the layout.

[0069] Furthermore, it also includes:

[0070] Step 25: If the number of resistance network nodes contained in the graph is 0 or 1, it means that the graph itself may be isolated, or there may be a problem with the connection relationship of the graph.

[0071] At this time, further inspection is required in combination with the layout information.

[0072] Based on the same inventive concept, the present application also provides a detection device for executing the above steps 11 to 15 and / or steps 21 to 25 to implement the connectivity detection method of the parasitic resistance network.

[0073] Figure 4Schematic diagram of the function of a connectivity detection device for a parasitic resistance network according to an embodiment of the present invention.

[0074] like Figure 4 As shown, the detection device mainly includes:

[0075] The node set creation module is used to create an empty node set.

[0076] The resistor network traversal module is used to traverse each resistor in the resistor network and obtain all node IDs connected to each resistor.

[0077] The node group creation and node storage module is used to detect each node ID and determine whether a node with the same ID can be found in the resistor node set; if not found, a new group is established and all node IDs are added to the node group; if a certain ID is found to already exist in a node group in the node set, all node IDs are added to the existing node group.

[0078] The node group detection module is used to detect how many node groups there are in the resistor node set; if there is only one node group, it means that the parasitic resistor network is fully connected; otherwise, it means that there is an open circuit in the parasitic resistor network. It is also used to output relevant detailed information of the resistor node set. The information of the output node set includes the number of node groups, the number of nodes contained in each node group, and which nodes are contained, i.e., node IDs, etc.

[0079] Here, the output information can be used to assist the user in locating problems (open circuits) in the parasitic resistance network connectivity of the parasitic resistance network.

[0080] Furthermore, the detection device also includes:

[0081] The layout traversal module is used to traverse all graphs involved in parasitic parameter extraction and obtain the node ID of the parasitic resistance network contained in each graph.

[0082] The graphics extraction and parasitic resistance network connectivity judgment module is used to determine whether each resistance node belongs to the same node group ID in the node set. If each node group ID belongs to the same node group, it means that the connectivity of the graph is complete. Otherwise, if it does not belong to the same node group, it means that the parasitic resistance network extracted from the graph has an open circuit / broken circuit. If there is an open circuit / broken circuit, the information of the graph is output in detail, such as the graph coordinates, the layer, the resistance nodes contained, the node group to which each resistance node belongs, etc. It is also used to output abnormal information: when it is judged that the number of resistance network nodes contained in the graph is 0 or 1, it means that the graph may be isolated itself, or there may be a problem with the connection relationship of the graph. At this time, an abnormal prompt message is output to remind the tester that further inspection is required in combination with the layout information.

[0083] Based on the same inventive concept, the present invention also provides a device comprising the connectivity detection device of the parasitic resistance network, that is, a connectivity detection device of the parasitic resistance network, wherein the detection device comprises the above-mentioned program module, and also includes a memory and at least one processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes the steps of the connectivity detection method of the parasitic resistance network described in the above-mentioned embodiments.

[0084] The present invention also provides a readable storage medium storing a computer program, wherein the computer program is configured to implement the above-mentioned parasitic resistance network connectivity determination method when executed by at least one processor.

[0085] The readable storage medium is a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. Specifically, the readable storage medium may be a tangible device capable of maintaining and storing instructions used by an instruction execution device, such as an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any combination of the above. More specific examples of readable storage media include: a computer hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash chip, a static random access memory (SRAM), a CD-ROM, a DVD, etc.

[0086] The above description is only a description of the preferred embodiments of the present application in combination with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for detecting connectivity of a parasitic resistance network, characterized in that: include: A. Create an empty node set; B. Traverse each resistor in the resistor network and obtain all node IDs connected to each resistor; C. Detect each node ID and determine whether a node with the same ID can be found in the resistor node set; D. Detecting how many node groups there are in the resistance node set; E. Detailed information of the output resistance node set.

2. The method for detecting connectivity of a parasitic resistance network according to claim 1, characterized in that: The step C also includes: If not found, a new group is created and all node IDs are added to the node group; if it is found that a certain ID already exists in a node group in the node set, all node IDs are added to the existing node group.

3. The method for detecting connectivity of a parasitic resistance network according to claim 1, characterized in that: The step D comprises: If there is only one node group, it means that the parasitic resistance network is fully connected; otherwise, it means that there is an open circuit in the parasitic resistance network.

4. The method for detecting connectivity of a parasitic resistance network according to claim 1, characterized in that: The detailed information of the output resistance node set in step E includes the number of node groups, the number of nodes contained in each node group and the specific node ID.

5. The method for detecting connectivity of a parasitic resistance network according to claim 3, characterized in that: After step E, the step of determining the connectivity of all resistance nodes in each graph is further included, specifically: F. Traverse all graphs involved in parasitic parameter extraction and obtain the nodes of the parasitic resistance network contained in each graph; G. Determine whether each resistor node belongs to the same node group ID in the node set; if so, it indicates that the connectivity of the graph is complete; Otherwise, it means that the parasitic resistance network extracted from the graph has an open circuit, and the detailed information of the graph is output.

6. The method for detecting connectivity of the parasitic resistance network according to claim 5, characterized in that: The detailed information of the outputted graph includes the graph coordinates, the layer, the resistor nodes included, and the node group to which each resistor node belongs.

7. The method for detecting connectivity of the parasitic resistance network according to claim 5, characterized in that: The step G further comprises: If the number of resistor network nodes contained in the graph is 0 or 1, further inspection is required in combination with the layout information.

8. A device for detecting connectivity of a parasitic resistance network, characterized in that: The detection device comprises: A node set establishment module, used to establish an empty resistance node set; A resistor network traversal module, used to traverse each resistor in the resistor network and obtain all node IDs connected to each resistor; The node group creation and node storage module is used to detect each node ID and determine whether a node with the same ID can be found in the resistor node set; if not found, a new group is created and all node IDs are added to the node group; if a certain ID is found to already exist in a node group in the node set, all node IDs are added to the existing node group; The node group detection module is used to detect how many node groups there are in the resistance node set; if there is only one node group, it means that the parasitic resistance network is fully connected; otherwise, it means that there is an open circuit in the parasitic resistance network.

9. The parasitic resistance network connectivity detection device according to claim 8, characterized in that: The detection device also includes: A layout traversal module is used to traverse all graphics involved in parasitic parameter extraction and obtain the node ID of the parasitic resistance network contained in each graphic; The graph extraction and parasitic resistance network connectivity judgment module is used to judge whether each resistance node belongs to the same node group ID in the node set; if each node group ID belongs to the same node group, it means that the connectivity of the graph is complete; otherwise, if they do not belong to the same node group, it means that the parasitic resistance network extracted from the graph has an open circuit / break circuit; if there is an open circuit / break circuit, the information of the graph is output in detail, including the graph coordinates, the layer, the resistance nodes contained, and the node group information to which each resistance node belongs.

10. A readable storage medium storing a computer program, characterized in that: The computer program is configured to implement the connectivity detection method of the parasitic resistance network according to any one of claims 1 to 7 when being executed by at least one processor.

11. A parasitic resistance network connectivity detection device, characterized in that: The program module comprises the detection device as claimed in claim 8 or 9, and further comprises a memory and at least one processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes the steps of the connectivity detection method of the parasitic resistance network as claimed in any one of claims 1 to 7.

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