Underwater multi-FPGA synchronous acquisition control system

Abstract

The invention relates to an underwater multi-FPGA (Field Programmable Gate Array) synchronous acquisition control system, which comprises a control module and a plurality of acquisition modules, the control module comprises a control FPGA unit and a reference clock source; the acquisition module comprises an acquisition FPGA unit and a plurality of acquisition channel circuits; the control FPGA unit is connected with the reference clock source and each acquisition FPGA unit; the acquisition FPGA unit is connected with each acquisition channel circuit in the acquisition module where the acquisition FPGA unit is located; the reference clock source is used for constructing a clock network among the control FPGA unit, the acquisition FPGA unit and the acquisition channel circuit; the clock network is used for realizing synchronous control of the FPGA unit on the acquisition FPGA units and synchronous control of the acquisition FPGA units on the acquisition channel circuits connected with the acquisition FPGA units; the control FPGA unit controls each acquisition channel circuit in each acquisition FPGA unit to perform synchronous underwater data acquisition based on a clock network; and the acquisition FPGA unit synchronously uploads the underwater data acquired in each acquisition channel circuit to the control FPGA unit based on a clock network.

Description

Technical Field

[0001] The present application relates to the field of underwater survey technology, and in particular to an underwater multi-FPGA synchronous acquisition control system. Background Art

[0002] The multi-channel acquisition system is an important equipment in the underwater detection industry. In the existing technology, underwater data is collected through a multi-channel acquisition system. The existing multi-channel acquisition system collects data from all channels through an FPGA chip and uploads it. As performance requirements continue to increase, the number of channels continues to increase. Dragging so many channels through only one FPGA chip will cause the design to become complicated.

[0003] The existing multi-channel acquisition system has the following disadvantages:

[0004] 1) Insufficient expansion and upgrading capabilities. Increasing the number of channels requires redevelopment, increasing product upgrade costs and market risks;

[0005] 2) The spatial layout is difficult and the layout cannot be optimized due to the limited structure size. Summary of the invention

[0006] In order to at least to some extent overcome the problems of insufficient expansion and upgrading capabilities and difficulty in spatial layout of multi-channel acquisition systems in related technologies, the present application provides an underwater multi-FPGA synchronous acquisition control system.

[0007] The scheme of this application is as follows:

[0008] An underwater multi-FPGA (Field Programmable Gate Array) synchronous acquisition control system, comprising:

[0009] One control module and multiple acquisition modules;

[0010] The control module includes: controlling the FPGA unit and the reference clock source;

[0011] The acquisition module includes: an acquisition FPGA unit and a plurality of acquisition channel circuits;

[0012] The control FPGA unit is connected to the reference clock source and each acquisition FPGA unit;

[0013] The acquisition FPGA unit is connected to each acquisition channel circuit inside the acquisition module where it is located;

[0014] The reference clock source is used to construct a clock network between the control FPGA unit, the acquisition FPGA unit and the acquisition channel circuit; the clock network is used to realize the synchronization control between the acquisition FPGA units by the control FPGA unit, and the synchronization control between the acquisition channel circuits connected to it by the acquisition FPGA unit;

[0015] The control FPGA unit controls each acquisition channel circuit in each acquisition FPGA unit to perform synchronous underwater data acquisition based on the clock network;

[0016] The acquisition FPGA unit synchronously uploads the underwater data collected in each acquisition channel circuit to the control FPGA unit based on the clock network.

[0017] Preferably, the control FPGA unit divides the reference clock source into a plurality of working clocks, and sends the working clocks to the acquisition FPGA unit one by one.

[0018] Preferably, the acquisition FPGA unit divides the working clock sent by the control FPGA unit and sends the divided clock to the acquisition channel circuits one by one.

[0019] Preferably, the control FPGA unit divides the reference clock source into a plurality of working clocks through an internal phase-locked loop.

[0020] Preferably, the acquisition FPGA unit divides the working clock sent by the control FPGA unit through an internal phase-locked loop.

[0021] Preferably, the control module further includes: a main isolation chip;

[0022] The control FPGA unit sends acquisition instructions to the acquisition FPGA unit through the main isolation chip, or receives underwater data uploaded by the acquisition FPGA unit.

[0023] Preferably, the acquisition module further includes: a sub-isolation chip;

[0024] The acquisition FPGA unit uploads underwater data to the control FPGA unit through the sub-isolation chip, or receives acquisition instructions issued by the control FPGA unit.

[0025] Preferably, the control FPGA unit is connected to each acquisition FPGA unit via a serial bus.

[0026] Preferably, an acquisition ADC (analog-to-digital converter) is provided in the acquisition channel circuit.

[0027] Preferably, the total number of the acquisition channel circuits is a multiple of 4 and is at least 96.

[0028] The technical solution provided by the present application may include the following beneficial effects: the underwater multi-FPGA synchronous acquisition control system in the present application includes: a control module and multiple acquisition modules; the control module includes: a control FPGA unit and a reference clock source; the acquisition module includes: an acquisition FPGA unit and multiple acquisition channel circuits; the control FPGA unit is connected to the reference clock source and each acquisition FPGA unit; the acquisition FPGA unit is connected to each acquisition channel circuit inside the acquisition module where it is located; the reference clock source is used to construct a clock network between the control FPGA unit, the acquisition FPGA unit and the acquisition channel circuit; the clock network is used to realize the synchronous control between the acquisition FPGA units by the control FPGA unit, and the synchronous control between the acquisition channel circuits connected to it by the acquisition FPGA unit; the control FPGA unit controls each acquisition channel circuit in each acquisition FPGA unit based on the clock network to perform synchronous underwater data acquisition; the acquisition FPGA unit synchronously uploads the underwater data collected in each acquisition channel circuit to the control FPGA unit based on the clock network.

[0029] In the architecture of this technical solution, the control module only needs to control the acquisition module, and the acquisition channel circuits inside the module are controlled through the acquisition FPGA unit in the acquisition module, thereby forming a tree-shaped control structure, reducing the burden of the control FPGA unit, and when expanding the product, it is sufficient to add acquisition modules, and the design of the control module connecting multiple acquisition modules is more flexible than the design of the control module directly connecting all acquisition channel circuits. Therefore, the architecture of this technical solution can enhance the product expansion and upgrade capabilities, and reduce the R&D costs and risks of product upgrades. And it can solve the acquisition system design problems of products with limited space size. In this technical solution, by constructing a clock network, the control FPGA unit can realize the synchronous control between the acquisition FPGA units, and the acquisition FPGA unit can realize the synchronous control between the acquisition channel circuits connected to it, so that the acquisition channel circuits can keep synchronization when performing data acquisition.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] Figure 1 It is a structural schematic diagram of an underwater multi-FPGA synchronous acquisition control system provided by an embodiment of the present application;

[0033] Figure 2This is a working principle diagram of an acquisition module in an underwater multi-FPGA synchronous acquisition control system provided by an embodiment of the present application;

[0034] Figure 3 This is a working principle diagram of a control module in an underwater multi-FPGA synchronous acquisition control system provided by an embodiment of the present application;

[0035] Figure 4 This is a synchronous clock timing diagram of an underwater multi-FPGA synchronous acquisition control system during operation provided by an embodiment of the present application.

[0036] Figure numerals: control module-1; control FPGA unit-11; reference clock source-12; main isolation chip-13; acquisition module-2; acquisition FPGA unit-21; acquisition channel circuit-22; sub-isolation chip--23. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0038] Figure 1 This is a schematic diagram of the structure of an underwater multi-FPGA synchronous acquisition control system provided by an embodiment of the present application, referring to Figure 1 , an underwater multi-FPGA synchronous acquisition control system, comprising:

[0039] A control module 1 and multiple acquisition modules 2;

[0040] The control module 1 includes: a control FPGA unit 11 and a reference clock source 12;

[0041] The acquisition module 2 includes: an acquisition FPGA unit 21 and a plurality of acquisition channel circuits 22;

[0042] The control FPGA unit 11 is connected to the reference clock source 12 and each acquisition FPGA unit 21;

[0043] The acquisition FPGA unit 21 is connected to each acquisition channel circuit 22 inside the acquisition module 2 where it is located;

[0044] The reference clock source 12 is used to construct a clock network between the control FPGA unit 11, the acquisition FPGA unit 21 and the acquisition channel circuit 22; the clock network is used to realize the synchronization control between the acquisition FPGA units 21 by the control FPGA unit 11, and the synchronization control between the acquisition channel circuits 22 connected to the acquisition FPGA unit 21;

[0045] The control FPGA unit 11 controls each acquisition channel circuit 22 in each acquisition FPGA unit 21 to perform synchronous underwater data acquisition based on the clock network;

[0046] The acquisition FPGA unit 21 synchronously uploads the underwater data collected in each acquisition channel circuit 22 to the control FPGA unit 11 based on the clock network.

[0047] FPGA devices are a kind of semi-customized circuit in application-specific integrated circuits. They are programmable logic arrays that can effectively solve the problem of the small number of gate circuits in the original devices. The basic structure of FPGA includes programmable input and output units, configurable logic blocks, digital clock management modules, embedded block RAM, wiring resources, embedded dedicated hard cores, and bottom-level embedded functional units. Since FPGA has the characteristics of rich wiring resources, reprogrammable and high integration, and low investment, it has been widely used in the field of digital circuit design. In this embodiment, the FPGA unit is used as the main chip in the control module 1 and the acquisition module 2.

[0048] It should be noted that the reference clock source 12 in this embodiment can be a crystal oscillator-level clock.

[0049] Underwater data collection requires that the collected data of each channel be sampled synchronously, and the number of channels for underwater collection is often hundreds of collection channel circuits 22, so the clock network of each collection channel circuit 22 needs to be planned.

[0050] like Figure 2 As shown, the acquisition FPGA unit 21 divides the working clock sent by the control FPGA unit 11 and sends it one-to-one to the acquisition channel circuit 22. Specifically, the acquisition FPGA unit 21 divides the working clock sent by the control FPGA unit 11 through an internal phase-locked loop.

[0051] like Figure 3 As shown, the control FPGA unit 11 divides the reference clock source 12 into multiple working clocks, and sends the working clocks one by one to the acquisition FPGA unit 21. Specifically, the control FPGA unit 11 divides the reference clock source 12 into multiple working clocks through an internal phase-locked loop.

[0052] A phase locked loop (PLL) is a negative feedback control system that uses the voltage generated by phase synchronization to tune a voltage controlled oscillator to generate a target frequency. According to the principle of automatic control, this is a typical feedback control circuit that uses an external reference signal to control the frequency and phase of the oscillation signal inside the loop, and realizes the automatic tracking of the output signal frequency to the input signal frequency. It is generally used in a closed-loop tracking circuit. It is a method to make the frequency more stable in radio transmission. It mainly includes VCO (voltage controlled oscillator) and PLL IC (phase locked loop integrated circuit). The voltage controlled oscillator gives a signal, one part of which is used as output, and the other part is compared with the local oscillator signal generated by the PLL IC through frequency division. In order to keep the frequency unchanged, the phase difference is required not to change. If there is a change in the phase difference, the voltage at the voltage output terminal of the PLL IC changes to control the VCO until the phase difference is restored to achieve the purpose of phase locking. A closed-loop electronic circuit that can keep the frequency and phase of the controlled oscillator in a certain relationship with the input signal.

[0053] Figure 4 For the synchronous clock timing diagram, Figure 4 As shown, Figure 4 Each acquisition channel circuit 22 in the control unit FPGA is kept consistent with the control unit FPGA 11, so that the control unit FPGA 11 can synchronously control all acquisition channel circuits 22.

[0054] In this technical solution, the control module 1 also includes: a main isolation chip 13;

[0055] The control FPGA unit 11 sends a collection instruction to the collection FPGA unit 21 through the main isolation chip 13 , or receives underwater data uploaded by the collection FPGA unit 21 .

[0056] The acquisition module 2 also includes: a sub-isolation chip 23;

[0057] The acquisition FPGA unit 21 uploads underwater data to the control FPGA unit 11 through the sub-isolation chip 23 , or receives an acquisition instruction issued by the control FPGA unit 11 .

[0058] Due to the problem of noise superposition interference caused by the increase in the number of channels in the prior art, in the present technical solution, an isolation chip is set up to enable the control FPGA unit 11 to send acquisition instructions to the acquisition FPGA unit 21 through the main isolation chip 13, or receive underwater data uploaded by the acquisition FPGA unit 21, so that the acquisition FPGA unit 21 uploads underwater data to the control FPGA unit 11 through the sub-isolation chip 23, or receives acquisition instructions issued by the control FPGA unit 11, and through the internal integrated isolation function, the increase in system noise caused by the increase in the number of channels is solved.

[0059] It should be noted that the control FPGA unit 11 is connected to each acquisition FPGA unit 21 via a serial bus, and an acquisition ADC is provided in the acquisition channel circuit 22 .

[0060] The high-speed serial bus has the characteristics of anti-interference and long wiring. The high-speed serial bus follows the standard high-speed protocol, supports verification, retransmission and meets high bandwidth requirements. The high-speed serial bus reduces IO occupancy compared to the parallel bus.

[0061] In specific practice, the total number of acquisition channel circuits 22 is a multiple of 4, and is at least 96.

[0062] In the architecture of the present technical solution, the control module 1 only needs to control the acquisition module 2, and the acquisition channel circuits 22 inside the module are controlled by the acquisition FPGA unit 21 in the acquisition module 2, thereby forming a tree-shaped control structure, reducing the burden of the control FPGA unit 11, and when expanding the product, it is sufficient to add the acquisition module 2, and the design of the control module 1 connecting multiple acquisition modules 2 is more flexible than the design of the control module 1 directly connecting all the acquisition channel circuits 22, so the architecture of the present technical solution can improve the product expansion and upgrading capabilities, reduce the product upgrade research and development costs and risks. And it can solve the acquisition system design problems of products with limited space size. In the present technical solution, by constructing a clock network, the control FPGA unit 11 can realize the synchronous control between the acquisition FPGA units 21, and the acquisition FPGA unit 21 can realize the synchronous control between the acquisition channel circuits 22 connected to it, so that each acquisition channel circuit 22 can keep synchronization when performing data acquisition.

[0063] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0064] It should be noted that, in the description of this application, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0065] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0066] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0067] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0068] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0069] The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0070] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0071] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An underwater multi-FPGA synchronous acquisition control system, characterized in that: include: One control module and multiple acquisition modules; The control module includes: controlling the FPGA unit and the reference clock source; The acquisition module includes: an acquisition FPGA unit and a plurality of acquisition channel circuits; The control FPGA unit is connected to the reference clock source and each acquisition FPGA unit; The acquisition FPGA unit is connected to each acquisition channel circuit inside the acquisition module where it is located; The reference clock source is used to construct a clock network between the control FPGA unit, the acquisition FPGA unit and the acquisition channel circuit; the clock network is used to realize the synchronization control between the acquisition FPGA units by the control FPGA unit, and the synchronization control between the acquisition channel circuits connected to it by the acquisition FPGA unit; The control FPGA unit controls each acquisition channel circuit in each acquisition FPGA unit to perform synchronous underwater data acquisition based on the clock network; The acquisition FPGA unit synchronously uploads the underwater data collected in each acquisition channel circuit to the control FPGA unit based on the clock network.

2. The underwater multi-FPGA synchronous acquisition control system according to claim 1 is characterized in that: The control FPGA unit divides the reference clock source into a plurality of working clocks, and sends the working clocks to the acquisition FPGA unit one by one.

3. The underwater multi-FPGA synchronous acquisition control system according to claim 2 is characterized in that: The acquisition FPGA unit divides the working clock sent by the control FPGA unit and sends the divided clock to the acquisition channel circuits one by one.

4. The underwater multi-FPGA synchronous acquisition control system according to claim 2 is characterized in that: The control FPGA unit divides the reference clock source into a plurality of working clocks through an internal phase-locked loop.

5. The underwater multi-FPGA synchronous acquisition control system according to claim 3 is characterized in that: The acquisition FPGA unit divides the working clock sent by the control FPGA unit through an internal phase-locked loop.

6. The underwater multi-FPGA synchronous acquisition control system according to claim 1, characterized in that: The control module also includes: a main isolation chip; The control FPGA unit sends acquisition instructions to the acquisition FPGA unit through the main isolation chip, or receives underwater data uploaded by the acquisition FPGA unit.

7. The underwater multi-FPGA synchronous acquisition control system according to claim 1 is characterized in that: The acquisition module also includes: a sub-isolation chip; The acquisition FPGA unit uploads underwater data to the control FPGA unit through the sub-isolation chip, or receives acquisition instructions issued by the control FPGA unit.

8. The underwater multi-FPGA synchronous acquisition control system according to claim 1, characterized in that: The control FPGA unit is connected to each acquisition FPGA unit via a serial bus.

9. The underwater multi-FPGA synchronous acquisition control system according to claim 1, characterized in that: The acquisition channel circuit is provided with an acquisition ADC.

10. The underwater multi-FPGA synchronous acquisition control system according to claim 1, characterized in that: The total number of the acquisition channel circuits is a multiple of 4 and is at least 96.

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