Low-dropout linear voltage stabilizing circuit, low-dropout linear voltage stabilizer, and electronic device

Abstract

The application belongs to the technical field of electronic circuits, and provides a low-dropout linear voltage stabilizing circuit, a low-dropout linear voltage stabilizer and electronic equipment. The low-dropout linear voltage stabilizing circuit comprises an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module. The buffer module is connected with the error amplification module, the power module and the transient enhancement module respectively. The power module is connected with the transient enhancement module, the feedback module and a load respectively. The feedback module is connected with the error amplification module. When the current on the load changes, the transient enhancement module provides a first current to the power module according to a target voltage, so that the power module quickly adjusts the target voltage according to the first current and quickly responds to the change of the load. The feedback module outputs a feedback voltage according to the target voltage. The error amplification module outputs an error signal according to the feedback voltage and a reference voltage. The buffer module outputs a driving signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the driving signal.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic circuits, and particularly relates to a low-dropout linear voltage stabilizing circuit, a low-dropout linear voltage stabilizer and electronic equipment. BACKGROUND

[0002] A low-dropout linear voltage stabilizer (LDO) has good power impulse suppression and fast response speed, and is therefore widely used in low-noise circuits. In transient response, when the current on the load changes from small to large, the power tube cannot provide the required current of the load due to insufficient response speed, resulting in rapid reduction of the output voltage and occurrence of a downward voltage spike, referred to as undershoot. Similarly, when the current on the load changes from large to small, the power tube cannot provide the required current of the load due to insufficient response speed, resulting in rapid increase of the output voltage and occurrence of an upward voltage spike, referred to as overshoot. Excessive voltage spikes can cause damage to the circuit.

[0003] A conventional LDO circuit uses a micro-farad-level large capacitor to achieve fast transient response, so as to reduce damage to the circuit caused by voltage spikes. However, to drive a micro-farad-level large capacitor, a large-size power tube is required, which not only increases the area and cost of the circuit, but also affects the overall performance of the circuit. SUMMARY

[0004] The low-dropout linear voltage stabilizing circuit, the low-dropout linear voltage stabilizer and the electronic equipment provided in the embodiments of the application can solve the problems of large circuit area and high cost of the conventional LDO circuit.

[0005] In a first aspect, the embodiments of the application provide a low-dropout linear voltage stabilizing circuit, comprising an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module, the buffer module is connected with the error amplification module, the power module and the transient enhancement module, the power module is connected with the transient enhancement module, the feedback module and a load, and the feedback module is connected with the error amplification module.

[0006] When the current on the load changes, the transient enhancement module is configured to provide a first current to the power module according to a target voltage, so that the power module quickly adjusts the target voltage according to the first current; the feedback module is configured to output a feedback voltage according to the target voltage; the error amplification module is configured to output an error signal according to the feedback voltage and a reference voltage; and the buffer module is configured to output a driving signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the driving signal; wherein the target voltage is an output voltage of the low-dropout linear voltage stabilizing circuit.

[0007] In a possible implementation manner of the first aspect, the transient enhancement module comprises a coupling unit, a first current mirror unit and a second current mirror unit, the coupling unit is connected with the power module, the first current mirror unit and the second current mirror unit respectively, and the first current mirror unit is connected with the power module and the second current mirror unit respectively; the first current comprises a second current and a third current.

[0008] When the current on the load changes from small to large, the coupling unit is configured to output a first coupling signal according to the target voltage; the first current mirror unit is configured to provide the second current to the power module according to the first coupling signal; the power module is configured to rapidly adjust the target voltage according to the second current, so that the target voltage becomes large; the second current mirror unit is configured to enter an off state according to the first coupling signal; when the current on the load changes from large to small, the coupling unit is configured to output a second coupling signal according to the target voltage; the second current mirror unit is configured to provide the third current to the power module according to the second coupling signal; the power module is configured to rapidly adjust the target voltage according to the third current, so that the target voltage becomes small; and the first current mirror unit is configured to enter an off state according to the second coupling signal.

[0009] In a possible implementation manner of the first aspect, the first current mirror unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first current source, the source of the first transistor and the source of the second transistor both receive a power supply voltage, the gate of the first transistor is connected with the drain of the first transistor, the first end of the first current source, the source of the fifth transistor and the source of the seventh transistor respectively, the second end of the first current source is grounded, the drain of the fifth transistor is connected with the drain of the sixth transistor, the gate of the fifth transistor and the gate of the sixth transistor respectively, the source of the sixth transistor is connected with the gate of the second transistor and the drain of the seventh transistor respectively, the gate of the seventh transistor is connected with the coupling unit and the second current mirror unit respectively, the drain of the second transistor is connected with the drain of the third transistor, the gate of the third transistor and the gate of the fourth transistor respectively, the drain of the fourth transistor is connected with the power module and the second current mirror unit respectively, and the source of the third transistor and the source of the fourth transistor are both grounded.

[0010] In a possible implementation manner of the first aspect, the second current mirror unit includes an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second current source, a first end of the second current source, a source of the eighth transistor and a source of the ninth transistor all receive a power supply voltage, a gate of the eighth transistor is connected with a gate of the ninth transistor, a drain of the ninth transistor and a drain of the thirteenth transistor respectively, a drain of the eighth transistor is connected with the power module and the first current mirror unit respectively, a second end of the second current source is connected with a drain of the tenth transistor, a gate of the tenth transistor, a drain of the fourteenth transistor and a source of the eleventh transistor respectively, a gate of the eleventh transistor is connected with a gate of the twelfth transistor, a drain of the eleventh transistor and a drain of the twelfth transistor respectively, a source of the twelfth transistor is connected with a source of the fourteenth transistor and a gate of the thirteenth transistor respectively, a gate of the fourteenth transistor is connected with the coupling unit and the first current mirror unit respectively, a source of the tenth transistor and a source of the thirteenth transistor are grounded.

[0011] In a possible implementation manner of the first aspect, the coupling unit includes a coupling capacitor, a first end of the coupling capacitor is connected with the power module, and a second end of the coupling capacitor is connected with the first current mirror unit and the second current mirror unit respectively.

[0012] In a possible implementation manner of the first aspect, the buffer module includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, a source of the fifteenth transistor receives a power supply voltage, a gate of the fifteenth transistor receives a bias voltage, a drain of the fifteenth transistor is connected with a source of the sixteenth transistor, a collector of the eighteenth transistor, the power module and the transient enhancement module respectively, a gate of the sixteenth transistor is connected with the error amplifier module, a drain of the sixteenth transistor is connected with a gate of the seventeenth transistor, a drain of the seventeenth transistor and a base of the eighteenth transistor respectively, a source of the seventeenth transistor and an emitter of the eighteenth transistor are grounded.

[0013] In a possible implementation manner of the first aspect, the power module includes a power transistor, a gate of the power transistor is connected with the buffer module and the transient enhancement module respectively, a source of the power transistor receives a power supply voltage, and a drain of the power transistor is connected with the feedback module, the transient enhancement module and the load respectively.

[0014] In a possible implementation of the first aspect, the low-dropout linear voltage stabilizing circuit further includes a Miller compensation module, which is connected to the error amplification module, the buffer module and the power module respectively.

[0015] The Miller compensation module is configured to perform phase compensation on the target voltage.

[0016] In a second aspect, the embodiments of the present application provide a low-dropout linear voltage stabilizer, including the low-dropout linear voltage stabilizing circuit in any of the first aspect.

[0017] In a third aspect, the embodiments of the present application provide an electronic device, including the low-dropout linear voltage stabilizing circuit in any of the first aspect.

[0018] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0019] The embodiments of the present application provide a low-dropout linear voltage stabilizing circuit, including an error amplification module, a buffer module, a power module, a feedback module and a transient enhancement module, the buffer module is connected to the error amplification module, the power module and the transient enhancement module respectively, the power module is connected to the transient enhancement module, the feedback module and a load respectively, and the feedback module is connected to the error amplification module.

[0020] When the current on the load changes: from small to large or from large to small, the transient enhancement module is configured to provide a first current to the power module according to the target voltage, so that the power module quickly adjusts the target voltage according to the first current, and the target voltage quickly becomes large or small, quickly responding to the change of the load. The feedback module is configured to output a feedback voltage according to the target voltage. The error amplification module is configured to output an error signal according to the feedback voltage and a reference voltage. The buffer module is configured to output a driving signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the driving signal, wherein the target voltage is an output voltage of the low-dropout linear voltage stabilizing circuit. The present application not only can quickly adjust the output voltage when the current on the load changes, but also can maintain the stability and accuracy of the output voltage.

[0021] In the transient response process, the transient enhancement module of the present application significantly improves the response speed of the power module, so that the target voltage can quickly respond to the change of the load, thereby effectively reducing the voltage spike and avoiding the damage of the voltage spike to the circuit. Compared with the traditional LDO, the present application does not need to use a large capacitor of micro-farad level, nor a large size power module, which not only reduces the area and cost of the circuit, but also improves the overall performance of the circuit.

[0022] It can be understood that the beneficial effects of the above-mentioned second aspect to third aspect can be referred to the related description in the above-mentioned first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0024] Figure 1 is a principle block diagram of a low-dropout linear voltage regulator circuit provided by an embodiment of the present application;

[0025] Figure 2 is a principle block diagram of a low-dropout linear voltage regulator circuit provided by another embodiment of the present application;

[0026] Figure 3 is a principle block diagram of a low-dropout linear voltage regulator circuit provided by another embodiment of the present application;

[0027] Figure 4 is a circuit connection schematic diagram of a low-dropout linear voltage regulator circuit provided by an embodiment of the present application;

[0028] Figure 5 is a circuit connection schematic diagram of an error amplifier in the present application.

[0029] In the figure: 10, error amplification module; 20, buffer module; 30, power module; 40, feedback module; 50, transient enhancement module; 51, coupling unit; 52, first current mirror unit; 53, second current mirror unit; 60, load; 70, Miller compensation module. DETAILED DESCRIPTION

[0030] In the following description, for the purpose of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

[0031] It should be understood that when used in the specification and the appended claims, the term "comprises" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] It should also be understood that the term "and / or" as used herein refers to a conjunction, an association, one or more of any combination of associated listed terms, and all possible combinations, and includes these combinations.

[0033] As used in the description of the application and the appended claims, the term "if' can be interpreted to mean "when" or "once" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "once it is determined" or "in response to determining" or "once [the described condition or event] is detected" or "in response to detecting [the described condition or event]," depending on the context.

[0034] In addition, in the description and the appended claims of the application, the terms "first", "second", "third", etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0035] The description of the application refers to "one embodiment" or "some embodiments" and the like means that the specific features, structures or characteristics described in connection with the embodiment are included in one or more embodiments of the application. Therefore, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in additional some embodiments" and the like appearing in different places in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "include", "contain", "have" and their variants mean "include but not limited to", unless otherwise specifically emphasized.

[0036] The conventional LDO circuit realizes fast transient response by using a micro-farad level large capacitor to reduce the damage of voltage spikes to the circuit. However, to drive a micro-farad level large capacitor, a large size power tube is needed, which will generate a large parasitic capacitance, not only sacrificing the response speed of the circuit, but also affecting the stability of the circuit. Therefore, the scheme of the conventional LDO circuit realizing fast transient response by using a micro-farad level large capacitor not only increases the area and cost of the circuit, but also affects the overall performance of the circuit.

[0037] In view of the above problems, the embodiments of the application provide a low dropout linear voltage stabilizing circuit, which comprises a low dropout linear voltage stabilizing circuit, a first capacitor, a second capacitor and a third capacitor. Figure 1As shown, the low-dropout linear regulator circuit includes an error amplification module 10, a buffer module 20, a power module 30, a feedback module 40, and a transient enhancement module 50. The buffer module 20 is connected to the error amplification module 10, the power module 30, and the transient enhancement module 50, respectively. The power module 30 is connected to the transient enhancement module 50, the feedback module 40, and the load 60, respectively. The feedback module 40 is connected to the error amplification module 10.

[0038] Specifically, when the current on load 60 changes—from small to large or from large to small—the transient enhancement module 50 provides a first current to the power module 30 based on the target voltage. This allows the power module 30 to quickly adjust the target voltage according to the first current, causing the target voltage to increase or decrease rapidly, thus quickly responding to changes in load 60. The feedback module 40 outputs a feedback voltage based on the target voltage. The error amplification module 10 outputs an error signal based on the feedback voltage and the reference voltage. The buffer module 20 outputs a drive signal to the power module 30 based on the error signal, enabling the power module 30 to maintain a stable target voltage. The target voltage is the output voltage of the low-dropout linear regulator circuit. This application not only rapidly adjusts the output voltage when the current on load 60 changes but also maintains the stability and accuracy of the output voltage.

[0039] The transient enhancement module 50 of this application significantly improves the response speed of the power module 30 during transient response, enabling the target voltage to respond quickly to changes in the load 60, thereby effectively reducing voltage spikes and preventing damage to the circuit from voltage spikes. Compared to traditional LDOs, this application eliminates the need for large microfarad-level capacitors and large-size power modules, which not only reduces circuit area and cost but also improves overall circuit performance.

[0040] The low-dropout linear regulator circuit provided in this application embodiment exhibits the following characteristics: when the current across the load 60 jumps from 0 to 50mA, the target voltage experiences undershoot, with a voltage change of 3.59mV. When the current across the load 60 jumps from 50mA to 0, the target voltage experiences overshoot, with a voltage change of 2.73mV. This circuit demonstrates good transient response and effectively reduces voltage spikes that occur during transient responses.

[0041] In some embodiments, such as Figure 2 As shown, the transient enhancement module 50 includes a coupling unit 51, a first current mirror unit 52, and a second current mirror unit 53. The coupling unit 51 is connected to the power module 30, the first current mirror unit 52, and the second current mirror unit 53, respectively. The first current mirror unit 52 is connected to the power module 30 and the second current mirror unit 53, respectively. The first current includes a second current and a third current, which are two currents in opposite directions.

[0042] Specifically, when the current on the load 60 changes from small to large, the target voltage will become small, and an undershoot phenomenon occurs. In order to reduce the voltage spike, the coupling unit 51 is configured to output a first coupling signal according to the target voltage. The first current mirror unit 52 is configured to provide a second current to the power module 30 according to the first coupling signal. The power module 30 is configured to quickly adjust the target voltage according to the second current, so that the target voltage becomes large, so as to quickly respond to the change of the load 60. The second current mirror unit 53 is configured to enter an off state according to the first coupling signal.

[0043] When the current on the load 60 changes from large to small, the target voltage will become large, and an overshoot phenomenon occurs. In order to reduce the voltage spike, the coupling unit 51 is configured to output a second coupling signal according to the target voltage. The second current mirror unit 53 is configured to provide a third current to the power module 30 according to the second coupling signal. The power module 30 is configured to quickly adjust the target voltage according to the third current, so that the target voltage becomes small, so as to quickly respond to the change of the load 60. The first current mirror unit 52 is configured to enter an off state according to the second coupling signal.

[0044] In some embodiments, as shown in FIG. 1, the low-dropout linear voltage regulator circuit provided by the embodiments of the present application further includes a Miller compensation module 70, which is connected with the error amplifier module 10, the buffer module 20 and the power module 30 respectively. Figure 3

[0045] Specifically, the Miller compensation module 70 is configured to perform phase compensation on the target voltage, so as to maintain the stability of the circuit.

[0046] In some embodiments, as shown in FIG. 1, the power module 30 includes a power transistor MP, the gate of the power transistor MP is connected with the buffer module 20 and the transient enhancement module 50 respectively, the source of the power transistor MP receives a power supply voltage VDD, and the drain of the power transistor MP is connected with the feedback module 40, the transient enhancement module 50 and the load 60 respectively. Figure 4

[0047] Specifically, the main function of the power transistor MP is to provide a large enough load current to ensure the stability of the output voltage VOUT (i.e. the target voltage). In the present application, when the load 60 changes, the power transistor MP adjusts its own voltage drop to cope with the change of the load 60, thereby maintaining the stability of the output voltage VOUT.

[0048] In some embodiments, as shown in FIG. 1, the coupling unit 51 includes a coupling capacitor Cc, the first end of the coupling capacitor Cc is connected with the power module 30, and the second end of the coupling capacitor Cc is connected with the first current mirror unit 52 and the second current mirror unit 53 respectively. Figure 4

[0049] ​​​Specifically, when the target voltage VOUT changes, the coupling capacitor Cc is used to output corresponding coupling signals to the first current mirror unit 52 and the second current mirror unit 53. When the target voltage VOUT remains stable, the coupling capacitor Cc is equivalent to an open circuit.

[0050] In some embodiments, such as Figure 4 As shown, the first current mirror unit 52 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first current source Ib1. The sources of the first transistor M1 and the second transistor M2 both receive the power supply voltage VDD. The gate of the first transistor M1 is connected to the drain of the first transistor M1, the first terminal of the first current source Ib1, the source of the fifth transistor M5, and the source of the seventh transistor M7, respectively. The second terminal of the first current source Ib1 is grounded. The drain of the fifth transistor M5 is connected to the sixth transistor M6. The drain of transistor M6, the gate of the fifth transistor M5, and the gate of the sixth transistor M6 are connected. The source of the sixth transistor M6 is connected to the gate of the second transistor M2 and the drain of the seventh transistor M7. The gate of the seventh transistor M7 is connected to the coupling unit 51 and the second current mirror unit 53. The drain of the second transistor M2 is connected to the drain of the third transistor M3, the gate of the third transistor M3, and the gate of the fourth transistor M4. The drain of the fourth transistor M4 is connected to the power module 30 and the second current mirror unit 53. The sources of the third transistor M3 and the fourth transistor M4 are both grounded. The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 constitute a current mirror. The first transistor M1 and the second transistor M2 form a PMOS current mirror, and the third transistor M3 and the fourth transistor M4 form an NMOS current mirror. The seventh transistor M7 is a switch that controls the current path.

[0051] Specifically, when the current ILOAD on the load 60 changes from small to large, the target voltage VOUT will become small, and an undershoot phenomenon occurs. The coupling capacitor Cc outputs a first coupling signal according to the changed target voltage VOUT. Since the target voltage VOUT becomes small, the first coupling signal also becomes small, so that the gate voltage of the seventh transistor M7 becomes small, and the seventh transistor M7 is turned on. Since the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 form a current mirror, after the seventh transistor M7 is turned on, the current provided by the first current source Ib1 flows through the first transistor M1, the seventh transistor M7, the second transistor M2, the third transistor M3, and the fourth transistor M4, and then provides a second current to the gate of the power transistor MP, discharges the parasitic capacitor of the power transistor MP, and makes the gate voltage of the power transistor MP small, thereby making the target voltage VOUT large, quickly responding to the change of the load 60, and reducing the voltage spike. It should be noted that the current provided by the first current source Ib1 is a small current, and the small current is amplified by a certain ratio after passing through the current mirror composed of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4.

[0052] When the current ILOAD on the load 60 changes from large to small, the target voltage VOUT will become large, and an overshoot phenomenon occurs. The coupling capacitor Cc outputs a second coupling signal according to the changed target voltage VOUT. Since the target voltage VOUT becomes large, the second coupling signal also becomes large, so that the gate voltage of the seventh transistor M7 becomes large, and the seventh transistor M7 is turned off. Since the fifth transistor M5 and the sixth transistor M6 are connected back-to-back and form a super-large resistance circuit, the super-large resistance circuit hinders the flow of current, and the first current mirror unit 52 is in an off state.

[0053] In some embodiments, as Figure 4As shown, the second current mirror unit 53 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a second current source Ib2, the first end of the second current source Ib2, the source of the eighth transistor M8, and the source of the ninth transistor M9 all receive a power supply voltage VDD, the gate of the eighth transistor M8 is connected with the gate of the ninth transistor M9, the drain of the ninth transistor M9, and the drain of the thirteenth transistor M13 respectively, the drain of the eighth transistor M8 is connected with the power module 30 and the first current mirror unit 52 respectively, the second end of the second current source Ib2 is connected with the drain of the tenth transistor M10, the gate of the tenth transistor M10, the drain of the fourteenth transistor M14, and the source of the eleventh transistor M11 respectively, the gate of the eleventh transistor M11 is connected with the gate of the twelfth transistor M12, the drain of the eleventh transistor M11, and the drain of the twelfth transistor M12 respectively, the source of the twelfth transistor M12 is connected with the source of the fourteenth transistor M14 and the gate of the thirteenth transistor M13 respectively, the gate of the fourteenth transistor M14 is connected with the coupling unit 51 and the first current mirror unit 52 respectively, and the source of the tenth transistor M10 and the source of the thirteenth transistor M13 are both grounded. Among them, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the thirteenth transistor M13 constitute a current mirror, the eighth transistor M8 and the ninth transistor M9 constitute a PMOS current mirror, and the tenth transistor M10 and the thirteenth transistor M13 constitute an NMOS current mirror. The fourteenth transistor M14 is a switch tube for controlling the current path.

[0054] Specifically, when the current ILOAD on the load 60 changes from small to large, the target voltage VOUT will become smaller, and an undershoot phenomenon occurs. The coupling capacitor Cc outputs the first coupling signal according to the changed target voltage VOUT, and since the target voltage VOUT becomes smaller, the first coupling signal also becomes smaller, so that the gate voltage of the fourteenth transistor M14 becomes smaller, and the fourteenth transistor M14 is turned off. Since the eleventh transistor M11 and the twelfth transistor M12 are connected back-to-back and constitute a super-large resistance circuit, the super-large resistance circuit hinders the flow of current, so that the second current mirror unit 53 is in a cut-off state.

[0055] When the current ILOAD on the load 60 changes from large to small, the target voltage VOUT increases, resulting in an overshoot phenomenon. The coupling capacitor Cc outputs a second coupling signal based on the changing target voltage VOUT. Since the target voltage VOUT increases, the second coupling signal also increases, causing the gate voltage of the fourteenth transistor M14 to increase, thus turning on the fourteenth transistor M14. Because the eighth transistor M8, ninth transistor M9, tenth transistor M10, and thirteenth transistor M13 form a current mirror, after the fourteenth transistor M14 turns on, the current provided by the second current source Ib2 flows through the tenth transistor M10, fourteenth transistor M14, thirteenth transistor M13, ninth transistor M9, and eighth transistor M8 to provide a third current to the gate of the power transistor MP. This charges the parasitic capacitance of the power transistor MP, increasing its gate voltage and consequently decreasing the target voltage VOUT, thus rapidly responding to changes in the load 60 and reducing voltage spikes. It should be noted that the current provided by the second current source Ib2 is a small current. After passing through the tenth transistor M10, the fourteenth transistor M14, the thirteenth transistor M13, the ninth transistor M9 and the eighth transistor M8, the small current will be amplified according to a certain ratio.

[0056] It should be noted that the first current source Ib1 and the second current source Ib2 are two identical current sources.

[0057] In summary, the transient enhancement module 50 in this application has a simple overall structure that is easy to implement, and its size can be designed to be as small as 220nm / 180nm. It adopts transistor back-to-back connection technology, with an equivalent resistance of hundreds of gigaohms. When the circuit is in a stable state, both the first current mirror unit 52 and the second current mirror unit 53 are in the off state, achieving low power consumption and saving circuit area by eliminating the need for large-area resistors.

[0058] In some embodiments, such as Figure 4 As shown, the buffer module 20 includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The source of the fifteenth transistor M15 receives the power supply voltage VDD, and the gate of the fifteenth transistor M15 receives the bias voltage Vb. The drain of the fifteenth transistor M15 is connected to the source of the sixteenth transistor M16, the collector of the eighteenth transistor M18, the power module 30, and the transient enhancement module 50, respectively. The gate of the sixteenth transistor M16 is connected to the error amplification module 10, and the drain of the sixteenth transistor M16 is connected to the gate of the seventeenth transistor M17, the drain of the seventeenth transistor M17, and the base of the eighteenth transistor M18, respectively. The source of the seventeenth transistor M17 and the emitter of the eighteenth transistor M18 are both grounded.

[0059] Specifically, the buffer module 20 is essentially an enhanced source follower, which adds an eighteenth transistor M18, i.e. a NPN transistor, compared to a traditional source follower. The enhanced source follower has the characteristics of low input capacitance and low output impedance, and is able to separate the pole of the output end of the error amplifier module 10 and the pole of the gate of the power transistor MP, thus obtaining better stability.

[0060] In some embodiments, as shown in Figure 4 The error amplifier module 10 includes an error amplifier EA, the output end of the error amplifier EA is connected with the buffer module 20 and the Miller compensation module 70 respectively, the non-inverting input end of the error amplifier EA is connected with the feedback module 40, and the inverting input end of the error amplifier EA receives a reference voltage VREF.

[0061] Specifically, the main function of the error amplifier EA is to compare the reference voltage VREF with a feedback voltage VFB. The feedback voltage VFB is obtained by the target voltage VOUT through the feedback module 40, and it represents the actual level of the current output voltage VOUT. By comparing the two voltages accurately, the error amplifier EA can perceive the deviation of the output voltage VOUT. When the feedback voltage VFB is lower than the reference voltage VREF, the error amplifier EA outputs a positive error signal; on the contrary, when the feedback voltage VFB is higher than the reference voltage VREF, a negative error signal is output. The size of the error signal is proportional to the difference between the two, which realizes the accurate amplification of the error. The error signal is then sent to the subsequent control loop for adjusting the conduction degree of the power transistor MP.

[0062] For example, as shown in Figure 5As shown, the error amplifier EA includes a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, a twenty-seventh transistor M27, a twenty-eighth transistor M28, and a twenty-ninth transistor M29, the source of the nineteenth transistor M19, the source of the twenty-second transistor M22, and the source of the twenty-third transistor M23 all receive a power supply voltage VDD, the gate of the nineteenth transistor M19 receives a bias voltage Vb1, the drain of the nineteenth transistor M19 is connected with the source of the twentieth transistor M20 and the source of the twenty-first transistor M21 respectively, the gate of the twentieth transistor M20 is connected with the feedback module 40 and receives a feedback voltage VFB, the gate of the twenty-first transistor M21 receives a reference voltage VREF, the drain of the twentieth transistor M20 is connected with the source of the twenty-sixth transistor M26 and the drain of the twenty-eighth transistor M28 respectively, the drain of the twenty-first transistor M21 is connected with the source of the twenty-seventh transistor M27 and the drain of the twenty-ninth transistor M29 respectively, the gate of the twenty-second transistor M22 is connected with the gate of the twenty-third transistor M23, the drain of the twenty-fourth transistor M24, and the drain of the twenty-sixth transistor M26 respectively, the drain of the twenty-second transistor M22 is connected with the source of the twenty-fourth transistor M24, the drain of the twenty-third transistor M23 is connected with the source of the twenty-fifth transistor M25, the gate of the twenty-fourth transistor M24 and the gate of the twenty-fifth transistor M25 both receive a bias voltage Vb2, the drain of the twenty-fifth transistor M25 is connected with the drain of the twenty-seventh transistor M27 and the buffer module 20 respectively, the gate of the twenty-sixth transistor M26 and the gate of the twenty-seventh transistor M27 both receive a bias voltage Vb3, the gate of the twenty-eighth transistor M28 and the gate of the twenty-ninth transistor M29 both receive a bias voltage Vb4, the source of the twenty-eighth transistor M28 and the source of the twenty-ninth transistor M29 are both grounded.

[0063] Specifically, the error amplifier EA is a folded cascode amplifier. Among them, the twentieth transistor M20 and the twenty-first transistor M21 are a PMOS differential input pair, used to amplify the difference between the reference voltage VREF and the feedback voltage VFB; the nineteenth transistor M19 is a tail current source for providing a bias current; and the transistors M22-M29 are output poles of a cascode structure.

[0064] In some embodiments, as Figure 4As shown, the feedback module 40 comprises a first resistor R1, a second resistor R2 and a load capacitor CL, a first end of the first resistor R1 is connected with a first end of the load capacitor CL and the power module 30 respectively, a second end of the first resistor R1 is connected with a first end of the second resistor R2 and the error amplifier module 10 respectively, a second end of the second resistor R2 and a second end of the load capacitor CL are grounded.

[0065] Specifically, the first resistor R1 and the second resistor R2 divide the output voltage VOUT to output a feedback voltage VFB to the error amplifier module 10, so that the error amplifier module 10 outputs an error signal according to the feedback voltage VFB and the reference voltage VREF, and the error signal is then sent to a subsequent control loop for adjusting the conduction degree of the power transistor MP to ensure the stability of the output voltage VOUT.

[0066] It should be noted that the load capacitor CL of the present application can use a common capacitor, and does not need to use a large capacitor of micro-farad level, thereby saving the circuit area and cost.

[0067] In some embodiments, as shown, Figure 4 As shown, the Miller compensation module 70 comprises a Miller compensation capacitor Cm and a Miller compensation resistor Rm, a first end of the Miller compensation capacitor Cm is connected with the error amplifier module 10 and the buffer module 20 respectively, a second end of the Miller compensation capacitor Cm is connected with a first end of the Miller compensation resistor Rm, and a second end of the Miller compensation resistor Rm is grounded.

[0068] Specifically, the Miller compensation capacitor Cm and the Miller compensation resistor Rm are used for compensating the phase of the target voltage VOUT to ensure the stability of the circuit.

[0069] In summary, the present application adds the transient enhancement module 50 in the low-dropout linear regulator circuit, which can quickly charge and discharge the parasitic capacitor of the power transistor MP when the power module 30 has a transient response, thereby improving the response speed of the power transistor MP and reducing the voltage spike. When the current ILOAD on the load 60 changes greatly in a short time, the voltage spike of the output voltage VOUT can be controlled within 4mV. The small voltage spike of the output voltage VOUT can be applied to devices sensitive to voltage changes. Compared with the traditional LDO which uses a large capacitor of micro-farad level to achieve better transient response, the load capacitor CL used in the present application is very small, thereby saving the circuit area and cost. The transient enhancement module 50 in the present application adopts the transistor back-to-back connection technology, and the equivalent resistance reaches hundreds of gigaohms, thereby solving the problem of occupying the circuit area by using a large-area resistor.

[0070] The embodiment of the present application further provides a low-dropout linear voltage regulator comprising the low-dropout linear voltage stabilizing circuit.

[0071] The embodiment of the present application further provides an electronic device comprising the low-dropout linear voltage stabilizing circuit.

[0072] For example, the electronic device can be a switching power supply device.

[0073] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0074] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A low dropout linear voltage regulator circuit, characterized by comprising: The error amplifier module, the buffer module, the power module, the feedback module and the transient enhancement module are included, the buffer module is connected with the error amplifier module, the power module and the transient enhancement module respectively, the power module is connected with the transient enhancement module, the feedback module and the load respectively, and the feedback module is connected with the error amplifier module; When the current on the load changes, the transient enhancement module is used for providing a first current to the power module according to a target voltage, so that the power module quickly adjusts the target voltage according to the first current; the feedback module is used for outputting a feedback voltage according to the target voltage; the error amplifier module is used for outputting an error signal according to the feedback voltage and a reference voltage; and the buffer module is used for outputting a driving signal to the power module according to the error signal, so that the power module maintains the target voltage stable according to the driving signal; wherein the target voltage is an output voltage of the low-dropout linear regulator circuit; The transient enhancement module includes a coupling unit, a first current mirror unit and a second current mirror unit, the coupling unit is connected with the power module, the first current mirror unit and the second current mirror unit respectively, and the first current includes a second current and a third current; When the current on the load changes from small to large, the coupling unit is used for outputting a first coupling signal according to the target voltage; the first current mirror unit is used for providing the second current to the power module according to the first coupling signal; the power module is used for quickly adjusting the target voltage according to the second current, so that the target voltage becomes large; and the second current mirror unit is used for entering an off state according to the first coupling signal; when the current on the load changes from large to small, the coupling unit is used for outputting a second coupling signal according to the target voltage; the second current mirror unit is used for providing the third current to the power module according to the second coupling signal; the power module is used for quickly adjusting the target voltage according to the third current, so that the target voltage becomes small; and the first current mirror unit is used for entering an off state according to the second coupling signal.

2. The low dropout linear regulator circuit of claim 1, wherein, The first current mirror unit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and a first current source, the source of the first transistor and the source of the second transistor both receive a power supply voltage, the gate of the first transistor is connected with the drain of the first transistor, the first end of the first current source, the source of the fifth transistor and the source of the seventh transistor respectively, the second end of the first current source is grounded, the drain of the fifth transistor is connected with the drain of the sixth transistor, the gate of the fifth transistor and the gate of the sixth transistor respectively, the source of the sixth transistor is connected with the gate of the second transistor and the drain of the seventh transistor respectively, the gate of the seventh transistor is connected with the coupling unit and the second current mirror unit respectively, the drain of the second transistor is connected with the drain of the third transistor, the gate of the third transistor and the gate of the fourth transistor respectively, the drain of the fourth transistor is connected with the power module and the second current mirror unit respectively, and the source of the third transistor and the source of the fourth transistor are both grounded.

3. The low dropout linear regulator circuit of claim 1, wherein, The second current mirror unit comprises an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a second current source, the first end of the second current source, the source of the eighth transistor and the source of the ninth transistor all receive a power supply voltage, the gate of the eighth transistor is connected with the gate of the ninth transistor, the drain of the ninth transistor and the drain of the thirteenth transistor respectively, the drain of the eighth transistor is connected with the power module and the first current mirror unit respectively, the second end of the second current source is connected with the drain of the tenth transistor, the gate of the tenth transistor, the drain of the fourteenth transistor and the source of the eleventh transistor respectively, the gate of the eleventh transistor is connected with the gate of the twelfth transistor, the drain of the eleventh transistor and the drain of the twelfth transistor respectively, the source of the twelfth transistor is connected with the source of the fourteenth transistor and the gate of the thirteenth transistor respectively, the gate of the fourteenth transistor is connected with the coupling unit and the first current mirror unit respectively, and the source of the tenth transistor and the source of the thirteenth transistor are both grounded.

4. The low dropout linear regulator of claim 1, wherein, The coupling unit comprises a coupling capacitor, the first end of the coupling capacitor is connected with the power module, and the second end of the coupling capacitor is connected with the first current mirror unit and the second current mirror unit respectively.

5. The low dropout linear regulator of claim 1, wherein, The buffer module comprises a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and an eighteenth transistor, a source of the fifteenth transistor receives a power supply voltage, a gate of the fifteenth transistor receives a bias voltage, a drain of the fifteenth transistor is connected with a source of the sixteenth transistor, a collector of the eighteenth transistor, the power module and the transient enhancement module respectively, a gate of the sixteenth transistor is connected with the error amplifier module, a drain of the sixteenth transistor is connected with a gate of the seventeenth transistor, a drain of the seventeenth transistor and a base of the eighteenth transistor respectively, and a source of the seventeenth transistor and an emitter of the eighteenth transistor are grounded.

6. The low dropout linear regulator of claim 1, wherein, The power module comprises a power tube, a gate of the power tube is connected with the buffer module and the transient enhancement module respectively, a source of the power tube receives the power supply voltage, and a drain of the power tube is connected with the feedback module, the transient enhancement module and the load respectively.

7. The low dropout linear regulator of any of claims 1-6, wherein, The low-dropout linear voltage stabilizing circuit further comprises a Miller compensation module, and the Miller compensation module is connected with the error amplifier module, the buffer module and the power module respectively. The Miller compensation module is used for performing phase compensation on the target voltage.

8. A low-dropout linear voltage regulator, characterized by, The low-dropout linear voltage stabilizing circuit comprises the low-dropout linear voltage stabilizing circuit of any one of claims 1-7.

9. An electronic device, comprising: The low-dropout linear voltage stabilizing circuit comprises the low-dropout linear voltage stabilizing circuit of any one of claims 1-7.

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