LDO circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides an LDO circuit, a chip and electronic equipment, and belongs to the technical field of analog chips. The LDO circuit comprises an input circuit which is connected with a reference current and correspondingly outputs a reference voltage at least through a main transistor; the amplifying circuit is connected with the reference voltage and amplifies the reference voltage; one end of the feedback circuit is connected with the output end of the amplifying circuit through a transistor geminate transistor, and the other end of the feedback circuit feeds back voltage to the amplifying circuit and serves as the output end of the LDO circuit. Wherein the main transistor and the transistor geminate transistor both work in a sub-threshold region, and the amplification factor of the amplification circuit is configured to enable the current flowing through the main transistor and the transistor geminate transistor to be equal. According to the LDO circuit disclosed by the embodiment of the invention, the transistor in the sub-threshold region is matched with the amplification factor of the amplification circuit, so that the voltage which can be determined and output by the LDO circuit is generated, a reference circuit is not needed, and the circuit is simple and low in power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of analog chips, and in particular to an LDO circuit, a chip and an electronic device. Background Art

[0002] LDO (Low Drop-Out Regulator) can provide clean and stable power in the circuit to ensure that the components and devices in the circuit can work normally, and reduce the impact of power supply noise and fluctuations on circuit performance. Figure 1 As shown in the figure, the traditional LDO circuit is composed of a reference circuit, an error amplifier, a power tube, a feedback network, etc. Its working process is as follows: the circuit detects the output voltage from the resistor feedback network and compares it with the reference voltage provided by the bandgap reference. The error amplifier then amplifies the compared voltage difference signal and transmits it to the power tube for linear adjustment, so that the output voltage and the input reference voltage maintain the corresponding ratio unchanged, thereby generating a stable voltage output.

[0003] However, in the process of implementing the present invention, the inventors of the present application discovered that the traditional LDO circuit requires modules with high complexity and power consumption, such as reference circuits and error amplifiers, and when applied in a specific system, it is necessary to ensure that the MOS tubes all operate in the saturation region, which leads to further increase in the power consumption generated by the circuit, making the system implementation cost higher.

[0004] Thus, the present application aims to propose a new design for an LDO circuit. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide an LDO circuit, a chip and an electronic device, which are used to at least partially solve the above technical problems.

[0006] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides an LDO circuit, comprising: an input circuit, including a main transistor, the input circuit is connected to a reference current, and at least outputs a corresponding reference voltage through the main transistor; an amplifier circuit, which is connected to the reference voltage and amplifies it; and a feedback circuit, including a transistor pair, one end of the feedback circuit is connected to the output end of the amplifier circuit through the transistor pair, and the other end feeds back a voltage to the amplifier circuit and serves as the output end of the LDO circuit. Wherein, the main transistor and the transistor pair both work in the subthreshold region, and the amplification factor of the amplifier circuit is configured so that the current flowing through the main transistor and the transistor pair is equal.

[0007] Optionally, the input circuit includes: a twelfth transistor M12, whose drain is connected to the gate and connected to the first bias current BIAS1; an eleventh transistor as the main transistor, whose drain is connected to the gate and connected to the source of the twelfth transistor M12; and a tenth transistor M10, whose drain is connected to the gate and connected to the second bias current BIAS2, and whose source is connected to the source of the eleventh transistor M11 and grounded. The gates of the twelfth transistor M12 and the tenth transistor M10 are respectively used to output a reference voltage.

[0008] Optionally, the amplifier circuit includes: an eighth transistor M8 and a ninth transistor M9 with a common gate, and the sources of both are grounded, and the gates are connected to a reference voltage; a fourth transistor M4 and a seventh transistor M7 with a common gate, and the gates of both are connected to another reference voltage, wherein the source of the fourth transistor M4 is connected to the drain of the eighth transistor M8 and serves as the output end of the amplifier circuit, and the source of the seventh transistor M7 is connected to the drain of the ninth transistor M9; and a fifth transistor M5 and a sixth transistor M6 with a common gate, and the sources of both are connected to an operating voltage, wherein the drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4, and the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7, and the gate of the sixth transistor M6 is also connected to its drain.

[0009] Optionally, the amplifying circuit further includes: a fourteenth transistor M14, whose gate and drain are connected to the drain of the eighth transistor M8; and a thirteenth transistor M13, whose gate and drain are connected to the source of the fourteenth transistor M14.

[0010] Optionally, the feedback circuit includes: a second transistor M2 and a third transistor M3 forming the transistor pair, wherein the drains and gates of the second transistor M2 and the third transistor M3 are connected to each other, the source of the second transistor M2 serves as the output end of the LDO circuit, and the source of the third transistor M3 is connected to the output end of the amplifier circuit; and a first transistor M1, whose drain is connected to the source of the second transistor M2, the source is connected to the working voltage, and the gate is connected to the amplifier circuit to feedback the voltage.

[0011] Optionally, the feedback circuit further includes: a PMOS tube M0, a gate of which is connected to a preset bias current, a source of which is connected to the source of the second transistor M2, and a drain of which is grounded.

[0012] Optionally, the feedback circuit further includes: a fifteenth transistor M15, whose drain is connected to the gate and connected to the gate of the first transistor M1; and a sixteenth transistor M16, whose drain is connected to the gate and connected to the source of the fifteenth transistor M15, and whose source is connected to the working voltage.

[0013] Optionally, the LDO circuit further includes: a compensation circuit, which is arranged on a feedback loop in which the feedback circuit feeds back a voltage to the amplifier circuit, and is used to achieve frequency compensation for the LDO circuit.

[0014] On the other hand, an embodiment of the present invention further provides a chip, wherein any of the above-mentioned LDO circuits is integrated in the chip.

[0015] On the other hand, an embodiment of the present invention further provides an electronic device, comprising any of the above chips.

[0016] Through the above technical solution, the LDO circuit of the embodiment of the present invention utilizes a main transistor and a group of transistor pairs in the subthreshold region, and cooperates with the amplification factor of the amplifier circuit to generate a voltage that can be used for the LDO circuit to determine the output, thereby avoiding the use of a reference circuit, and the circuit is simple and has low power consumption.

[0017] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0019] Figure 1 It is a schematic diagram of the structure of a traditional LDO circuit;

[0020] Figure 2 is a schematic structural diagram of an LDO circuit according to an embodiment of the present invention; and

[0021] Figure 3 Schematic diagram of an exemplary design of an LDO circuit according to an embodiment of the present invention.

[0022] Description of Reference Numerals

[0023] 100, input circuit; 200, amplifier circuit; 300, feedback circuit; 400, compensation circuit. DETAILED DESCRIPTION

[0024] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0025] It should be noted that the “connection” and “access” involved in the embodiments of the present invention mainly refer to “electrical connection”, which is used to express the signal connection between two components, such as connection through a circuit, and the “connection” and “access” involved can be a direct electrical connection between the two components, or an indirect electrical connection through other components or circuits.

[0026] Figure 2 Schematic diagram of the structure of the LDO circuit of the embodiment of the present invention. Figure 2 As shown, the LDO circuit includes: an input circuit 100, including a main transistor, the input circuit 100 is connected to a reference current, and at least outputs a corresponding reference voltage through the main transistor; an amplifier circuit 200, which is connected to the reference voltage and amplifies it; and a feedback circuit 300, including a transistor pair, one end of the feedback circuit 300 is connected to the output end of the amplifier circuit through the transistor pair, and the other end feeds back a voltage to the amplifier circuit 200 and serves as the output end of the LDO circuit. Wherein, the main transistor and the transistor pair both work in the subthreshold region, and the amplification factor of the amplifier circuit 200 is configured so that the current flowing through the main transistor and the transistor pair is equal. Wherein, the reference current and the reference voltage are two-way, which will be further described in conjunction with examples below.

[0027] Among them, when the gate voltage of the transistor (MOSFET) is lower than the threshold voltage, its electrons cannot completely flow from the source to the drain, thus generating a subthreshold region. The characteristic of this subthreshold region is that some electrons still flow from the source to the drain, but the current is small, because in the subthreshold region, the channel formation of the MOSFET is limited and cannot be fully opened.

[0028] In this way, the LDO circuit of the embodiment of the present invention utilizes a main transistor and a group of transistor pairs in the subthreshold region, and cooperates with the amplification factor of the amplifier circuit to generate a voltage that can be used for the LDO circuit to determine the output, which is equivalent to realizing the function of outputting a reference voltage by the reference circuit, thereby avoiding the use of the reference circuit and reducing the power consumption of the system using the LDO circuit.

[0029] The design of the LDO circuit in the embodiment of the present invention is specifically described below by way of examples.

[0030] Figure 3 Schematic diagram of an exemplary design of an LDO circuit according to an embodiment of the present invention. Figure 3As shown, the input circuit 100 includes: a twelfth transistor M12, whose drain is connected to the gate and connected to the first bias current BIAS1; an eleventh transistor M11 as the main transistor, whose drain is connected to the gate and connected to the source of the twelfth transistor M12; a tenth transistor M10, whose drain is connected to the gate and connected to the second bias current BIAS2, and whose source is connected to the source of the eleventh transistor M11 and grounded. The gates of the twelfth transistor M12 and the tenth transistor M10 are respectively used to output a reference voltage. The first bias current BIAS1 and the second bias current BIAS2 are two reference currents from a preset power supply.

[0031] The amplifier circuit 200 includes: an eighth transistor M8 and a ninth transistor M9 with a common gate, and both sources are grounded, and the gates are connected to a reference voltage; a fourth transistor M4 and a seventh transistor M7 with a common gate, and both gates are connected to another reference voltage, wherein the source of the fourth transistor M4 is connected to the drain of the eighth transistor M8 and serves as the output end of the amplifier circuit, and the source of the seventh transistor M7 is connected to the drain of the ninth transistor M9; and a fifth transistor M5 and a sixth transistor M6 with a common gate, and both sources are connected to an operating voltage V+, wherein the drain of the fifth transistor M5 is connected to the drain of the fourth transistor M4, and the drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7, and the gate of the sixth transistor M6 is also connected to its drain.

[0032] The feedback circuit 300 includes: a second transistor M2 and a third transistor M3 forming the transistor pair, wherein the drains and gates of the second transistor M2 and the third transistor M3 are connected to each other, the source of the second transistor M2 serves as the output end of the LDO circuit, and the source of the third transistor M3 is connected to the output end of the amplifier circuit; and a first transistor M1, whose drain is connected to the source of the second transistor M2, the source is connected to the working voltage, and the gate is connected to the amplifier circuit to feedback the voltage.

[0033] For the LDO circuit including the input circuit 100, the amplifier circuit 200 and the feedback circuit 300, in the example, the two bias currents are set to 5uA, and are respectively recorded as BIAS1_0P5uA and BIAS2_0P5uA, and the output voltage of the LDO circuit is recorded as VDD_DIG, and each transistor adopts the following Figure 3 The PMOS tube or NMOS tube shown, and the amplifier circuit 200 is configured to achieve a double amplification factor, the working principle of the LDO circuit can be described as:

[0034] The bias current BIAS1_0P5uA flows through transistors M11 and M12, and a bias voltage is obtained on the gate of transistor M12, which is the sum of the gate-source voltages of transistors M11 and M12. Since the ratio of transistors M8 and M9 is 2:1, the currents on transistors M4, M7 and M12 are the same, and the currents on transistors M2, M3 and M11 are also the same. Ignoring the channel modulation effect, it can be obtained that the drain voltage of transistor M8 is approximately the gate-source voltage of transistor M11. The other half of the current mirrored by transistor M8 flows through transistors M2 and M3 to generate voltage. Since transistors M2, M3 and M11 are in the subthreshold region, the voltage of VDD_DIG under no-load is finally obtained:

[0035]

[0036] in:

[0037] NMOS subthreshold current = I tn *(W / L)*exp[(V gs -V t ) / (nV T )];

[0038] PMOS subthreshold current = I tp *(W / L)*exp[(V sg -V t ) / (nV T )];

[0039] V SG2 is the difference between the source and gate voltage of PMOS tube M2, V t2 is the threshold voltage of the PMOS tube M2;

[0040] V GS3 is the gate-source voltage difference of NMOS tube M3, V t3 is the threshold voltage of NMOS tube M3;

[0041] V GS11 is the gate-source voltage difference of NMOS tube M11, V t11 is the threshold voltage of the NMOS tube M11;

[0042] n is the empirical coefficient, V T is the thermal voltage, S is the width-to-length ratio (W / L) of the MOS tube, where S2 corresponds to transistor M2, S3 corresponds to transistor M3, and S 11 Corresponding to transistor M11; I is the on-current of the MOS tube, and the on-current of transistors M2, M3 and M11 are all equal to 0.5uA; I tp is the subthreshold current of the PMOS tube when W / L=1, I tnIt is the subthreshold current of NMOS tube when W / L=1.

[0043] It should be noted that the ratio of transistors M8 and M9 is consistent with the amplification factor of the amplifier circuit 200, but it is not limited to 2:1. The ratio can be adjusted according to the adaptability of specific circuit components as long as the same current is ensured on transistors M2, M3 and M11.

[0044] That is, the output terminal VDD_DIG of the LDO circuit generates a stable output voltage V o The negative feedback loop formed by transistors M1-M2-M3-M4-M1 helps to ensure the voltage stability.

[0045] Furthermore, combined with Figure 2 and Figure 3 In a preferred embodiment, the LDO circuit further includes: a compensation circuit 400, which is arranged on the feedback loop of the feedback circuit 300 feeding back the voltage to the amplifier circuit 200, and is used to achieve frequency compensation for the LDO circuit. Figure 3 The compensation circuit 400 is arranged between the gate and the source of the first transistor M1, which can be a TYPE-2 compensator composed of a resistor R1, a resistor R2 and a capacitor C2, for ensuring the stability of the entire feedback loop. In addition, in order to reduce overshoot and perform withstand voltage protection, Figure 3 The LDO circuit shown is also configured with components such as a resistor RL, a capacitor CL, a capacitor C1, and a resistor R3.

[0046] Therefore, from the perspective of transfer function, Figure 3 The principle of loop compensation achieved by the coordination of various components in the LDO circuit can be described as follows:

[0047] Calculate the corresponding loop gain from the gate break of transistor M1, and ignore the load shunting of the LDO circuit. The no-load-light-load transfer function can be obtained as follows:

[0048]

[0049] Among them, z1 is the main zero, z2 is the secondary zero, p1 is the main pole, p2 is the secondary pole, g m1 , g m2 and g m3 are the transconductances of transistors M1, M2, and M3, respectively, and r o5 is the channel resistance of transistor M5, R1, R2, R3, R L Indicates the resistance value of the corresponding resistor, C1, C2 and C LIndicates the capacitance of the corresponding capacitor. The frequency of the secondary zero z2 is much higher than the op amp gain bandwidth product GBW of the amplifier circuit, so the entire loop is approximately a "two poles + one zero" system. The use of zeros to compensate for the secondary poles can ensure the stability of the entire loop. Under heavy load, the secondary pole moves to high frequency, and the zero point is ahead of the secondary pole. At the same time, the loop gain decreases, while the main pole remains unchanged, so the unit gain bandwidth is reduced, making the entire loop more stable.

[0050] Furthermore, the amplifier circuit 200 further includes: a fourteenth transistor M14, whose gate is connected to the drain and connected to the drain of the eighth transistor M8; and a thirteenth transistor M13, whose gate is connected to the drain and connected to the source of the fourteenth transistor M14. That is, the transistors M13 and M14 cooperate to protect the transistor M8, and prevent the drain voltage of the transistor M8 from being too high and breaking down due to capacitive coupling when the LDO circuit is powered on.

[0051] Furthermore, the feedback circuit 300 further includes: a fifteenth transistor M15, whose drain is connected to the gate and connected to the gate of the first transistor M1; a sixteenth transistor M16, whose drain is connected to the gate and connected to the source of the fifteenth transistor (M15), and whose source is connected to the working voltage. That is, the transistors M15 and M16 cooperate to limit the maximum gate-source voltage of the transistor M1, and can also play a certain current limiting role.

[0052] Furthermore, the feedback circuit 300 further includes: a PMOS transistor M0, whose gate is connected to a preset bias current, whose source is connected to the source of the second transistor M2, and whose drain is grounded. Figure 3 The LDO_TEG signal provides a bias for the gate of the PMOS tube M0 connected to the output end of the LDO circuit. When the load switches from heavy load to light load, the output overshoots and the PMOS tube M0 discharges, thereby limiting the overshoot to a certain extent.

[0053] It should be noted that Figure 3 The division of the input circuit 100, the amplifying circuit 200, the feedback circuit 300 and the compensation circuit 400 is exemplary, and each circuit may include devices outside the corresponding virtual frame, or even not in the virtual frame. Figure 3 The device shown in the figure is configured with a corresponding protection circuit for the purpose of reducing overshoot and withstand voltage protection. Figure 3 The invention also involves devices not described above, whose functions have little impact on the working principle of the LDO circuit in the embodiment of the present invention, are not devices concerned with the embodiment of the present invention, and those skilled in the art can easily know their functions, so they will not be described in detail here.

[0054] In summary, the embodiments of the present invention substantially provide a subthreshold low-power LDO circuit without a reference voltage, which directly generates a stable LDO output voltage by using transistors in the subthreshold region through input current. Since no reference circuit is required, the circuit structure is simpler and the power consumption is low. In addition, since the transistor works in the subthreshold region, the circuit power consumption is further reduced, which can solve the problems of complexity and high power consumption in traditional LDO circuit design.

[0055] The embodiment of the present invention also provides a chip, which integrates any of the above LDO circuits. The chip is, for example, a power management chip. The LDO circuit of this embodiment does not require a reference circuit, so when integrated in the chip, it occupies less space, which is conducive to reducing the chip size.

[0056] An embodiment of the present invention further provides an electronic device, comprising the above chip, such as a communication device, an automotive electronic device, etc.

[0057] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0058] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A low dropout linear stabilizer LDO circuit, characterized in that: include: An input circuit (100) comprising a main transistor, the input circuit (100) being connected to a reference current and correspondingly outputting a reference voltage at least through the main transistor; an amplifier circuit (200) which is connected to the reference voltage and performs amplification; as well as A feedback circuit (300) comprises a transistor pair, one end of the feedback circuit (300) is connected to the output end of the amplifier circuit (200) via the transistor pair, and the other end feeds back voltage to the amplifier circuit (200) and serves as the output end of the LDO circuit; The main transistor and the transistor pair both operate in a subthreshold region, and the amplification factor of the amplifier circuit (200) is configured so that the currents flowing through the main transistor and the transistor pair are equal.

2. The LDO circuit according to claim 1, characterized in that: The input circuit (100) comprises: A twelfth transistor (M12), a drain of which is connected to the gate and connected to the first bias current (BIAS1); an eleventh transistor (M11) as the main transistor, the drain of which is connected to the gate and connected to the source of the twelfth transistor (M12); and a tenth transistor (M10), whose drain is connected to the gate and connected to the second bias current (BIAS2), and whose source is connected to the source of the eleventh transistor (M11) and grounded; Wherein, the gates of the twelfth transistor (M12) and the tenth transistor (M10) respectively output a reference voltage.

3. The LDO circuit according to claim 1, characterized in that: The amplifier circuit (200) comprises: An eighth transistor (M8) and a ninth transistor (M9) having a common gate, wherein the sources of the transistors are grounded and the gates are connected to a reference voltage; a fourth transistor (M4) and a seventh transistor (M7) having a common gate, and the gates of the two transistors are connected to another reference voltage, wherein the source of the fourth transistor (M4) is connected to the drain of the eighth transistor (M8) and serves as the output end of the amplifier circuit (200), and the source of the seventh transistor (M7) is connected to the drain of the ninth transistor (M9); and A fifth transistor (M5) and a sixth transistor (M6) having a common gate, and the sources of both transistors are connected to an operating voltage, wherein the drain of the fifth transistor (M5) is connected to the drain of the fourth transistor (M4), and the drain of the sixth transistor (M6) is connected to the drain of the seventh transistor (M7), and the gate of the sixth transistor (M6) is also connected to its drain.

4. The LDO circuit according to claim 3, characterized in that: The amplifying circuit (200) further includes: a fourteenth transistor (M14), whose gate and drain are connected to the drain of the eighth transistor (M8); and The gate of the thirteenth transistor (M13) is connected to the drain and is also connected to the source of the fourteenth transistor (M14).

5. The LDO circuit according to claim 1, characterized in that: The feedback circuit (300) comprises: a second transistor (M2) and a third transistor (M3) forming the transistor pair, wherein the drains and gates of the second transistor (M2) and the third transistor (M3) are connected to each other, the source of the second transistor (M2) serves as the output end of the LDO circuit, and the source of the third transistor (M3) is connected to the output end of the amplifier circuit; and The first transistor (M1) has a drain connected to the source of the second transistor (M2), a source connected to an operating voltage, and a gate connected to the amplifier circuit to feedback a voltage.

6. The LDO circuit according to claim 5, characterized in that: The feedback circuit (300) further includes: The PMOS tube (M0) has a gate connected to a preset bias current, a source connected to the source of the second transistor (M2), and a drain connected to the ground.

7. The LDO circuit according to claim 5, characterized in that: The feedback circuit (300) further includes: a fifteenth transistor (M15), whose drain is connected to the gate and connected to the gate of the first transistor (M1); and The sixteenth transistor (M16) has a drain connected to the gate and connected to the source of the fifteenth transistor (M15), and a source connected to the operating voltage.

8. The LDO circuit according to any one of claims 1 to 7, characterized in that: The LDO circuit further includes: A compensation circuit (400) is provided on a feedback loop in which the feedback circuit (300) feeds back a voltage to the amplifier circuit (200), and is used to achieve frequency compensation for the LDO circuit.

9. A chip, characterized in that: The chip integrates the LDO circuit described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises the chip as claimed in claims 1 to 9.

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